- 9e884d5 Add new draft by mrg · 5 years ago master
- d9d742e Add updated layout for sky130 (no longer s8) by mrg · 5 years ago
- b5d5f70 Updates...many DRC, no LVS. by mrg · 5 years ago
- 29aba2a Updated ram by mrg · 5 years ago
- 6f1299a Update with better nonfunctional layout by mrg · 5 years ago
- 28f3391 Nonfunctional memory example in s8. No power routes, incmoplete. by mrg · 5 years ago
- 98cce76 Add demo RAM by mrg · 5 years ago
- 3dba69a Remove cell multiple options by mrg · 5 years ago
- 01450ed Merge branch 'master' of github.com:VLSIDA/skywater-tech by mrg · 5 years ago
- 3c88619 Add M5 and stack indices. by mrg · 5 years ago
- e419a1c track 1rw_1r cell by jcirimel · 5 years ago
- 17b2196 Merge branch 'master' of github.com:VLSIDA/skywater-tech by Joey Kunzler · 5 years ago
- 44078af dff update for dff_buf by Joey Kunzler · 5 years ago
- 83e0d3a merge discrete into master by jcirimel · 5 years ago
- af82b25 add bin accuracy parameter to tech by jcirimel · 5 years ago
- be2630e dff Q pin moved for dff_buf drc by Joey Kunzler · 5 years ago
- 8146564 updated writedriver and senseamp with discrete sizes by Joey Kunzler · 5 years ago
- a50efcb Add bounding box to write driver by mrg · 5 years ago
- d8cf9f8 Merge branch 'master' of github.com:VLSIDA/skywater-tech by mrg · 5 years ago
- a247490 Remove jog from write driver cell by mrg · 5 years ago
- 5627e2c Merge branch 'master' of github.com:VLSIDA/skywater-tech by Joey Kunzler · 5 years ago
- 36ed8be dff updated for dff_buf by Joey Kunzler · 5 years ago
- 053593b Merge branch 'master' of github.com:VLSIDA/skywater-tech by mrg · 5 years ago
- 5ac34db Ad RISC-V memories configs. by mrg · 5 years ago
- 43dc7e8 Add bitcell multiple option. by mrg · 5 years ago
- 7030e80 provisional dff with discrete sizes by Joey Kunzler · 5 years ago
- d8d05b7 update library for discrete tx models by jcirimel · 5 years ago
- 4d8264a Merge branch 'master' of https://github.com/VLSIDA/skywater-tech by jcirimel · 5 years ago
- e0a20a6 add support for discreete models by jcirimel · 5 years ago
- ec551b3 dff gds and lvs fix by Joey Kunzler · 5 years ago
- acc349e write driver update for mask test by Joey Kunzler · 5 years ago
- 548ddd8 dff gds change for overlapping vdd/gnd pins by Joey Kunzler · 5 years ago
- 96cb348 added border to dff and removed duplicate pins from magic by Joey Kunzler · 5 years ago
- 794f55a dff pin fix by Joey Kunzler · 5 years ago
- e48702d Add correctly scaled dff by mrg · 5 years ago
- 7724c77 Merge branch 'master' of github.com:VLSIDA/skywater-tech by mrg · 5 years ago
- 7d784a3 Re-add bitcells in both sp_lib and lvs_lib by mrg · 5 years ago
- f313b84 add sp_lib bitcells, bring dff pins to m2 in gds by Jesse Cirimelli-Low · 5 years ago
- 4eb4f80 Merge branch 'master' of github.com:VLSIDA/skywater-tech by mrg · 5 years ago
- e072d9e Add LVS lib by mrg · 5 years ago
- 6a62002 fix typo in comment by Jesse Cirimelli-Low · 5 years ago
- ec3ed56 update s8 spice model paths with environment variables by Jesse Cirimelli-Low · 5 years ago
- 948128c Separate lvs_lib and sp_lib by mrg · 5 years ago
- 90d48fc updated sense_amp and write_driver: gds, mag, spice by Joey Kunzler · 5 years ago
- 9f4e02c Rename top level cell in dff to dff instead of dff_new by mrg · 5 years ago
- c0f7659 Merge branch 'master' of github.com:VLSIDA/skywater-tech by mrg · 5 years ago
- ae093de Add NA spacing rule by mrg · 5 years ago
- 5719f11 Update circuit model names in setup.tcl by mrg · 5 years ago
- d712f13 Remove trigate temporarily by mrg · 5 years ago
- bf55027 fix bitcell parasitic tx by Jesse Cirimelli-Low · 5 years ago
- ae18f7e update sense_amp and write_driver layout by Joey Kunzler · 5 years ago
- dba9e0b update sense amp spice to extracted, update write driver spice to scmos by Jesse Cirimelli-Low · 5 years ago
- 6590967 Merge branch 'master' of https://github.com/VLSIDA/skywater-tech by Jesse Cirimelli-Low · 5 years ago
- bc10b57 update write driver to extracted by Jesse Cirimelli-Low · 5 years ago
- c08d4f6 update dff caps to match new dff by Jesse Cirimelli-Low · 5 years ago
- 287bc03 Merge branch 'master' of github.com:VLSIDA/skywater-tech by mrg · 5 years ago
- cb93b7a Fix mcon width and add setup.tcl by mrg · 5 years ago
- 5cc0d20 fixed vdd label by Joey Kunzler · 5 years ago
- 223b7fb update sense_amp & wordline driver, gds & mag by Joey Kunzler · 6 years ago
- 7d13186 add write_driver.mag (untested) by Joey Kunzler · 6 years ago
- f339fd0 corrected sense amp gds scale by Joey Kunzler · 6 years ago
- b5b6ac2 replace Qbar with vdd in replica bitcell by Jesse Cirimelli-Low · 6 years ago
- 96e4b13 update bitcell models for all corners by jcirimel · 6 years ago
- 920c986 add spice variables for bitcell by jcirimel · 6 years ago
- 040b25a use correct bitcell sizing, use bitcell tx models by Jesse Cirimelli-Low · 6 years ago
- 78abe3e remove dff parameters by jcirimel · 6 years ago
- 7ee723d adjust bitcell sizing by Jesse Cirimelli-Low · 6 years ago
- 68e50e5 resolve bitcell merge conflicts by Jesse Cirimelli-Low · 6 years ago
- 01b1e40 scale bitcell to fit within model constraints by Jesse Cirimelli-Low · 6 years ago
- 19b7295 remove dff optional parameters, bring dff pins to m2 by Jesse Cirimelli-Low · 6 years ago
- 5277a0a dummy/replica layout update by Joey Kunzler · 6 years ago
- 694d2ed Added dummy and replica bitcells, small edit to tech.py by Joey Kunzler · 6 years ago
- ffc69c7 connect taps by Joey Kunzler · 6 years ago
- 63757fe Merge branch 's8_layout' by Joey Kunzler · 6 years ago
- f0acda3 moved cell_6t vias, added cell property to techfile by Joey Kunzler · 6 years ago
- 6d46ada update dff gds by Jesse Cirimelli-Low · 6 years ago
- 30b01c3 update to X2 dff by Jesse Cirimelli-Low · 6 years ago
- 0f9c528 via location change by Joey Kunzler · 6 years ago
- 7632f22 Switch calibre falg to a boolean by mrg · 6 years ago
- 35deebe Switch calibre falg to a boolean by mrg · 6 years ago
- 876fa23 via drc fix by Joey Kunzler · 6 years ago
- 4185b13 worldlines on m2 by Joey Kunzler · 6 years ago
- 1f91634 connect bitcell wl, unconnect dummy bl, replace sub Qbar with vdd replica bl by Jesse Cirimelli-Low · 6 years ago
- 8b04695 updated bitcell to include taps and single wordline by Joey Kunzler · 6 years ago
- a325bd9 update dff spice with sa sb ds, set nominal voltage to 1.8, change voltage corners by Jesse Cirimelli-Low · 6 years ago
- 297068d tie vpb and vnb to gnd and vdd; force tx sizes to fit in model bin by Jesse Cirimelli-Low · 6 years ago
- 40c009e Merge branch 'master' of https://github.com/VLSIDA/skywater-tech by Jesse Cirimelli-Low · 6 years ago
- da8ebc4 update dff to pass drc by Jesse Cirimelli-Low · 6 years ago
- 81786b1 Merge branch 'master' of github.com:VLSIDA/skywater-tech by mrg · 6 years ago
- 6383eaa update tech.py to work with merged property files by Jesse Cirimelli-Low · 6 years ago
- cee3c0d scale spice library by jcirimel · 6 years ago
- 084d157 Merge branch 'master' of github.com:VLSIDA/skywater-tech by mrg · 6 years ago
- 20e0d76 support new custom modules by jcirimel · 6 years ago
- e3dc11e add placeholder spice files and update tech.py for custom modules by jcirimel · 6 years ago
- bdbe3a6 update sense_amp gds labels, update sense_amp spice file labels by jcirimel · 6 years ago
- 5f4247a add bounding layer to sense amp gds by jcirimel · 6 years ago
- 157f502 add proper header to sense_amp.sp by jcirimel · 6 years ago
- 85ff30c Update design rules. by mrg · 6 years ago
- 110ddae bring dff pins to m2 by jcirimel · 6 years ago
- f41e088 Merge branch 'master' of https://github.com/VLSIDA/skywater-tech by jcirimel · 6 years ago
