add SOFA-Plus GDS, LEF and DEF macro files
8 files changed
tree: c866a7261b8ae3f2e5135d9432db57755bc5064a
  1. SOFA_CHD/
  2. SOFA_HD/
  3. SOFA_PLUS_HD/
  4. SOFA_QLHD/
  5. README.md
README.md

OpenFPGA ready-to-use Macros

This repository provide the following GDS-ready eFPGA IPs using OpenFPGA prototyping tool.

Available FPGA Macros

  • SOFA_CHD: Skywater Open-source FPGA (SOFA) - Custom High-Density Design

    • Open-source 12x12 FPGA with adapted QuickLogic' soft-adder CLB architecture (documentation, github)
    • Designed with Skywater130nm PDK with HD standard cell library + Custom Transmission Gate Cells
    • Base K4 architecture from VPR with 60 vertical and horizontal channels
    • Fabricated with eFabless Open-MPW shuttle program (mpw-one/slot-039)
  • SOFA_HD: Skywater Open-source FPGA (SOFA) - High-Density Design

    • Open-source 12x12 FPGA (documentation, github)
    • Designed with Skywater130nm PDK with HD standard cell library
    • Base K4 architecture from VPR with 40 vertical and horizontal channels
    • No adders (carry-chain) or flipflop reset pins
    • Fabricated with eFabless Open-MPW shuttle program (mpw-one/slot-017)
  • SOFA_PLUS_HD: Skywater Open-source FPGA (SOFA) - Second version of SOFA with enhanced DSP features

    • Open-source 12x12 FPGA (github)
    • Designed with Skywater130nm PDK with HD standard cell library
    • Enhanced DSP features (18x18 fracturable multipliers)
    • Fabricated with eFabless Open-MPW shuttle program (mpw-two/slot-021)
  • SOFA_QLHD: Skywater Open-source FPGA (SOFA) - QuickLogic' soft-adder High-Density Design

    • Open-source 12x12 FPGA with adapted QuickLogic' soft-adder CLB architecture (documentation, github)
    • Designed with Skywater130nm PDK with HD standard cell library
    • Base K4 architecture from VPR with 60 vertical and horizontal channels
    • Fabricated with eFabless Open-MPW shuttle program (mpw-one/slot-036)