notes.md

### SVRF statments for opensta friendly spef

```
LAYOUT CASE YES
LAYOUT PRESERVE NET CASE YES
SOURCE CASE YES
 
PEX REDUCE ANALOG NO
PEX NETLIST UPPERCASE KEYWORDS NO
PEX NETLIST VIRTUAL CONNECT NO
PEX NETLIST NOXREF NET NAMES YES
PEX NETLIST MUTUAL RESISTANCE YES
PEX NETLIST ESCAPE CHARACTERS "!@#$%^&*()+{}|\:;’‘<>?/.,-=[]"
PEX EXTRACT EXCLUDE LAYOUTNAMES RECURSIVE "?VGND?"
PEX EXTRACT EXCLUDE LAYOUTNAMES RECURSIVE "?VPWR?"
PEX EXTRACT EXCLUDE LAYOUTNAMES RECURSIVE "?VPB?"
PEX EXTRACT EXCLUDE LAYOUTNAMES RECURSIVE "?VNB?"
PEX NETLIST "$JOB_HOME/spef/$PEX_NETLIST" SPEF PRIMETIME SOURCENAMES
```

### Notes

- avoid gds views in caravel. most of the time they are outdated. use magic instead
- `SOURCE CASE YES` is needed to preserve the case of source nets
- Some escaped square brackets cause issues with opensta:
    - this casues an issue:
    > div\[4\]
    - also this causes an issue:
    > ringosc.dstage[3].id.delayen0
    
    to be investigated..
    
    - turns out the in the verilog netlist we have things like
    > \ringosc.dstage[3].id.delayen0

    this means that the everything following the backslash is escaped.
    and in turn the square brackets don't actually refer to buses.
    everything following the backslash is escaped into, let's call it static variable name

    calibre verilog to spice tool, `vlog2lvs`, doesn't escape special characters in these static variable names
    escaping characters happen in the end during `calibre -xrc -fmt` step
    if we told calibre to escape square brackets, actual buses would be esacped, which isn't something we desire
    the workaround is as follows:
        - set bus delimeter to `<>` using `vlog2lvs -a "<>"` 
        - replace square brackets in the spice netlist with backlash-escaped square brackets
        - replace bus delimeter `<>` with non-backslash-escaped square brackets

- we don't need power connections so we exclude them
- some of the above statments may not be needed. the inclusion of every single statment is not fully tested.

- `LAYOUT RENAME TEXT "/div/RENAMED/"` replaces div with RENAMED
    - now we need to find the equivelent source statment

- `LVS BOX sky130_fd_sc_hvl__lsbufhv2lv_1 SOURCE` eliminates 

    ```
    1    M0(3.975,0.755)  MN(nshort)                               MI29  MN(nfet_01v8)
            bad component subtype
    ```

    in `mgmt_protect_hv`

- substrate cut layer reported in gpio_control_block `Dpar(reslocsub)`
    - use `LVS FILTER` to eliminate

- `mgmt_protect_hv` verilog (source) view is missing three fill cells

- `mgmt_protect_hv` met2 and met3 wrong pin layers. They are swapped with pin label?

- `gpio_control_block` manually add substrateCut layer to separate gpio_logic_high

- in `caravel` top level ports `flash_clk_ieb_core` and `flash_csb_ieb_core` are connected to nets which aren't connected to anything so remove them from `chip_io` verilog model and in the instance in `caravel`