//# -*- c++ -*-
//# xControlFile
//# Copyright (c) 2017 by Cypress Semiconductor
//# Cypress Confidential Information
//#
#DEFINE PEX
UNIT CAPACITANCE ff
TEXT DEPTH PRIMARY
PORT DEPTH PRIMARY
INCLUDE $PDK_HOME/PEX/xRC/cap_models


VARIABLE JOB_NAME ENVIRONMENT

LAYOUT PATH  "$JOB_HOME/gds/$LAYOUT_NAME"
LAYOUT PRIMARY JOB_NAME
LAYOUT SYSTEM GDSII

LVS REPORT "$JOB_HOME/lvs/$LVS_REPORT"

MASK SVDB DIRECTORY "$JOB_HOME/svdb" QUERY XRC CCI NOPINLOC IXF NXF SLPH


// PEX NETLIST "$JOB_HOME/pex/$PEX_NETLIST" SPEF SOURCENAMES

PEX NETLIST "$JOB_HOME/spef/$PEX_NETLIST" SPEF PRIMETIME SOURCENAMES
//PEX NETLIST "$TEST_DIR/torture_tests/$JOB_NAME/pex/$PEX_NETLIST" HSPICE 1 SOURCENAMES
//PEX NETLIST "$TEST_DIR/torture_tests/$JOB_NAME/pex/$PEX_NETLIST" HSPICE 1 SOURCENAMES RLOCATION RWIDTH RLENGTH RLAYER RTHICKNESS RACTUAL RVIACOUNT CLOCATION
 
//
//
//
// Filter Devices in include file to give LVS & xRC consistency
/////// INCLUDE $PDK_HOME/LVS/Calibre/s8_filter_devices

LVS FILTER R(cds_thru) SHORT SOURCE
LVS FILTER R(cds_thru) SHORT LAYOUT

// LVS FILTER D		              		OPEN  LAYOUT
// LVS FILTER Dpar                    		OPEN  SOURCE
// LVS FILTER Dpar                    		OPEN  LAYOUT
// LVS FILTER Dpar(DNWDIODE_PW)       		OPEN  SOURCE
// LVS FILTER Dpar(DNWDIODE_PW)       		OPEN  LAYOUT

//LVS FILTER Dpar(NWDIODE)            		OPEN  SOURCE
LVS FILTER Dpar(NWDIODE)              		OPEN  LAYOUT

// LVS FILTER Dpar(DIODE_PW2ND_05V5)  		OPEN  SOURCE
LVS FILTER D(DIODE_PW2ND_05V5)        		OPEN  LAYOUT

// LVS FILTER D(NDIODE)               		OPEN  SOURCE
// LVS FILTER D(NDIODE)               		OPEN  LAYOUT

//LVS FILTER sky130_fd_sc_hd__diode_2   	OPEN  SOURCE

//LVS FILTER sky130_fd_sc_hd__tapvpwrvgnd_1 	OPEN  LAYOUT
//LVS FILTER sky130_fd_sc_hd__tapvpwrvgnd_1 	OPEN  SOURCE
//LVS FILTER sky130_fd_sc_hd__fill_1        	OPEN  LAYOUT
//LVS FILTER sky130_fd_sc_hd__fill_1        	OPEN  SOURCE
//LVS FILTER sky130_fd_sc_hd__fill_2        	OPEN  LAYOUT
//LVS FILTER sky130_fd_sc_hd__fill_2        	OPEN  SOURCE

LVS FILTER Probe                    		OPEN  SOURCE
LVS FILTER Probe                   		OPEN  LAYOUT
LVS Filter icecap 				open source
LVS Filter s8fmlt_iref_termx  			open source
LVS Filter s8fmlt_neg_termx   			open source
LVS Filter s8fmlt_termx       			open source
LVS Filter s8fmlt_vdac_termx  			open source

//# diff/tap devices
LVS FILTER diff_dev                		OPEN  SOURCE
LVS FILTER diff_dev                		OPEN  LAYOUT
// LVS FILTER tap_dev                 		OPEN  SOURCE
// LVS FILTER tap_dev                 		OPEN  LAYOUT

//# dummy device to prevent empty cells from becoming subckt primitives
LVS FILTER cad_dummy_open_device   OPEN  SOURCE
LVS FILTER cad_dummy_open_device   OPEN  LAYOUT

//# Look further
LVS SIGNATURE MAXIMUM              ALL

//# Be thorough in resolving ambiguity
LVS PROPERTY RESOLUTION MAXIMUM    ALL

//# Interpret devices and arguments strictly
LVS STRICT    SUBTYPES             YES
LVS SPICE     STRICT WL            YES
LVS SPICE     SLASH IS SPACE       NO
LVS COMPARE   CASE                 NO

//# allows exact m-factor comparison
LVS SPICE     REPLICATE  DEVICES   YES

//# Should help out in making an IP spice/verilog
//# flow accurate and strict.
LVS SPICE     PREFER     PINS      YES
LVS SPICE     OVERRIDE   GLOBALS   YES
LVS SPICE     REDEFINE   PARAM     YES
LVS SPICE ALLOW INLINE PARAMETERS  NO

//# expanding would flatten most cells during comparison
LVS EXPAND    SEED   PROMOTIONS    NO
LVS DISCARD   PINS   BY DEVICE    YES

//# Cypress methodology will require setting this on a per-model basis
//# using LVS REDUCE component(model)
LVS REDUCE PARALLEL RESISTORS      NO
LVS REDUCE SERIES   RESISTORS      NO
LVS REDUCE PARALLEL CAPACITORS     NO
LVS REDUCE SERIES   CAPACITORS     NO
//////
LVS REDUCE PARALLEL DIODES         NO
LVS REDUCE PARALLEL BIPOLAR        NO
LVS REDUCE PARALLEL MOS            YES
LVS REDUCE SERIES   MOS            NO

//# Allows recoginition of logic gates.  Should be NONE for good dspf.
LVS RECOGNIZE GATES                NONE
LVS IGNORE PORTS                   NO
LVS CHECK  PORT   NAMES            YES

//# Don't use these nets as initial bind points (convenience)
//# n<number>
LVS NON USER NAME NET "^n[0-9]*$"

//# net<number>
LVS NON USER NAME NET "^net[0-9]*$"

//# This gets disabled anyway because we have
//# MASK SVDB DIRECTORY "$PDK_HOME/PEX/xRC/svdb" QUERY XRC
//# By forcibly disabling it, we turn off a warning
LVS PUSH     DEVICES               NO
LVS EXECUTE ERC YES
ERC RESULTS DATABASE "erc.db" ASCII
ERC CELL NAME YES ALL CELL SPACE XFORM

//# For now, RFI is needed for xErrorSum. Will eventually change.
ERC CHECK TEXT COMMENTS RFI
ERC SUMMARY REPORT "erc.rep"
//MASK SVDB DIRECTORY "$PDK_HOME/PEX/xRC/svdb" QUERY XRC
// LVS REPORT "lvs.rep"

//# report detailed SCONNECT conflicts
LVS REPORT OPTION S

//# disable warning about missing smashed mosfets
LVS REPORT OPTION F

//# give report on source passthroughs, same as layout does by default
LVS REPORT OPTION SP

//# maximum short isolation
LVS ISOLATE SHORTS YES BY LAYER CELL ALL

//# while the training on this seems safe enough, the documentation still
//# makes it sound like the nets get connected regardless of VIRTUAL CONNECT NAME,
//# so I will not use this directly
//#VIRTUAL CONNECT COLON YES
//# I think this is a little safer, and exactly what assura seems to do.  I know
//# this will not connect the disjoint labels without VIRTUAL CONNECT NAME
LAYOUT RENAME TEXT "/:.*//"

//# go ahead and report if nets are virtually connected
VIRTUAL CONNECT REPORT YES


PEX REDUCE ANALOG NO
PEX NETLIST UPPERCASE KEYWORDS YES
PEX NETLIST VIRTUAL CONNECT NO
PEX NETLIST NOXREF NET NAMES YES
PEX NETLIST MUTUAL RESISTANCE YES
PEX NETLIST ESCAPE CHARACTERS "!@#$%^&*()+{}|\:;’‘<>?/.,-=[]"
PEX EXTRACT EXCLUDE LAYOUTNAMES RECURSIVE "?VGND?"
PEX EXTRACT EXCLUDE LAYOUTNAMES RECURSIVE "?VPWR?"
PEX EXTRACT EXCLUDE LAYOUTNAMES RECURSIVE "?VPB?"
PEX EXTRACT EXCLUDE LAYOUTNAMES RECURSIVE "?VNB?"
LAYOUT CASE YES
LAYOUT PRESERVE NET CASE YES
LVS REPORT OPTION NONE
LVS FILTER UNUSED OPTION NONE SOURCE
LVS FILTER UNUSED OPTION NONE LAYOUT
LVS RECOGNIZE GATES ALL

VIRTUAL CONNECT COLON NO
// VIRTUAL CONNECT REPORT NO

DRC ICSTATION YES

//# include the technology rules
//INCLUDE "/data/pdks/skywater/s8/V1.3.0/PEX/xRC/xrcControlFile_s8"
//INCLUDE "$PDK_HOME/PEX/xRC/extLvsRules_s8_5lm"

INCLUDE "$TEST_DIR/pdk/skywater/s8/V2.0.1/PEX/extLvsRules_s8_5lm_s130-names"

//# -join
VIRTUAL CONNECT NAME "?"

//# Expand Pcells
EXPAND CELL "*$$*"
//   LVS DEVICE TYPE                        MP "SKY130_FD_PR__PFET_01V8" SOURCE LAYOUT

//LVS MAP DEVICE MP(pfet_g5v0d10v5) MP(phv) SOURCE LAYOUT
//LVS MAP DEVICE MN(NFET_G5V0D10V5) MN(nhv) SOURCE LAYOUT


INCLUDE "$TEST_DIR/runsets/bbox.sky130_fd_sc_hd.txt"

LVS BOX sky130_sram_2kbyte_1rw1r_32x512_8    LAYOUT
LVS BOX sky130_sram_2kbyte_1rw1r_32x512_8    SOURCE


//LVS BOX mgmt_protect_hv LAYOUT
//LVS BOX mgmt_protect_hv SOURCE


// LVS GROUND NAME VSSD1 VSSD