diff --git a/docs/cells b/docs/cells
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--- /dev/null
+++ b/docs/cells
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+../cells
\ No newline at end of file
diff --git a/docs/index.rst b/docs/index.rst
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+++ b/docs/index.rst
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+
+**********************
+9 track Standard Cells
+**********************
+
+.. toctree::
+    :maxdepth: 1
+    :glob:
+
+    setup
+    symbols
+
+    spec/physical
+    spec/electrical
+    spec/transitions
+    spec/corners
+
+    cells/*/*
diff --git a/docs/setup.rst b/docs/setup.rst
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+++ b/docs/setup.rst
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+================================
+5V Databook Setup and Conditions
+================================
+
+
++-----------------------------+
+| **Process Corner:** Typical |
++-----------------------------+
+| **Voltage:** 5.00 volt      |
++-----------------------------+
+| **Temperature:** 25.0 °C    |
++-----------------------------+
+
diff --git a/docs/spec/corners.rst b/docs/spec/corners.rst
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index 0000000..520c2fe
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+++ b/docs/spec/corners.rst
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+=============================
+PVT Characterization Corners
+=============================
+
+=========== =============== =============== ==========
+**Process** **Temperature** **VDD Voltage** **PEX**
+SS          -40°C           4.5V            Worst RC
+SS          125°C           4.5V            Worst RC
+TT          25°C            5.0V            Typical RC
+FF          -40°C           5.5V            Best RC
+FF          125°C           5.5V            Best RC
+SS          -40°C           3.0V            Worst RC
+SS          125°C           3.0V            Worst RC
+TT          25°C            3.3V            Typical RC
+FF          -40°C           3.6V            Best RC
+FF          125°C           3.6V            Best RC
+SS          -40°C           1.62V           Worst RC
+SS          125°C           1.62V           Worst RC
+TT          25°C            1.8V            Typical RC
+FF          -40°C           1.98V           Best RC
+FF          125°C           1.98V           Best RC
+=========== =============== =============== ==========
+
diff --git a/docs/spec/electrical.rst b/docs/spec/electrical.rst
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index 0000000..666b563
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+++ b/docs/spec/electrical.rst
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+==========================
+Electrical Specifications
+==========================
+
+===================== =================
+Operating Voltage     VDD = 1.62 - 5.5V
+Operation Temperature -40°C to 125°C
+===================== =================
diff --git a/docs/spec/physical.rst b/docs/spec/physical.rst
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index 0000000..c2e4c65
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+++ b/docs/spec/physical.rst
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+========================
+Physical Specifications
+========================
+
+================================= =================
+Process Scheme (#Poly/#Metal)     1P1M
+Device Type                       5V NMOS & 5V PMOS
+Drawn Gate Length PMOS/NMOS(um)   0.50/0.60
+Layer of Poly                     1
+Well Option                       Outside DNWELL
+Layer Grid (um)                   0.005
+Tracks per Cell                   9
+Cell Height (um)                  5.04
+Vertical/Horizontal Pin Grid (um) 0.56
+================================= =================
diff --git a/docs/spec/transitions.rst b/docs/spec/transitions.rst
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index 0000000..9ed1e56
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+++ b/docs/spec/transitions.rst
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+===================
+Maximum Transition
+===================
+
+Lesser of 20% clock period or recommended value below
+
+=========== =============== =============== ==================
+**Process** **Temperature** **VDD Voltage** **Max Transition**
+SS          -40°C           4.5V            1.30ns
+SS          125°C           4.5V            1.80ns
+TT          25°C            5.0V            1.00ns
+FF          -40°C           5.5V            0.70ns
+FF          125°C           5.5V            0.90ns
+SS          -40°C           3.0V            2.00ns
+SS          125°C           3.0V            2.80ns
+TT          25°C            3.3V            1.50ns
+FF          -40°C           3.6V            0.95ns
+FF          125°C           3.6V            1.30ns
+SS          -40°C           1.62V           4.25ns
+SS          125°C           1.62V           5.00ns
+TT          25°C            1.8V            3.00ns
+FF          -40°C           1.98V           1.50ns
+FF          125°C           1.98V           2.10ns
+=========== =============== =============== ==================
+
diff --git a/docs/symbols.rst b/docs/symbols.rst
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index 0000000..bb77bc9
--- /dev/null
+++ b/docs/symbols.rst
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+=========================
+Reading Databook Symbols
+=========================
+
+========== ================================
+**Symbol** **Definition**
+0          Logic Low
+1          Logic High
+HL         High to Low Transition
+LH         Low to High Transition
+↑          Positive Clock Edge
+↓          Negative Clock edge
+Tin        Input Transition 30 to70 %
+Delay      50 to 50%
+Tout       Output Transition 30 to 70%
+?          Don't Care (Combinatorial Cells)
+X          Don't Care (Sequential Cells)
+default    No “when” condition for Input
+n/a        No Transition
+========== ================================