| { | |
| "cell gf180mcu_fd_sc_mcu9t5v0__aoi21_1": { | |
| "area": "22.579200", | |
| "leakage_power ": [ | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "!A1&!A2&!B", | |
| "value": "0.00043335" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "!A1&!A2&B", | |
| "value": "0.0004446" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "!A1&A2&!B", | |
| "value": "0.00043908" | |
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| { | |
| "related_pg_pin": "VDD", | |
| "when": "!A1&A2&B", | |
| "value": "0.00044529" | |
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| { | |
| "related_pg_pin": "VDD", | |
| "when": "A1&!A2&!B", | |
| "value": "0.00045111" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "A1&!A2&B", | |
| "value": "0.00044529" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "A1&A2&!B", | |
| "value": "0.00042636" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "when": "A1&A2&B", | |
| "value": "0.00042627" | |
| }, | |
| { | |
| "related_pg_pin": "VDD", | |
| "value": "0.00045111" | |
| } | |
| ], | |
| "pg_pin VDD": { | |
| "voltage_name": "VDD", | |
| "pg_type": "primary_power" | |
| }, | |
| "pg_pin VSS": { | |
| "voltage_name": "VSS", | |
| "pg_type": "primary_ground" | |
| }, | |
| "pin A1": { | |
| "capacitance": "0.007152", | |
| "direction": "input", | |
| "driver_waveform_rise": "driver_waveform_default_rise", | |
| "driver_waveform_fall": "driver_waveform_default_fall", | |
| "input_voltage": "default", | |
| "max_transition": "13.2", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
| "internal_power ": [ | |
| { | |
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| "rise_power pwr_tin_10": { | |
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| }, | |
| { | |
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| }, | |
| { | |
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| }, | |
| "rise_power pwr_tin_10": { | |
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| } | |
| } | |
| ] | |
| }, | |
| "pin A2": { | |
| "capacitance": "0.006798", | |
| "direction": "input", | |
| "driver_waveform_rise": "driver_waveform_default_rise", | |
| "driver_waveform_fall": "driver_waveform_default_fall", | |
| "input_voltage": "default", | |
| "max_transition": "13.2", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
| "internal_power ": [ | |
| { | |
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| 7.287, | |
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| ], | |
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| 0.02067 | |
| ] | |
| }, | |
| "rise_power pwr_tin_10": { | |
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| } | |
| }, | |
| { | |
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| "fall_power pwr_tin_10": { | |
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| 0.006645, | |
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| "rise_power pwr_tin_10": { | |
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| }, | |
| { | |
| "when": "A1&B", | |
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| "rise_power pwr_tin_10": { | |
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| } | |
| ] | |
| }, | |
| "pin B": { | |
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| "direction": "input", | |
| "driver_waveform_rise": "driver_waveform_default_rise", | |
| "driver_waveform_fall": "driver_waveform_default_fall", | |
| "input_voltage": "default", | |
| "max_transition": "13.2", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
| "internal_power ": { | |
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| "rise_power pwr_tin_10": { | |
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| } | |
| } | |
| }, | |
| "pin ZN": { | |
| "direction": "output", | |
| "function": "(((!A1)&(!B))|((!A2)&(!B)))", | |
| "max_capacitance": "0.2225", | |
| "max_transition": "13.2", | |
| "min_capacitance": "0.001", | |
| "output_voltage": "default", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
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| { | |
| "related_pin": "A1", | |
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| }, | |
| "rise_power pwr_tin_oload_10x10": { | |
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| ] | |
| } | |
| }, | |
| { | |
| "related_pin": "A2", | |
| "when": "A1&!B", | |
| "fall_power pwr_tin_oload_10x10": { | |
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| [ | |
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| { | |
| "related_pin": "B", | |
| "sdf_cond": "A1===1'b0 && A2===1'b0", | |
| "timing_sense": "negative_unate", | |
| "timing_type": "combinational", | |
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| "fall_transition tmg_ntin_oload_10x10": { | |
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