Merge pull request #8 from mabrains/definition_json
Adding definition.json files
diff --git a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_1.cdl b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_1.cdl
index 24bb3b8..1da239c 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_1.cdl
+++ b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_1.cdl
@@ -15,32 +15,32 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__addf_1 A B CI CO S VDD VNW VPW VSS
*.PININFO A:I B:I CI:I CO:O S:O VDD:P VNW:P VPW:P VSS:G
*.EQN CO=(((B * CI) + (B * A)) + (CI * A));S=!((!((B * CI) + !(B + CI)) * A) + !(!((B * CI) + !(B + CI)) + A))
-M_M51 VSS net9 S VPW nmos_5p0 W=1.180000U L=0.600000U
-M_M50 net49 A VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M48 net47 B net49 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M46 net9 CI net47 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M41 net9 net7 net42 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M43 net42 A VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M44 VSS B net42 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M45 net42 CI VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M40 VSS B net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M39 net5 A VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M38 net7 CI net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M37 net36 B net7 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M35 VSS A net36 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_M34 CO net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M33 VDD net9 S VNW pmos_5p0 W=1.830000U L=0.500000U
-M_M32 net31 A VDD VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M30 net29 B net31 VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M28 net9 CI net29 VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M24 net9 net7 net3 VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M25 net3 A VDD VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M26 VDD B net3 VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M27 net3 CI VDD VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M23 VDD B net1 VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M22 net1 A VDD VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M21 net7 CI net1 VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M20 net19 B net7 VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M18 VDD A net19 VNW pmos_5p0 W=0.990000U L=0.500000U
-M_M17 CO net7 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_M51 VSS net9 S VPW nfet_05v0 W=1.180000U L=0.600000U
+M_M50 net49 A VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M48 net47 B net49 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M46 net9 CI net47 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M41 net9 net7 net42 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M43 net42 A VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M44 VSS B net42 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M45 net42 CI VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M40 VSS B net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M39 net5 A VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M38 net7 CI net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M37 net36 B net7 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M35 VSS A net36 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_M34 CO net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M33 VDD net9 S VNW pfet_05v0 W=1.830000U L=0.500000U
+M_M32 net31 A VDD VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M30 net29 B net31 VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M28 net9 CI net29 VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M24 net9 net7 net3 VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M25 net3 A VDD VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M26 VDD B net3 VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M27 net3 CI VDD VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M23 VDD B net1 VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M22 net1 A VDD VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M21 net7 CI net1 VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M20 net19 B net7 VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M18 VDD A net19 VNW pfet_05v0 W=0.990000U L=0.500000U
+M_M17 CO net7 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.cdl b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.cdl
index da90273..2529a05 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.cdl
+++ b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.cdl
@@ -15,36 +15,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__addf_2 A B CI CO S VDD VNW VPW VSS
*.PININFO A:I B:I CI:I CO:O S:O VDD:P VNW:P VPW:P VSS:G
*.EQN CO=(((B * CI) + (B * A)) + (CI * A));S=!((!((B * CI) + !(B + CI)) * A) + !(!((B * CI) + !(B + CI)) + A))
-M_M51_17 VSS net9 S VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M51 VSS net9 S VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M50 net49 A VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M48 net47 B net49 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M46 net9 CI net47 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M41 net9 net7 net42 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M43 net42 A VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M44 VSS B net42 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M45 net42 CI VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M40 VSS B net5 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M39 net5 A VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M38 net7 CI net5 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M37 net36 B net7 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M35 VSS A net36 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M34 CO net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M34_25 CO net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M33_12 VDD net9 S VNW pmos_5p0 W=1.800000U L=0.500000U
-M_M33 VDD net9 S VNW pmos_5p0 W=1.800000U L=0.500000U
-M_M32 net31 A VDD VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M30 net29 B net31 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M28 net9 CI net29 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M24 net9 net7 net3 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M25 net3 A VDD VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M26 VDD B net3 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M27 net3 CI VDD VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M23 VDD B net1 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M22 net1 A VDD VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M21 net7 CI net1 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M20 net19 B net7 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M18 VDD A net19 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M17 CO net7 VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_M17_23 CO net7 VDD VNW pmos_5p0 W=1.800000U L=0.500000U
+M_M51_17 VSS net9 S VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M51 VSS net9 S VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M50 net49 A VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M48 net47 B net49 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M46 net9 CI net47 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M41 net9 net7 net42 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M43 net42 A VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M44 VSS B net42 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M45 net42 CI VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M40 VSS B net5 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M39 net5 A VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M38 net7 CI net5 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M37 net36 B net7 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M35 VSS A net36 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M34 CO net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M34_25 CO net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M33_12 VDD net9 S VNW pfet_05v0 W=1.800000U L=0.500000U
+M_M33 VDD net9 S VNW pfet_05v0 W=1.800000U L=0.500000U
+M_M32 net31 A VDD VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M30 net29 B net31 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M28 net9 CI net29 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M24 net9 net7 net3 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M25 net3 A VDD VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M26 VDD B net3 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M27 net3 CI VDD VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M23 VDD B net1 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M22 net1 A VDD VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M21 net7 CI net1 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M20 net19 B net7 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M18 VDD A net19 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M17 CO net7 VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_M17_23 CO net7 VDD VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.cdl b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.cdl
index ba80579..b268b6a 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.cdl
+++ b/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.cdl
@@ -15,44 +15,44 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__addf_4 A B CI CO S VDD VNW VPW VSS
*.PININFO A:I B:I CI:I CO:O S:O VDD:P VNW:P VPW:P VSS:G
*.EQN CO=(((B * CI) + (B * A)) + (CI * A));S=!((!((B * CI) + !(B + CI)) * A) + !(!((B * CI) + !(B + CI)) + A))
-M_M51_17_0 VSS net9 S VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M51_18 VSS net9 S VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M51_17 VSS net9 S VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M51 VSS net9 S VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M50 net49 A VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M48 net47 B net49 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M46 net9 CI net47 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M41 net9 net7 net42 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M43 net42 A VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M44 VSS B net42 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M45 net42 CI VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M40 VSS B net5 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M39 net5 A VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M38 net7 CI net5 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M37 net36 B net7 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M35 VSS A net36 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_M34 CO net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M34_25 CO net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M34_53 CO net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M34_25_56 CO net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_M33_12_23 VDD net9 S VNW pmos_5p0 W=1.830000U L=0.500000U
-M_M33_34 VDD net9 S VNW pmos_5p0 W=1.830000U L=0.500000U
-M_M33_12 VDD net9 S VNW pmos_5p0 W=1.830000U L=0.500000U
-M_M33 VDD net9 S VNW pmos_5p0 W=1.830000U L=0.500000U
-M_M32 net31 A VDD VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M30 net29 B net31 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M28 net9 CI net29 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M24 net9 net7 net3 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M25 net3 A VDD VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M26 VDD B net3 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M27 net3 CI VDD VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M23 VDD B net1 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M22 net1 A VDD VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M21 net7 CI net1 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M20 net19 B net7 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M18 VDD A net19 VNW pmos_5p0 W=1.390000U L=0.500000U
-M_M17 CO net7 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_M17_23 CO net7 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_M17_66 CO net7 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_M17_23_46 CO net7 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_M51_17_0 VSS net9 S VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M51_18 VSS net9 S VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M51_17 VSS net9 S VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M51 VSS net9 S VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M50 net49 A VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M48 net47 B net49 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M46 net9 CI net47 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M41 net9 net7 net42 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M43 net42 A VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M44 VSS B net42 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M45 net42 CI VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M40 VSS B net5 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M39 net5 A VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M38 net7 CI net5 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M37 net36 B net7 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M35 VSS A net36 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_M34 CO net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M34_25 CO net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M34_53 CO net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M34_25_56 CO net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_M33_12_23 VDD net9 S VNW pfet_05v0 W=1.830000U L=0.500000U
+M_M33_34 VDD net9 S VNW pfet_05v0 W=1.830000U L=0.500000U
+M_M33_12 VDD net9 S VNW pfet_05v0 W=1.830000U L=0.500000U
+M_M33 VDD net9 S VNW pfet_05v0 W=1.830000U L=0.500000U
+M_M32 net31 A VDD VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M30 net29 B net31 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M28 net9 CI net29 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M24 net9 net7 net3 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M25 net3 A VDD VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M26 VDD B net3 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M27 net3 CI VDD VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M23 VDD B net1 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M22 net1 A VDD VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M21 net7 CI net1 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M20 net19 B net7 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M18 VDD A net19 VNW pfet_05v0 W=1.390000U L=0.500000U
+M_M17 CO net7 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_M17_23 CO net7 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_M17_66 CO net7 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_M17_23_46 CO net7 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.cdl b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.cdl
index c30a35e..46b6729 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.cdl
+++ b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.cdl
@@ -15,18 +15,18 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__addh_1 A B CO S VDD VNW VPW VSS
*.PININFO A:I B:I CO:O S:O VDD:P VNW:P VPW:P VSS:G
*.EQN CO=(A * B);S=!((A * B) + !(A + B))
-M_i_2 VSS NCO CO VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5 net_0 A VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_4 NCO B net_0 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_9 NS B net_1 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_8 net_1 A NS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_10 VSS NCO net_1 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0 S NS VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 VDD NCO CO VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7 NCO A VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_6 VDD B NCO VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_12 net_2 B VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_11 NS A net_2 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_13 VDD NCO NS VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_1 S NS VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 VSS NCO CO VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5 net_0 A VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_4 NCO B net_0 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_9 NS B net_1 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_8 net_1 A NS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_10 VSS NCO net_1 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0 S NS VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 VDD NCO CO VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7 NCO A VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_6 VDD B NCO VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_12 net_2 B VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_11 NS A net_2 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_13 VDD NCO NS VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_1 S NS VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_2.cdl b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_2.cdl
index 578acee..557091a 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_2.cdl
+++ b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_2.cdl
@@ -15,22 +15,22 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__addh_2 A B CO S VDD VNW VPW VSS
*.PININFO A:I B:I CO:O S:O VDD:P VNW:P VPW:P VSS:G
*.EQN CO=(A * B);S=!((A * B) + !(A + B))
-M_i_2_1 CO NCO VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 VSS NCO CO VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5 net_0 A VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4 NCO B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_9 NS B net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_8 net_1 A NS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_10 VSS NCO net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 S NS VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 VSS NS S VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 CO NCO VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0 VDD NCO CO VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7 NCO A VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 VDD B NCO VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_12 net_2 B VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11 NS A net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_13 VDD NCO NS VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 S NS VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 VDD NS S VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_1 CO NCO VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 VSS NCO CO VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5 net_0 A VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4 NCO B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_9 NS B net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_8 net_1 A NS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_10 VSS NCO net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 S NS VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 VSS NS S VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 CO NCO VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0 VDD NCO CO VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7 NCO A VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 VDD B NCO VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_12 net_2 B VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11 NS A net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_13 VDD NCO NS VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 S NS VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 VDD NS S VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_4.cdl b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_4.cdl
index e2285f7..fc2c37b 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_4.cdl
+++ b/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_4.cdl
@@ -15,40 +15,40 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__addh_4 A B CO S VDD VNW VPW VSS
*.PININFO A:I B:I CO:O S:O VDD:P VNW:P VPW:P VSS:G
*.EQN CO=(A * B);S=!((A * B) + !(A + B))
-M_i_5_1 net_0_0 A VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_1 NCO B net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_0 net_0_1 B NCO VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_0 VSS A net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_10_0 net_1 NCO VSS VPW nmos_5p0 W=0.880000U L=0.600000U
-M_i_8_0 NS A net_1 VPW nmos_5p0 W=0.880000U L=0.600000U
-M_i_9_0 net_1 B NS VPW nmos_5p0 W=0.880000U L=0.600000U
-M_i_9_1 NS B net_1 VPW nmos_5p0 W=0.880000U L=0.600000U
-M_i_8_1 net_1 A NS VPW nmos_5p0 W=0.880000U L=0.600000U
-M_i_10_1 VSS NCO net_1 VPW nmos_5p0 W=0.880000U L=0.600000U
-M_i_2_3 CO NCO VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 VSS NCO CO VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 CO NCO VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 VSS NCO CO VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 S NS VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 VSS NS S VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 S NS VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 VSS NS S VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7_1 NCO A VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 VDD B NCO VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 NCO B VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 VDD A NCO VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_13_0 NS NCO VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_0 net_2_0 A NS VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_12_0 VDD B net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_12_1 net_2_1 B VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_1 NS A net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_13_1 VDD NCO NS VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 CO NCO VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 VDD NCO CO VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 CO NCO VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0 VDD NCO CO VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 S NS VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 VDD NS S VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 S NS VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 VDD NS S VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_5_1 net_0_0 A VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_1 NCO B net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_0 net_0_1 B NCO VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_0 VSS A net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_10_0 net_1 NCO VSS VPW nfet_05v0 W=0.880000U L=0.600000U
+M_i_8_0 NS A net_1 VPW nfet_05v0 W=0.880000U L=0.600000U
+M_i_9_0 net_1 B NS VPW nfet_05v0 W=0.880000U L=0.600000U
+M_i_9_1 NS B net_1 VPW nfet_05v0 W=0.880000U L=0.600000U
+M_i_8_1 net_1 A NS VPW nfet_05v0 W=0.880000U L=0.600000U
+M_i_10_1 VSS NCO net_1 VPW nfet_05v0 W=0.880000U L=0.600000U
+M_i_2_3 CO NCO VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 VSS NCO CO VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 CO NCO VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 VSS NCO CO VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 S NS VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 VSS NS S VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 S NS VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 VSS NS S VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7_1 NCO A VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 VDD B NCO VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 NCO B VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 VDD A NCO VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_13_0 NS NCO VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_0 net_2_0 A NS VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_12_0 VDD B net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_12_1 net_2_1 B VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_1 NS A net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_13_1 VDD NCO NS VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 CO NCO VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 VDD NCO CO VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 CO NCO VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0 VDD NCO CO VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 S NS VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 VDD NS S VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 S NS VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 VDD NS S VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_1.cdl b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_1.cdl
index 76bb089..ffcc053 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_1.cdl
+++ b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_1.cdl
@@ -15,10 +15,10 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__and2_1 A1 A2 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(A1 * A2)
-M_i_2 net_0 A1 Z_neg VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_3 VSS A2 net_0 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4 Z_neg A1 VDD VNW pmos_5p0 W=0.820000U L=0.500000U
-M_i_5 VDD A2 Z_neg VNW pmos_5p0 W=0.820000U L=0.500000U
-M_i_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 net_0 A1 Z_neg VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_3 VSS A2 net_0 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4 Z_neg A1 VDD VNW pfet_05v0 W=0.820000U L=0.500000U
+M_i_5 VDD A2 Z_neg VNW pfet_05v0 W=0.820000U L=0.500000U
+M_i_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_2.cdl b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_2.cdl
index b987ca7..fc70dd3 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_2.cdl
+++ b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_2.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__and2_2 A1 A2 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(A1 * A2)
-M_i_2 net_0 A1 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 VSS A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4 Z_neg A1 VDD VNW pmos_5p0 W=1.640000U L=0.500000U
-M_i_5 VDD A2 Z_neg VNW pmos_5p0 W=1.640000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 net_0 A1 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 VSS A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4 Z_neg A1 VDD VNW pfet_05v0 W=1.640000U L=0.500000U
+M_i_5 VDD A2 Z_neg VNW pfet_05v0 W=1.640000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_4.cdl b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_4.cdl
index e1b1df4..b53e19a 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_4.cdl
+++ b/cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_4.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__and2_4 A1 A2 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(A1 * A2)
-M_i_3_1 net_0_1 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 Z_neg A1 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_0_0 A1 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS A2 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_1 Z_neg A2 VDD VNW pmos_5p0 W=1.640000U L=0.500000U
-M_i_4_1 VDD A1 Z_neg VNW pmos_5p0 W=1.640000U L=0.500000U
-M_i_4_0 Z_neg A1 VDD VNW pmos_5p0 W=1.640000U L=0.500000U
-M_i_5_0 VDD A2 Z_neg VNW pmos_5p0 W=1.640000U L=0.500000U
-M_i_1_3 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3_1 net_0_1 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 Z_neg A1 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_0_0 A1 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS A2 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_1 Z_neg A2 VDD VNW pfet_05v0 W=1.640000U L=0.500000U
+M_i_4_1 VDD A1 Z_neg VNW pfet_05v0 W=1.640000U L=0.500000U
+M_i_4_0 Z_neg A1 VDD VNW pfet_05v0 W=1.640000U L=0.500000U
+M_i_5_0 VDD A2 Z_neg VNW pfet_05v0 W=1.640000U L=0.500000U
+M_i_1_3 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_1.cdl b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_1.cdl
index 8e1680f..3d12248 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_1.cdl
+++ b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_1.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__and3_1 A1 A2 A3 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((A1 * A2) * A3)
-M_i_2 net_0 A1 Z_neg VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_3 net_1 A2 net_0 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_4 VSS A3 net_1 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5 VDD A1 Z_neg VNW pmos_5p0 W=0.730000U L=0.500000U
-M_i_6 Z_neg A2 VDD VNW pmos_5p0 W=0.730000U L=0.500000U
-M_i_7 VDD A3 Z_neg VNW pmos_5p0 W=0.730000U L=0.500000U
-M_i_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 net_0 A1 Z_neg VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_3 net_1 A2 net_0 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_4 VSS A3 net_1 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5 VDD A1 Z_neg VNW pfet_05v0 W=0.730000U L=0.500000U
+M_i_6 Z_neg A2 VDD VNW pfet_05v0 W=0.730000U L=0.500000U
+M_i_7 VDD A3 Z_neg VNW pfet_05v0 W=0.730000U L=0.500000U
+M_i_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_2.cdl b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_2.cdl
index 1451794..7318c3e 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_2.cdl
+++ b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_2.cdl
@@ -15,14 +15,14 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__and3_2 A1 A2 A3 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((A1 * A2) * A3)
-M_i_2 net_0 A1 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 net_1 A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4 VSS A3 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5 VDD A1 Z_neg VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_6 Z_neg A2 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7 VDD A3 Z_neg VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 net_0 A1 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 net_1 A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4 VSS A3 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5 VDD A1 Z_neg VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_6 Z_neg A2 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7 VDD A3 Z_neg VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_4.cdl b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_4.cdl
index 2182139..54913dc 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_4.cdl
+++ b/cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_4.cdl
@@ -15,24 +15,24 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__and3_4 A1 A2 A3 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((A1 * A2) * A3)
-M_i_4_0 net_1_1 A3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_0_1 A2 net_1_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 Z_neg A1 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_0_0 A1 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 net_1_0 A2 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_1 VSS A3 net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7_0 Z_neg A3 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_6_1 VDD A2 Z_neg VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_5_1 Z_neg A1 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_5_0 VDD A1 Z_neg VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_6_0 Z_neg A2 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7_1 VDD A3 Z_neg VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_1_3 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_4_0 net_1_1 A3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_0_1 A2 net_1_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 Z_neg A1 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_0_0 A1 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 net_1_0 A2 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_1 VSS A3 net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7_0 Z_neg A3 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_6_1 VDD A2 Z_neg VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_5_1 Z_neg A1 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_5_0 VDD A1 Z_neg VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_6_0 Z_neg A2 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7_1 VDD A3 Z_neg VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_1_3 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_1.cdl b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_1.cdl
index c43c528..5067bda 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_1.cdl
+++ b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_1.cdl
@@ -15,14 +15,14 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__and4_1 A1 A2 A3 A4 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(((A1 * A2) * A3) * A4)
-M_i_2 net_0 A1 Z_neg VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_3 net_1 A2 net_0 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_4 net_2 A3 net_1 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_5 VSS A4 net_2 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6 Z_neg A1 VDD VNW pmos_5p0 W=0.640000U L=0.500000U
-M_i_7 VDD A2 Z_neg VNW pmos_5p0 W=0.640000U L=0.500000U
-M_i_8 Z_neg A3 VDD VNW pmos_5p0 W=0.640000U L=0.500000U
-M_i_9 VDD A4 Z_neg VNW pmos_5p0 W=0.640000U L=0.500000U
-M_i_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 net_0 A1 Z_neg VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_3 net_1 A2 net_0 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_4 net_2 A3 net_1 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_5 VSS A4 net_2 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6 Z_neg A1 VDD VNW pfet_05v0 W=0.640000U L=0.500000U
+M_i_7 VDD A2 Z_neg VNW pfet_05v0 W=0.640000U L=0.500000U
+M_i_8 Z_neg A3 VDD VNW pfet_05v0 W=0.640000U L=0.500000U
+M_i_9 VDD A4 Z_neg VNW pfet_05v0 W=0.640000U L=0.500000U
+M_i_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_2.cdl b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_2.cdl
index fb7b0c1..82ad7c5 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_2.cdl
+++ b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_2.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__and4_2 A1 A2 A3 A4 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(((A1 * A2) * A3) * A4)
-M_i_2 net_0 A1 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 net_1 A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4 net_2 A3 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5 VSS A4 net_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6 Z_neg A1 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_7 VDD A2 Z_neg VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_8 Z_neg A3 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_9 VDD A4 Z_neg VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 net_0 A1 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 net_1 A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4 net_2 A3 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5 VSS A4 net_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6 Z_neg A1 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_7 VDD A2 Z_neg VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_8 Z_neg A3 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_9 VDD A4 Z_neg VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_4.cdl b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_4.cdl
index ec48c7e..17c6de2 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_4.cdl
+++ b/cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_4.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__and4_4 A1 A2 A3 A4 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(((A1 * A2) * A3) * A4)
-M_i_5_1 net_2_1 A4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_1 net_1_1 A3 net_2_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_0_1 A2 net_1_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 Z_neg A1 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_0_0 A1 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 net_1_0 A2 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_0 net_2_0 A3 net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_0 VSS A4 net_2_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_9_1 Z_neg A4 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_8_1 VDD A3 Z_neg VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_7_1 Z_neg A2 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_6_1 VDD A1 Z_neg VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_6_0 Z_neg A1 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_7_0 VDD A2 Z_neg VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_8_0 Z_neg A3 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_9_0 VDD A4 Z_neg VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_1_3 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_5_1 net_2_1 A4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_1 net_1_1 A3 net_2_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_0_1 A2 net_1_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 Z_neg A1 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_0_0 A1 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 net_1_0 A2 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_0 net_2_0 A3 net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_0 VSS A4 net_2_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_9_1 Z_neg A4 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_8_1 VDD A3 Z_neg VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_7_1 Z_neg A2 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_6_1 VDD A1 Z_neg VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_6_0 Z_neg A1 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_7_0 VDD A2 Z_neg VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_8_0 Z_neg A3 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_9_0 VDD A4 Z_neg VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_1_3 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/antenna/gf180mcu_fd_sc_mcu9t5v0__antenna.cdl b/cells/antenna/gf180mcu_fd_sc_mcu9t5v0__antenna.cdl
index ea316b1..dc18921 100644
--- a/cells/antenna/gf180mcu_fd_sc_mcu9t5v0__antenna.cdl
+++ b/cells/antenna/gf180mcu_fd_sc_mcu9t5v0__antenna.cdl
@@ -13,6 +13,6 @@
* limitations under the License.
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__antenna I VDD VNW VPW VSS
-d0 VPW I np_6p0 0.2034p 1.85u $m=1
-d1 I VNW pn_6p0 0.2034p 1.85u $m=1
+d0 VPW I diode_nd2ps_06v0 0.2034p 1.85u $m=1
+d1 I VNW diode_pd2nw_06v0 0.2034p 1.85u $m=1
.ENDS
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.cdl b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.cdl
index d9427cc..53ef44a 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.cdl
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.cdl
@@ -15,10 +15,10 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi21_1 A1 A2 B ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 * A2) + B)
-M_i_1 net_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 VSS B ZN VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_4 ZN A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 VDD B net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_1 net_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 VSS B ZN VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_4 ZN A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 VDD B net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.cdl b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.cdl
index b0ef3da..48b0a2e 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.cdl
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi21_2 A1 A2 B ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 * A2) + B)
-M_i_2_0 ZN B VSS VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_2_1 VSS B ZN VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_1_0 net_0_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0_1 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 VSS A2 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_0 VDD B net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 net_1 B VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 ZN A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0 ZN A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 net_1 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 ZN B VSS VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_2_1 VSS B ZN VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_1_0 net_0_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0_1 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 VSS A2 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_0 VDD B net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 net_1 B VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 ZN A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0 ZN A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 net_1 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_4.cdl b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_4.cdl
index 330f096..a10d8bf 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_4.cdl
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_4.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi21_4 A1 A2 B ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 * A2) + B)
-M_i_1_3 net_0_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 ZN A1 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 net_0_1 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 VSS A2 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0_2 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0_3 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 VSS A2 net_0_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 ZN B VSS VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_2_2 VSS B ZN VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_2_1 ZN B VSS VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_2_0 VSS B ZN VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_4_3 ZN A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 ZN A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_2 net_1 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 ZN A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0 ZN A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_1 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_3 VDD B net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_2 net_1 B VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 VDD B net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_1 B VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_1_3 net_0_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 ZN A1 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 net_0_1 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 VSS A2 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0_2 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0_3 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 VSS A2 net_0_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 ZN B VSS VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_2_2 VSS B ZN VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_2_1 ZN B VSS VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_2_0 VSS B ZN VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_4_3 ZN A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 ZN A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_2 net_1 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 ZN A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0 ZN A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_1 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_3 VDD B net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_2 net_1 B VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 VDD B net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_1 B VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_1.cdl b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_1.cdl
index 86258f7..0406850 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_1.cdl
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_1.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi211_1 A1 A2 B C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) + B) + C)
-M_i_1 net_0 A2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0 ZN A1 net_0 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_2 VSS B ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_3 ZN C VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_5 ZN A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 net_2 B net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7 VDD C net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_1 net_0 A2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0 ZN A1 net_0 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_2 VSS B ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_3 ZN C VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_5 ZN A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 net_2 B net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7 VDD C net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_2.cdl b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_2.cdl
index 2926a2f..872df1f 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_2.cdl
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_2.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi211_2 A1 A2 B C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) + B) + C)
-M_i_1_1 net_0_0 A2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0_1 ZN A1 net_0_0 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0_0 net_0_1 A1 ZN VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_1_0 VSS A2 net_0_1 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_2_0 ZN B VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_3_0 VSS C ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_3_1 ZN C VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_1 VSS B ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_5_1 ZN A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 ZN A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_1 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_2_0 B net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 VDD C net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 net_2_1 C VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_1 B net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_1_1 net_0_0 A2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0_1 ZN A1 net_0_0 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0_0 net_0_1 A1 ZN VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_1_0 VSS A2 net_0_1 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_2_0 ZN B VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_3_0 VSS C ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_3_1 ZN C VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_1 VSS B ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_5_1 ZN A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 ZN A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_1 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_2_0 B net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 VDD C net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 net_2_1 C VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_1 B net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_4.cdl b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_4.cdl
index 50a4e59..25fce2a 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_4.cdl
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_4.cdl
@@ -15,36 +15,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi211_4 A1 A2 B C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) + B) + C)
-M_i_1_3 net_0_0 A2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0_3 ZN A1 net_0_0 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0_2 net_0_1 A1 ZN VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_1_2 VSS A2 net_0_1 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_1_1 net_0_2 A2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0_1 ZN A1 net_0_2 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0_0 net_0_3 A1 ZN VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_1_0 VSS A2 net_0_3 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_2_0 ZN B VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_3_0 VSS C ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_3_1 ZN C VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_1 VSS B ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_2 ZN B VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_3_2 VSS C ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_3_3 ZN C VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_3 VSS B ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_5_3 ZN A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_3 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_2 ZN A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_2 net_1 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 ZN A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 ZN A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_1 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_2_0 B net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 VDD C net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 net_2_1 C VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_1 B net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_2 net_2_2 B net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_2 VDD C net_2_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_3 net_2_3 C VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_3 net_1 B net_2_3 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_1_3 net_0_0 A2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0_3 ZN A1 net_0_0 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0_2 net_0_1 A1 ZN VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_1_2 VSS A2 net_0_1 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_1_1 net_0_2 A2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0_1 ZN A1 net_0_2 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0_0 net_0_3 A1 ZN VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_1_0 VSS A2 net_0_3 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_2_0 ZN B VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_3_0 VSS C ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_3_1 ZN C VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_1 VSS B ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_2 ZN B VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_3_2 VSS C ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_3_3 ZN C VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_3 VSS B ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_5_3 ZN A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_3 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_2 ZN A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_2 net_1 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 ZN A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 ZN A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_1 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_2_0 B net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 VDD C net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 net_2_1 C VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_1 B net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_2 net_2_2 B net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_2 VDD C net_2_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_3 net_2_3 C VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_3 net_1 B net_2_3 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.cdl b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.cdl
index 74892c5..bb700b2 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.cdl
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi22_1 A1 A2 B1 B2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 * A2) + (B1 * B2))
-M_i_3 net_1 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 ZN B1 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 VSS A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7 VDD B2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 net_2 B1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 net_2 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3 net_1 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 ZN B1 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 VSS A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7 VDD B2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 net_2 B1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 net_2 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_2.cdl b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_2.cdl
index 11d9919..7ae1761 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_2.cdl
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_2.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi22_2 A1 A2 B1 B2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 * A2) + (B1 * B2))
-M_i_3_1 net_1_0 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 ZN B1 net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_1_1 B1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS B2 net_1_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0_1 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 VSS A2 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7_1 VDD B2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_2 B1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 VDD B1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_2 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 ZN A2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 net_2 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_2 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3_1 net_1_0 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 ZN B1 net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_1_1 B1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS B2 net_1_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0_1 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 VSS A2 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7_1 VDD B2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_2 B1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 VDD B1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_2 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 ZN A2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 net_2 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_2 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_4.cdl b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_4.cdl
index cd649d4..b9c5f90 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_4.cdl
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_4.cdl
@@ -15,36 +15,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi22_4 A1 A2 B1 B2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 * A2) + (B1 * B2))
-M_i_3_3 net_1_0 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 ZN B1 net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 net_1_1 B1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_2 VSS B2 net_1_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_1_2 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 ZN B1 net_1_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_1_3 B1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS B2 net_1_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0_1 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 VSS A2 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 net_0_2 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN A1 net_0_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 net_0_3 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_3 VSS A2 net_0_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7_3 VDD B2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_3 net_2 B1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_2 VDD B1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_2 net_2 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 VDD B2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_2 B1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 VDD B1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_2 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 ZN A2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_2 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 net_2 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_2 ZN A2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_2 net_2 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_3 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_3 net_2 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3_3 net_1_0 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 ZN B1 net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 net_1_1 B1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_2 VSS B2 net_1_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_1_2 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 ZN B1 net_1_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_1_3 B1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS B2 net_1_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0_1 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 VSS A2 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 net_0_2 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN A1 net_0_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 net_0_3 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_3 VSS A2 net_0_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7_3 VDD B2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_3 net_2 B1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_2 VDD B1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_2 net_2 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 VDD B2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_2 B1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 VDD B1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_2 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 ZN A2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_2 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 net_2 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_2 ZN A2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_2 net_2 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_3 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_3 net_2 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_1.cdl b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_1.cdl
index e459754..7aa251b 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_1.cdl
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_1.cdl
@@ -15,14 +15,14 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi221_1 A1 A2 B1 B2 C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) + (B1 * B2)) + C)
-M_i_4 net_1 B2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_3 ZN B1 net_1 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_2 VSS C ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_1 net_0 A2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0 ZN A1 net_0 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_9 VDD B2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8 net_3 B1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7 net_2 C net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 ZN A2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 net_2 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_4 net_1 B2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_3 ZN B1 net_1 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_2 VSS C ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_1 net_0 A2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0 ZN A1 net_0 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_9 VDD B2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8 net_3 B1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7 net_2 C net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 ZN A2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 net_2 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.cdl b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.cdl
index 194c935..3b680bd 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.cdl
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.cdl
@@ -15,24 +15,24 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi221_2 A1 A2 B1 B2 C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) + (B1 * B2)) + C)
-M_i_2_1 VSS C ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_4_1 net_1_0 B2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_3_1 ZN B1 net_1_0 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_3_0 net_1_1 B1 ZN VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_4_0 VSS B2 net_1_1 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_2_0 ZN C VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_0_1 net_0_0 A1 ZN VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_1_1 VSS A2 net_0_0 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_1_0 net_0_1 A2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0_0 ZN A1 net_0_1 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_7_1 net_3 C net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_1 VDD B2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 net_3 B1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 VDD B1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 net_3 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_2 C net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_2 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 ZN A2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_2 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_1 VSS C ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_4_1 net_1_0 B2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_3_1 ZN B1 net_1_0 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_3_0 net_1_1 B1 ZN VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_4_0 VSS B2 net_1_1 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_2_0 ZN C VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_0_1 net_0_0 A1 ZN VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_1_1 VSS A2 net_0_0 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_1_0 net_0_1 A2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0_0 ZN A1 net_0_1 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_7_1 net_3 C net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_1 VDD B2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 net_3 B1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 VDD B1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 net_3 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_2 C net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_2 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 ZN A2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_2 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_4.cdl b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_4.cdl
index 0433d89..48a926a 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_4.cdl
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_4.cdl
@@ -15,44 +15,44 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi221_4 A1 A2 B1 B2 C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) + (B1 * B2)) + C)
-M_i_3_3 net_1_0 B1 ZN VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_4_3 VSS B2 net_1_0 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_4_2 net_1_1 B2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_3_2 ZN B1 net_1_1 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_3_1 net_1_2 B1 ZN VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_4_1 VSS B2 net_1_2 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_4_0 net_1_3 B2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_3_0 ZN B1 net_1_3 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_2_3 VSS C ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_2 ZN C VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_1 VSS C ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_0 ZN C VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_0_3 net_0_0 A1 ZN VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_1_3 VSS A2 net_0_0 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_1_2 net_0_1 A2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0_2 ZN A1 net_0_1 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0_1 net_0_2 A1 ZN VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_1_1 VSS A2 net_0_2 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_1_0 net_0_3 A2 VSS VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_0_0 ZN A1 net_0_3 VPW nmos_5p0 W=1.185000U L=0.600000U
-M_i_8_3 net_3 B1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_3 VDD B2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_2 net_3 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_2 VDD B1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 net_3 B1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_1 VDD B2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 net_3 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 VDD B1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_3 net_3 C net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_2 net_2 C net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 net_3 C net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_2 C net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_3 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_3 net_2 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_2 ZN A2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_2 net_2 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_2 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 ZN A2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_2 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3_3 net_1_0 B1 ZN VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_4_3 VSS B2 net_1_0 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_4_2 net_1_1 B2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_3_2 ZN B1 net_1_1 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_3_1 net_1_2 B1 ZN VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_4_1 VSS B2 net_1_2 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_4_0 net_1_3 B2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_3_0 ZN B1 net_1_3 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_2_3 VSS C ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_2 ZN C VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_1 VSS C ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_0 ZN C VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_0_3 net_0_0 A1 ZN VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_1_3 VSS A2 net_0_0 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_1_2 net_0_1 A2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0_2 ZN A1 net_0_1 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0_1 net_0_2 A1 ZN VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_1_1 VSS A2 net_0_2 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_1_0 net_0_3 A2 VSS VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_0_0 ZN A1 net_0_3 VPW nfet_05v0 W=1.185000U L=0.600000U
+M_i_8_3 net_3 B1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_3 VDD B2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_2 net_3 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_2 VDD B1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 net_3 B1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_1 VDD B2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 net_3 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 VDD B1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_3 net_3 C net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_2 net_2 C net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 net_3 C net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_2 C net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_3 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_3 net_2 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_2 ZN A2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_2 net_2 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_2 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 ZN A2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_2 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.cdl b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.cdl
index 9cc6484..743f49c 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.cdl
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi222_1 A1 A2 B1 B2 C1 C2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C1:I C2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) + (B1 * B2)) + (C1 * C2))
-M_i_5 net_2 C2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4 ZN C1 net_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 net_1 B1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 VSS B2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 net_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_11 net_4 C2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10 VDD C1 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8 net_4 B1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9 net_3 B2 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7 ZN A2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 net_3 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_5 net_2 C2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4 ZN C1 net_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 net_1 B1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 VSS B2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 net_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_11 net_4 C2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10 VDD C1 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8 net_4 B1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9 net_3 B2 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7 ZN A2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 net_3 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.cdl b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.cdl
index 129d62c..92f14b9 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.cdl
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi222_2 A1 A2 B1 B2 C1 C2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C1:I C2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) + (B1 * B2)) + (C1 * C2))
-M_i_4_1 net_2_1 C1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_1 VSS C2 net_2_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_0 net_2_0 C2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_0 ZN C1 net_2_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_1_1 B1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS B2 net_1_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_1_0 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 ZN B1 net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0_1 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 VSS A2 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_10_1 net_4 C1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_1 VDD C2 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_0 net_4 C2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_0 VDD C1 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 net_4 B1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 net_3 B2 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_1 net_4 B2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 net_3 B1 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 ZN A1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_3 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 ZN A2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_3 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_4_1 net_2_1 C1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_1 VSS C2 net_2_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_0 net_2_0 C2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_0 ZN C1 net_2_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_1_1 B1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS B2 net_1_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_1_0 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 ZN B1 net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0_1 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 VSS A2 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_10_1 net_4 C1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_1 VDD C2 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_0 net_4 C2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_0 VDD C1 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 net_4 B1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 net_3 B2 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_1 net_4 B2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 net_3 B1 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 ZN A1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_3 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 ZN A2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_3 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_4.cdl b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_4.cdl
index b4d9bfd..0f414cb 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_4.cdl
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_4.cdl
@@ -15,52 +15,52 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__aoi222_4 A1 A2 B1 B2 C1 C2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C1:I C2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) + (B1 * B2)) + (C1 * C2))
-M_i_4_3 net_2_3 C1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_3 VSS C2 net_2_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_2 net_2_2 C2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_2 ZN C1 net_2_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_1 net_2_1 C1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_1 VSS C2 net_2_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_0 net_2_0 C2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_0 ZN C1 net_2_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_1_3 B1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS B2 net_1_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_1_2 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 ZN B1 net_1_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 net_1_1 B1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_2 VSS B2 net_1_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_3 net_1_0 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 ZN B1 net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0_3 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 VSS A2 net_0_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0_2 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 net_0_1 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 VSS A2 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_3 net_0_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 ZN A1 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_10_3 net_4 C1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_3 VDD C2 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_2 net_4 C2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_2 VDD C1 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_1 net_4 C1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_1 VDD C2 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_0 net_4 C2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_0 VDD C1 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 net_4 B1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 net_3 B2 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_1 net_4 B2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 net_3 B1 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_2 net_4 B1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_2 net_3 B2 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_3 net_4 B2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_3 net_3 B1 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 ZN A1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_3 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 ZN A2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_3 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_2 ZN A1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_2 net_3 A2 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_3 ZN A2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_3 net_3 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_4_3 net_2_3 C1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_3 VSS C2 net_2_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_2 net_2_2 C2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_2 ZN C1 net_2_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_1 net_2_1 C1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_1 VSS C2 net_2_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_0 net_2_0 C2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_0 ZN C1 net_2_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_1_3 B1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS B2 net_1_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_1_2 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 ZN B1 net_1_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 net_1_1 B1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_2 VSS B2 net_1_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_3 net_1_0 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 ZN B1 net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0_3 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 VSS A2 net_0_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0_2 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 net_0_1 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 VSS A2 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_3 net_0_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 ZN A1 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_10_3 net_4 C1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_3 VDD C2 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_2 net_4 C2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_2 VDD C1 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_1 net_4 C1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_1 VDD C2 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_0 net_4 C2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_0 VDD C1 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 net_4 B1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 net_3 B2 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_1 net_4 B2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 net_3 B1 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_2 net_4 B1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_2 net_3 B2 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_3 net_4 B2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_3 net_3 B1 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 ZN A1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_3 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 ZN A2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_3 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_2 ZN A1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_2 net_3 A2 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_3 ZN A2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_3 net_3 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_1.cdl b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_1.cdl
index 7034991..63d75fa 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_1.cdl
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_1.cdl
@@ -15,8 +15,8 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__buf_1 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2 VSS I Z_neg VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 VDD I Z_neg VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 VSS I Z_neg VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 VDD I Z_neg VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_12.cdl b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_12.cdl
index 3434850..394798e 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_12.cdl
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_12.cdl
@@ -15,40 +15,40 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__buf_12 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_4 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_5 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_4 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_5 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_6 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_7 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_8 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_9 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_10 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_11 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_4 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_5 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_4 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_5 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_4 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_5 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_6 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_7 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_8 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_9 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_10 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_11 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_4 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_5 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_16.cdl b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_16.cdl
index bff93b7..fe96fc9 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_16.cdl
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_16.cdl
@@ -15,52 +15,52 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__buf_16 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_4 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_5 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_6 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_7 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_4 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_5 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_6 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_7 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_8 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_9 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_10 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_11 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_12 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_13 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_14 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_15 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_4 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_5 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_6 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_7 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_12 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_13 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_14 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_15 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_4 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_5 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_6 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_7 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_4 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_5 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_6 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_7 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_8 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_9 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_10 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_11 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_12 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_13 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_14 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_15 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_4 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_5 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_6 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_7 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_12 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_13 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_14 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_15 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.cdl b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.cdl
index 1ca4620..20f1631 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.cdl
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.cdl
@@ -15,10 +15,10 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__buf_2 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_20.cdl b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_20.cdl
index 1cd773d..a996f98 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_20.cdl
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_20.cdl
@@ -15,64 +15,64 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__buf_20 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_4 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_5 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_6 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_7 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_8 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_9 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_4 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_5 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_6 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_7 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_8 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_9 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_10 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_11 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_12 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_13 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_14 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_15 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_16 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_17 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_18 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_19 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_4 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_5 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_6 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_7 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_8 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_9 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_12 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_13 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_14 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_15 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_16 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_17 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_18 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_19 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_4 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_5 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_6 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_7 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_8 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_9 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_4 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_5 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_6 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_7 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_8 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_9 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_10 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_11 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_12 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_13 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_14 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_15 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_16 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_17 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_18 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_19 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_4 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_5 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_6 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_7 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_8 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_9 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_12 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_13 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_14 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_15 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_16 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_17 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_18 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_19 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_3.cdl b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_3.cdl
index a750d1e..760ca7e 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_3.cdl
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_3.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__buf_3 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_4.cdl b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_4.cdl
index ceae1ed..af7d512 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_4.cdl
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_4.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__buf_4 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_8.cdl b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_8.cdl
index 2975ab8..427dce9 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_8.cdl
+++ b/cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_8.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__buf_8 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 VSS I Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_4 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_5 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_6 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_7 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 VSS I Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_4 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_5 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_6 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_7 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_1.cdl b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_1.cdl
index 607c05b..70194fb 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_1.cdl
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_1.cdl
@@ -15,14 +15,14 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__bufz_1 EN I Z VDD VNW VPW VSS
*.PININFO EN:I I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_XX27 VSS EN NEN VPW nmos_5p0 W=0.590000U L=0.600000U
-M_XX44 VSS NEN NI_N VPW nmos_5p0 W=0.590000U L=0.600000U
-M_XX36 NI_N EN NI_P VPW nmos_5p0 W=0.590000U L=0.600000U
-M_XX43 NI_N I VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_XX22 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX28 VDD EN NEN VNW pmos_5p0 W=0.990000U L=0.500000U
-M_XX45 NI_P EN VDD VNW pmos_5p0 W=0.990000U L=0.500000U
-M_XX39 NI_N NEN NI_P VNW pmos_5p0 W=0.990000U L=0.500000U
-M_XX46 NI_P I VDD VNW pmos_5p0 W=0.990000U L=0.500000U
-M_XX21 VDD NI_P Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_XX27 VSS EN NEN VPW nfet_05v0 W=0.590000U L=0.600000U
+M_XX44 VSS NEN NI_N VPW nfet_05v0 W=0.590000U L=0.600000U
+M_XX36 NI_N EN NI_P VPW nfet_05v0 W=0.590000U L=0.600000U
+M_XX43 NI_N I VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_XX22 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX28 VDD EN NEN VNW pfet_05v0 W=0.990000U L=0.500000U
+M_XX45 NI_P EN VDD VNW pfet_05v0 W=0.990000U L=0.500000U
+M_XX39 NI_N NEN NI_P VNW pfet_05v0 W=0.990000U L=0.500000U
+M_XX46 NI_P I VDD VNW pfet_05v0 W=0.990000U L=0.500000U
+M_XX21 VDD NI_P Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_12.cdl b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_12.cdl
index 59336ec..d0aa0bf 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_12.cdl
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_12.cdl
@@ -15,46 +15,46 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__bufz_12 EN I Z VDD VNW VPW VSS
*.PININFO EN:I I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_mn VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn8 NI_N NEN VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn21 NI_P EN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9 VSS I NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_10 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_17 VSS I NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_10_0 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_17_30 VSS I NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_34 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_88 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_33 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_99 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_35 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_80 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_34 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_89 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mp VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp7 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp22 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10 VDD I NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_11 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_8 VDD I NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_11_21 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_8_17 VDD I NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_75 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_111 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_106 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_58 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_69 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_105 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_96 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_57 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
+M_mn VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn8 NI_N NEN VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn21 NI_P EN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9 VSS I NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_10 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_17 VSS I NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_10_0 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_17_30 VSS I NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_34 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_88 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_33 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_99 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_35 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_80 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_34 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_89 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mp VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp7 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp22 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10 VDD I NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_11 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_8 VDD I NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_11_21 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_8_17 VDD I NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_75 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_111 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_106 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_58 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_69 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_105 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_96 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_57 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_16.cdl b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_16.cdl
index 2f3763a..9624383 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_16.cdl
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_16.cdl
@@ -15,58 +15,58 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__bufz_16 EN I Z VDD VNW VPW VSS
*.PININFO EN:I I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_mn VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn8 NI_N NEN VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn21 NI_P EN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9 VSS I NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_10 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_17 VSS I NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_34 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_41 VSS I NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_10_30 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_17_61 VSS I NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_34 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_88 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_33 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_99 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_34_75 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_88_82 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_33_198 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_99_125 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_137 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_181 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_65 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_118 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mp VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp7 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp22 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10 VDD I NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_11 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_8 VDD I NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_7 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_32 VDD I NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_11_55 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_8_20 VDD I NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_75 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_111 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_106 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_58 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_75_85 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_111_134 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_106_111 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_58_95 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_97 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_133 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_126 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_153 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
+M_mn VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn8 NI_N NEN VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn21 NI_P EN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9 VSS I NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_10 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_17 VSS I NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_34 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_41 VSS I NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_10_30 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_17_61 VSS I NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_34 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_88 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_33 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_99 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_34_75 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_88_82 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_33_198 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_99_125 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_137 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_181 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_65 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_118 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mp VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp7 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp22 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10 VDD I NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_11 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_8 VDD I NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_7 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_32 VDD I NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_11_55 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_8_20 VDD I NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_75 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_111 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_106 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_58 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_75_85 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_111_134 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_106_111 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_58_95 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_97 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_133 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_126 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_153 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_2.cdl b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_2.cdl
index 61a534a..c1709d9 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_2.cdl
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_2.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__bufz_2 EN I Z VDD VNW VPW VSS
*.PININFO EN:I I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_XX27 VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX44 VSS NEN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX36 NI_N EN NI_P VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX43 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX22 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX22_4 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX28 VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX45 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX39 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX46 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX21 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX21_5 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
+M_XX27 VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX44 VSS NEN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX36 NI_N EN NI_P VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX43 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX22 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX22_4 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX28 VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX45 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX39 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX46 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX21 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX21_5 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_3.cdl b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_3.cdl
index 69a1a3d..f662c08 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_3.cdl
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_3.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__bufz_3 EN I Z VDD VNW VPW VSS
*.PININFO EN:I I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_XX27 VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX44 VSS NEN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX36 NI_N EN NI_P VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX43 NI_N I VSS VPW nmos_5p0 W=0.885000U L=0.600000U
-M_XX43_17 NI_N I VSS VPW nmos_5p0 W=0.885000U L=0.600000U
-M_XX22 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX22_4 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX22_4_97 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX28 VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX45 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX39 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX46 NI_P I VDD VNW pmos_5p0 W=1.485000U L=0.500000U
-M_XX46_9 NI_P I VDD VNW pmos_5p0 W=1.485000U L=0.500000U
-M_XX21 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX21_5 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX21_5_72 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
+M_XX27 VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX44 VSS NEN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX36 NI_N EN NI_P VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX43 NI_N I VSS VPW nfet_05v0 W=0.885000U L=0.600000U
+M_XX43_17 NI_N I VSS VPW nfet_05v0 W=0.885000U L=0.600000U
+M_XX22 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX22_4 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX22_4_97 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX28 VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX45 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX39 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX46 NI_P I VDD VNW pfet_05v0 W=1.485000U L=0.500000U
+M_XX46_9 NI_P I VDD VNW pfet_05v0 W=1.485000U L=0.500000U
+M_XX21 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX21_5 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX21_5_72 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_4.cdl b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_4.cdl
index 498a2a6..b583130 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_4.cdl
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_4.cdl
@@ -15,22 +15,22 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__bufz_4 EN I Z VDD VNW VPW VSS
*.PININFO EN:I I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_XX27 VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX44 VSS NEN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX36 NI_N EN NI_P VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX43 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX43_17 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX22 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX22_4 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX22_4_97 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX22_4_97_16 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX28 VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX45 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX39 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX46 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX46_9 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX21 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX21_5 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX21_5_72 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX21_5_72_5 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
+M_XX27 VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX44 VSS NEN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX36 NI_N EN NI_P VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX43 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX43_17 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX22 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX22_4 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX22_4_97 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX22_4_97_16 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX28 VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX45 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX39 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX46 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX46_9 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX21 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX21_5 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX21_5_72 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX21_5_72_5 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_8.cdl b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_8.cdl
index 5281b70..0c31c56 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_8.cdl
+++ b/cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_8.cdl
@@ -15,34 +15,34 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__bufz_8 EN I Z VDD VNW VPW VSS
*.PININFO EN:I I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_mn VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn8 NI_N NEN VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn21 NI_P EN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9 VSS I NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_10 NI_N I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_17 VSS I NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_34 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_88 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_33 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_99 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1 Z NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3 VSS NI_N Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mp VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp7 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp22 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10 VDD I NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_11 NI_P I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_8 VDD I NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_75 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_111 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_106 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_58 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12 Z NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4 VDD NI_P Z VNW pmos_5p0 W=1.800000U L=0.500000U
+M_mn VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn8 NI_N NEN VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn21 NI_P EN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9 VSS I NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_10 NI_N I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_17 VSS I NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_34 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_88 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_33 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_99 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1 Z NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3 VSS NI_N Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mp VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp7 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp22 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10 VDD I NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_11 NI_P I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_8 VDD I NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_75 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_111 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_106 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_58 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12 Z NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4 VDD NI_P Z VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.cdl b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.cdl
index a4163a1..b2418dd 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.cdl
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.cdl
@@ -15,8 +15,8 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkbuf_1 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2 VSS I Z_neg VPW nmos_5p0 W=0.365000U L=0.600000U
-M_i_0 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_3 VDD I Z_neg VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 VSS I Z_neg VPW nfet_05v0 W=0.365000U L=0.600000U
+M_i_0 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_3 VDD I Z_neg VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.cdl b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.cdl
index ee60e7c..d09e8f5 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.cdl
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.cdl
@@ -15,40 +15,40 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkbuf_12 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_1 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_2 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_3 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_4 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_5 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_4 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_5 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_6 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_7 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_8 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_9 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_10 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_11 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_4 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_5 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_1 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_2 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_3 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_4 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_5 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_4 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_5 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_6 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_7 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_8 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_9 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_10 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_11 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_4 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_5 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.cdl b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.cdl
index 1823618..dd8b76b 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.cdl
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.cdl
@@ -15,52 +15,52 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkbuf_16 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_1 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_2 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_3 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_4 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_5 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_6 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_7 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_4 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_5 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_6 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_7 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_8 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_9 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_10 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_11 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_12 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_13 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_14 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_15 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_4 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_5 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_6 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_7 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_12 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_13 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_14 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_15 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_1 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_2 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_3 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_4 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_5 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_6 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_7 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_4 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_5 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_6 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_7 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_8 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_9 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_10 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_11 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_12 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_13 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_14 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_15 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_4 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_5 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_6 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_7 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_12 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_13 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_14 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_15 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.cdl b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.cdl
index 3d23602..9210435 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.cdl
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.cdl
@@ -15,10 +15,10 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkbuf_2 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_3 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_3 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.cdl b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.cdl
index 42925f0..2fcfef5 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.cdl
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.cdl
@@ -15,64 +15,64 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkbuf_20 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_1 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_2 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_3 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_4 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_5 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_6 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_7 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_8 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_9 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_4 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_5 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_6 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_7 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_8 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_9 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_10 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_11 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_12 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_13 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_14 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_15 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_16 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_17 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_18 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_19 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_4 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_5 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_6 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_7 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_8 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_9 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_12 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_13 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_14 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_15 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_16 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_17 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_18 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_19 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_1 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_2 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_3 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_4 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_5 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_6 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_7 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_8 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_9 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_4 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_5 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_6 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_7 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_8 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_9 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_10 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_11 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_12 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_13 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_14 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_15 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_16 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_17 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_18 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_19 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_4 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_5 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_6 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_7 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_8 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_9 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_12 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_13 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_14 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_15 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_16 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_17 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_18 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_19 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.cdl b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.cdl
index 2f7eba5..5139dd4 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.cdl
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkbuf_3 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.550000U L=0.600000U
-M_i_2_1 VSS I Z_neg VPW nmos_5p0 W=0.550000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=0.600000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=0.600000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=0.600000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=0.600000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=1.375000U L=0.500000U
-M_i_3_1 VDD I Z_neg VNW pmos_5p0 W=1.375000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.375000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.375000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.375000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.375000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.550000U L=0.600000U
+M_i_2_1 VSS I Z_neg VPW nfet_05v0 W=0.550000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=0.600000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=0.600000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=0.600000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=0.600000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=1.375000U L=0.500000U
+M_i_3_1 VDD I Z_neg VNW pfet_05v0 W=1.375000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.375000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.375000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.375000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.375000U L=0.500000U
.ENDS
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.cdl b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.cdl
index d06216d..76c7ea1 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.cdl
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkbuf_4 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_1 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_1 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.cdl b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.cdl
index b1232ed..a92d53b 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.cdl
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkbuf_8 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_1 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_2 Z_neg I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_2_3 VSS I Z_neg VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_4 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_5 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_6 Z Z_neg VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_0_7 VSS Z_neg Z VPW nmos_5p0 W=0.800000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 VDD I Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_1 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_2 Z_neg I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_2_3 VSS I Z_neg VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_4 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_5 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_6 Z Z_neg VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_0_7 VSS Z_neg Z VPW nfet_05v0 W=0.800000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 VDD I Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_1.cdl b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_1.cdl
index 556bfa1..3c859d5 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_1.cdl
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_1.cdl
@@ -15,6 +15,6 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkinv_1 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_1 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_1 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_12.cdl b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_12.cdl
index ca04c34..ab8aed0 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_12.cdl
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_12.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkinv_12 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_2 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_3 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_4 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_5 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_6 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_7 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_8 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_9 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_10 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_11 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_2 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_3 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_4 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_5 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_6 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_7 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_8 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_9 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_10 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_11 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_16.cdl b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_16.cdl
index 5915cc9..99a75ed 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_16.cdl
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_16.cdl
@@ -15,36 +15,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkinv_16 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_2 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_3 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_4 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_5 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_6 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_7 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_8 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_9 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_10 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_11 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_12 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_13 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_14 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_15 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_12 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_13 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_14 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_15 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_2 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_3 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_4 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_5 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_6 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_7 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_8 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_9 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_10 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_11 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_12 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_13 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_14 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_15 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_12 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_13 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_14 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_15 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_2.cdl b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_2.cdl
index 74e5d27..12f6858 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_2.cdl
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_2.cdl
@@ -15,8 +15,8 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkinv_2 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_20.cdl b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_20.cdl
index 4288133..3c56f2f 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_20.cdl
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_20.cdl
@@ -15,44 +15,44 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkinv_20 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_2 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_3 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_4 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_5 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_6 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_7 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_8 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_9 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_10 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_11 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_12 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_13 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_14 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_15 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_16 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_17 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_18 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_19 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_12 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_13 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_14 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_15 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_16 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_17 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_18 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_19 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_2 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_3 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_4 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_5 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_6 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_7 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_8 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_9 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_10 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_11 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_12 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_13 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_14 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_15 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_16 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_17 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_18 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_19 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_12 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_13 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_14 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_15 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_16 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_17 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_18 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_19 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_3.cdl b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_3.cdl
index 9cc7335..8ed1ecc 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_3.cdl
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_3.cdl
@@ -15,10 +15,10 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkinv_3 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_2 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_2 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_4.cdl b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_4.cdl
index f867817..3b50e93 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_4.cdl
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_4.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkinv_4 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_2 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_3 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_2 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_3 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_8.cdl b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_8.cdl
index 0943178..05d4809 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_8.cdl
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_8.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__clkinv_8 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0_x8_0 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0_x8_1 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0_x8_2 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0_x8_3 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0_x8_4 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0_x8_5 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0_x8_6 ZN I VSS VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_0_0_x8_7 VSS I ZN VPW nmos_5p0 W=0.730000U L=0.600000U
-M_i_1_0_x8_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_3 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_4 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_5 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_6 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_7 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0_x8_0 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0_x8_1 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0_x8_2 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0_x8_3 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0_x8_4 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0_x8_5 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0_x8_6 ZN I VSS VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_0_0_x8_7 VSS I ZN VPW nfet_05v0 W=0.730000U L=0.600000U
+M_i_1_0_x8_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_3 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_4 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_5 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_6 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_7 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_1.cdl b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_1.cdl
index 4b52c3a..30da49c 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_1.cdl
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_1.cdl
@@ -14,28 +14,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnq_1 D CLKN Q VDD VNW VPW VSS
*.PININFO D:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn9 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn16 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 VSS D net2 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn11 net2 cki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn0 net5 ncki net11 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 VSS net10 net11 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net10 net5 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 ncki net10 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net7 cki net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 VSS net1 net7 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn5 net1 net0 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn6 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp9 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp16 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp10 VDD D net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp11 net5 ncki net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net4 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 VDD net10 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net10 net5 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net0 cki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net7 ncki net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD net1 net7 VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp3 net1 net0 VDD VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp4 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn9 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn16 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 VSS D net2 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn11 net2 cki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn0 net5 ncki net11 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 VSS net10 net11 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net10 net5 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 ncki net10 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net7 cki net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 VSS net1 net7 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn5 net1 net0 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn6 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp9 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp16 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp10 VDD D net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp11 net5 ncki net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net4 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 VDD net10 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net10 net5 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net0 cki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net7 ncki net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD net1 net7 VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp3 net1 net0 VDD VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp4 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_2.cdl b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_2.cdl
index 14a449f..7d580e9 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_2.cdl
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_2.cdl
@@ -14,30 +14,30 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnq_2 D CLKN Q VDD VNW VPW VSS
*.PININFO D:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn9 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn16 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 VSS D net2 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn11 net2 cki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn0 net5 ncki net11 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 VSS net10 net11 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net10 net5 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 ncki net10 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net7 cki net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 VSS net1 net7 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn5 net1 net0 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6_7 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp9 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp16 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp10 VDD D net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp11 net5 ncki net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net4 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 VDD net10 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net10 net5 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net0 cki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net7 ncki net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD net1 net7 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp3 net1 net0 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4_13 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn9 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn16 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 VSS D net2 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn11 net2 cki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn0 net5 ncki net11 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 VSS net10 net11 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net10 net5 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 ncki net10 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net7 cki net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 VSS net1 net7 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn5 net1 net0 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6_7 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp9 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp16 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp10 VDD D net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp11 net5 ncki net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net4 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 VDD net10 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net10 net5 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net0 cki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net7 ncki net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD net1 net7 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp3 net1 net0 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4_13 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_4.cdl b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_4.cdl
index 34c41be..e3d7f1f 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_4.cdl
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_4.cdl
@@ -14,34 +14,34 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnq_4 D CLKN Q VDD VNW VPW VSS
*.PININFO D:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn9 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn16 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 VSS D net2 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn11 net2 cki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn0 net5 ncki net11 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 VSS net10 net11 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net10 net5 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 ncki net10 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net7 cki net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 VSS net1 net7 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn5 net1 net0 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6_7 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6_7_61 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6_49 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp9 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp16 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp10 VDD D net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp11 net5 ncki net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net4 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 VDD net10 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net10 net5 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net0 cki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net7 ncki net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD net1 net7 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp3 net1 net0 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4_13 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4_13_64 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4_55 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn9 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn16 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 VSS D net2 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn11 net2 cki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn0 net5 ncki net11 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 VSS net10 net11 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net10 net5 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 ncki net10 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net7 cki net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 VSS net1 net7 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn5 net1 net0 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6_7 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6_7_61 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6_49 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp9 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp16 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp10 VDD D net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp11 net5 ncki net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net4 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 VDD net10 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net10 net5 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net0 cki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net7 ncki net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD net1 net7 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp3 net1 net0 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4_13 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4_13_64 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4_55 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.cdl b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.cdl
index 71e4012..d5b82a2 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.cdl
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.cdl
@@ -14,32 +14,32 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1 D RN CLKN Q VDD VNW VPW VSS
*.PININFO D:I RN:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn13 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn11 net6 D VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn15 net6 cki net1 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn14 net1 ncki net15 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn8 net12 net2 net15 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn9 VSS RN net12 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn18 VSS net1 net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn0 net8 ncki net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn1 net11 cki net8 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn12 net11 net4 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net0 RN VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn4 net4 net8 net0 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn3 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp11 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 VDD D net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net1 ncki net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net9 cki net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 VDD net2 net9 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net9 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 VDD net1 net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net2 cki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 ncki net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net4 RN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp4 VDD net8 net4 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp1 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn13 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn11 net6 D VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn15 net6 cki net1 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn14 net1 ncki net15 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn8 net12 net2 net15 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn9 VSS RN net12 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn18 VSS net1 net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn0 net8 ncki net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn1 net11 cki net8 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn12 net11 net4 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net0 RN VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn4 net4 net8 net0 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn3 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp11 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 VDD D net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net1 ncki net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net9 cki net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 VDD net2 net9 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net9 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 VDD net1 net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net2 cki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 ncki net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net4 RN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp4 VDD net8 net4 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp1 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.cdl b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.cdl
index 93d4ea9..71f916c 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.cdl
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.cdl
@@ -14,34 +14,34 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2 D RN CLKN Q VDD VNW VPW VSS
*.PININFO D:I RN:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn13 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn11 net6 D VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn15 net6 cki net1 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn14 net1 ncki net15 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn8 net12 net2 net15 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn9 VSS RN net12 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn18 VSS net1 net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn0 net8 ncki net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn1 net11 cki net8 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn12 net11 net4 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net0 RN VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn4 net4 net8 net0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3_42 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp11 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 VDD D net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net1 ncki net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net9 cki net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 VDD net2 net9 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net9 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 VDD net1 net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net2 cki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 ncki net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net4 RN VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4 VDD net8 net4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_40 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn13 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn11 net6 D VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn15 net6 cki net1 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn14 net1 ncki net15 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn8 net12 net2 net15 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn9 VSS RN net12 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn18 VSS net1 net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn0 net8 ncki net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn1 net11 cki net8 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn12 net11 net4 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net0 RN VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn4 net4 net8 net0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3_42 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp11 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 VDD D net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net1 ncki net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net9 cki net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 VDD net2 net9 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net9 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 VDD net1 net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net2 cki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 ncki net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net4 RN VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4 VDD net8 net4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_40 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.cdl b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.cdl
index 6ea6652..918ef5c 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.cdl
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.cdl
@@ -14,38 +14,38 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4 D RN CLKN Q VDD VNW VPW VSS
*.PININFO D:I RN:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn13 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn11 net6 D VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn15 net6 cki net1 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn14 net1 ncki net15 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn8 net12 net2 net15 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn9 VSS RN net12 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn18 VSS net1 net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn0 net8 ncki net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn1 net11 cki net8 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn12 net11 net4 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net0 RN VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn4 net4 net8 net0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3_42 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3_42_63 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3_69 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp11 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 VDD D net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net1 ncki net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net9 cki net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 VDD net2 net9 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net9 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 VDD net1 net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net2 cki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 ncki net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net4 RN VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4 VDD net8 net4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_40 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_40_64 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_66 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn13 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn11 net6 D VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn15 net6 cki net1 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn14 net1 ncki net15 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn8 net12 net2 net15 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn9 VSS RN net12 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn18 VSS net1 net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn0 net8 ncki net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn1 net11 cki net8 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn12 net11 net4 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net0 RN VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn4 net4 net8 net0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3_42 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3_42_63 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3_69 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp11 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 VDD D net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net1 ncki net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net9 cki net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 VDD net2 net9 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net9 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 VDD net1 net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net2 cki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 ncki net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net4 RN VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4 VDD net8 net4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_40 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_40_64 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_66 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.cdl b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.cdl
index 6203699..0b151ed 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.cdl
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.cdl
@@ -14,36 +14,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1 D RN SETN CLKN Q VDD VNW VPW VSS
*.PININFO D:I RN:I SETN:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn2 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn1 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 net14 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net14 cki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net3 ncki net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net15 net4 net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS RN net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net5 ncki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net7 cki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net1 SETN net7 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn16 VSS net6 net1 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn18 net2 RN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn17 net6 net5 net2 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn19 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp1 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 VDD D net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net3 ncki net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net13 cki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net13 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 VDD net3 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp20 net4 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp19 net5 ncki net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net7 SETN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp14 net7 net6 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp16 net6 RN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp15 VDD net5 net6 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp17 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn2 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn1 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 net14 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net14 cki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net3 ncki net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net15 net4 net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS RN net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net5 ncki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net7 cki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net1 SETN net7 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn16 VSS net6 net1 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn18 net2 RN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn17 net6 net5 net2 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn19 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp1 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 VDD D net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net3 ncki net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net13 cki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net13 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 VDD net3 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp20 net4 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp19 net5 ncki net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net7 SETN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp14 net7 net6 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp16 net6 RN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp15 VDD net5 net6 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp17 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.cdl b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.cdl
index 242e552..2cfb26a 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.cdl
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.cdl
@@ -14,38 +14,38 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2 D RN SETN CLKN Q VDD VNW VPW VSS
*.PININFO D:I RN:I SETN:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn2 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn1 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 net14 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net14 cki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net3 ncki net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net15 net4 net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS RN net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net5 ncki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net7 cki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net1 SETN net7 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn16 VSS net6 net1 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn18 net2 RN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn17 net6 net5 net2 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn19_16 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp1 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 VDD D net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net3 ncki net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net13 cki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net13 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 VDD net3 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp20 net4 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp19 net5 ncki net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net7 SETN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp14 net7 net6 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp16 net6 RN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp15 VDD net5 net6 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp17_9 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn2 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn1 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 net14 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net14 cki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net3 ncki net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net15 net4 net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS RN net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net5 ncki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net7 cki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net1 SETN net7 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn16 VSS net6 net1 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn18 net2 RN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn17 net6 net5 net2 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn19_16 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp1 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 VDD D net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net3 ncki net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net13 cki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net13 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 VDD net3 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp20 net4 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp19 net5 ncki net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net7 SETN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp14 net7 net6 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp16 net6 RN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp15 VDD net5 net6 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp17_9 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.cdl b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.cdl
index e352427..a60e695 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.cdl
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.cdl
@@ -14,42 +14,42 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4 D RN SETN CLKN Q VDD VNW VPW VSS
*.PININFO D:I RN:I SETN:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn2 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn1 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 net14 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net14 cki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net3 ncki net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net15 net4 net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS RN net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net5 ncki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net7 cki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net1 SETN net7 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn16 VSS net6 net1 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn18 net2 RN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn17 net6 net5 net2 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn19_16 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19_16_44 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19_64 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp1 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 VDD D net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net3 ncki net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net13 cki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net13 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 VDD net3 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp20 net4 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp19 net5 ncki net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net7 SETN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp14 net7 net6 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp16 net6 RN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp15 VDD net5 net6 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp17_9 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17_9_60 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17_57 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn2 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn1 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 net14 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net14 cki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net3 ncki net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net15 net4 net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS RN net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net5 ncki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net7 cki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net1 SETN net7 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn16 VSS net6 net1 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn18 net2 RN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn17 net6 net5 net2 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn19_16 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19_16_44 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19_64 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp1 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 VDD D net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net3 ncki net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net13 cki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net13 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 VDD net3 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp20 net4 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp19 net5 ncki net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net7 SETN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp14 net7 net6 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp16 net6 RN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp15 VDD net5 net6 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp17_9 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17_9_60 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17_57 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.cdl b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.cdl
index 4e4524d..e047d82 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.cdl
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.cdl
@@ -14,32 +14,32 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1 D SETN CLKN Q VDD VNW VPW VSS
*.PININFO D:I SETN:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn0 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn3 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net13 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net13 cki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net3 ncki net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 VSS net4 net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net5 ncki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net7 cki net5 VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn14 net1 SETN net7 VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn15 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net6 net5 VSS VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn16 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp0 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp4 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 VDD D net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net3 ncki net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net10 cki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net4 net3 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 net5 cki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp17 net7 ncki net5 VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp12 net7 SETN VDD VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp13 VDD net6 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 net5 VDD VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp14 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn0 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn3 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net13 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net13 cki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net3 ncki net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 VSS net4 net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net5 ncki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net7 cki net5 VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn14 net1 SETN net7 VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn15 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net6 net5 VSS VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn16 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp0 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp4 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 VDD D net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net3 ncki net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net10 cki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net4 net3 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 net5 cki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp17 net7 ncki net5 VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp12 net7 SETN VDD VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp13 VDD net6 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 net5 VDD VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp14 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.cdl b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.cdl
index 564400b..d8516ae 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.cdl
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.cdl
@@ -14,34 +14,34 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2 D SETN CLKN Q VDD VNW VPW VSS
*.PININFO D:I SETN:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn0 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn3 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net13 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net13 cki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net3 ncki net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 VSS net4 net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net5 ncki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net7 cki net5 VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn14 net1 SETN net7 VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn15 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net6 net5 VSS VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn16_30 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp0 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp4 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 VDD D net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net3 ncki net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net10 cki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net4 net3 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 net5 cki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp17 net7 ncki net5 VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp12 net7 SETN VDD VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp13 VDD net6 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 net5 VDD VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp14_24 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn0 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn3 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net13 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net13 cki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net3 ncki net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 VSS net4 net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net5 ncki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net7 cki net5 VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn14 net1 SETN net7 VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn15 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net6 net5 VSS VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn16_30 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp0 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp4 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 VDD D net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net3 ncki net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net10 cki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net4 net3 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 net5 cki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp17 net7 ncki net5 VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp12 net7 SETN VDD VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp13 VDD net6 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 net5 VDD VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp14_24 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.cdl b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.cdl
index 356128b..d2c59e6 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.cdl
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.cdl
@@ -14,38 +14,38 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4 D SETN CLKN Q VDD VNW VPW VSS
*.PININFO D:I SETN:I CLKN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn0 ncki CLKN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn3 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net13 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net13 cki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net3 ncki net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 VSS net4 net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net5 ncki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net7 cki net5 VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn14 net1 SETN net7 VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn15 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net6 net5 VSS VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn16_30 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16_30_46 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16_51 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp0 ncki CLKN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp4 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 VDD D net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net3 ncki net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net10 cki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net4 net3 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 net5 cki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp17 net7 ncki net5 VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp12 net7 SETN VDD VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp13 VDD net6 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 net5 VDD VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp14_24 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14_24_63 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14_44 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn0 ncki CLKN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn3 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net13 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net13 cki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net3 ncki net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 VSS net4 net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net5 ncki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net7 cki net5 VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn14 net1 SETN net7 VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn15 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net6 net5 VSS VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn16_30 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16_30_46 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16_51 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp0 ncki CLKN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp4 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 VDD D net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net3 ncki net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net10 cki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net4 net3 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 net5 cki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp17 net7 ncki net5 VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp12 net7 SETN VDD VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp13 VDD net6 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 net5 VDD VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp14_24 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14_24_63 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14_44 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_1.cdl b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_1.cdl
index 67071c6..6a6f0c3 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_1.cdl
+++ b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_1.cdl
@@ -14,28 +14,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffq_1 D CLK Q VDD VNW VPW VSS
*.PININFO D:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 VSS CLK ncki VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn4 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn5 net5 ncki VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn8 net4 D net5 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn6 net6 cki net4 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn7 VSS net0 net6 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn0 net0 net4 VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn9 net2 cki net0 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn11 net1 ncki net2 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn12 VSS net3 net1 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn10 net3 net2 VSS VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn1 Q net3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp3 VDD CLK ncki VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp4 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp12 net7 cki VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp11 net4 D net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net8 ncki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net0 net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net0 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net2 ncki net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net1x cki net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 VDD net3 net1x VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net3 net2 VDD VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp1 Q net3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn3 VSS CLK ncki VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn4 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn5 net5 ncki VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn8 net4 D net5 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn6 net6 cki net4 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn7 VSS net0 net6 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn0 net0 net4 VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn9 net2 cki net0 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn11 net1 ncki net2 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn12 VSS net3 net1 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn10 net3 net2 VSS VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn1 Q net3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp3 VDD CLK ncki VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp4 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp12 net7 cki VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp11 net4 D net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net8 ncki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net0 net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net0 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net2 ncki net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net1x cki net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 VDD net3 net1x VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net3 net2 VDD VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp1 Q net3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_2.cdl b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_2.cdl
index 0bc26ab..217b9f5 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_2.cdl
+++ b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_2.cdl
@@ -14,30 +14,30 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffq_2 D CLK Q VDD VNW VPW VSS
*.PININFO D:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 VSS CLK ncki VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn4 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn5 net5 ncki VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn8 net4 D net5 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn6 net6 cki net4 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn7 VSS net0 net6 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn0 net0 net4 VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn9 net2 cki net0 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn11 net1 ncki net2 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn12 VSS net3 net1 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn10 net3 net2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1 Q net3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_18 Q net3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp3 VDD CLK ncki VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp4 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp12 net7 cki VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp11 net4 D net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net8 ncki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net0 net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net0 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net2 ncki net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net1x cki net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 VDD net3 net1x VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net3 net2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1 Q net3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_16 Q net3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn3 VSS CLK ncki VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn4 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn5 net5 ncki VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn8 net4 D net5 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn6 net6 cki net4 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn7 VSS net0 net6 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn0 net0 net4 VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn9 net2 cki net0 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn11 net1 ncki net2 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn12 VSS net3 net1 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn10 net3 net2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1 Q net3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_18 Q net3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp3 VDD CLK ncki VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp4 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp12 net7 cki VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp11 net4 D net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net8 ncki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net0 net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net0 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net2 ncki net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net1x cki net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 VDD net3 net1x VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net3 net2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1 Q net3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_16 Q net3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_4.cdl b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_4.cdl
index f7c50a4..7919606 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_4.cdl
+++ b/cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_4.cdl
@@ -14,36 +14,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffq_4 D CLK Q VDD VNW VPW VSS
*.PININFO D:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 VSS CLK ncki VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn4 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn5 net5 ncki VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn8 net4 D net5 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn6 net6 cki net4 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn7 VSS net0 net6 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn0 net0 net4 VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn9 net2 cki net0 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn11 net1 ncki net2 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn12 VSS net3 net1 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn10 net3 net2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn10_6 net3 net2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_39 Q net3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_18_47 Q net3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1 Q net3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_18 Q net3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp3 VDD CLK ncki VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp4 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp12 net7 cki VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp11 net4 D net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net8 ncki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net0 net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net0 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net2 ncki net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net1x cki net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 VDD net3 net1x VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net3 net2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp8_10 net3 net2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_58 Q net3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_16_34 Q net3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1 Q net3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_16 Q net3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn3 VSS CLK ncki VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn4 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn5 net5 ncki VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn8 net4 D net5 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn6 net6 cki net4 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn7 VSS net0 net6 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn0 net0 net4 VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn9 net2 cki net0 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn11 net1 ncki net2 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn12 VSS net3 net1 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn10 net3 net2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn10_6 net3 net2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_39 Q net3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_18_47 Q net3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1 Q net3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_18 Q net3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp3 VDD CLK ncki VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp4 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp12 net7 cki VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp11 net4 D net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net8 ncki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net0 net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net0 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net2 ncki net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net1x cki net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 VDD net3 net1x VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net3 net2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp8_10 net3 net2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_58 Q net3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_16_34 Q net3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1 Q net3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_16 Q net3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.cdl b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.cdl
index 1224602..452a056 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.cdl
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.cdl
@@ -14,32 +14,32 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffrnq_1 D RN CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn10 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn13 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn11 net10 D VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn15 net10 ncki net1 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn14 net1 cki net15 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn8 net12 net2 net15 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn9 VSS RN net12 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn18 VSS net1 net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn0 net8 cki net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn1 net11 ncki net8 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn12 net11 net4 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net0 RN VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn4 net4 net8 net0 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn3 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp8 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp11 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 VDD D net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net1 cki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net9 ncki net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 VDD net2 net9 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net9 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 VDD net1 net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net2 ncki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 cki net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net4 RN VDD VNW pmos_5p0 W=0.980000U L=0.500000U
-M_tp4 VDD net8 net4 VNW pmos_5p0 W=0.980000U L=0.500000U
-M_tp1 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn10 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn13 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn11 net10 D VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn15 net10 ncki net1 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn14 net1 cki net15 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn8 net12 net2 net15 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn9 VSS RN net12 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn18 VSS net1 net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn0 net8 cki net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn1 net11 ncki net8 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn12 net11 net4 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net0 RN VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn4 net4 net8 net0 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn3 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp8 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp11 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 VDD D net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net1 cki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net9 ncki net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 VDD net2 net9 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net9 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 VDD net1 net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net2 ncki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 cki net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net4 RN VDD VNW pfet_05v0 W=0.980000U L=0.500000U
+M_tp4 VDD net8 net4 VNW pfet_05v0 W=0.980000U L=0.500000U
+M_tp1 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.cdl b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.cdl
index 02c0ac4..433ece9 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.cdl
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.cdl
@@ -14,34 +14,34 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffrnq_2 D RN CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn10 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn13 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn11 net10 D VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn15 net10 ncki net1 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn14 net1 cki net15 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn8 net12 net2 net15 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn9 VSS RN net12 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn18 VSS net1 net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn0 net8 cki net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn1 net11 ncki net8 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn12 net11 net4 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net0 RN VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn4 net4 net8 net0 VPW nmos_5p0 W=1.180000U L=0.600000U
-M_tn3_15 Q net4 VSS VPW nmos_5p0 W=1.250000U L=0.600000U
-M_tn3 Q net4 VSS VPW nmos_5p0 W=1.250000U L=0.600000U
-M_tp8 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp11 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 VDD D net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net1 cki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net9 ncki net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 VDD net2 net9 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net9 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 VDD net1 net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net2 ncki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 cki net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net4 RN VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4 VDD net8 net4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_13 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn10 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn13 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn11 net10 D VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn15 net10 ncki net1 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn14 net1 cki net15 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn8 net12 net2 net15 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn9 VSS RN net12 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn18 VSS net1 net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn0 net8 cki net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn1 net11 ncki net8 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn12 net11 net4 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net0 RN VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn4 net4 net8 net0 VPW nfet_05v0 W=1.180000U L=0.600000U
+M_tn3_15 Q net4 VSS VPW nfet_05v0 W=1.250000U L=0.600000U
+M_tn3 Q net4 VSS VPW nfet_05v0 W=1.250000U L=0.600000U
+M_tp8 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp11 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 VDD D net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net1 cki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net9 ncki net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 VDD net2 net9 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net9 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 VDD net1 net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net2 ncki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 cki net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net4 RN VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4 VDD net8 net4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_13 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.cdl b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.cdl
index 14058a7..b35e898 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.cdl
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.cdl
@@ -14,38 +14,38 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffrnq_4 D RN CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn10 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn13 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn11 net10 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net10 ncki net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net1 cki net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net12 net2 net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn9 VSS RN net12 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 VSS net1 net2 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn0 net8 cki net2 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net11 ncki net8 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net11 net4 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net0 RN VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net4 net8 net0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3_15 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3_15_13 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3_10 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp8 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp11 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 VDD D net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net1 cki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net9 ncki net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 VDD net2 net9 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net9 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 VDD net1 net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net2 ncki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 cki net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net4 RN VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4 VDD net8 net4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_13 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_13_25 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_30 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn10 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn13 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn11 net10 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net10 ncki net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net1 cki net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net12 net2 net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn9 VSS RN net12 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 VSS net1 net2 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn0 net8 cki net2 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net11 ncki net8 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net11 net4 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net0 RN VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net4 net8 net0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3_15 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3_15_13 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3_10 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp8 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp11 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 VDD D net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net1 cki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net9 ncki net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 VDD net2 net9 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net9 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 VDD net1 net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net2 ncki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 cki net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net4 RN VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4 VDD net8 net4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_13 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_13_25 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_30 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.cdl b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.cdl
index d1b30b3..d8a2596 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.cdl
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.cdl
@@ -14,36 +14,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1 D RN SETN CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I SETN:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn1 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn2 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 net14 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net14 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net3 cki net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net15 net4 net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS RN net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net1 SETN net7 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn16 VSS net6 net1 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn18 net2 RN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn17 net6 net5 net2 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn19 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp1 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp2 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 VDD D net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net3 cki net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net13 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net13 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 VDD net3 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp20 net4 ncki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp19 net5 cki net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net7 SETN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp14 net7 net6 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp16 net6 RN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp15 VDD net5 net6 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp17 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn1 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn2 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 net14 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net14 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net3 cki net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net15 net4 net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS RN net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net1 SETN net7 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn16 VSS net6 net1 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn18 net2 RN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn17 net6 net5 net2 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn19 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp1 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp2 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 VDD D net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net3 cki net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net13 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net13 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 VDD net3 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp20 net4 ncki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp19 net5 cki net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net7 SETN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp14 net7 net6 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp16 net6 RN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp15 VDD net5 net6 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp17 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.cdl b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.cdl
index e5b4020..12af342 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.cdl
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.cdl
@@ -14,38 +14,38 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2 D RN SETN CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I SETN:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn1 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn2 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 net14 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net14 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net3 cki net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net15 net4 net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS RN net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net1 SETN net7 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn16 VSS net6 net1 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn18 net2 RN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn17 net6 net5 net2 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn19_39 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp1 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp2 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 VDD D net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net3 cki net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net13 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net13 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 VDD net3 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp20 net4 ncki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp19 net5 cki net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net7 SETN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp14 net7 net6 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp16 net6 RN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp15 VDD net5 net6 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp17_33 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn1 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn2 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 net14 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net14 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net3 cki net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net15 net4 net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS RN net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net1 SETN net7 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn16 VSS net6 net1 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn18 net2 RN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn17 net6 net5 net2 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn19_39 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp1 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp2 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 VDD D net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net3 cki net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net13 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net13 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 VDD net3 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp20 net4 ncki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp19 net5 cki net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net7 SETN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp14 net7 net6 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp16 net6 RN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp15 VDD net5 net6 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp17_33 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.cdl b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.cdl
index bdc0677..eacabf0 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.cdl
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.cdl
@@ -14,42 +14,42 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4 D RN SETN CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I SETN:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn1 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn2 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 net14 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net14 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net3 cki net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net15 net4 net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS RN net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net1 SETN net7 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn16 VSS net6 net1 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn18 net2 RN VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn17 net6 net5 net2 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn19_39 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19_39_20 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19_24 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp1 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp2 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 VDD D net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net3 cki net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net13 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net13 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 VDD net3 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp20 net4 ncki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp19 net5 cki net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net7 SETN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp14 net7 net6 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp16 net6 RN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp15 VDD net5 net6 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp17_33 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17_33_0 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17_16 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn1 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn2 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 net14 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net14 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net3 cki net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net15 net4 net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS RN net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net1 SETN net7 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn16 VSS net6 net1 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn18 net2 RN VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn17 net6 net5 net2 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn19_39 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19_39_20 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19_24 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp1 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp2 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 VDD D net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net3 cki net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net13 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net13 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 VDD net3 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp20 net4 ncki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp19 net5 cki net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net7 SETN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp14 net7 net6 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp16 net6 RN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp15 VDD net5 net6 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp17_33 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17_33_0 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17_16 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.cdl b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.cdl
index 7266383..b513c28 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.cdl
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.cdl
@@ -14,32 +14,32 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffsnq_1 D SETN CLK Q VDD VNW VPW VSS
*.PININFO D:I SETN:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net13 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net13 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net3 cki net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 VSS net4 net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net1 SETN net7 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net6 net5 VSS VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn16 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp4 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 VDD D net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net3 cki net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net10 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net4 net3 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 net5 ncki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp17 net7 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net7 SETN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 VDD net6 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 net5 VDD VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp14 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn3 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net13 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net13 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net3 cki net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 VSS net4 net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net1 SETN net7 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net6 net5 VSS VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn16 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp4 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 VDD D net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net3 cki net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net10 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net4 net3 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 net5 ncki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp17 net7 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net7 SETN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 VDD net6 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 net5 VDD VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp14 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.cdl b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.cdl
index 326f6e9..0b862de 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.cdl
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.cdl
@@ -14,34 +14,34 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffsnq_2 D SETN CLK Q VDD VNW VPW VSS
*.PININFO D:I SETN:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net13 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net13 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net3 cki net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 VSS net4 net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net1 SETN net7 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net6 net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16_7 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp4 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 VDD D net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net3 cki net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net10 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net4 net3 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 net5 ncki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp17 net7 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net7 SETN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 VDD net6 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14_2 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn3 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net13 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net13 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net3 cki net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 VSS net4 net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net1 SETN net7 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net6 net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16_7 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp4 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 VDD D net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net3 cki net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net10 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net4 net3 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 net5 ncki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp17 net7 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net7 SETN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 VDD net6 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14_2 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.cdl b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.cdl
index 7b23ace..cd83c64 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.cdl
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.cdl
@@ -14,40 +14,40 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dffsnq_4 D SETN CLK Q VDD VNW VPW VSS
*.PININFO D:I SETN:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net13 D VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net13 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net3 cki net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 VSS net4 net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net1 SETN net7 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net6 net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn18_45 net6 net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16_7 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16_23 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16_7_36 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp4 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 VDD D net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net3 cki net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net10 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net4 net3 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 net5 ncki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp17 net7 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net7 SETN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 VDD net6 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp16_52 net6 net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14_2 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14_19 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14_2_27 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn3 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net13 D VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net13 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net3 cki net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 VSS net4 net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net1 SETN net7 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net6 net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn18_45 net6 net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16_7 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16_23 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16_7_36 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp4 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 VDD D net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net3 cki net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net10 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net4 net3 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 net5 ncki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp17 net7 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net7 SETN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 VDD net6 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp16_52 net6 net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14_2 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14_19 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14_2_27 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_1.cdl b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_1.cdl
index ec51cf6..3b9defd 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_1.cdl
+++ b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_1.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlya_1 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 VSS Z_neg net_2 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_3 net_2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 VDD Z_neg net_2 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_3 net_2 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 VSS Z_neg net_2 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_3 net_2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 VDD Z_neg net_2 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_3 net_2 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_2.cdl b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_2.cdl
index 3990360..0e1f213 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_2.cdl
+++ b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_2.cdl
@@ -15,14 +15,14 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlya_2 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 VSS Z_neg net_2 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_3 net_2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_1 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 VDD Z_neg net_2 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_3 net_2 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_14 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 VSS Z_neg net_2 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_3 net_2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_1 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 VDD Z_neg net_2 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_3 net_2 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_14 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_4.cdl b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_4.cdl
index 57c80c0..6ab82b0 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_4.cdl
+++ b/cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_4.cdl
@@ -15,18 +15,18 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlya_4 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 VSS Z_neg net_2 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_3 net_2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_1 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_2 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_1_15 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 VDD Z_neg net_2 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_3 net_2 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_14 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_34 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_14_19 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 VSS Z_neg net_2 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_3 net_2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_1 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_2 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_1_15 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 VDD Z_neg net_2 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_3 net_2 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_14 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_34 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_14_19 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_1.cdl b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_1.cdl
index 071004a..764caec 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_1.cdl
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_1.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlyb_1 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 net_2 Z_neg net_1 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3 net_1 Z_neg VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_21 net_3 net_2 net_6 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_6 net_2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0 net_0 Z_neg VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 net_2 Z_neg net_0 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_5 net_2 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_39 net_3 net_2 net_5 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 net_2 Z_neg net_1 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3 net_1 Z_neg VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_21 net_3 net_2 net_6 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_6 net_2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0 net_0 Z_neg VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 net_2 Z_neg net_0 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_5 net_2 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_39 net_3 net_2 net_5 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_2.cdl b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_2.cdl
index 67398b1..f744114 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_2.cdl
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_2.cdl
@@ -15,18 +15,18 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlyb_2 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 net_2 Z_neg net_1 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3 net_1 Z_neg VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_21 net_3 net_2 net_6 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_6 net_2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_1 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0 net_0 Z_neg VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 net_2 Z_neg net_0 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_5 net_2 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_39 net_3 net_2 net_5 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_14 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 net_2 Z_neg net_1 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3 net_1 Z_neg VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_21 net_3 net_2 net_6 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_6 net_2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_1 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0 net_0 Z_neg VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 net_2 Z_neg net_0 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_5 net_2 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_39 net_3 net_2 net_5 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_14 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_4.cdl b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_4.cdl
index 02012f2..715eb7a 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_4.cdl
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_4.cdl
@@ -15,22 +15,22 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlyb_4 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 net_2 Z_neg net_1 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3 net_1 Z_neg VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_21 net_3 net_2 net_6 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_6 net_2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_1 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_2 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_1_15 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0 net_0 Z_neg VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 net_2 Z_neg net_0 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_5 net_2 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_39 net_3 net_2 net_5 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_14 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_34 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_14_19 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 net_2 Z_neg net_1 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3 net_1 Z_neg VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_21 net_3 net_2 net_6 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_6 net_2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_1 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_2 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_1_15 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0 net_0 Z_neg VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 net_2 Z_neg net_0 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_5 net_2 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_39 net_3 net_2 net_5 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_14 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_34 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_14_19 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_1.cdl b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_1.cdl
index 21143d8..e52a211 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_1.cdl
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_1.cdl
@@ -15,24 +15,24 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlyc_1 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 net_7 Z_neg net_1 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3 net_1 Z_neg VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_26 net_9 net_7 net_13 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_30 net_13 net_7 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_0 net_8 net_9 net_11 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_4 net_11 net_9 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_21 net_3 net_8 net_6 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_6 net_8 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0 net_0 Z_neg VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 net_7 Z_neg net_0 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_35 net_12 net_7 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_47 net_9 net_7 net_12 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_9 net_10 net_9 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_22 net_8 net_9 net_10 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_5 net_8 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_39 net_3 net_8 net_5 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 net_7 Z_neg net_1 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3 net_1 Z_neg VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_26 net_9 net_7 net_13 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_30 net_13 net_7 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_0 net_8 net_9 net_11 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_4 net_11 net_9 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_21 net_3 net_8 net_6 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_6 net_8 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0 net_0 Z_neg VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 net_7 Z_neg net_0 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_35 net_12 net_7 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_47 net_9 net_7 net_12 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_9 net_10 net_9 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_22 net_8 net_9 net_10 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_5 net_8 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_39 net_3 net_8 net_5 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_2.cdl b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_2.cdl
index 29faa91..4348729 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_2.cdl
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_2.cdl
@@ -15,26 +15,26 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlyc_2 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 net_7 Z_neg net_1 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3 net_1 Z_neg VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_26 net_9 net_7 net_13 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_30 net_13 net_7 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_0 net_8 net_9 net_11 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_4 net_11 net_9 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_21 net_3 net_8 net_6 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_6 net_8 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_2 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0 net_0 Z_neg VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 net_7 Z_neg net_0 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_35 net_12 net_7 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_47 net_9 net_7 net_12 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_9 net_10 net_9 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_22 net_8 net_9 net_10 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_5 net_8 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_39 net_3 net_8 net_5 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_16 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 net_7 Z_neg net_1 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3 net_1 Z_neg VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_26 net_9 net_7 net_13 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_30 net_13 net_7 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_0 net_8 net_9 net_11 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_4 net_11 net_9 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_21 net_3 net_8 net_6 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_6 net_8 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_2 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0 net_0 Z_neg VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 net_7 Z_neg net_0 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_35 net_12 net_7 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_47 net_9 net_7 net_12 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_9 net_10 net_9 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_22 net_8 net_9 net_10 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_5 net_8 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_39 net_3 net_8 net_5 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_16 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_4.cdl b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_4.cdl
index ab1f57e..ee6c828 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_4.cdl
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_4.cdl
@@ -15,30 +15,30 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlyc_4 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 net_7 Z_neg net_1 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3 net_1 Z_neg VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_26 net_9 net_7 net_13 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_30 net_13 net_7 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_0 net_8 net_9 net_11 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_4 net_11 net_9 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_21 net_3 net_8 net_6 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_6 net_8 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_2 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_1 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_2_36 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0 net_0 Z_neg VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 net_7 Z_neg net_0 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_35 net_12 net_7 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_47 net_9 net_7 net_12 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_9 net_10 net_9 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_22 net_8 net_9 net_10 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_5 net_8 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_39 net_3 net_8 net_5 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_16 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_32 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_16_16 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 net_7 Z_neg net_1 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3 net_1 Z_neg VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_26 net_9 net_7 net_13 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_30 net_13 net_7 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_0 net_8 net_9 net_11 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_4 net_11 net_9 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_21 net_3 net_8 net_6 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_6 net_8 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_2 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_1 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_2_36 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0 net_0 Z_neg VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 net_7 Z_neg net_0 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_35 net_12 net_7 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_47 net_9 net_7 net_12 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_9 net_10 net_9 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_22 net_8 net_9 net_10 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_5 net_8 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_39 net_3 net_8 net_5 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_16 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_32 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_16_16 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_1.cdl b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_1.cdl
index d9a4f77..2c291a0 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_1.cdl
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_1.cdl
@@ -15,32 +15,32 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlyd_1 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 net_7 Z_neg net_1 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3 net_1 Z_neg VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_26 net_9 net_7 net_13 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_30 net_13 net_7 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_0 net_15 net_9 net_11 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_4 net_11 net_9 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_26_13 net_16 net_15 net_18 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_30_34 net_18 net_15 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_10 net_14 net_16 net_19 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_4_49 net_19 net_16 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_21 net_3 net_14 net_6 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_6 net_14 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0 net_0 Z_neg VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 net_7 Z_neg net_0 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_35 net_12 net_7 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_47 net_9 net_7 net_12 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_9 net_10 net_9 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_22 net_15 net_9 net_10 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_35_50 net_17 net_15 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_47_46 net_16 net_15 net_17 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_9_2 net_20 net_16 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_22_38 net_14 net_16 net_20 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_5 net_14 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_39 net_3 net_14 net_5 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 net_7 Z_neg net_1 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3 net_1 Z_neg VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_26 net_9 net_7 net_13 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_30 net_13 net_7 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_0 net_15 net_9 net_11 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_4 net_11 net_9 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_26_13 net_16 net_15 net_18 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_30_34 net_18 net_15 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_10 net_14 net_16 net_19 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_4_49 net_19 net_16 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_21 net_3 net_14 net_6 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_6 net_14 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0 net_0 Z_neg VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 net_7 Z_neg net_0 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_35 net_12 net_7 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_47 net_9 net_7 net_12 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_9 net_10 net_9 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_22 net_15 net_9 net_10 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_35_50 net_17 net_15 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_47_46 net_16 net_15 net_17 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_9_2 net_20 net_16 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_22_38 net_14 net_16 net_20 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_5 net_14 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_39 net_3 net_14 net_5 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_2.cdl b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_2.cdl
index 830433b..5776498 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_2.cdl
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_2.cdl
@@ -15,34 +15,34 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlyd_2 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 net_7 Z_neg net_1 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3 net_1 Z_neg VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_26 net_9 net_7 net_13 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_30 net_13 net_7 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_0 net_15 net_9 net_11 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_4 net_11 net_9 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_26_13 net_16 net_15 net_18 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_30_34 net_18 net_15 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_10 net_14 net_16 net_19 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_4_49 net_19 net_16 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_21 net_3 net_14 net_6 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_6 net_14 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_1 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0 net_0 Z_neg VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 net_7 Z_neg net_0 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_35 net_12 net_7 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_47 net_9 net_7 net_12 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_9 net_10 net_9 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_22 net_15 net_9 net_10 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_35_50 net_17 net_15 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_47_46 net_16 net_15 net_17 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_9_2 net_20 net_16 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_22_38 net_14 net_16 net_20 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_5 net_14 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_39 net_3 net_14 net_5 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_14 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 net_7 Z_neg net_1 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3 net_1 Z_neg VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_26 net_9 net_7 net_13 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_30 net_13 net_7 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_0 net_15 net_9 net_11 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_4 net_11 net_9 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_26_13 net_16 net_15 net_18 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_30_34 net_18 net_15 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_10 net_14 net_16 net_19 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_4_49 net_19 net_16 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_21 net_3 net_14 net_6 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_6 net_14 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_1 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0 net_0 Z_neg VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 net_7 Z_neg net_0 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_35 net_12 net_7 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_47 net_9 net_7 net_12 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_9 net_10 net_9 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_22 net_15 net_9 net_10 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_35_50 net_17 net_15 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_47_46 net_16 net_15 net_17 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_9_2 net_20 net_16 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_22_38 net_14 net_16 net_20 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_5 net_14 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_39 net_3 net_14 net_5 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_14 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_4.cdl b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_4.cdl
index 198fc11..7bc5178 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_4.cdl
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_4.cdl
@@ -15,38 +15,38 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__dlyd_4 I Z VDD VNW VPW VSS
*.PININFO I:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=I
-M_i_2_0 Z_neg I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 net_7 Z_neg net_1 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3 net_1 Z_neg VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_26 net_9 net_7 net_13 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_30 net_13 net_7 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_0 net_15 net_9 net_11 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_4 net_11 net_9 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_26_13 net_16 net_15 net_18 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_30_34 net_18 net_15 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_10 net_14 net_16 net_19 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_4_49 net_19 net_16 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_21 net_3 net_14 net_6 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_3_6 net_6 net_14 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2_0_18 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_1 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_2 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0_18_1_15 Z net_3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 Z_neg I VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0 net_0 Z_neg VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1 net_7 Z_neg net_0 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_35 net_12 net_7 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_47 net_9 net_7 net_12 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_9 net_10 net_9 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_22 net_15 net_9 net_10 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_35_50 net_17 net_15 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_47_46 net_16 net_15 net_17 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_9_2 net_20 net_16 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_22_38 net_14 net_16 net_20 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_0_29 net_5 net_14 VDD VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_1_39 net_3 net_14 net_5 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_3_0_0 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_14 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_34 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0_0_14_19 Z net_3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_0 Z_neg I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 net_7 Z_neg net_1 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3 net_1 Z_neg VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_26 net_9 net_7 net_13 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_30 net_13 net_7 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_0 net_15 net_9 net_11 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_4 net_11 net_9 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_26_13 net_16 net_15 net_18 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_30_34 net_18 net_15 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_10 net_14 net_16 net_19 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_4_49 net_19 net_16 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_21 net_3 net_14 net_6 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_3_6 net_6 net_14 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2_0_18 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_1 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_2 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0_18_1_15 Z net_3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 Z_neg I VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0 net_0 Z_neg VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1 net_7 Z_neg net_0 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_35 net_12 net_7 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_47 net_9 net_7 net_12 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_9 net_10 net_9 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_22 net_15 net_9 net_10 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_35_50 net_17 net_15 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_47_46 net_16 net_15 net_17 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_9_2 net_20 net_16 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_22_38 net_14 net_16 net_20 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_0_29 net_5 net_14 VDD VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_1_39 net_3 net_14 net_5 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_3_0_0 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_14 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_34 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0_0_14_19 Z net_3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_16.cdl b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_16.cdl
index 2bc5e33..3bc1ff5 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_16.cdl
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_16.cdl
@@ -14,12 +14,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__fillcap_16 VDD VNW VPW VSS
*.PININFO VDD:P VNW:P VPW:P VSS:G
-M_i_17 net_3 net_2 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23 net_4 net_5 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_24 net_7 net_9 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23_55 net_6 net_8 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_19 VDD net_3 net_2 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7 VDD net_4 net_5 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_33 VDD net_7 net_9 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7_23 VDD net_6 net_8 VNW pmos_5p0 W=1.830000U L=1.000000U
+M_i_17 net_3 net_2 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23 net_4 net_5 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_24 net_7 net_9 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23_55 net_6 net_8 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_19 VDD net_3 net_2 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7 VDD net_4 net_5 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_33 VDD net_7 net_9 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7_23 VDD net_6 net_8 VNW pfet_05v0 W=1.830000U L=1.000000U
.ENDS
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_32.cdl b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_32.cdl
index 0f4ba4b..1c40996 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_32.cdl
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_32.cdl
@@ -14,20 +14,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__fillcap_32 VDD VNW VPW VSS
*.PININFO VDD:P VNW:P VPW:P VSS:G
-M_i_17 net_3 net_2 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23 net_4 net_5 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_24 net_7 net_9 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23_55 net_6 net_8 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_27 net_17 net_14 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23_63 net_16 net_15 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_24_22 net_13 net_11 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23_55_93 net_12 net_10 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_19 VDD net_3 net_2 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7 VDD net_4 net_5 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_33 VDD net_7 net_9 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7_23 VDD net_6 net_8 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_94 VDD net_17 net_14 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7_87 VDD net_16 net_15 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_33_95 VDD net_13 net_11 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7_23_23 VDD net_12 net_10 VNW pmos_5p0 W=1.830000U L=1.000000U
+M_i_17 net_3 net_2 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23 net_4 net_5 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_24 net_7 net_9 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23_55 net_6 net_8 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_27 net_17 net_14 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23_63 net_16 net_15 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_24_22 net_13 net_11 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23_55_93 net_12 net_10 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_19 VDD net_3 net_2 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7 VDD net_4 net_5 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_33 VDD net_7 net_9 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7_23 VDD net_6 net_8 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_94 VDD net_17 net_14 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7_87 VDD net_16 net_15 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_33_95 VDD net_13 net_11 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7_23_23 VDD net_12 net_10 VNW pfet_05v0 W=1.830000U L=1.000000U
.ENDS
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_4.cdl b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_4.cdl
index fff0680..dc3dc28 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_4.cdl
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_4.cdl
@@ -14,6 +14,6 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__fillcap_4 VDD VNW VPW VSS
*.PININFO VDD:P VNW:P VPW:P VSS:G
-M_i_17 net_1 net_0 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_19 VDD net_1 net_0 VNW pmos_5p0 W=1.830000U L=1.000000U
+M_i_17 net_1 net_0 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_19 VDD net_1 net_0 VNW pfet_05v0 W=1.830000U L=1.000000U
.ENDS
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_64.cdl b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_64.cdl
index 7ef00d4..8510157 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_64.cdl
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_64.cdl
@@ -14,36 +14,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__fillcap_64 VDD VNW VPW VSS
*.PININFO VDD:P VNW:P VPW:P VSS:G
-M_i_17 net_3 net_2 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23 net_4 net_5 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_24 net_7 net_9 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23_55 net_6 net_8 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_27 net_17 net_14 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23_63 net_16 net_15 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_24_22 net_13 net_11 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23_55_93 net_12 net_10 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_20 net_30 net_26 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23_59 net_25 net_20 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_24_135 net_23 net_28 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23_55_90 net_33 net_18 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_27_139 net_31 net_29 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23_63_82 net_32 net_24 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_24_22_30 net_22 net_27 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23_55_93_110 net_19 net_21 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_19 VDD net_3 net_2 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7 VDD net_4 net_5 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_33 VDD net_7 net_9 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7_23 VDD net_6 net_8 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_94 VDD net_17 net_14 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7_87 VDD net_16 net_15 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_33_95 VDD net_13 net_11 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7_23_23 VDD net_12 net_10 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_95 VDD net_30 net_26 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7_188 VDD net_25 net_20 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_33_98 VDD net_23 net_28 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7_23_16 VDD net_33 net_18 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_94_91 VDD net_31 net_29 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7_87_65 VDD net_32 net_24 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_33_95_109 VDD net_22 net_27 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7_23_23_99 VDD net_19 net_21 VNW pmos_5p0 W=1.830000U L=1.000000U
+M_i_17 net_3 net_2 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23 net_4 net_5 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_24 net_7 net_9 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23_55 net_6 net_8 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_27 net_17 net_14 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23_63 net_16 net_15 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_24_22 net_13 net_11 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23_55_93 net_12 net_10 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_20 net_30 net_26 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23_59 net_25 net_20 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_24_135 net_23 net_28 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23_55_90 net_33 net_18 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_27_139 net_31 net_29 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23_63_82 net_32 net_24 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_24_22_30 net_22 net_27 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23_55_93_110 net_19 net_21 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_19 VDD net_3 net_2 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7 VDD net_4 net_5 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_33 VDD net_7 net_9 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7_23 VDD net_6 net_8 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_94 VDD net_17 net_14 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7_87 VDD net_16 net_15 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_33_95 VDD net_13 net_11 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7_23_23 VDD net_12 net_10 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_95 VDD net_30 net_26 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7_188 VDD net_25 net_20 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_33_98 VDD net_23 net_28 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7_23_16 VDD net_33 net_18 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_94_91 VDD net_31 net_29 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7_87_65 VDD net_32 net_24 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_33_95_109 VDD net_22 net_27 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7_23_23_99 VDD net_19 net_21 VNW pfet_05v0 W=1.830000U L=1.000000U
.ENDS
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_8.cdl b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_8.cdl
index f45c023..21318e4 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_8.cdl
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_8.cdl
@@ -14,8 +14,8 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__fillcap_8 VDD VNW VPW VSS
*.PININFO VDD:P VNW:P VPW:P VSS:G
-M_i_17 net_3 net_2 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_17_23 net_4 net_5 VSS VPW nmos_5p0 W=1.320000U L=1.000000U
-M_i_19 VDD net_3 net_2 VNW pmos_5p0 W=1.830000U L=1.000000U
-M_i_19_7 VDD net_4 net_5 VNW pmos_5p0 W=1.830000U L=1.000000U
+M_i_17 net_3 net_2 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_17_23 net_4 net_5 VSS VPW nfet_05v0 W=1.320000U L=1.000000U
+M_i_19 VDD net_3 net_2 VNW pfet_05v0 W=1.830000U L=1.000000U
+M_i_19_7 VDD net_4 net_5 VNW pfet_05v0 W=1.830000U L=1.000000U
.ENDS
diff --git a/cells/hold/gf180mcu_fd_sc_mcu9t5v0__hold.cdl b/cells/hold/gf180mcu_fd_sc_mcu9t5v0__hold.cdl
index 2db946c..75313b5 100644
--- a/cells/hold/gf180mcu_fd_sc_mcu9t5v0__hold.cdl
+++ b/cells/hold/gf180mcu_fd_sc_mcu9t5v0__hold.cdl
@@ -14,8 +14,8 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__hold Z VDD VNW VPW VSS
*.PININFO Z:B VDD:P VNW:P VPW:P VSS:G
-M_u7 VDD Z net8 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_u3 VSS Z net8 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MU12 Z net8 VDD VNW pmos_5p0 W=0.360000U L=2.00000U
-M_MU11 Z net8 VSS VPW nmos_5p0 W=0.360000U L=2.00000U
+M_u7 VDD Z net8 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_u3 VSS Z net8 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MU12 Z net8 VDD VNW pfet_05v0 W=0.360000U L=2.00000U
+M_MU11 Z net8 VSS VPW nfet_05v0 W=0.360000U L=2.00000U
.ENDS
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.cdl b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.cdl
index 3a9fa32..6c7a0a6 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.cdl
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.cdl
@@ -14,28 +14,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__icgtn_1 CLKN E TE Q VDD VNW VPW VSS
*.PININFO CLKN:I E:I TE:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_MU19 VSS TE net50 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU20 net50 E VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI82 net53 NCP net50 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI91 net038 CP net53 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI92 VSS QD net038 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU82_M_u2 NCP CP VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI95_M_u2 VSS net53 QD VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI89_M_u2 net36 QD VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU81_M_u2 VSS CLKN CP VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI1_M_u3 d3 net36 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI1_M_u4 VSS CLKN d3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU75_M_u2 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MI81 net58 TE VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU17 net61 E net58 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU16 net53 CP net61 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI90 net067 NCP net53 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI88 VDD QD net067 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU82_M_u3 NCP CP VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI95_M_u3 VDD net53 QD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI89_M_u3 net36 QD VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU81_M_u3 VDD CLKN CP VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI1_M_u1 XI1-net8 net36 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI1_M_u2 d3 CLKN XI1-net8 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU75_M_u3 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_MU19 VSS TE net50 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU20 net50 E VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI82 net53 NCP net50 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI91 net038 CP net53 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI92 VSS QD net038 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU82_M_u2 NCP CP VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI95_M_u2 VSS net53 QD VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI89_M_u2 net36 QD VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU81_M_u2 VSS CLKN CP VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI1_M_u3 d3 net36 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI1_M_u4 VSS CLKN d3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU75_M_u2 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MI81 net58 TE VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU17 net61 E net58 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU16 net53 CP net61 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI90 net067 NCP net53 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI88 VDD QD net067 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU82_M_u3 NCP CP VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI95_M_u3 VDD net53 QD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI89_M_u3 net36 QD VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU81_M_u3 VDD CLKN CP VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI1_M_u1 XI1-net8 net36 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI1_M_u2 d3 CLKN XI1-net8 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU75_M_u3 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.cdl b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.cdl
index 39a91fe..c6bf094 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.cdl
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.cdl
@@ -14,30 +14,30 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__icgtn_2 CLKN E TE Q VDD VNW VPW VSS
*.PININFO CLKN:I E:I TE:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_MU19 VSS TE net50 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU20 net50 E VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI82 net53 NCP net50 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI91 net038 CP net53 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI92 VSS QD net038 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU82_M_u2 NCP CP VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI95_M_u2 VSS net53 QD VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI89_M_u2 net36 QD VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU81_M_u2 VSS CLKN CP VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MI1_M_u3 d3 net36 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MI1_M_u4 VSS CLKN d3 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MU75_M_u2 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MU75_M_u2_19 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MI81 net58 TE VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU17 net61 E net58 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU16 net53 CP net61 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI90 net067 NCP net53 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI88 VDD QD net067 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU82_M_u3 NCP CP VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI95_M_u3 VDD net53 QD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI89_M_u3 net36 QD VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU81_M_u3 VDD CLKN CP VNW pmos_5p0 W=1.680000U L=0.500000U
-M_MI1_M_u1 XI1-net8 net36 VDD VNW pmos_5p0 W=1.680000U L=0.500000U
-M_MI1_M_u2 d3 CLKN XI1-net8 VNW pmos_5p0 W=1.680000U L=0.500000U
-M_MU75_M_u3 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MU75_M_u3_1 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_MU19 VSS TE net50 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU20 net50 E VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI82 net53 NCP net50 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI91 net038 CP net53 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI92 VSS QD net038 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU82_M_u2 NCP CP VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI95_M_u2 VSS net53 QD VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI89_M_u2 net36 QD VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU81_M_u2 VSS CLKN CP VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MI1_M_u3 d3 net36 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MI1_M_u4 VSS CLKN d3 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MU75_M_u2 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MU75_M_u2_19 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MI81 net58 TE VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU17 net61 E net58 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU16 net53 CP net61 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI90 net067 NCP net53 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI88 VDD QD net067 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU82_M_u3 NCP CP VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI95_M_u3 VDD net53 QD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI89_M_u3 net36 QD VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU81_M_u3 VDD CLKN CP VNW pfet_05v0 W=1.680000U L=0.500000U
+M_MI1_M_u1 XI1-net8 net36 VDD VNW pfet_05v0 W=1.680000U L=0.500000U
+M_MI1_M_u2 d3 CLKN XI1-net8 VNW pfet_05v0 W=1.680000U L=0.500000U
+M_MU75_M_u3 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MU75_M_u3_1 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.cdl b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.cdl
index ea5d674..7ffb713 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.cdl
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.cdl
@@ -14,34 +14,34 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__icgtn_4 CLKN E TE Q VDD VNW VPW VSS
*.PININFO CLKN:I E:I TE:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_MU19 VSS TE net50 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU20 net50 E VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI82 net53 NCP net50 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI91 net038 CP net53 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI92 VSS QD net038 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU82_M_u2 NCP CP VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI95_M_u2 VSS net53 QD VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI89_M_u2 net36 QD VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU81_M_u2 VSS CLKN CP VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MI1_M_u3 d3 net36 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MI1_M_u4 VSS CLKN d3 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MU75_M_u2 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MU75_M_u2_19 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MU75_M_u2_33 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MU75_M_u2_19_5 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MI81 net58 TE VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU17 net61 E net58 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU16 net53 CP net61 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI90 net067 NCP net53 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI88 VDD QD net067 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU82_M_u3 NCP CP VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI95_M_u3 VDD net53 QD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI89_M_u3 net36 QD VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU81_M_u3 VDD CLKN CP VNW pmos_5p0 W=1.680000U L=0.500000U
-M_MI1_M_u1 XI1-net8 net36 VDD VNW pmos_5p0 W=1.680000U L=0.500000U
-M_MI1_M_u2 d3 CLKN XI1-net8 VNW pmos_5p0 W=1.680000U L=0.500000U
-M_MU75_M_u3 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MU75_M_u3_1 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MU75_M_u3_2 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MU75_M_u3_1_35 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_MU19 VSS TE net50 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU20 net50 E VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI82 net53 NCP net50 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI91 net038 CP net53 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI92 VSS QD net038 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU82_M_u2 NCP CP VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI95_M_u2 VSS net53 QD VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI89_M_u2 net36 QD VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU81_M_u2 VSS CLKN CP VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MI1_M_u3 d3 net36 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MI1_M_u4 VSS CLKN d3 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MU75_M_u2 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MU75_M_u2_19 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MU75_M_u2_33 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MU75_M_u2_19_5 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MI81 net58 TE VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU17 net61 E net58 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU16 net53 CP net61 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI90 net067 NCP net53 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI88 VDD QD net067 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU82_M_u3 NCP CP VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI95_M_u3 VDD net53 QD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI89_M_u3 net36 QD VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU81_M_u3 VDD CLKN CP VNW pfet_05v0 W=1.680000U L=0.500000U
+M_MI1_M_u1 XI1-net8 net36 VDD VNW pfet_05v0 W=1.680000U L=0.500000U
+M_MI1_M_u2 d3 CLKN XI1-net8 VNW pfet_05v0 W=1.680000U L=0.500000U
+M_MU75_M_u3 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MU75_M_u3_1 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MU75_M_u3_2 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MU75_M_u3_1_35 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_1.cdl b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_1.cdl
index 4d6e718..989c54d 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_1.cdl
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_1.cdl
@@ -14,26 +14,26 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__icgtp_1 CLK E TE Q VDD VNW VPW VSS
*.PININFO CLK:I E:I TE:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_MU19 net50 TE VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU20 VSS E net50 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI82 net50 NCK net53 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI91 net53 CK net033 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI92 net033 QD VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI80_M_u2 VSS net53 QD VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU82_M_u2 VSS NCK CK VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU81_M_u2 NCK CLK VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI85_M_u3 XI85-net6 CLK d3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI85_M_u4 VSS QD XI85-net6 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU75_M_u2 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MI81 VDD TE net58 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU17 net58 E net61 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU16 net61 CK net53 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI90 net53 NCK net062 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI88 net062 QD VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI80_M_u3 VDD net53 QD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU82_M_u3 CK NCK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU81_M_u3 VDD CLK NCK VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI85_M_u1 d3 CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI85_M_u2 VDD QD d3 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU75_M_u3 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_MU19 net50 TE VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU20 VSS E net50 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI82 net50 NCK net53 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI91 net53 CK net033 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI92 net033 QD VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI80_M_u2 VSS net53 QD VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU82_M_u2 VSS NCK CK VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU81_M_u2 NCK CLK VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI85_M_u3 XI85-net6 CLK d3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI85_M_u4 VSS QD XI85-net6 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU75_M_u2 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MI81 VDD TE net58 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU17 net58 E net61 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU16 net61 CK net53 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI90 net53 NCK net062 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI88 net062 QD VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI80_M_u3 VDD net53 QD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU82_M_u3 CK NCK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU81_M_u3 VDD CLK NCK VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI85_M_u1 d3 CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI85_M_u2 VDD QD d3 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU75_M_u3 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.cdl b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.cdl
index 0f35b90..24bb349 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.cdl
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.cdl
@@ -14,28 +14,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__icgtp_2 CLK E TE Q VDD VNW VPW VSS
*.PININFO CLK:I E:I TE:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_MU19 net50 TE VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU20 VSS E net50 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI82 net50 NCK net53 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI91 net53 CK net033 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI92 net033 QD VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI80_M_u2 VSS net53 QD VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU82_M_u2 VSS NCK CK VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU81_M_u2 NCK CLK VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI85_M_u3 XI85-net6 CLK d3 VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MI85_M_u4 VSS QD XI85-net6 VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MU75_M_u2 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MU75_M_u2_22 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MI81 VDD TE net58 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU17 net58 E net61 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU16 net61 CK net53 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI90 net53 NCK net062 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI88 net062 QD VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI80_M_u3 VDD net53 QD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU82_M_u3 CK NCK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU81_M_u3 VDD CLK NCK VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI85_M_u1 d3 CLK VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MI85_M_u2 VDD QD d3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MU75_M_u3 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MU75_M_u3_3 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_MU19 net50 TE VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU20 VSS E net50 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI82 net50 NCK net53 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI91 net53 CK net033 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI92 net033 QD VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI80_M_u2 VSS net53 QD VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU82_M_u2 VSS NCK CK VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU81_M_u2 NCK CLK VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI85_M_u3 XI85-net6 CLK d3 VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MI85_M_u4 VSS QD XI85-net6 VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MU75_M_u2 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MU75_M_u2_22 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MI81 VDD TE net58 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU17 net58 E net61 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU16 net61 CK net53 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI90 net53 NCK net062 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI88 net062 QD VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI80_M_u3 VDD net53 QD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU82_M_u3 CK NCK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU81_M_u3 VDD CLK NCK VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI85_M_u1 d3 CLK VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MI85_M_u2 VDD QD d3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MU75_M_u3 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MU75_M_u3_3 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_4.cdl b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_4.cdl
index 4189e7c..3c12fcf 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_4.cdl
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_4.cdl
@@ -14,32 +14,32 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__icgtp_4 CLK E TE Q VDD VNW VPW VSS
*.PININFO CLK:I E:I TE:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_MU19 net50 TE VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU20 VSS E net50 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI82 net50 NCK net53 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI91 net53 CK net033 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI92 net033 QD VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI80_M_u2 VSS net53 QD VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU82_M_u2 VSS NCK CK VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MU81_M_u2 NCK CLK VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_MI85_M_u3 XI85-net6 CLK d3 VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MI85_M_u4 VSS QD XI85-net6 VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MU75_M_u2 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MU75_M_u2_22 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MU75_M_u2_41 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MU75_M_u2_22_37 Q d3 VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_MI81 VDD TE net58 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU17 net58 E net61 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU16 net61 CK net53 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI90 net53 NCK net062 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI88 net062 QD VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI80_M_u3 VDD net53 QD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU82_M_u3 CK NCK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MU81_M_u3 VDD CLK NCK VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MI85_M_u1 d3 CLK VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MI85_M_u2 VDD QD d3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MU75_M_u3 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MU75_M_u3_3 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MU75_M_u3_1 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MU75_M_u3_3_28 Q d3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_MU19 net50 TE VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU20 VSS E net50 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI82 net50 NCK net53 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI91 net53 CK net033 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI92 net033 QD VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI80_M_u2 VSS net53 QD VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU82_M_u2 VSS NCK CK VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MU81_M_u2 NCK CLK VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_MI85_M_u3 XI85-net6 CLK d3 VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MI85_M_u4 VSS QD XI85-net6 VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MU75_M_u2 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MU75_M_u2_22 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MU75_M_u2_41 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MU75_M_u2_22_37 Q d3 VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_MI81 VDD TE net58 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU17 net58 E net61 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU16 net61 CK net53 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI90 net53 NCK net062 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI88 net062 QD VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI80_M_u3 VDD net53 QD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU82_M_u3 CK NCK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MU81_M_u3 VDD CLK NCK VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MI85_M_u1 d3 CLK VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MI85_M_u2 VDD QD d3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MU75_M_u3 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MU75_M_u3_3 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MU75_M_u3_1 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MU75_M_u3_3_28 Q d3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_1.cdl b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_1.cdl
index a641247..67cf760 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_1.cdl
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_1.cdl
@@ -15,6 +15,6 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__inv_1 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_12.cdl b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_12.cdl
index c561f63..7e24155 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_12.cdl
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_12.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__inv_12 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_4 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_5 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_6 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_7 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_8 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_9 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_10 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_11 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_4 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_5 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_6 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_7 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_8 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_9 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_10 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_11 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_16.cdl b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_16.cdl
index 7d393a2..9d2d268 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_16.cdl
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_16.cdl
@@ -15,36 +15,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__inv_16 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_4 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_5 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_6 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_7 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_8 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_9 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_10 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_11 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_12 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_13 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_14 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_15 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_12 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_13 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_14 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_15 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_4 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_5 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_6 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_7 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_8 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_9 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_10 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_11 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_12 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_13 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_14 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_15 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_12 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_13 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_14 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_15 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_2.cdl b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_2.cdl
index 1a4c18c..f33ec25 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_2.cdl
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_2.cdl
@@ -15,8 +15,8 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__inv_2 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_20.cdl b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_20.cdl
index 1dc8cba..c2aa32f 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_20.cdl
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_20.cdl
@@ -15,44 +15,44 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__inv_20 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_4 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_5 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_6 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_7 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_8 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_9 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_10 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_11 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_12 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_13 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_14 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_15 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_16 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_17 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_18 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_19 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_4 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_5 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_6 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_7 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_8 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_9 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_10 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_11 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_12 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_13 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_14 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_15 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_16 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_17 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_18 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_19 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_4 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_5 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_6 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_7 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_8 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_9 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_10 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_11 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_12 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_13 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_14 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_15 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_16 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_17 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_18 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_19 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_4 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_5 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_6 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_7 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_8 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_9 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_10 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_11 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_12 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_13 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_14 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_15 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_16 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_17 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_18 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_19 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_3.cdl b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_3.cdl
index 9cd4ed6..e73beec 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_3.cdl
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_3.cdl
@@ -15,10 +15,10 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__inv_3 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_4.cdl b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_4.cdl
index 73c49d7..34ff9b8 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_4.cdl
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_4.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__inv_4 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_8.cdl b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_8.cdl
index 5762432..4074ce2 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_8.cdl
+++ b/cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_8.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__inv_8 I ZN VDD VNW VPW VSS
*.PININFO I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_i_0_0_x8_0 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0_x8_1 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0_x8_2 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0_x8_3 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0_x8_4 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0_x8_5 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0_x8_6 ZN I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0_x8_7 VSS I ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0_x8_0 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_1 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_2 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_3 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_4 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_5 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_6 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0_x8_7 VDD I ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_0_0_x8_0 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0_x8_1 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0_x8_2 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0_x8_3 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0_x8_4 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0_x8_5 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0_x8_6 ZN I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0_x8_7 VSS I ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0_x8_0 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_1 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_2 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_3 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_4 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_5 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_6 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0_x8_7 VDD I ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_1.cdl b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_1.cdl
index 2098228..98260ed 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_1.cdl
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_1.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__invz_1 EN I ZN VDD VNW VPW VSS
*.PININFO EN:I I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_mn VSS EN NEN VPW nmos_5p0 W=0.590000U L=0.600000U
-M_mn8 NI_N NEN VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_mn21 NI_P EN NI_N VPW nmos_5p0 W=0.590000U L=0.600000U
-M_mn3 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17 VSS NI NI_N VPW nmos_5p0 W=0.590000U L=0.600000U
-M_Mn_inv NI I VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_mp VDD EN NEN VNW pmos_5p0 W=0.990000U L=0.500000U
-M_mp7 NI_P EN VDD VNW pmos_5p0 W=0.990000U L=0.500000U
-M_mp22 NI_N NEN NI_P VNW pmos_5p0 W=0.990000U L=0.500000U
-M_mp4 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14 VDD NI NI_P VNW pmos_5p0 W=0.990000U L=0.500000U
-M_Mp_inv NI I VDD VNW pmos_5p0 W=0.990000U L=0.500000U
+M_mn VSS EN NEN VPW nfet_05v0 W=0.590000U L=0.600000U
+M_mn8 NI_N NEN VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_mn21 NI_P EN NI_N VPW nfet_05v0 W=0.590000U L=0.600000U
+M_mn3 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17 VSS NI NI_N VPW nfet_05v0 W=0.590000U L=0.600000U
+M_Mn_inv NI I VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_mp VDD EN NEN VNW pfet_05v0 W=0.990000U L=0.500000U
+M_mp7 NI_P EN VDD VNW pfet_05v0 W=0.990000U L=0.500000U
+M_mp22 NI_N NEN NI_P VNW pfet_05v0 W=0.990000U L=0.500000U
+M_mp4 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14 VDD NI NI_P VNW pfet_05v0 W=0.990000U L=0.500000U
+M_Mp_inv NI I VDD VNW pfet_05v0 W=0.990000U L=0.500000U
.ENDS
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_12.cdl b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_12.cdl
index 341ac6b..f70b075 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_12.cdl
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_12.cdl
@@ -15,52 +15,52 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__invz_12 EN I ZN VDD VNW VPW VSS
*.PININFO EN:I I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_mn VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn8 NI_N NEN VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn21 NI_P EN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv1 VSS I NI VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv2 NI I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv3 VSS I NI VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17 NI_N NI VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9 VSS NI NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_10 NI_N NI VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_17 VSS NI NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_10_0 NI_N NI VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_17_30 VSS NI NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_89 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_34 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_80 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_35 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_99 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_33 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_88 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_34 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mp VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp7 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp22 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv1 VDD I NI VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv2 NI I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv3 VDD I NI VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14 NI_P NI VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10 VDD NI NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_11 NI_P NI VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_8 VDD NI NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_11_21 NI_P NI VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_8_17 VDD NI NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_57 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_96 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_105 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_69 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_58 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_106 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_111 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_75 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
+M_mn VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn8 NI_N NEN VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn21 NI_P EN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv1 VSS I NI VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv2 NI I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv3 VSS I NI VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17 NI_N NI VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9 VSS NI NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_10 NI_N NI VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_17 VSS NI NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_10_0 NI_N NI VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_17_30 VSS NI NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_89 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_34 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_80 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_35 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_99 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_33 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_88 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_34 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mp VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp7 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp22 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv1 VDD I NI VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv2 NI I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv3 VDD I NI VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14 NI_P NI VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10 VDD NI NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_11 NI_P NI VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_8 VDD NI NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_11_21 NI_P NI VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_8_17 VDD NI NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_57 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_96 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_105 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_69 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_58 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_106 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_111 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_75 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_16.cdl b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_16.cdl
index ab76d0e..128b1d8 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_16.cdl
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_16.cdl
@@ -15,66 +15,66 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__invz_16 EN I ZN VDD VNW VPW VSS
*.PININFO EN:I I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_mn VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn8 NI_N NEN VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn21 NI_P EN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv1 NI I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv2 VSS I NI VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv3 NI I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv4 VSS I NI VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17 NI_N NI VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9 VSS NI NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_10 NI_N NI VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_17 VSS NI NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_34 NI_N NI VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_41 VSS NI NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_10_30 NI_N NI VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_17_61 VSS NI NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_118 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_65 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_181 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_137 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_99_125 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_33_198 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_88_82 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_34_75 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_99 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_33 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_88 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_34 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mp VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp7 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp22 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv1 NI I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv2 VDD I NI VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv3 NI I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv4 VDD I NI VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14 NI_P NI VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10 VDD NI NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_11 NI_P NI VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_8 VDD NI NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_7 NI_P NI VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_32 VDD NI NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_11_55 NI_P NI VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_8_20 VDD NI NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_153 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_126 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_133 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_97 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_58_95 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_106_111 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_111_134 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_75_85 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_58 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_106 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_111 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_75 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
+M_mn VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn8 NI_N NEN VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn21 NI_P EN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv1 NI I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv2 VSS I NI VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv3 NI I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv4 VSS I NI VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17 NI_N NI VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9 VSS NI NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_10 NI_N NI VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_17 VSS NI NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_34 NI_N NI VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_41 VSS NI NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_10_30 NI_N NI VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_17_61 VSS NI NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_118 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_65 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_181 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_137 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_99_125 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_33_198 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_88_82 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_34_75 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_99 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_33 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_88 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_34 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mp VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp7 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp22 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv1 NI I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv2 VDD I NI VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv3 NI I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv4 VDD I NI VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14 NI_P NI VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10 VDD NI NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_11 NI_P NI VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_8 VDD NI NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_7 NI_P NI VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_32 VDD NI NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_11_55 NI_P NI VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_8_20 VDD NI NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_153 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_126 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_133 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_97 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_58_95 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_106_111 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_111_134 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_75_85 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_58 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_106 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_111 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_75 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_2.cdl b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_2.cdl
index 0d3ee79..3aca3e1 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_2.cdl
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_2.cdl
@@ -15,18 +15,18 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__invz_2 EN I ZN VDD VNW VPW VSS
*.PININFO EN:I I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_XX27 VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX44 NI_N NEN VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX36 NI_P EN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX43 VSS NI NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX22 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX22_4 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv NI I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_XX28 VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX45 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX39 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX46 VDD NI NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX21 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_XX21_5 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv NI I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
+M_XX27 VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX44 NI_N NEN VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX36 NI_P EN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX43 VSS NI NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX22 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX22_4 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv NI I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_XX28 VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX45 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX39 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX46 VDD NI NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX21 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_XX21_5 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv NI I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_3.cdl b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_3.cdl
index be39f99..005b2e0 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_3.cdl
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_3.cdl
@@ -15,22 +15,22 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__invz_3 EN I ZN VDD VNW VPW VSS
*.PININFO EN:I I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_mn VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn8 NI_N NEN VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn21 NI_P EN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv VSS I NI VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17 NI_N NI VSS VPW nmos_5p0 W=0.885000U L=0.600000U
-M_mn17_1 VSS NI NI_N VPW nmos_5p0 W=0.885000U L=0.600000U
-M_mn3 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_2 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mp VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp7 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp22 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv VDD I NI VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14 NI_P NI VDD VNW pmos_5p0 W=1.485000U L=0.500000U
-M_mp14_1 VDD NI NI_P VNW pmos_5p0 W=1.485000U L=0.500000U
-M_mp4 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_1 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_2 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
+M_mn VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn8 NI_N NEN VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn21 NI_P EN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv VSS I NI VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17 NI_N NI VSS VPW nfet_05v0 W=0.885000U L=0.600000U
+M_mn17_1 VSS NI NI_N VPW nfet_05v0 W=0.885000U L=0.600000U
+M_mn3 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_2 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mp VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp7 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp22 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv VDD I NI VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14 NI_P NI VDD VNW pfet_05v0 W=1.485000U L=0.500000U
+M_mp14_1 VDD NI NI_P VNW pfet_05v0 W=1.485000U L=0.500000U
+M_mp4 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_1 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_2 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_4.cdl b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_4.cdl
index 36991f1..185cb96 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_4.cdl
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_4.cdl
@@ -15,24 +15,24 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__invz_4 EN I ZN VDD VNW VPW VSS
*.PININFO EN:I I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_mn VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn8 NI_N NEN VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn21 NI_P EN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv VSS I NI VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17 NI_N NI VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9 VSS NI NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mp VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp7 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp22 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv VDD I NI VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14 NI_P NI VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10 VDD NI NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
+M_mn VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn8 NI_N NEN VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn21 NI_P EN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv VSS I NI VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17 NI_N NI VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9 VSS NI NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mp VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp7 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp22 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv VDD I NI VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14 NI_P NI VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10 VDD NI NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_8.cdl b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_8.cdl
index 53ae404..6e35c14 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_8.cdl
+++ b/cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_8.cdl
@@ -15,38 +15,38 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__invz_8 EN I ZN VDD VNW VPW VSS
*.PININFO EN:I I:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!I
-M_mn VSS EN NEN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn8 NI_N NEN VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn21 NI_P EN NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv1 NI I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_Mn_inv2 VSS I NI VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17 NI_N NI VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9 VSS NI NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_10 NI_N NI VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn17_9_17 VSS NI NI_N VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_99 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_33 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_49_88 ZN NI_N VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mn3_1_25_34 VSS NI_N ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_mp VDD EN NEN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp7 NI_P EN VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp22 NI_N NEN NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv1 NI I VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_Mp_inv2 VDD I NI VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14 NI_P NI VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10 VDD NI NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_11 NI_P NI VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp14_10_8 VDD NI NI_P VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_58 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_106 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_56_111 ZN NI_P VDD VNW pmos_5p0 W=1.800000U L=0.500000U
-M_mp4_12_57_75 VDD NI_P ZN VNW pmos_5p0 W=1.800000U L=0.500000U
+M_mn VSS EN NEN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn8 NI_N NEN VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn21 NI_P EN NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv1 NI I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_Mn_inv2 VSS I NI VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17 NI_N NI VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9 VSS NI NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_10 NI_N NI VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn17_9_17 VSS NI NI_N VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_99 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_33 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_49_88 ZN NI_N VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mn3_1_25_34 VSS NI_N ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_mp VDD EN NEN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp7 NI_P EN VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp22 NI_N NEN NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv1 NI I VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_Mp_inv2 VDD I NI VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14 NI_P NI VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10 VDD NI NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_11 NI_P NI VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp14_10_8 VDD NI NI_P VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_58 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_106 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_56_111 ZN NI_P VDD VNW pfet_05v0 W=1.800000U L=0.500000U
+M_mp4_12_57_75 VDD NI_P ZN VNW pfet_05v0 W=1.800000U L=0.500000U
.ENDS
diff --git a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_1.cdl b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_1.cdl
index 3dcc708..546c2bd 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_1.cdl
+++ b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_1.cdl
@@ -14,20 +14,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latq_1 D E Q VDD VNW VPW VSS
*.PININFO D:I E:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn0 VSS E net4 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn8 net7 net4 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn4 VSS D net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net5 net7 net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn1 net2 net4 net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn2 net2 net6 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn3 net6 net5 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn6 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp0 VDD E net4 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 net7 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD D net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 net1 net4 net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net5 net7 net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 net0 net6 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp3 net6 net5 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp6 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn0 VSS E net4 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn8 net7 net4 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn4 VSS D net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net5 net7 net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn1 net2 net4 net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn2 net2 net6 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn3 net6 net5 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn6 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp0 VDD E net4 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 net7 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD D net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 net1 net4 net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net5 net7 net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 net0 net6 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp3 net6 net5 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp6 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_2.cdl b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_2.cdl
index bceb133..44963f0 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_2.cdl
+++ b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_2.cdl
@@ -14,22 +14,22 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latq_2 D E Q VDD VNW VPW VSS
*.PININFO D:I E:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn0 VSS E net4 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn8 net7 net4 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn4 VSS D net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net5 net7 net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn1 net2 net4 net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn2 net2 net6 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn3 net6 net5 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn6_30 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp0 VDD E net4 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 net7 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD D net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 net1 net4 net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net5 net7 net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 net0 net6 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp3 net6 net5 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp6_31 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp6 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn0 VSS E net4 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn8 net7 net4 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn4 VSS D net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net5 net7 net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn1 net2 net4 net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn2 net2 net6 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn3 net6 net5 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn6_30 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp0 VDD E net4 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 net7 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD D net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 net1 net4 net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net5 net7 net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 net0 net6 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp3 net6 net5 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp6_31 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp6 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_4.cdl b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_4.cdl
index 0a9b62c..59103ff 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_4.cdl
+++ b/cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_4.cdl
@@ -14,28 +14,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latq_4 D E Q VDD VNW VPW VSS
*.PININFO D:I E:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn0 VSS E net4 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn8 net7 net4 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn4 VSS D net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net5 net7 net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn1 net2 net4 net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn2 net2 net6 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn3 net6 net5 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn3_94 net6 net5 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn6_30_66 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6_46 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6_30 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp0 VDD E net4 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 net7 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD D net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 net1 net4 net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net5 net7 net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 net0 net6 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp3 net6 net5 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp3_85 net6 net5 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp6_31_68 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp6_71 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp6_31 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp6 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn0 VSS E net4 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn8 net7 net4 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn4 VSS D net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net5 net7 net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn1 net2 net4 net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn2 net2 net6 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn3 net6 net5 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn3_94 net6 net5 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn6_30_66 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6_46 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6_30 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp0 VDD E net4 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 net7 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD D net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 net1 net4 net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net5 net7 net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 net0 net6 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp3 net6 net5 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp3_85 net6 net5 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp6_31_68 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp6_71 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp6_31 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp6 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_1.cdl b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_1.cdl
index 06094df..3c7737b 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_1.cdl
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_1.cdl
@@ -14,23 +14,23 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latrnq_1 D E RN Q VDD VNW VPW VSS
*.PININFO D:I E:I RN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 net7 E VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net1 RN VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn9 net2 D net1 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn8 net2 E net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn7 net3 net7 net4 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net5 net0 net4 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn0 VSS RN net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn6 net0 net3 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn4 net6 net0 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn1 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 net7 E VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 VDD RN net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net8 D VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net3 net7 net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 net9 E net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net9 net0 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net0 net3 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp7 net6 net0 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn3 net7 E VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net1 RN VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn9 net2 D net1 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn8 net2 E net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn7 net3 net7 net4 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net5 net0 net4 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn0 VSS RN net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn6 net0 net3 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn4 net6 net0 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn1 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 net7 E VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 VDD RN net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net8 D VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net3 net7 net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 net9 E net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net9 net0 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net0 net3 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp7 net6 net0 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_2.cdl b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_2.cdl
index 66c9dbd..3f65791 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_2.cdl
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_2.cdl
@@ -14,25 +14,25 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latrnq_2 D E RN Q VDD VNW VPW VSS
*.PININFO D:I E:I RN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 net7 E VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net1 RN VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn9 net2 D net1 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn8 net2 E net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn7 net3 net7 net4 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net5 net0 net4 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn0 VSS RN net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn6 net0 net3 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn4 net6 net0 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn1 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_38 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 net7 E VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 VDD RN net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net8 D VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net3 net7 net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 net9 E net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net9 net0 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net0 net3 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp7 net6 net0 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0_27 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn3 net7 E VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net1 RN VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn9 net2 D net1 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn8 net2 E net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn7 net3 net7 net4 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net5 net0 net4 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn0 VSS RN net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn6 net0 net3 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn4 net6 net0 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn1 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_38 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 net7 E VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 VDD RN net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net8 D VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net3 net7 net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 net9 E net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net9 net0 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net0 net3 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp7 net6 net0 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0_27 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_4.cdl b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_4.cdl
index 2f046db..62c4dda 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_4.cdl
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_4.cdl
@@ -14,33 +14,33 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latrnq_4 D E RN Q VDD VNW VPW VSS
*.PININFO D:I E:I RN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 net7 E VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net1 RN VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn9 net2 D net1 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn8 net2 E net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn7 net3 net7 net4 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net5 net0 net4 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn0 VSS RN net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn6 net0 net3 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn6_109 net0 net3 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn4 net6 net0 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn4_77 net6 net0 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn1 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_38 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_15 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_38_14 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 net7 E VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 VDD RN net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net8 D VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net3 net7 net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 net9 E net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net9 net0 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net0 net3 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9_110 net0 net3 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp7 net6 net0 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp7_78 net6 net0 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0_27 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0_24 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0_27_20 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn3 net7 E VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net1 RN VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn9 net2 D net1 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn8 net2 E net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn7 net3 net7 net4 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net5 net0 net4 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn0 VSS RN net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn6 net0 net3 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn6_109 net0 net3 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn4 net6 net0 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn4_77 net6 net0 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn1 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_38 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_15 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_38_14 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 net7 E VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 VDD RN net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net8 D VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net3 net7 net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 net9 E net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net9 net0 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net0 net3 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9_110 net0 net3 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp7 net6 net0 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp7_78 net6 net0 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0_27 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0_24 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0_27_20 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.cdl b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.cdl
index 641c8b9..b26399e 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.cdl
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.cdl
@@ -14,25 +14,25 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latrsnq_1 D E RN SETN Q VDD VNW VPW VSS
*.PININFO D:I E:I RN:I SETN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 net8 E VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn9 net2 RN VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn8 net3 D net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn7 net3 E net4 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn6 net4 net8 net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net6 net1 net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn0 VSS RN net6 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn11 VSS net4 net0 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net0 SETN net1 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn4 net7 net1 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn1 Q net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 net8 E VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 VDD RN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net9 D VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net4 net8 net9 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 net10 E net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net10 net1 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 VDD net4 net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net1 SETN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp7 net7 net1 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 Q net7 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn3 net8 E VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn9 net2 RN VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn8 net3 D net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn7 net3 E net4 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn6 net4 net8 net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net6 net1 net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn0 VSS RN net6 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn11 VSS net4 net0 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net0 SETN net1 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn4 net7 net1 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn1 Q net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 net8 E VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 VDD RN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net9 D VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net4 net8 net9 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 net10 E net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net10 net1 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 VDD net4 net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net1 SETN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp7 net7 net1 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 Q net7 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.cdl b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.cdl
index 5d7757b..f935309 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.cdl
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.cdl
@@ -14,27 +14,27 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latrsnq_2 D E RN SETN Q VDD VNW VPW VSS
*.PININFO D:I E:I RN:I SETN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 net8 E VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn9 net2 RN VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn8 net3 D net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn7 net3 E net4 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn6 net4 net8 net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net6 net1 net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn0 VSS RN net6 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn11 VSS net4 net0 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net0 SETN net1 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn4 net7 net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1 Q net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_19 Q net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 net8 E VDD VNW pmos_5p0 W=1.380000U L=0.600000U
-M_tp8 VDD RN net4 VNW pmos_5p0 W=1.000000U L=0.600000U
-M_tp6 net9 D VDD VNW pmos_5p0 W=1.000000U L=0.600000U
-M_tp5 net4 net8 net9 VNW pmos_5p0 W=1.000000U L=0.600000U
-M_tp4 net10 E net4 VNW pmos_5p0 W=1.000000U L=0.600000U
-M_tp3 net10 net1 VDD VNW pmos_5p0 W=1.000000U L=0.600000U
-M_tp10 VDD net4 net1 VNW pmos_5p0 W=1.000000U L=0.600000U
-M_tp9 net1 SETN VDD VNW pmos_5p0 W=1.380000U L=0.600000U
-M_tp7 net7 net1 VDD VNW pmos_5p0 W=1.830000U L=0.600000U
-M_tp0 Q net7 VDD VNW pmos_5p0 W=1.830000U L=0.600000U
-M_tp0_9 Q net7 VDD VNW pmos_5p0 W=1.830000U L=0.600000U
+M_tn3 net8 E VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn9 net2 RN VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn8 net3 D net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn7 net3 E net4 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn6 net4 net8 net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net6 net1 net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn0 VSS RN net6 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn11 VSS net4 net0 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net0 SETN net1 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn4 net7 net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1 Q net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_19 Q net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 net8 E VDD VNW pfet_05v0 W=1.380000U L=0.600000U
+M_tp8 VDD RN net4 VNW pfet_05v0 W=1.000000U L=0.600000U
+M_tp6 net9 D VDD VNW pfet_05v0 W=1.000000U L=0.600000U
+M_tp5 net4 net8 net9 VNW pfet_05v0 W=1.000000U L=0.600000U
+M_tp4 net10 E net4 VNW pfet_05v0 W=1.000000U L=0.600000U
+M_tp3 net10 net1 VDD VNW pfet_05v0 W=1.000000U L=0.600000U
+M_tp10 VDD net4 net1 VNW pfet_05v0 W=1.000000U L=0.600000U
+M_tp9 net1 SETN VDD VNW pfet_05v0 W=1.380000U L=0.600000U
+M_tp7 net7 net1 VDD VNW pfet_05v0 W=1.830000U L=0.600000U
+M_tp0 Q net7 VDD VNW pfet_05v0 W=1.830000U L=0.600000U
+M_tp0_9 Q net7 VDD VNW pfet_05v0 W=1.830000U L=0.600000U
.ENDS
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.cdl b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.cdl
index 4a0b88f..00e2085 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.cdl
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.cdl
@@ -14,33 +14,33 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latrsnq_4 D E RN SETN Q VDD VNW VPW VSS
*.PININFO D:I E:I RN:I SETN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn3 net8 E VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn9 net2 RN VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn8 net3 D net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn7 net3 E net4 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn6 net4 net8 net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net6 net1 net5 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn0 VSS RN net6 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn11 VSS net4 net0 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn10 net0 SETN net1 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn4_44 net7 net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn4 net7 net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1 Q net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_19 Q net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_18 Q net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn1_19_0 Q net7 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 net8 E VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 VDD RN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net9 D VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net4 net8 net9 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 net10 E net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net10 net1 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 VDD net4 net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net1 SETN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp7_47 net7 net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp7 net7 net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0 Q net7 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0_9 Q net7 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0_26 Q net7 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0_9_34 Q net7 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn3 net8 E VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn9 net2 RN VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn8 net3 D net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn7 net3 E net4 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn6 net4 net8 net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net6 net1 net5 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn0 VSS RN net6 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn11 VSS net4 net0 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn10 net0 SETN net1 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn4_44 net7 net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn4 net7 net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1 Q net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_19 Q net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_18 Q net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn1_19_0 Q net7 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 net8 E VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 VDD RN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net9 D VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net4 net8 net9 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 net10 E net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net10 net1 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 VDD net4 net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net1 SETN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp7_47 net7 net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp7 net7 net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0 Q net7 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0_9 Q net7 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0_26 Q net7 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0_9_34 Q net7 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_1.cdl b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_1.cdl
index 636d94b..6833f2b 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_1.cdl
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_1.cdl
@@ -14,22 +14,22 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latsnq_1 D E SETN Q VDD VNW VPW VSS
*.PININFO D:I E:I SETN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn2 net6 E VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn7 VSS D net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn6 net3 E net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net4 net6 net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn4 net4 net1 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn9 VSS net3 net0 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn8 net0 SETN net1 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn3 net5 net1 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 net6 E VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp6 VDD D net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net7 net6 net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 net3 E net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 net1 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 VDD net3 net1 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp8 net1 SETN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp7 net5 net1 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn2 net6 E VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn7 VSS D net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn6 net3 E net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net4 net6 net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn4 net4 net1 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn9 VSS net3 net0 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn8 net0 SETN net1 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn3 net5 net1 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 net6 E VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp6 VDD D net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net7 net6 net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 net3 E net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 net1 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 VDD net3 net1 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp8 net1 SETN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp7 net5 net1 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_2.cdl b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_2.cdl
index 72d877d..de7d000 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_2.cdl
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_2.cdl
@@ -14,24 +14,24 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latsnq_2 D E SETN Q VDD VNW VPW VSS
*.PININFO D:I E:I SETN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn2 net6 E VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn7 VSS D net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn6 net3 E net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net4 net6 net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn4 net4 net1 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn9 VSS net3 net0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn8 net0 SETN net1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3 net5 net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn0 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn0_11 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 net6 E VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp6 VDD D net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net7 net6 net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 net3 E net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 net1 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 VDD net3 net1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp8 net1 SETN VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp7 net5 net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0_8 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn2 net6 E VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn7 VSS D net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn6 net3 E net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net4 net6 net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn4 net4 net1 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn9 VSS net3 net0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn8 net0 SETN net1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3 net5 net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn0 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn0_11 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 net6 E VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp6 VDD D net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net7 net6 net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 net3 E net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 net1 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 VDD net3 net1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp8 net1 SETN VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp7 net5 net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0_8 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_4.cdl b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_4.cdl
index c9d46e2..bc58b7d 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_4.cdl
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_4.cdl
@@ -14,30 +14,30 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__latsnq_4 D E SETN Q VDD VNW VPW VSS
*.PININFO D:I E:I SETN:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn2 net6 E VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn7 VSS D net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn6 net3 E net2 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn5 net4 net6 net3 VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn4 net4 net1 VSS VPW nmos_5p0 W=0.700000U L=0.600000U
-M_tn9 VSS net3 net0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn8 net0 SETN net1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3_56 net5 net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3 net5 net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn0 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn0_11 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn0_12 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn0_11_1 Q net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp2 net6 E VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp6 VDD D net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net7 net6 net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 net3 E net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 net1 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 VDD net3 net1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp8 net1 SETN VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp7_53 net5 net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp7 net5 net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0_8 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0_32 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp0_8_30 Q net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn2 net6 E VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn7 VSS D net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn6 net3 E net2 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn5 net4 net6 net3 VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn4 net4 net1 VSS VPW nfet_05v0 W=0.700000U L=0.600000U
+M_tn9 VSS net3 net0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn8 net0 SETN net1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3_56 net5 net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3 net5 net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn0 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn0_11 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn0_12 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn0_11_1 Q net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp2 net6 E VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp6 VDD D net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net7 net6 net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 net3 E net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 net1 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 VDD net3 net1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp8 net1 SETN VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp7_53 net5 net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp7 net5 net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0_8 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0_32 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp0_8_30 Q net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_1.cdl b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_1.cdl
index f65aed4..fd76f50 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_1.cdl
+++ b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_1.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__mux2_1 I0 I1 S Z VDD VNW VPW VSS
*.PININFO I0:I I1:I S:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((S * I1) + (!S * I0))
-M_MN2 VSS int04 Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN4 net_1 I1 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN8 int04 S net_1 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN7 net_3 sel1_n int04 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN3 VSS I0 net_3 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN1 sel1_n S VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MP5 VDD int04 Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP4 net_0 I1 VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP8 int04 sel1_n net_0 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP7 net_2 S int04 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP3 VDD I0 net_2 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP1 sel1_n S VDD VNW pmos_5p0 W=0.915000U L=0.500000U
+M_MN2 VSS int04 Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN4 net_1 I1 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN8 int04 S net_1 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN7 net_3 sel1_n int04 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN3 VSS I0 net_3 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN1 sel1_n S VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MP5 VDD int04 Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP4 net_0 I1 VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP8 int04 sel1_n net_0 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP7 net_2 S int04 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP3 VDD I0 net_2 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP1 sel1_n S VDD VNW pfet_05v0 W=0.915000U L=0.500000U
.ENDS
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_2.cdl b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_2.cdl
index 901ecfb..4c2e090 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_2.cdl
+++ b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_2.cdl
@@ -15,18 +15,18 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__mux2_2 I0 I1 S Z VDD VNW VPW VSS
*.PININFO I0:I I1:I S:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((S * I1) + (!S * I0))
-M_MN2_12 VSS int04 Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN2 VSS int04 Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN4 net_1 I1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN8 int04 S net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN7 net_3 sel1_n int04 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN3 VSS I0 net_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN1 sel1_n S VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MP5_6 VDD int04 Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP5 VDD int04 Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP4 net_0 I1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP8 int04 sel1_n net_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP7 net_2 S int04 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP3 VDD I0 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP1 sel1_n S VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_MN2_12 VSS int04 Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN2 VSS int04 Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN4 net_1 I1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN8 int04 S net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN7 net_3 sel1_n int04 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN3 VSS I0 net_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN1 sel1_n S VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MP5_6 VDD int04 Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP5 VDD int04 Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP4 net_0 I1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP8 int04 sel1_n net_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP7 net_2 S int04 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP3 VDD I0 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP1 sel1_n S VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.cdl b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.cdl
index 9fb02fe..bd7e3e9 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.cdl
+++ b/cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.cdl
@@ -15,22 +15,22 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__mux2_4 I0 I1 S Z VDD VNW VPW VSS
*.PININFO I0:I I1:I S:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((S * I1) + (!S * I0))
-M_MN2_12_7 VSS int04 Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN2_8 VSS int04 Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN2_12 VSS int04 Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN2 VSS int04 Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN4 net_1 I1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN8 int04 S net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN7 net_3 sel1_n int04 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN3 VSS I0 net_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MN1 sel1_n S VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_MP5_6_5 VDD int04 Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP5_0 VDD int04 Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP5_6 VDD int04 Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP5 VDD int04 Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP4 net_0 I1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP8 int04 sel1_n net_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP7 net_2 S int04 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP3 VDD I0 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_MP1 sel1_n S VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_MN2_12_7 VSS int04 Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN2_8 VSS int04 Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN2_12 VSS int04 Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN2 VSS int04 Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN4 net_1 I1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN8 int04 S net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN7 net_3 sel1_n int04 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN3 VSS I0 net_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MN1 sel1_n S VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_MP5_6_5 VDD int04 Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP5_0 VDD int04 Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP5_6 VDD int04 Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP5 VDD int04 Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP4 net_0 I1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP8 int04 sel1_n net_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP7 net_2 S int04 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP3 VDD I0 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_MP1 sel1_n S VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_1.cdl b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_1.cdl
index bc6d587..90e82a7 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_1.cdl
+++ b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_1.cdl
@@ -15,30 +15,30 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__mux4_1 I0 I1 I2 I3 S0 S1 Z VDD VNW VPW VSS
*.PININFO I0:I I1:I I2:I I3:I S0:I S1:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((S0 * ((S1 * I3) + (!S1 * I1))) + (!S0 * ((S1 * I2) + (!S1 * I0))))
-M_MN5 int01 I2 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN9 int02 sel1_n int01 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN10 int07 S0 int02 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN6 VSS I3 int07 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_instance_22 Z int03 VSS VPW nmos_5p0 W=0.900000U L=0.600000U
-M_MN12 int03 S1 int02 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN11 int04 sel2_n int03 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN2 VSS S1 sel2_n VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN4 int06 I1 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN8 int04 S0 int06 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN7 int05 sel1_n int04 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN3 VSS I0 int05 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MN1 sel1_n S0 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_MP2 int01 I2 VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP9 int02 S0 int01 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP10 int07 sel1_n int02 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP6 VDD I3 int07 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_instance_1 Z int03 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_MP12 int03 sel2_n int02 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP11 int04 S1 int03 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP5 VDD S1 sel2_n VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP4 int06 I1 VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP8 int04 sel1_n int06 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP7 int05 S0 int04 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP3 VDD I0 int05 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_MP1 sel1_n S0 VDD VNW pmos_5p0 W=0.915000U L=0.500000U
+M_MN5 int01 I2 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN9 int02 sel1_n int01 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN10 int07 S0 int02 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN6 VSS I3 int07 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_instance_22 Z int03 VSS VPW nfet_05v0 W=0.900000U L=0.600000U
+M_MN12 int03 S1 int02 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN11 int04 sel2_n int03 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN2 VSS S1 sel2_n VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN4 int06 I1 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN8 int04 S0 int06 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN7 int05 sel1_n int04 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN3 VSS I0 int05 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MN1 sel1_n S0 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_MP2 int01 I2 VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP9 int02 S0 int01 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP10 int07 sel1_n int02 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP6 VDD I3 int07 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_instance_1 Z int03 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_MP12 int03 sel2_n int02 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP11 int04 S1 int03 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP5 VDD S1 sel2_n VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP4 int06 I1 VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP8 int04 sel1_n int06 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP7 int05 S0 int04 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP3 VDD I0 int05 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_MP1 sel1_n S0 VDD VNW pfet_05v0 W=0.915000U L=0.500000U
.ENDS
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.cdl b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.cdl
index 118a3f4..025d2a3 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.cdl
+++ b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.cdl
@@ -15,32 +15,32 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__mux4_2 I0 I1 I2 I3 S0 S1 Z VDD VNW VPW VSS
*.PININFO I0:I I1:I I2:I I3:I S0:I S1:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((S0 * ((S1 * I3) + (!S1 * I1))) + (!S0 * ((S1 * I2) + (!S1 * I0))))
-M_MN5 int01 I2 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN9 int02 sel1_n int01 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN10 int07 S0 int02 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN6 VSS I3 int07 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_instance_22 Z int03 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_instance_22_11 Z int03 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN12 int03 S1 int02 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN11 int04 sel2_n int03 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN2 VSS S1 sel2_n VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN4 int06 I1 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN8 int04 S0 int06 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN7 int05 sel1_n int04 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN3 VSS I0 int05 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN1 sel1_n S0 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MP2 int01 I2 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP9 int02 S0 int01 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP10 int07 sel1_n int02 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP6 VDD I3 int07 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_instance_1 Z int03 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_instance_1_6 Z int03 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP12 int03 sel2_n int02 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP11 int04 S1 int03 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP5 VDD S1 sel2_n VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP4 int06 I1 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP8 int04 sel1_n int06 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP7 int05 S0 int04 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP3 VDD I0 int05 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP1 sel1_n S0 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
+M_MN5 int01 I2 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN9 int02 sel1_n int01 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN10 int07 S0 int02 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN6 VSS I3 int07 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_instance_22 Z int03 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_instance_22_11 Z int03 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN12 int03 S1 int02 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN11 int04 sel2_n int03 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN2 VSS S1 sel2_n VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN4 int06 I1 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN8 int04 S0 int06 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN7 int05 sel1_n int04 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN3 VSS I0 int05 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN1 sel1_n S0 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MP2 int01 I2 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP9 int02 S0 int01 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP10 int07 sel1_n int02 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP6 VDD I3 int07 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_instance_1 Z int03 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_instance_1_6 Z int03 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP12 int03 sel2_n int02 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP11 int04 S1 int03 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP5 VDD S1 sel2_n VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP4 int06 I1 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP8 int04 sel1_n int06 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP7 int05 S0 int04 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP3 VDD I0 int05 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP1 sel1_n S0 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
.ENDS
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.cdl b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.cdl
index 4dacaa2..7d553f5 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.cdl
+++ b/cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.cdl
@@ -15,36 +15,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__mux4_4 I0 I1 I2 I3 S0 S1 Z VDD VNW VPW VSS
*.PININFO I0:I I1:I I2:I I3:I S0:I S1:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((S0 * ((S1 * I3) + (!S1 * I1))) + (!S0 * ((S1 * I2) + (!S1 * I0))))
-M_MN5 int01 I2 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN9 int02 sel1_n int01 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN10 int07 S0 int02 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN6 VSS I3 int07 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_instance_22 Z int03 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_instance_22_11 Z int03 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_instance_22_18 Z int03 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_instance_22_11_19 Z int03 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN12 int03 S1 int02 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN11 int04 sel2_n int03 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN2 VSS S1 sel2_n VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN4 int06 I1 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN8 int04 S0 int06 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN7 int05 sel1_n int04 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN3 VSS I0 int05 VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MN1 sel1_n S0 VSS VPW nmos_5p0 W=0.800000U L=0.600000U
-M_MP2 int01 I2 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP9 int02 S0 int01 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP10 int07 sel1_n int02 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP6 VDD I3 int07 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_instance_1 Z int03 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_instance_1_6 Z int03 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_instance_1_9 Z int03 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_instance_1_6_3 Z int03 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP12 int03 sel2_n int02 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP11 int04 S1 int03 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP5 VDD S1 sel2_n VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP4 int06 I1 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP8 int04 sel1_n int06 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP7 int05 S0 int04 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP3 VDD I0 int05 VNW pmos_5p0 W=1.280000U L=0.500000U
-M_MP1 sel1_n S0 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
+M_MN5 int01 I2 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN9 int02 sel1_n int01 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN10 int07 S0 int02 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN6 VSS I3 int07 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_instance_22 Z int03 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_instance_22_11 Z int03 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_instance_22_18 Z int03 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_instance_22_11_19 Z int03 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN12 int03 S1 int02 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN11 int04 sel2_n int03 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN2 VSS S1 sel2_n VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN4 int06 I1 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN8 int04 S0 int06 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN7 int05 sel1_n int04 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN3 VSS I0 int05 VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MN1 sel1_n S0 VSS VPW nfet_05v0 W=0.800000U L=0.600000U
+M_MP2 int01 I2 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP9 int02 S0 int01 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP10 int07 sel1_n int02 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP6 VDD I3 int07 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_instance_1 Z int03 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_instance_1_6 Z int03 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_instance_1_9 Z int03 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_instance_1_6_3 Z int03 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP12 int03 sel2_n int02 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP11 int04 S1 int03 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP5 VDD S1 sel2_n VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP4 int06 I1 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP8 int04 sel1_n int06 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP7 int05 S0 int04 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP3 VDD I0 int05 VNW pfet_05v0 W=1.280000U L=0.500000U
+M_MP1 sel1_n S0 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
.ENDS
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_1.cdl b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_1.cdl
index cd94a7d..f61459a 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_1.cdl
+++ b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_1.cdl
@@ -15,8 +15,8 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nand2_1 A1 A2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(A1 * A2)
-M_i_1 net_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 ZN A2 VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_2 VDD A1 ZN VNW pmos_5p0 W=1.645000U L=0.500000U
+M_i_1 net_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 ZN A2 VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_2 VDD A1 ZN VNW pfet_05v0 W=1.645000U L=0.500000U
.ENDS
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.cdl b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.cdl
index 4953d87..3916e25 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.cdl
+++ b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nand2_2 A1 A2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(A1 * A2)
-M_i_1_1 net_0_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0_1 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 VSS A2 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 ZN A2 VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_2_1 VDD A1 ZN VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_2_0 ZN A1 VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_3_0 VDD A2 ZN VNW pmos_5p0 W=1.645000U L=0.500000U
+M_i_1_1 net_0_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0_1 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 VSS A2 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 ZN A2 VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_2_1 VDD A1 ZN VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_2_0 ZN A1 VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_3_0 VDD A2 ZN VNW pfet_05v0 W=1.645000U L=0.500000U
.ENDS
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_4.cdl b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_4.cdl
index adf94c8..e14e7b6 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_4.cdl
+++ b/cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_4.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nand2_4 A1 A2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(A1 * A2)
-M_i_1_3 net_0_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 ZN A1 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 net_0_1 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 VSS A2 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0_2 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0_3 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 VSS A2 net_0_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_3 ZN A2 VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_2_3 VDD A1 ZN VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_2_2 ZN A1 VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_3_2 VDD A2 ZN VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_3_1 ZN A2 VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_2_1 VDD A1 ZN VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_2_0 ZN A1 VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_3_0 VDD A2 ZN VNW pmos_5p0 W=1.645000U L=0.500000U
+M_i_1_3 net_0_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 ZN A1 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 net_0_1 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 VSS A2 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0_2 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0_3 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 VSS A2 net_0_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_3 ZN A2 VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_2_3 VDD A1 ZN VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_2_2 ZN A1 VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_3_2 VDD A2 ZN VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_3_1 ZN A2 VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_2_1 VDD A1 ZN VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_2_0 ZN A1 VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_3_0 VDD A2 ZN VNW pfet_05v0 W=1.645000U L=0.500000U
.ENDS
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_1.cdl b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_1.cdl
index c75c37d..36964bc 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_1.cdl
+++ b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_1.cdl
@@ -15,10 +15,10 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nand3_1 A1 A2 A3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 * A2) * A3)
-M_i_2 net_1 A3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 net_0 A2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5 ZN A3 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_4 VDD A2 ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_3 ZN A1 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
+M_i_2 net_1 A3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 net_0 A2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5 ZN A3 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_4 VDD A2 ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_3 ZN A1 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
.ENDS
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_2.cdl b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_2.cdl
index edadb1b..c34feda 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_2.cdl
+++ b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_2.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nand3_2 A1 A2 A3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 * A2) * A3)
-M_i_2_1 net_1_0 A3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0_0 A2 net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0_1 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_1_1 A2 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 VSS A3 net_1_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_1 ZN A3 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_4_0 VDD A2 ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_3_0 ZN A1 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_3_1 VDD A1 ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_4_1 ZN A2 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_5_0 VDD A3 ZN VNW pmos_5p0 W=1.460000U L=0.500000U
+M_i_2_1 net_1_0 A3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0_0 A2 net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0_1 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_1_1 A2 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 VSS A3 net_1_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_1 ZN A3 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_4_0 VDD A2 ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_3_0 ZN A1 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_3_1 VDD A1 ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_4_1 ZN A2 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_5_0 VDD A3 ZN VNW pfet_05v0 W=1.460000U L=0.500000U
.ENDS
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_4.cdl b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_4.cdl
index 59502bd..3832fbd 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_4.cdl
+++ b/cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_4.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nand3_4 A1 A2 A3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 * A2) * A3)
-M_i_1_3 net_1_3 A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 VSS A3 net_1_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_1_2 A3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 net_0 A2 net_1_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_1_1 A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 VSS A3 net_1_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 net_1_0 A3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0_0 A2 net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 ZN A1 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_3 ZN A2 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_5_0 VDD A3 ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_5_1 ZN A3 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_4_2 VDD A2 ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_4_1 ZN A2 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_5_2 VDD A3 ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_5_3 ZN A3 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_4_0 VDD A2 ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_3_3 ZN A1 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_3_2 VDD A1 ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_3_1 ZN A1 VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_3_0 VDD A1 ZN VNW pmos_5p0 W=1.460000U L=0.500000U
+M_i_1_3 net_1_3 A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 VSS A3 net_1_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_1_2 A3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 net_0 A2 net_1_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_1_1 A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 VSS A3 net_1_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 net_1_0 A3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0_0 A2 net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 ZN A1 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_3 ZN A2 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_5_0 VDD A3 ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_5_1 ZN A3 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_4_2 VDD A2 ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_4_1 ZN A2 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_5_2 VDD A3 ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_5_3 ZN A3 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_4_0 VDD A2 ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_3_3 ZN A1 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_3_2 VDD A1 ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_3_1 ZN A1 VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_3_0 VDD A1 ZN VNW pfet_05v0 W=1.460000U L=0.500000U
.ENDS
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.cdl b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.cdl
index f9118ed..b41a509 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.cdl
+++ b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nand4_1 A1 A2 A3 A4 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) * A3) * A4)
-M_i_3 net_2 A4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 net_1 A3 net_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 net_0 A2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7 ZN A4 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_6 VDD A3 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_5 ZN A2 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_4 VDD A1 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
+M_i_3 net_2 A4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 net_1 A3 net_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 net_0 A2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7 ZN A4 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_6 VDD A3 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_5 ZN A2 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_4 VDD A1 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
.ENDS
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.cdl b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.cdl
index 3788367..7d71198 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.cdl
+++ b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nand4_2 A1 A2 A3 A4 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) * A3) * A4)
-M_i_3_0 net_2_0 A4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_1_0 A3 net_2_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0_0 A2 net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0_1 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_1_1 A2 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_2_1 A3 net_1_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 VSS A4 net_2_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7_0 VDD A4 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_6_0 ZN A3 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_5_0 VDD A2 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_4_0 ZN A1 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_4_1 VDD A1 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_5_1 ZN A2 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_6_1 VDD A3 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_7_1 ZN A4 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
+M_i_3_0 net_2_0 A4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_1_0 A3 net_2_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0_0 A2 net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0_1 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_1_1 A2 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_2_1 A3 net_1_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 VSS A4 net_2_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7_0 VDD A4 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_6_0 ZN A3 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_5_0 VDD A2 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_4_0 ZN A1 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_4_1 VDD A1 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_5_1 ZN A2 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_6_1 VDD A3 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_7_1 ZN A4 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
.ENDS
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.cdl b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.cdl
index 63cef44..c5e42ad 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.cdl
+++ b/cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.cdl
@@ -15,36 +15,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nand4_4 A1 A2 A3 A4 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 * A2) * A3) * A4)
-M_i_2_3 net_2_3 A3 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_3 VSS A4 net_2_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_2 net_2_2 A4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 net_1 A3 net_2_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_2_1 A3 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 VSS A4 net_2_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 net_2_0 A4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_1_0 A3 net_2_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_3 net_0_3 A2 net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 ZN A1 net_0_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 net_0_2 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 net_1 A2 net_0_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0_1 A2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_1 A2 net_0_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_3 ZN A3 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_7_3 VDD A4 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_7_2 ZN A4 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_6_2 VDD A3 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_6_1 ZN A3 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_7_1 VDD A4 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_7_0 ZN A4 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_6_0 VDD A3 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_5_3 ZN A2 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_4_3 VDD A1 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_4_2 ZN A1 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_5_2 VDD A2 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_5_1 ZN A2 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_4_1 VDD A1 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_4_0 ZN A1 VDD VNW pmos_5p0 W=1.280000U L=0.500000U
-M_i_5_0 VDD A2 ZN VNW pmos_5p0 W=1.280000U L=0.500000U
+M_i_2_3 net_2_3 A3 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_3 VSS A4 net_2_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_2 net_2_2 A4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 net_1 A3 net_2_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_2_1 A3 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 VSS A4 net_2_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 net_2_0 A4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_1_0 A3 net_2_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_3 net_0_3 A2 net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 ZN A1 net_0_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 net_0_2 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 net_1 A2 net_0_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0_1 A2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_1 A2 net_0_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_3 ZN A3 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_7_3 VDD A4 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_7_2 ZN A4 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_6_2 VDD A3 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_6_1 ZN A3 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_7_1 VDD A4 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_7_0 ZN A4 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_6_0 VDD A3 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_5_3 ZN A2 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_4_3 VDD A1 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_4_2 ZN A1 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_5_2 VDD A2 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_5_1 ZN A2 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_4_1 VDD A1 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_4_0 ZN A1 VDD VNW pfet_05v0 W=1.280000U L=0.500000U
+M_i_5_0 VDD A2 ZN VNW pfet_05v0 W=1.280000U L=0.500000U
.ENDS
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_1.cdl b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_1.cdl
index 9694aa4..7039663 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_1.cdl
+++ b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_1.cdl
@@ -15,8 +15,8 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nor2_1 A1 A2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(A1 + A2)
-M_i_1 ZN A2 VSS VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_0 VSS A1 ZN VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_3 net_0 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_2 ZN A1 net_0 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_1 ZN A2 VSS VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_0 VSS A1 ZN VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_3 net_0 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_2 ZN A1 net_0 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.cdl b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.cdl
index 3d84fc7..6fe791f 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.cdl
+++ b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nor2_2 A1 A2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(A1 + A2)
-M_i_1_1 ZN A2 VSS VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_0_1 VSS A1 ZN VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_0_0 ZN A1 VSS VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_1_0 VSS A2 ZN VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_3_1 net_0_0 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_2_1 ZN A1 net_0_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_2_0 net_0_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0 VDD A2 net_0_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_1_1 ZN A2 VSS VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_0_1 VSS A1 ZN VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_0_0 ZN A1 VSS VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_1_0 VSS A2 ZN VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_3_1 net_0_0 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_2_1 ZN A1 net_0_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_2_0 net_0_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0 VDD A2 net_0_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_4.cdl b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_4.cdl
index e0d9189..ee141ab 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_4.cdl
+++ b/cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_4.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nor2_4 A1 A2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(A1 + A2)
-M_i_1_3 ZN A2 VSS VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_0_3 VSS A1 ZN VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_0_2 ZN A1 VSS VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_1_2 VSS A2 ZN VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_1_1 ZN A2 VSS VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_0_1 VSS A1 ZN VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_0_0 ZN A1 VSS VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_1_0 VSS A2 ZN VPW nmos_5p0 W=0.920000U L=0.600000U
-M_i_3_3 net_0_0 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_2_3 ZN A1 net_0_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_2_2 net_0_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 VDD A2 net_0_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 net_0_2 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_2_1 ZN A1 net_0_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_2_0 net_0_3 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0 VDD A2 net_0_3 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_1_3 ZN A2 VSS VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_0_3 VSS A1 ZN VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_0_2 ZN A1 VSS VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_1_2 VSS A2 ZN VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_1_1 ZN A2 VSS VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_0_1 VSS A1 ZN VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_0_0 ZN A1 VSS VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_1_0 VSS A2 ZN VPW nfet_05v0 W=0.920000U L=0.600000U
+M_i_3_3 net_0_0 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_2_3 ZN A1 net_0_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_2_2 net_0_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 VDD A2 net_0_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 net_0_2 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_2_1 ZN A1 net_0_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_2_0 net_0_3 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0 VDD A2 net_0_3 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_1.cdl b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_1.cdl
index cf42c86..e7cc5c0 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_1.cdl
+++ b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_1.cdl
@@ -15,10 +15,10 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nor3_1 A1 A2 A3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 + A2) + A3)
-M_i_2 ZN A3 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_1 VSS A2 ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_0 ZN A1 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_5 net_1 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4 net_0 A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3 ZN A1 net_0 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 ZN A3 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_1 VSS A2 ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_0 ZN A1 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_5 net_1 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4 net_0 A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3 ZN A1 net_0 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_2.cdl b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_2.cdl
index 7d86552..3e30d14 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_2.cdl
+++ b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_2.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nor3_2 A1 A2 A3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 + A2) + A3)
-M_i_2_1 VSS A3 ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_1_0 ZN A2 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_0_0 VSS A1 ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_0_1 ZN A1 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_1_1 VSS A2 ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_0 ZN A3 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_5_1 net_1_0 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_0_0 A2 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0 ZN A1 net_0_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 net_0_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 net_1_1 A2 net_0_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 VDD A3 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_1 VSS A3 ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_1_0 ZN A2 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_0_0 VSS A1 ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_0_1 ZN A1 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_1_1 VSS A2 ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_0 ZN A3 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_5_1 net_1_0 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_0_0 A2 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0 ZN A1 net_0_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 net_0_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 net_1_1 A2 net_0_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 VDD A3 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_4.cdl b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_4.cdl
index 19bdc60..4273632 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_4.cdl
+++ b/cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_4.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nor3_4 A1 A2 A3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 + A2) + A3)
-M_i_1_3 ZN A2 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_0 VSS A3 ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_1 ZN A3 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_1_2 VSS A2 ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_1_1 ZN A2 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_2 VSS A3 ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_3 ZN A3 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_1_0 VSS A2 ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_0_3 ZN A1 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_0_2 VSS A1 ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_0_1 ZN A1 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_0_0 VSS A1 ZN VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_4_3 net_1_3 A2 net_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 VDD A3 net_1_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 net_1_2 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_2 net_0 A2 net_1_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 net_1_1 A2 net_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_2 VDD A3 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_3 net_1_0 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_0_0 A2 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 ZN A1 net_0_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 net_0 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 ZN A1 net_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0 net_0 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_1_3 ZN A2 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_0 VSS A3 ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_1 ZN A3 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_1_2 VSS A2 ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_1_1 ZN A2 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_2 VSS A3 ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_3 ZN A3 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_1_0 VSS A2 ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_0_3 ZN A1 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_0_2 VSS A1 ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_0_1 ZN A1 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_0_0 VSS A1 ZN VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_4_3 net_1_3 A2 net_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 VDD A3 net_1_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 net_1_2 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_2 net_0 A2 net_1_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 net_1_1 A2 net_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_2 VDD A3 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_3 net_1_0 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_0_0 A2 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 ZN A1 net_0_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 net_0 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 ZN A1 net_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0 net_0 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_1.cdl b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_1.cdl
index 41bc255..8bc3a8b 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_1.cdl
+++ b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_1.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nor4_1 A1 A2 A3 A4 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) + A4)
-M_i_3 ZN A4 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_2 VSS A3 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_1 ZN A2 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0 VSS A1 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_7 net_2 A4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 net_1 A3 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 net_0 A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4 ZN A1 net_0 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3 ZN A4 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_2 VSS A3 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_1 ZN A2 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0 VSS A1 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_7 net_2 A4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 net_1 A3 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 net_0 A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4 ZN A1 net_0 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.cdl b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.cdl
index 13b3640..a7720d9 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.cdl
+++ b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nor4_2 A1 A2 A3 A4 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) + A4)
-M_i_2_1 ZN A3 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_3_1 VSS A4 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_3_0 ZN A4 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_2_0 VSS A3 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_1_1 ZN A2 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0_1 VSS A1 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0_0 ZN A1 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_1_0 VSS A2 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_6_1 net_2_1 A3 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 VDD A4 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_2_0 A4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_1_0 A3 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 net_0_1 A2 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 ZN A1 net_0_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_0_0 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_1 A2 net_0_0 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_1 ZN A3 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_3_1 VSS A4 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_3_0 ZN A4 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_2_0 VSS A3 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_1_1 ZN A2 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0_1 VSS A1 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0_0 ZN A1 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_1_0 VSS A2 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_6_1 net_2_1 A3 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 VDD A4 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_2_0 A4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_1_0 A3 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 net_0_1 A2 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 ZN A1 net_0_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_0_0 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_1 A2 net_0_0 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.cdl b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.cdl
index 9d2dca0..b4b40a0 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.cdl
+++ b/cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.cdl
@@ -15,36 +15,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__nor4_4 A1 A2 A3 A4 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) + A4)
-M_i_2_3 ZN A3 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_3_3 VSS A4 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_3_2 ZN A4 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_2_2 VSS A3 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_2_1 ZN A3 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_3_1 VSS A4 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_3_0 ZN A4 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_2_0 VSS A3 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_1_3 ZN A2 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0_3 VSS A1 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0_2 ZN A1 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_1_2 VSS A2 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_1_1 ZN A2 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0_1 VSS A1 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0_0 ZN A1 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_1_0 VSS A2 ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_6_3 net_2_3 A3 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_3 VDD A4 net_2_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_2 net_2_2 A4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_2 net_1 A3 net_2_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_2_1 A3 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 VDD A4 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_2_0 A4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_1_0 A3 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_3 net_0_3 A2 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_3 ZN A1 net_0_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_2 net_0_2 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_2 net_1 A2 net_0_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 net_0_1 A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 ZN A1 net_0_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_0_0 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_1 A2 net_0_0 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_3 ZN A3 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_3_3 VSS A4 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_3_2 ZN A4 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_2_2 VSS A3 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_2_1 ZN A3 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_3_1 VSS A4 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_3_0 ZN A4 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_2_0 VSS A3 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_1_3 ZN A2 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0_3 VSS A1 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0_2 ZN A1 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_1_2 VSS A2 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_1_1 ZN A2 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0_1 VSS A1 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0_0 ZN A1 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_1_0 VSS A2 ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_6_3 net_2_3 A3 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_3 VDD A4 net_2_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_2 net_2_2 A4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_2 net_1 A3 net_2_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_2_1 A3 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 VDD A4 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_2_0 A4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_1_0 A3 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_3 net_0_3 A2 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_3 ZN A1 net_0_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_2 net_0_2 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_2 net_1 A2 net_0_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 net_0_1 A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 ZN A1 net_0_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_0_0 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_1 A2 net_0_0 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_1.cdl b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_1.cdl
index 89c096e..f570e50 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_1.cdl
+++ b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_1.cdl
@@ -15,10 +15,10 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai21_1 A1 A2 B ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 + A2) * B)
-M_i_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 VSS B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4 net_1 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3 ZN A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 VDD B ZN VNW pmos_5p0 W=1.645000U L=0.500000U
+M_i_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 VSS B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4 net_1 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3 ZN A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 VDD B ZN VNW pfet_05v0 W=1.645000U L=0.500000U
.ENDS
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_2.cdl b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_2.cdl
index fecc1f8..6a127ac 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_2.cdl
+++ b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_2.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai21_2 A1 A2 B ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 + A2) * B)
-M_i_2_1 VSS B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_0 B VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_1 ZN B VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_5_0 VDD B ZN VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_4_1 net_1_0 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 ZN A1 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0 net_1_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 VDD A2 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_1 VSS B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_0 B VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_1 ZN B VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_5_0 VDD B ZN VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_4_1 net_1_0 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 ZN A1 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0 net_1_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 VDD A2 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.cdl b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.cdl
index fff46ee..9f28887 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.cdl
+++ b/cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai21_4 A1 A2 B ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 + A2) * B)
-M_i_1_3 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 VSS B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 net_0 B VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 VSS B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_0 B VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_3 net_1_0 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_3 ZN A1 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_2 net_1_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_2 VDD A2 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 net_1_2 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_1 ZN A1 net_1_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3_0 net_1_3 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 VDD A2 net_1_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_3 ZN B VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_5_2 VDD B ZN VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_5_1 ZN B VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_5_0 VDD B ZN VNW pmos_5p0 W=1.645000U L=0.500000U
+M_i_1_3 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 VSS B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 net_0 B VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 VSS B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_0 B VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_3 net_1_0 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_3 ZN A1 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_2 net_1_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_2 VDD A2 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 net_1_2 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_1 ZN A1 net_1_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3_0 net_1_3 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 VDD A2 net_1_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_3 ZN B VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_5_2 VDD B ZN VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_5_1 ZN B VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_5_0 VDD B ZN VNW pfet_05v0 W=1.645000U L=0.500000U
.ENDS
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.cdl b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.cdl
index 49187bd..cb219df 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.cdl
+++ b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai211_1 A1 A2 B C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) * B) * C)
-M_i_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 net_1 B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 VSS C net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5 net_2 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 VDD B ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7 ZN C VDD VNW pmos_5p0 W=1.460000U L=0.500000U
+M_i_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 net_1 B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 VSS C net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5 net_2 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 VDD B ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7 ZN C VDD VNW pfet_05v0 W=1.460000U L=0.500000U
.ENDS
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.cdl b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.cdl
index 033a8c2..979f1a4 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.cdl
+++ b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai211_2 A1 A2 B C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) * B) * C)
-M_i_1_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_1_0 B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS C net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_1_1 C VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_0 B net_1_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_1 net_2_0 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 ZN A1 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_2_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 VDD A2 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 ZN B VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7_0 VDD C ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7_1 ZN C VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_6_1 VDD B ZN VNW pmos_5p0 W=1.460000U L=0.500000U
+M_i_1_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_1_0 B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS C net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_1_1 C VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_0 B net_1_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_1 net_2_0 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 ZN A1 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_2_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 VDD A2 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 ZN B VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7_0 VDD C ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7_1 ZN C VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_6_1 VDD B ZN VNW pfet_05v0 W=1.460000U L=0.500000U
.ENDS
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.cdl b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.cdl
index 8e2af6a..16520b3 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.cdl
+++ b/cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.cdl
@@ -15,36 +15,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai211_4 A1 A2 B C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) * B) * C)
-M_i_1_3 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_1_0 B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS C net_1_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_1_1 C VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_0 B net_1_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 net_1_2 B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_2 VSS C net_1_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_3 net_1_3 C VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 net_0 B net_1_3 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_3 net_2_0 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_3 ZN A1 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_2 net_2_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_2 VDD A2 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 net_2_2 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 ZN A1 net_2_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_2_3 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 VDD A2 net_2_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 ZN B VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7_0 VDD C ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7_1 ZN C VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_6_1 VDD B ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_6_2 ZN B VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7_2 VDD C ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7_3 ZN C VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_6_3 VDD B ZN VNW pmos_5p0 W=1.460000U L=0.500000U
+M_i_1_3 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_1_0 B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS C net_1_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_1_1 C VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_0 B net_1_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 net_1_2 B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_2 VSS C net_1_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_3 net_1_3 C VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 net_0 B net_1_3 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_3 net_2_0 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_3 ZN A1 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_2 net_2_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_2 VDD A2 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 net_2_2 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 ZN A1 net_2_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_2_3 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 VDD A2 net_2_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 ZN B VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7_0 VDD C ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7_1 ZN C VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_6_1 VDD B ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_6_2 ZN B VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7_2 VDD C ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7_3 ZN C VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_6_3 VDD B ZN VNW pfet_05v0 W=1.460000U L=0.500000U
.ENDS
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.cdl b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.cdl
index 5b46b14..5e1a43f 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.cdl
+++ b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai22_1 A1 A2 B1 B2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 + A2) * (B1 + B2))
-M_i_3 VSS B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 net_0 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7 net_2 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 ZN B1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 VDD A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3 VSS B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 net_0 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7 net_2 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 ZN B1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 VDD A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.cdl b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.cdl
index 43cdcad..9deb316 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.cdl
+++ b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai22_2 A1 A2 B1 B2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 + A2) * (B1 + B2))
-M_i_3_1 VSS B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_0 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 VSS B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 net_0 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7_1 net_2_0 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 ZN B1 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_2_1 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 VDD B2 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 net_1_0 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 ZN A1 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_1_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 VDD A2 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3_1 VSS B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_0 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 VSS B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 net_0 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7_1 net_2_0 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 ZN B1 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_2_1 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 VDD B2 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 net_1_0 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 ZN A1 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_1_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 VDD A2 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_4.cdl b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_4.cdl
index bd740a1..016b5e2 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_4.cdl
+++ b/cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_4.cdl
@@ -15,36 +15,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai22_4 A1 A2 B1 B2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!((A1 + A2) * (B1 + B2))
-M_i_3_3 VSS B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 net_0 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 VSS B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_2 net_0 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 VSS B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_0 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 VSS B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 net_0 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_3 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7_3 net_2_0 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_3 ZN B1 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_2 net_2_1 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_2 VDD B2 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 net_2_2 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 ZN B1 net_2_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_2_3 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 VDD B2 net_2_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_1_0 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 ZN A1 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 net_1_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 VDD A2 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_2 net_1_2 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_2 ZN A1 net_1_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_3 net_1_3 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_3 VDD A2 net_1_3 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3_3 VSS B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 net_0 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 VSS B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_2 net_0 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 VSS B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_0 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 VSS B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 net_0 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_3 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7_3 net_2_0 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_3 ZN B1 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_2 net_2_1 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_2 VDD B2 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 net_2_2 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 ZN B1 net_2_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_2_3 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 VDD B2 net_2_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_1_0 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 ZN A1 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 net_1_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 VDD A2 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_2 net_1_2 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_2 ZN A1 net_1_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_3 net_1_3 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_3 VDD A2 net_1_3 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.cdl b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.cdl
index abb9db2..deefa96 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.cdl
+++ b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.cdl
@@ -15,14 +15,14 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai221_1 A1 A2 B1 B2 C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) * (B1 + B2)) * C)
-M_i_4 VSS B2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 net_1 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 net_0 C net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_9 net_3 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8 ZN B1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7 VDD C ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_6 net_2 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_4 VSS B2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 net_1 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 net_0 C net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_9 net_3 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8 ZN B1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7 VDD C ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_6 net_2 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.cdl b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.cdl
index a65d861..1e4ef75 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.cdl
+++ b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.cdl
@@ -15,24 +15,24 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai221_2 A1 A2 B1 B2 C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) * (B1 + B2)) * C)
-M_i_2_1 net_1 C net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_1 VSS B2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_1 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS B1 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_0 net_1 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_0 C net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7_1 VDD C ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_9_1 net_3_0 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 ZN B1 net_3_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 net_3_1 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 VDD B2 net_3_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 ZN C VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_5_1 net_2_0 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 VDD A2 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_2_1 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 ZN A1 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2_1 net_1 C net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_1 VSS B2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_1 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS B1 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_0 net_1 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_0 C net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7_1 VDD C ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_9_1 net_3_0 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 ZN B1 net_3_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 net_3_1 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 VDD B2 net_3_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 ZN C VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_5_1 net_2_0 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 VDD A2 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_2_1 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 ZN A1 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.cdl b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.cdl
index 08215c0..73269c4 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.cdl
+++ b/cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.cdl
@@ -15,44 +15,44 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai221_4 A1 A2 B1 B2 C ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) * (B1 + B2)) * C)
-M_i_3_3 net_1 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_3 VSS B2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_2 net_1 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_2 VSS B1 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_1 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_1 VSS B2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_0 net_1 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS B1 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 net_1 C net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 net_0 C net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_1 C net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_0 C net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_3 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_8_3 net_3_0 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_3 VDD B2 net_3_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_2 net_3_1 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_2 ZN B1 net_3_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 net_3_2 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_1 VDD B2 net_3_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 net_3_3 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 ZN B1 net_3_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_3 VDD C ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7_2 ZN C VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7_1 VDD C ZN VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_7_0 ZN C VDD VNW pmos_5p0 W=1.460000U L=0.500000U
-M_i_5_3 net_2_0 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_3 VDD A2 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_2 net_2_1 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_2 ZN A1 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 net_2_2 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 VDD A2 net_2_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_2_3 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 ZN A1 net_2_3 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3_3 net_1 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_3 VSS B2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_2 net_1 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_2 VSS B1 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_1 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_1 VSS B2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_0 net_1 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS B1 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 net_1 C net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 net_0 C net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_1 C net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_0 C net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_3 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_8_3 net_3_0 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_3 VDD B2 net_3_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_2 net_3_1 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_2 ZN B1 net_3_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 net_3_2 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_1 VDD B2 net_3_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 net_3_3 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 ZN B1 net_3_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_3 VDD C ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7_2 ZN C VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7_1 VDD C ZN VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_7_0 ZN C VDD VNW pfet_05v0 W=1.460000U L=0.500000U
+M_i_5_3 net_2_0 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_3 VDD A2 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_2 net_2_1 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_2 ZN A1 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 net_2_2 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 VDD A2 net_2_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_2_3 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 ZN A1 net_2_3 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_1.cdl b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_1.cdl
index 21e79b1..82bf786 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_1.cdl
+++ b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_1.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai222_1 A1 A2 B1 B2 C1 C2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C1:I C2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) * (B1 + B2)) * (C1 + C2))
-M_i_5 net_1 C2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4 VSS C1 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 net_1 B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 net_0 B2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_11 net_4 C2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10 ZN C1 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8 net_3 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9 VDD B2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7 net_2 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_5 net_1 C2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4 VSS C1 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 net_1 B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 net_0 B2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_11 net_4 C2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10 ZN C1 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8 net_3 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9 VDD B2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7 net_2 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_2.cdl b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_2.cdl
index fea0213..2cc99b5 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_2.cdl
+++ b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_2.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai222_2 A1 A2 B1 B2 C1 C2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C1:I C2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) * (B1 + B2)) * (C1 + C2))
-M_i_4_1 net_1 C1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_1 VSS C2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_0 net_1 C2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_0 VSS C1 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_1 B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 net_0 B2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_1 B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_0 B1 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_10_1 net_4_1 C1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_1 VDD C2 net_4_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_0 net_4_0 C2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_0 ZN C1 net_4_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 net_3_1 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 VDD B2 net_3_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_1 net_3_0 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 ZN B1 net_3_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_2_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 VDD A2 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 net_2_0 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 ZN A1 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_4_1 net_1 C1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_1 VSS C2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_0 net_1 C2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_0 VSS C1 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_1 B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 net_0 B2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_1 B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_0 B1 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_10_1 net_4_1 C1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_1 VDD C2 net_4_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_0 net_4_0 C2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_0 ZN C1 net_4_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 net_3_1 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 VDD B2 net_3_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_1 net_3_0 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 ZN B1 net_3_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_2_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 VDD A2 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 net_2_0 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 ZN A1 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_4.cdl b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_4.cdl
index 51820ff..f7c49cc 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_4.cdl
+++ b/cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_4.cdl
@@ -15,52 +15,52 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai222_4 A1 A2 B1 B2 C1 C2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I B1:I B2:I C1:I C2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) * (B1 + B2)) * (C1 + C2))
-M_i_4_3 net_1 C1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_3 VSS C2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_2 net_1 C2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_2 VSS C1 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_1 net_1 C1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_1 VSS C2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_0 net_1 C2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_0 VSS C1 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_1 B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 net_0 B2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_1 B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_0 B1 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 net_1 B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_2 net_0 B2 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_3 net_1 B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 net_0 B1 net_1 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_3 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_10_3 net_4_3 C1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_3 VDD C2 net_4_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_2 net_4_2 C2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_2 ZN C1 net_4_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_1 net_4_1 C1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_1 VDD C2 net_4_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_0 net_4_0 C2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_0 ZN C1 net_4_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 net_3_3 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 VDD B2 net_3_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_1 net_3_2 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 ZN B1 net_3_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_2 net_3_1 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_2 VDD B2 net_3_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_3 net_3_0 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_3 ZN B1 net_3_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_2_3 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 VDD A2 net_2_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 net_2_2 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 ZN A1 net_2_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_2 net_2_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_2 VDD A2 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_3 net_2_0 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_3 ZN A1 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_4_3 net_1 C1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_3 VSS C2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_2 net_1 C2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_2 VSS C1 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_1 net_1 C1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_1 VSS C2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_0 net_1 C2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_0 VSS C1 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_1 B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 net_0 B2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_1 B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_0 B1 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 net_1 B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_2 net_0 B2 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_3 net_1 B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 net_0 B1 net_1 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_3 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_10_3 net_4_3 C1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_3 VDD C2 net_4_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_2 net_4_2 C2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_2 ZN C1 net_4_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_1 net_4_1 C1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_1 VDD C2 net_4_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_0 net_4_0 C2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_0 ZN C1 net_4_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 net_3_3 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 VDD B2 net_3_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_1 net_3_2 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 ZN B1 net_3_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_2 net_3_1 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_2 VDD B2 net_3_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_3 net_3_0 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_3 ZN B1 net_3_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_2_3 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 VDD A2 net_2_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 net_2_2 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 ZN A1 net_2_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_2 net_2_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_2 VDD A2 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_3 net_2_0 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_3 ZN A1 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.cdl b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.cdl
index bea82f2..e77a422 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.cdl
+++ b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai31_1 A1 A2 A3 B ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I B:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) * B)
-M_i_3 net_0 B VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 ZN A3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7 ZN B VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_4 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 net_2 A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 VDD A3 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3 net_0 B VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 ZN A3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7 ZN B VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_4 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 net_2 A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 VDD A3 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.cdl b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.cdl
index dd8c137..a7dbb80 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.cdl
+++ b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai31_2 A1 A2 A3 B ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I B:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) * B)
-M_i_3_1 VSS B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 net_0 B VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 ZN A3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_0 A3 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7_1 ZN B VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_7_0 VDD B ZN VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_6_1 net_2_0 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 net_1_0 A2 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 ZN A1 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_1_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_2_1 A2 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 VDD A3 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3_1 VSS B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 net_0 B VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 ZN A3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_0 A3 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7_1 ZN B VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_7_0 VDD B ZN VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_6_1 net_2_0 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 net_1_0 A2 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 ZN A1 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_1_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_2_1 A2 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 VDD A3 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_4.cdl b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_4.cdl
index aa8aebb..92bdb37 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_4.cdl
+++ b/cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_4.cdl
@@ -15,36 +15,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai31_4 A1 A2 A3 B ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I B:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) * B)
-M_i_2_3 ZN A3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 net_0 A3 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 ZN A3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_0 A3 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_3 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_3 VSS B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_2 net_0 B VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 VSS B net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 net_0 B VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_3 VDD A3 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_2 net_2 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 VDD A3 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_2_0 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_3 net_1_0 A2 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_3 ZN A1 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_2 net_1_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_2 net_2 A2 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 net_1_2 A2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 ZN A1 net_1_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_1_3 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_2 A2 net_1_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_3 ZN B VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_7_2 VDD B ZN VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_7_1 ZN B VDD VNW pmos_5p0 W=1.645000U L=0.500000U
-M_i_7_0 VDD B ZN VNW pmos_5p0 W=1.645000U L=0.500000U
+M_i_2_3 ZN A3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 net_0 A3 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 ZN A3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_0 A3 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_3 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_3 VSS B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_2 net_0 B VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 VSS B net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 net_0 B VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_3 VDD A3 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_2 net_2 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 VDD A3 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_2_0 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_3 net_1_0 A2 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_3 ZN A1 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_2 net_1_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_2 net_2 A2 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 net_1_2 A2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 ZN A1 net_1_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_1_3 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_2 A2 net_1_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_3 ZN B VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_7_2 VDD B ZN VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_7_1 ZN B VDD VNW pfet_05v0 W=1.645000U L=0.500000U
+M_i_7_0 VDD B ZN VNW pfet_05v0 W=1.645000U L=0.500000U
.ENDS
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.cdl b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.cdl
index 8dac50b..552a4bc 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.cdl
+++ b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.cdl
@@ -15,14 +15,14 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai32_1 A1 A2 A3 B1 B2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I B1:I B2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) * (B1 + B2))
-M_i_4 net_0 A3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 VSS A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 net_0 A1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 ZN B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 net_0 B2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_9 net_3 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8 net_2 A2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 net_1 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 VDD B2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_4 net_0 A3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 VSS A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 net_0 A1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 ZN B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 net_0 B2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_9 net_3 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8 net_2 A2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 net_1 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 VDD B2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.cdl b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.cdl
index 4f67397..b5bd27f 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.cdl
+++ b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.cdl
@@ -15,24 +15,24 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai32_2 A1 A2 A3 B1 B2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I B1:I B2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) * (B1 + B2))
-M_i_4_1 VSS A3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 VSS A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_0 A1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_0 net_0 A3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0 B1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0 B2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_9_1 net_3_0 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 net_2_0 A2 net_3_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 ZN A1 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_2_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 net_3_1 A2 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 VDD A3 net_3_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_1_0 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 ZN B1 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 net_1_1 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 VDD B2 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_4_1 VSS A3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 VSS A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_0 A1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_0 net_0 A3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0 B1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0 B2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_9_1 net_3_0 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 net_2_0 A2 net_3_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 ZN A1 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_2_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 net_3_1 A2 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 VDD A3 net_3_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_1_0 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 ZN B1 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 net_1_1 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 VDD B2 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.cdl b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.cdl
index cf8b7a2..fa9b564 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.cdl
+++ b/cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.cdl
@@ -15,44 +15,44 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai32_4 A1 A2 A3 B1 B2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I B1:I B2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) * (B1 + B2))
-M_i_3_3 VSS A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_3 net_0 A3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_2 VSS A3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_2 net_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 VSS A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_1 net_0 A3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_0 VSS A3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 net_0 A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 VSS A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 net_0 A1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 VSS A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 net_0 A1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_3 ZN B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 net_0 B1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 net_0 B2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 ZN B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0 B1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0 B2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_8_3 net_3_0 A2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_3 VDD A3 net_3_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_2 net_3_1 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_2 net_2 A2 net_3_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 net_3_2 A2 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_1 VDD A3 net_3_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 net_3_3 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 net_2_0 A2 net_3_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_3 ZN A1 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_2 net_2 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 ZN A1 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_2 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_3 net_1_0 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_3 ZN B1 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_2 net_1_1 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_2 VDD B2 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_1_2 B2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 ZN B1 net_1_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_1_3 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 VDD B2 net_1_3 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3_3 VSS A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_3 net_0 A3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_2 VSS A3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_2 net_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 VSS A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_1 net_0 A3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_0 VSS A3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 net_0 A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 VSS A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 net_0 A1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 VSS A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 net_0 A1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_3 ZN B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 net_0 B1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 net_0 B2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 ZN B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0 B1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0 B2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_8_3 net_3_0 A2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_3 VDD A3 net_3_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_2 net_3_1 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_2 net_2 A2 net_3_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 net_3_2 A2 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_1 VDD A3 net_3_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 net_3_3 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 net_2_0 A2 net_3_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_3 ZN A1 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_2 net_2 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 ZN A1 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_2 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_3 net_1_0 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_3 ZN B1 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_2 net_1_1 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_2 VDD B2 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_1_2 B2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 ZN B1 net_1_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_1_3 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 VDD B2 net_1_3 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.cdl b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.cdl
index abdeacf..42705ce 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.cdl
+++ b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai33_1 A1 A2 A3 B1 B2 B3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I B1:I B2:I B3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) * ((B1 + B2) + B3))
-M_i_5 net_0 B3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4 VSS B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 net_0 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 ZN A3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_11 net_4 B3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10 net_3 B2 net_4 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9 ZN B1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7 net_2 A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8 VDD A3 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_5 net_0 B3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4 VSS B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 net_0 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 ZN A3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_11 net_4 B3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10 net_3 B2 net_4 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9 ZN B1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7 net_2 A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8 VDD A3 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_2.cdl b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_2.cdl
index 305a72e..a82cec0 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_2.cdl
+++ b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_2.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai33_2 A1 A2 A3 B1 B2 B3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I B1:I B2:I B3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) * ((B1 + B2) + B3))
-M_i_5_0 VSS B3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_1 net_0 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 VSS B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 net_0 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_0 VSS B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_1 net_0 B3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 ZN A3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_0 A3 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_11_0 net_4_0 B3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_1 net_3_0 B2 net_4_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_1 ZN B1 net_3_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 net_3_1 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_0 net_4_1 B2 net_3_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_1 VDD B3 net_4_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 net_2_0 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 net_1_0 A2 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 ZN A1 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_1_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_2_1 A2 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 VDD A3 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_5_0 VSS B3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_1 net_0 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 VSS B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 net_0 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_0 VSS B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_1 net_0 B3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 ZN A3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_0 A3 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_11_0 net_4_0 B3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_1 net_3_0 B2 net_4_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_1 ZN B1 net_3_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 net_3_1 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_0 net_4_1 B2 net_3_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_1 VDD B3 net_4_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 net_2_0 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 net_1_0 A2 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 ZN A1 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_1_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_2_1 A2 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 VDD A3 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.cdl b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.cdl
index 3d9d363..769d82e 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.cdl
+++ b/cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.cdl
@@ -15,52 +15,52 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__oai33_4 A1 A2 A3 B1 B2 B3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I B1:I B2:I B3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(((A1 + A2) + A3) * ((B1 + B2) + B3))
-M_i_4_0 VSS B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_0 net_0 B3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_1 VSS B3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_1 net_0 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_2 VSS B2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_2 net_0 B3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_3 VSS B3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4_3 net_0 B2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_1 net_0 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_2 VSS B1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_3 net_0 B1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 net_0 A1 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_3 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_3 net_0 A3 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_2 ZN A3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_2 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_1 ZN A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 net_0 A3 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 ZN A3 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1_0 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_10_0 net_4_0 B2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_0 VDD B3 net_4_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_1 net_4_1 B3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_1 net_3 B2 net_4_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_2 net_4_2 B2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_2 VDD B3 net_4_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11_3 net_4_3 B3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10_3 net_3_0 B2 net_4_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0 ZN B1 net_3_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_1 net_3 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_2 ZN B1 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_3 net_3 B1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 ZN A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_2 ZN A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_3 net_1_0 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_3 net_2_0 A2 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_3 VDD A3 net_2_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_2 net_2_1 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_2 net_1 A2 net_2_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 net_2_2 A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_1 VDD A3 net_2_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0 net_2_3 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 net_1 A2 net_2_3 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_4_0 VSS B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_0 net_0 B3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_1 VSS B3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_1 net_0 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_2 VSS B2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_2 net_0 B3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_3 VSS B3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4_3 net_0 B2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_1 net_0 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_2 VSS B1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_3 net_0 B1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 net_0 A1 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_3 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_3 net_0 A3 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_2 ZN A3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_2 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_1 ZN A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 net_0 A3 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 ZN A3 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1_0 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_10_0 net_4_0 B2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_0 VDD B3 net_4_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_1 net_4_1 B3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_1 net_3 B2 net_4_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_2 net_4_2 B2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_2 VDD B3 net_4_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11_3 net_4_3 B3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10_3 net_3_0 B2 net_4_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0 ZN B1 net_3_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_1 net_3 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_2 ZN B1 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_3 net_3 B1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 ZN A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_2 ZN A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_3 net_1_0 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_3 net_2_0 A2 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_3 VDD A3 net_2_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_2 net_2_1 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_2 net_1 A2 net_2_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 net_2_2 A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_1 VDD A3 net_2_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0 net_2_3 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 net_1 A2 net_2_3 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_1.cdl b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_1.cdl
index 79e0add..d0db993 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_1.cdl
+++ b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_1.cdl
@@ -15,10 +15,10 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__or2_1 A1 A2 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(A1 + A2)
-M_i_2 Z_neg A1 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_3 VSS A2 Z_neg VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4 net_0 A1 Z_neg VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_5 VDD A2 net_0 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 Z_neg A1 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_3 VSS A2 Z_neg VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4 net_0 A1 Z_neg VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_5 VDD A2 net_0 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_2.cdl b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_2.cdl
index f2bd0cc..b56c3fd 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_2.cdl
+++ b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_2.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__or2_2 A1 A2 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(A1 + A2)
-M_i_2 Z_neg A1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 VSS A2 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_4 net_0 A1 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 VDD A2 net_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 Z_neg A1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 VSS A2 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_4 net_0 A1 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 VDD A2 net_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_4.cdl b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_4.cdl
index e9bfbae..05d2879 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_4.cdl
+++ b/cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_4.cdl
@@ -15,20 +15,20 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__or2_4 A1 A2 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(A1 + A2)
-M_i_3_1 Z_neg A2 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_1 VSS A1 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2_0 Z_neg A1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3_0 VSS A2 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5_1 net_0_1 A2 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_1 Z_neg A1 net_0_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4_0 net_0_0 A1 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 VDD A2 net_0_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_3_1 Z_neg A2 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_1 VSS A1 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2_0 Z_neg A1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3_0 VSS A2 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5_1 net_0_1 A2 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_1 Z_neg A1 net_0_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4_0 net_0_0 A1 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 VDD A2 net_0_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_1.cdl b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_1.cdl
index a14b1cb..4d0ffec 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_1.cdl
+++ b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_1.cdl
@@ -15,12 +15,12 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__or3_1 A1 A2 A3 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((A1 + A2) + A3)
-M_i_2 VSS A1 Z_neg VPW nmos_5p0 W=0.525000U L=0.600000U
-M_i_3 Z_neg A2 VSS VPW nmos_5p0 W=0.525000U L=0.600000U
-M_i_4 VSS A3 Z_neg VPW nmos_5p0 W=0.525000U L=0.600000U
-M_i_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5 net_0 A1 Z_neg VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_6 net_1 A2 net_0 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_7 VDD A3 net_1 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 VSS A1 Z_neg VPW nfet_05v0 W=0.525000U L=0.600000U
+M_i_3 Z_neg A2 VSS VPW nfet_05v0 W=0.525000U L=0.600000U
+M_i_4 VSS A3 Z_neg VPW nfet_05v0 W=0.525000U L=0.600000U
+M_i_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5 net_0 A1 Z_neg VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_6 net_1 A2 net_0 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_7 VDD A3 net_1 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_2.cdl b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_2.cdl
index c4bdc1b..1313e54 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_2.cdl
+++ b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_2.cdl
@@ -15,14 +15,14 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__or3_2 A1 A2 A3 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((A1 + A2) + A3)
-M_i_2 VSS A1 Z_neg VPW nmos_5p0 W=1.050000U L=0.600000U
-M_i_3 Z_neg A2 VSS VPW nmos_5p0 W=1.050000U L=0.600000U
-M_i_4 VSS A3 Z_neg VPW nmos_5p0 W=1.050000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_5 net_0 A1 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 net_1 A2 net_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7 VDD A3 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 VSS A1 Z_neg VPW nfet_05v0 W=1.050000U L=0.600000U
+M_i_3 Z_neg A2 VSS VPW nfet_05v0 W=1.050000U L=0.600000U
+M_i_4 VSS A3 Z_neg VPW nfet_05v0 W=1.050000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_5 net_0 A1 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 net_1 A2 net_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7 VDD A3 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_4.cdl b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_4.cdl
index 44f8f34..eb6ed13 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_4.cdl
+++ b/cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_4.cdl
@@ -15,24 +15,24 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__or3_4 A1 A2 A3 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=((A1 + A2) + A3)
-M_i_4_0 Z_neg A3 VSS VPW nmos_5p0 W=1.050000U L=0.600000U
-M_i_3_1 VSS A2 Z_neg VPW nmos_5p0 W=1.050000U L=0.600000U
-M_i_2_1 Z_neg A1 VSS VPW nmos_5p0 W=1.050000U L=0.600000U
-M_i_2_0 VSS A1 Z_neg VPW nmos_5p0 W=1.050000U L=0.600000U
-M_i_3_0 Z_neg A2 VSS VPW nmos_5p0 W=1.050000U L=0.600000U
-M_i_4_1 VSS A3 Z_neg VPW nmos_5p0 W=1.050000U L=0.600000U
-M_i_0_3 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7_0 net_1_1 A3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_1 net_0_1 A2 net_1_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_1 Z_neg A1 net_0_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5_0 net_0_0 A1 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0 net_1_0 A2 net_0_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 VDD A3 net_1_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_4_0 Z_neg A3 VSS VPW nfet_05v0 W=1.050000U L=0.600000U
+M_i_3_1 VSS A2 Z_neg VPW nfet_05v0 W=1.050000U L=0.600000U
+M_i_2_1 Z_neg A1 VSS VPW nfet_05v0 W=1.050000U L=0.600000U
+M_i_2_0 VSS A1 Z_neg VPW nfet_05v0 W=1.050000U L=0.600000U
+M_i_3_0 Z_neg A2 VSS VPW nfet_05v0 W=1.050000U L=0.600000U
+M_i_4_1 VSS A3 Z_neg VPW nfet_05v0 W=1.050000U L=0.600000U
+M_i_0_3 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7_0 net_1_1 A3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_1 net_0_1 A2 net_1_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_1 Z_neg A1 net_0_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5_0 net_0_0 A1 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0 net_1_0 A2 net_0_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 VDD A3 net_1_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_1.cdl b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_1.cdl
index 245e8e7..12ce5a7 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_1.cdl
+++ b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_1.cdl
@@ -15,14 +15,14 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__or4_1 A1 A2 A3 A4 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(((A1 + A2) + A3) + A4)
-M_i_2 Z_neg A1 VSS VPW nmos_5p0 W=0.395000U L=0.600000U
-M_i_3 VSS A2 Z_neg VPW nmos_5p0 W=0.395000U L=0.600000U
-M_i_4 Z_neg A3 VSS VPW nmos_5p0 W=0.395000U L=0.600000U
-M_i_5 VSS A4 Z_neg VPW nmos_5p0 W=0.395000U L=0.600000U
-M_i_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6 net_0 A1 Z_neg VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_7 net_1 A2 net_0 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_8 net_2 A3 net_1 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_9 VDD A4 net_2 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 Z_neg A1 VSS VPW nfet_05v0 W=0.395000U L=0.600000U
+M_i_3 VSS A2 Z_neg VPW nfet_05v0 W=0.395000U L=0.600000U
+M_i_4 Z_neg A3 VSS VPW nfet_05v0 W=0.395000U L=0.600000U
+M_i_5 VSS A4 Z_neg VPW nfet_05v0 W=0.395000U L=0.600000U
+M_i_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6 net_0 A1 Z_neg VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_7 net_1 A2 net_0 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_8 net_2 A3 net_1 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_9 VDD A4 net_2 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_2.cdl b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_2.cdl
index 9acc387..6ca24e7 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_2.cdl
+++ b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_2.cdl
@@ -15,16 +15,16 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__or4_2 A1 A2 A3 A4 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(((A1 + A2) + A3) + A4)
-M_i_2 Z_neg A1 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_3 VSS A2 Z_neg VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_4 Z_neg A3 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_5 VSS A4 Z_neg VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6 net_0 A1 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7 net_1 A2 net_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8 net_2 A3 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9 VDD A4 net_2 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_2 Z_neg A1 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_3 VSS A2 Z_neg VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_4 Z_neg A3 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_5 VSS A4 Z_neg VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6 net_0 A1 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7 net_1 A2 net_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8 net_2 A3 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9 VDD A4 net_2 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_4.cdl b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_4.cdl
index 9c6100b..1feb8f7 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_4.cdl
+++ b/cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_4.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__or4_4 A1 A2 A3 A4 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I A4:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=(((A1 + A2) + A3) + A4)
-M_i_5_1_x2_1 Z_neg A4 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_4_1_x2_1 VSS A3 Z_neg VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_3_1_x2_1 Z_neg A2 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_1_x2_1 VSS A1 Z_neg VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_2_1_x2_0 Z_neg A1 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_3_1_x2_0 VSS A2 Z_neg VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_4_1_x2_0 Z_neg A3 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_5_1_x2_0 VSS A4 Z_neg VPW nmos_5p0 W=0.790000U L=0.600000U
-M_i_0_3_x4_3 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3_x4_2 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3_x4_1 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3_x4_0 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_9_0_m2_1 net_2_0_1 A4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0_m2_1 net_1_0_1 A3 net_2_0_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0_m2_1 net_0_0_1 A2 net_1_0_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0_m2_1 Z_neg A1 net_0_0_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6_0_m2_0 net_0_0_0 A1 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0_m2_0 net_1_0_0 A2 net_0_0_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_8_0_m2_0 net_2_0_0 A3 net_1_0_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9_0_m2_0 VDD A4 net_2_0_0 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3_x4_3 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3_x4_2 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3_x4_1 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3_x4_0 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_5_1_x2_1 Z_neg A4 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_4_1_x2_1 VSS A3 Z_neg VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_3_1_x2_1 Z_neg A2 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_1_x2_1 VSS A1 Z_neg VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_2_1_x2_0 Z_neg A1 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_3_1_x2_0 VSS A2 Z_neg VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_4_1_x2_0 Z_neg A3 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_5_1_x2_0 VSS A4 Z_neg VPW nfet_05v0 W=0.790000U L=0.600000U
+M_i_0_3_x4_3 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3_x4_2 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3_x4_1 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3_x4_0 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_9_0_m2_1 net_2_0_1 A4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0_m2_1 net_1_0_1 A3 net_2_0_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0_m2_1 net_0_0_1 A2 net_1_0_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0_m2_1 Z_neg A1 net_0_0_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6_0_m2_0 net_0_0_0 A1 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0_m2_0 net_1_0_0 A2 net_0_0_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_8_0_m2_0 net_2_0_0 A3 net_1_0_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9_0_m2_0 VDD A4 net_2_0_0 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3_x4_3 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3_x4_2 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3_x4_1 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3_x4_0 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_1.cdl b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_1.cdl
index 6215b3d..f02bc96 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_1.cdl
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_1.cdl
@@ -14,36 +14,36 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffq_1 D SE SI CLK Q VDD VNW VPW VSS
*.PININFO D:I SE:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn14 net8 SE VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn12 net12 SI VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn13 net12 SE net6 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn8 net6 net8 net9n VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn10 VSS D net9n VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn16 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn9 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn11 net6 ncki net5 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn0 net5 cki net11 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn1 VSS net10 net11 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn15 net10 net5 VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn2 net0 cki net10 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn3 net7 ncki net0 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn4 VSS net1 net7 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn5 net1 net0 VSS VPW nmos_5p0 W=0.750000U L=0.600000U
-M_tn6 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp14 net8 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net3 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net2 net8 net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net9p SE net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 VDD D net9p VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp11 net5 cki net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net4 ncki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 VDD net10 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net10 net5 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net0 ncki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net7_p cki net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD net1 net7_p VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net1 net0 VDD VNW pmos_5p0 W=1.100000U L=0.500000U
-M_tp4 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn14 net8 SE VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn12 net12 SI VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn13 net12 SE net6 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn8 net6 net8 net9n VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn10 VSS D net9n VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn16 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn9 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn11 net6 ncki net5 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn0 net5 cki net11 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn1 VSS net10 net11 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn15 net10 net5 VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn2 net0 cki net10 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn3 net7 ncki net0 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn4 VSS net1 net7 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn5 net1 net0 VSS VPW nfet_05v0 W=0.750000U L=0.600000U
+M_tn6 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp14 net8 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net3 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net2 net8 net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net9p SE net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 VDD D net9p VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp11 net5 cki net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net4 ncki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 VDD net10 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net10 net5 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net0 ncki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net7_p cki net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD net1 net7_p VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net1 net0 VDD VNW pfet_05v0 W=1.100000U L=0.500000U
+M_tp4 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_2.cdl b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_2.cdl
index 8df1848..ed13837 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_2.cdl
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_2.cdl
@@ -14,38 +14,38 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffq_2 D SE SI CLK Q VDD VNW VPW VSS
*.PININFO D:I SE:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn14 net8 SE VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn12 net12 SI VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn13 net12 SE net6 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn8 net6 net8 net9n VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn10 VSS D net9n VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn16 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn9 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn11 net6 ncki net5 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn0 net5 cki net11 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn1 VSS net10 net11 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn15 net10 net5 VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn2 net0 cki net10 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn3 net7 ncki net0 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn4 VSS net1 net7 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn5 net1 net0 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6_6 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp14 net8 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net3 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net2 net8 net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net9p SE net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 VDD D net9p VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp11 net5 cki net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net4 ncki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 VDD net10 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net10 net5 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net0 ncki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net7_p cki net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD net1 net7_p VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp3 net1 net0 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4_12 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn14 net8 SE VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn12 net12 SI VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn13 net12 SE net6 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn8 net6 net8 net9n VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn10 VSS D net9n VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn16 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn9 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn11 net6 ncki net5 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn0 net5 cki net11 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn1 VSS net10 net11 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn15 net10 net5 VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn2 net0 cki net10 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn3 net7 ncki net0 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn4 VSS net1 net7 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn5 net1 net0 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6_6 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp14 net8 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net3 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net2 net8 net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net9p SE net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 VDD D net9p VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp11 net5 cki net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net4 ncki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 VDD net10 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net10 net5 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net0 ncki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net7_p cki net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD net1 net7_p VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp3 net1 net0 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4_12 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.cdl b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.cdl
index 8f867b3..538796e 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.cdl
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.cdl
@@ -14,42 +14,42 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffq_4 D SE SI CLK Q VDD VNW VPW VSS
*.PININFO D:I SE:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn14 net8 SE VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn12 net12 SI VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn13 net12 SE net6 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn8 net6 net8 net9n VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn10 VSS D net9n VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn16 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn9 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn11 net6 ncki net5 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn0 net5 cki net11 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn1 VSS net10 net11 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn15 net10 net5 VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn2 net0 cki net10 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn3 net7 ncki net0 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn4 VSS net1 net7 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn5 net1 net0 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6_6_25 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6_5 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6_6 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn6 Q net1 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp14 net8 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net3 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net2 net8 net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net9p SE net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 VDD D net9p VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp11 net5 cki net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net4 ncki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 VDD net10 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp15 net10 net5 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net0 ncki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net7_p cki net0 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD net1 net7_p VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp3 net1 net0 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4_12_24 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4_16 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4_12 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp4 Q net1 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn14 net8 SE VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn12 net12 SI VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn13 net12 SE net6 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn8 net6 net8 net9n VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn10 VSS D net9n VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn16 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn9 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn11 net6 ncki net5 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn0 net5 cki net11 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn1 VSS net10 net11 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn15 net10 net5 VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn2 net0 cki net10 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn3 net7 ncki net0 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn4 VSS net1 net7 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn5 net1 net0 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6_6_25 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6_5 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6_6 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn6 Q net1 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp14 net8 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net3 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net2 net8 net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net9p SE net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 VDD D net9p VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp11 net5 cki net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net4 ncki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 VDD net10 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp15 net10 net5 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net0 ncki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net7_p cki net0 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD net1 net7_p VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp3 net1 net0 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4_12_24 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4_16 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4_12 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp4 Q net1 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.cdl b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.cdl
index 4e619d7..1584899 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.cdl
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.cdl
@@ -14,40 +14,40 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1 D RN SE SI CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I SE:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn17 net3 SE VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn7 VSS SI net13 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn6 net13 SE net10 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn11 net10 D net5 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn16 net5 net3 VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn10 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn13 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn15 net10 ncki net1 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn14 net1 cki net15 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn8 net12 net2 net15 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn9 VSS RN net12 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn18 VSS net1 net2 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn0 net8 cki net2 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn1 net11 ncki net8 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn12 net11 net4 VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn5 net0 RN VSS VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn4 net4 net8 net0 VPW nmos_5p0 W=0.580000U L=0.600000U
-M_tn3 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp17 net3 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net7 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net6 net3 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net14 D net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp14 VDD SE net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp11 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp15 net1 cki net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net9 ncki net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 VDD net2 net9 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net9 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 VDD net1 net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net2 ncki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 cki net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net4 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 VDD net8 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn17 net3 SE VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn7 VSS SI net13 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn6 net13 SE net10 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn11 net10 D net5 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn16 net5 net3 VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn10 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn13 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn15 net10 ncki net1 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn14 net1 cki net15 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn8 net12 net2 net15 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn9 VSS RN net12 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn18 VSS net1 net2 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn0 net8 cki net2 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn1 net11 ncki net8 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn12 net11 net4 VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn5 net0 RN VSS VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn4 net4 net8 net0 VPW nfet_05v0 W=0.580000U L=0.600000U
+M_tn3 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp17 net3 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net7 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net6 net3 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net14 D net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp14 VDD SE net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp11 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp15 net1 cki net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net9 ncki net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 VDD net2 net9 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net9 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 VDD net1 net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net2 ncki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 cki net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net4 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 VDD net8 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.cdl b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.cdl
index 8de3497..24cfa2d 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.cdl
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.cdl
@@ -14,42 +14,42 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2 D RN SE SI CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I SE:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn17 net3 SE VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS SI net13 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net13 SE net10 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn11 net10 D net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn16 net5 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn10 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn13 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn15 net10 ncki net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net1 cki net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net12 net2 net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn9 VSS RN net12 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 VSS net1 net2 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn0 net8 cki net2 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net11 ncki net8 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net11 net4 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net0 RN VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_tn4 net4 net8 net0 VPW nmos_5p0 W=1.000000U L=0.600000U
-M_tn3_17 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp17 net3 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net7 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net6 net3 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net14 D net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp14 VDD SE net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp11 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp15 net1 cki net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net9 ncki net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 VDD net2 net9 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net9 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 VDD net1 net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net2 ncki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 cki net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net4 RN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp4 VDD net8 net4 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp1_16 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn17 net3 SE VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS SI net13 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net13 SE net10 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn11 net10 D net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn16 net5 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn10 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn13 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn15 net10 ncki net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net1 cki net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net12 net2 net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn9 VSS RN net12 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 VSS net1 net2 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn0 net8 cki net2 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net11 ncki net8 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net11 net4 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net0 RN VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_tn4 net4 net8 net0 VPW nfet_05v0 W=1.000000U L=0.600000U
+M_tn3_17 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp17 net3 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net7 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net6 net3 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net14 D net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp14 VDD SE net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp11 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp15 net1 cki net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net9 ncki net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 VDD net2 net9 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net9 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 VDD net1 net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net2 ncki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 cki net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net4 RN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp4 VDD net8 net4 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp1_16 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.cdl b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.cdl
index bd4ece4..0a9046c 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.cdl
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.cdl
@@ -14,46 +14,46 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4 D RN SE SI CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I SE:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn17 net3 SE VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS SI net13 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net13 SE net10 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn11 net10 D net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn16 net5 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn10 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn13 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn15 net10 ncki net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net1 cki net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net12 net2 net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn9 VSS RN net12 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 VSS net1 net2 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn0 net8 cki net2 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net11 ncki net8 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net11 net4 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net0 RN VSS VPW nmos_5p0 W=1.000000U L=0.600000U
-M_tn4 net4 net8 net0 VPW nmos_5p0 W=1.000000U L=0.600000U
-M_tn3_17_4 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3_27 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3_17 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn3 Q net4 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp17 net3 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net7 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net6 net3 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 net14 D net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp14 VDD SE net14 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp11 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp15 net1 cki net6 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net9 ncki net1 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 VDD net2 net9 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net9 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 VDD net1 net2 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 net2 ncki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net8 cki net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 net4 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 net4 RN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp4 VDD net8 net4 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp1_16_17 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_25 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1_16 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp1 Q net4 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn17 net3 SE VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS SI net13 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net13 SE net10 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn11 net10 D net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn16 net5 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn10 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn13 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn15 net10 ncki net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net1 cki net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net12 net2 net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn9 VSS RN net12 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 VSS net1 net2 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn0 net8 cki net2 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net11 ncki net8 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net11 net4 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net0 RN VSS VPW nfet_05v0 W=1.000000U L=0.600000U
+M_tn4 net4 net8 net0 VPW nfet_05v0 W=1.000000U L=0.600000U
+M_tn3_17_4 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3_27 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3_17 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn3 Q net4 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp17 net3 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net7 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net6 net3 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 net14 D net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp14 VDD SE net14 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp11 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp15 net1 cki net6 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net9 ncki net1 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 VDD net2 net9 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net9 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 VDD net1 net2 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 net2 ncki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net8 cki net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 net4 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 net4 RN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp4 VDD net8 net4 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp1_16_17 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_25 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1_16 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp1 Q net4 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.cdl b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.cdl
index 646d0f9..18e9a40 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.cdl
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.cdl
@@ -14,44 +14,44 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1 D RN SE SETN SI CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I SE:I SETN:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn12 net9 SE VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn9 VSS SI net17 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn10 net17 SE net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn0 net14 D net8 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn11 net8 net9 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn2 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn8 net14 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net3 cki net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net15 net4 net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS RN net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net1 SETN net7 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn16 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net2 RN VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn17 net6 net5 net2 VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn19 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp12 net9 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp11 net12 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net10 net9 net12 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net11 D net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 VDD SE net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp2 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp10 net3 cki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net13 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net13 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 VDD net3 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp20 net4 ncki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp19 net5 cki net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net7 SETN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp14 net7 net6 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 RN VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp15 VDD net5 net6 VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp17 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn12 net9 SE VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn9 VSS SI net17 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn10 net17 SE net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn0 net14 D net8 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn11 net8 net9 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn2 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn8 net14 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net3 cki net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net15 net4 net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS RN net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net1 SETN net7 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn16 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net2 RN VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn17 net6 net5 net2 VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn19 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp12 net9 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp11 net12 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net10 net9 net12 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net11 D net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 VDD SE net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp2 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp10 net3 cki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net13 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net13 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 VDD net3 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp20 net4 ncki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp19 net5 cki net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net7 SETN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp14 net7 net6 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 RN VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp15 VDD net5 net6 VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp17 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.cdl b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.cdl
index 562135c..36d410f 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.cdl
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.cdl
@@ -14,46 +14,46 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2 D RN SE SETN SI CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I SE:I SETN:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn12 net9 SE VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn9 VSS SI net17 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn10 net17 SE net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn0 net14 D net8 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn11 net8 net9 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn2 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn8 net14 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net3 cki net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net15 net4 net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS RN net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net1 SETN net7 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn16 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net2 RN VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn17 net6 net5 net2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19_14 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp12 net9 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp11 net12 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net10 net9 net12 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net11 D net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 VDD SE net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp2 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp10 net3 cki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net13 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net13 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 VDD net3 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp20 net4 ncki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp19 net5 cki net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net7 SETN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp14 net7 net6 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 RN VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp15 VDD net5 net6 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17_7 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn12 net9 SE VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn9 VSS SI net17 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn10 net17 SE net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn0 net14 D net8 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn11 net8 net9 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn2 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn8 net14 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net3 cki net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net15 net4 net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS RN net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net1 SETN net7 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn16 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net2 RN VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn17 net6 net5 net2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19_14 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp12 net9 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp11 net12 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net10 net9 net12 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net11 D net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 VDD SE net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp2 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp10 net3 cki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net13 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net13 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 VDD net3 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp20 net4 ncki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp19 net5 cki net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net7 SETN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp14 net7 net6 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 RN VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp15 VDD net5 net6 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17_7 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.cdl b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.cdl
index 052d1a9..2233175 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.cdl
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.cdl
@@ -14,50 +14,50 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4 D RN SE SETN SI CLK Q VDD VNW VPW VSS
*.PININFO D:I RN:I SE:I SETN:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn12 net9 SE VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn9 VSS SI net17 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn10 net17 SE net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn0 net14 D net8 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn11 net8 net9 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn2 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn8 net14 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 net3 cki net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn6 net15 net4 net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS RN net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 net1 SETN net7 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn16 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net2 RN VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn17 net6 net5 net2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19_14 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19_12 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn19_14_0 Q net6 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp12 net9 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp11 net12 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net10 net9 net12 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp0 net11 D net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp9 VDD SE net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp2 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp10 net3 cki net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 net13 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net13 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net13 RN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 VDD net3 net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp20 net4 ncki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp19 net5 cki net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 net7 SETN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp14 net7 net6 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 RN VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp15 VDD net5 net6 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17_7 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17_8 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp17_7_4 Q net6 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn12 net9 SE VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn9 VSS SI net17 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn10 net17 SE net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn0 net14 D net8 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn11 net8 net9 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn2 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn8 net14 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 net3 cki net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn6 net15 net4 net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS RN net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 net1 SETN net7 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn16 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net2 RN VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn17 net6 net5 net2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19_14 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19_12 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn19_14_0 Q net6 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp12 net9 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp11 net12 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net10 net9 net12 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp0 net11 D net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp9 VDD SE net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp2 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp10 net3 cki net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 net13 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net13 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net13 RN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 VDD net3 net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp20 net4 ncki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp19 net5 cki net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 net7 SETN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp14 net7 net6 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 RN VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp15 VDD net5 net6 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17_7 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17_8 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp17_7_4 Q net6 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.cdl b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.cdl
index 88698aa..b83ab0d 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.cdl
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.cdl
@@ -14,40 +14,40 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1 D SE SETN SI CLK Q VDD VNW VPW VSS
*.PININFO D:I SE:I SETN:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn11 net9 SE VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS SI net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn9 net15 SE net13 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn10 net13 D net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net16 net9 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn6 net13 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net3 cki net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 VSS net4 net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net1 SETN net7 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net6 net5 VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn16 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp11 net9 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 net8 net9 net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net12 D net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 VDD SE net12 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 net3 cki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net10 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net4 net3 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 net5 ncki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp17 net7 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net7 SETN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 VDD net6 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 net5 VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp14 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn11 net9 SE VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS SI net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn9 net15 SE net13 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn10 net13 D net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net16 net9 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn6 net13 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net3 cki net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 VSS net4 net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net1 SETN net7 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net6 net5 VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn16 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp11 net9 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 net8 net9 net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net12 D net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 VDD SE net12 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 net3 cki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net10 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net4 net3 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 net5 ncki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp17 net7 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net7 SETN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 VDD net6 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 net5 VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp14 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.cdl b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.cdl
index 9952231..b0ef67a 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.cdl
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.cdl
@@ -14,42 +14,42 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2 D SE SETN SI CLK Q VDD VNW VPW VSS
*.PININFO D:I SE:I SETN:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn11 net9 SE VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS SI net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn9 net15 SE net13 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn10 net13 D net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net16 net9 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn6 net13 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net3 cki net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 VSS net4 net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net1 SETN net7 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net6 net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16_8 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp11 net9 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 net8 net9 net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net12 D net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 VDD SE net12 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 net3 cki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net10 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net4 net3 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 net5 ncki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp17 net7 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net7 SETN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 VDD net6 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14_2 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn11 net9 SE VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS SI net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn9 net15 SE net13 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn10 net13 D net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net16 net9 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn6 net13 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net3 cki net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 VSS net4 net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net1 SETN net7 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net6 net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16_8 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp11 net9 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 net8 net9 net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net12 D net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 VDD SE net12 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 net3 cki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net10 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net4 net3 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 net5 ncki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp17 net7 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net7 SETN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 VDD net6 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14_2 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.cdl b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.cdl
index 9af1d0a..0270985 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.cdl
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.cdl
@@ -14,48 +14,48 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4 D SE SETN SI CLK Q VDD VNW VPW VSS
*.PININFO D:I SE:I SETN:I SI:I CLK:I Q:O VDD:P VNW:P VPW:P VSS:G
-M_tn11 net9 SE VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn7 VSS SI net15 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn9 net15 SE net13 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn10 net13 D net16 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn8 net16 net9 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn3 ncki CLK VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn0 cki ncki VSS VPW nmos_5p0 W=0.790000U L=0.600000U
-M_tn6 net13 ncki net3 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn4 net3 cki net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn5 VSS net4 net14 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn2 net0 net3 VSS VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn1 net4 SETN net0 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn13 net5 cki net4 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn12 net7 ncki net5 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn14 net1 SETN net7 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn15 VSS net6 net1 VPW nmos_5p0 W=0.590000U L=0.600000U
-M_tn18 net6 net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn18_45 net6 net5 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16_8 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16_23 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tn16_8_32 VSS net6 Q VPW nmos_5p0 W=1.320000U L=0.600000U
-M_tp11 net9 SE VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp10 net11 SI VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp1 net8 net9 net11 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp8 net12 D net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp7 VDD SE net12 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp4 ncki CLK VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp0 cki ncki VDD VNW pmos_5p0 W=1.380000U L=0.500000U
-M_tp9 net3 cki net8 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp6 net10 ncki net3 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp5 VDD net4 net10 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp3 net4 net3 VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp2 VDD SETN net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp18 net5 ncki net4 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp17 net7 cki net5 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp12 net7 SETN VDD VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp13 VDD net6 net7 VNW pmos_5p0 W=1.000000U L=0.500000U
-M_tp16 net6 net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp16_52 net6 net5 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14_2 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14_18 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
-M_tp14_2_28 VDD net6 Q VNW pmos_5p0 W=1.830000U L=0.500000U
+M_tn11 net9 SE VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn7 VSS SI net15 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn9 net15 SE net13 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn10 net13 D net16 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn8 net16 net9 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn3 ncki CLK VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn0 cki ncki VSS VPW nfet_05v0 W=0.790000U L=0.600000U
+M_tn6 net13 ncki net3 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn4 net3 cki net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn5 VSS net4 net14 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn2 net0 net3 VSS VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn1 net4 SETN net0 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn13 net5 cki net4 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn12 net7 ncki net5 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn14 net1 SETN net7 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn15 VSS net6 net1 VPW nfet_05v0 W=0.590000U L=0.600000U
+M_tn18 net6 net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn18_45 net6 net5 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16_8 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16_23 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tn16_8_32 VSS net6 Q VPW nfet_05v0 W=1.320000U L=0.600000U
+M_tp11 net9 SE VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp10 net11 SI VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp1 net8 net9 net11 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp8 net12 D net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp7 VDD SE net12 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp4 ncki CLK VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp0 cki ncki VDD VNW pfet_05v0 W=1.380000U L=0.500000U
+M_tp9 net3 cki net8 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp6 net10 ncki net3 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp5 VDD net4 net10 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp3 net4 net3 VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp2 VDD SETN net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp18 net5 ncki net4 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp17 net7 cki net5 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp12 net7 SETN VDD VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp13 VDD net6 net7 VNW pfet_05v0 W=1.000000U L=0.500000U
+M_tp16 net6 net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp16_52 net6 net5 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14_2 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14_18 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
+M_tp14_2_28 VDD net6 Q VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/tieh/gf180mcu_fd_sc_mcu9t5v0__tieh.cdl b/cells/tieh/gf180mcu_fd_sc_mcu9t5v0__tieh.cdl
index 4771410..952540e 100644
--- a/cells/tieh/gf180mcu_fd_sc_mcu9t5v0__tieh.cdl
+++ b/cells/tieh/gf180mcu_fd_sc_mcu9t5v0__tieh.cdl
@@ -14,6 +14,6 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__tieh Z VDD VNW VPW VSS
*.PININFO Z:O VDD:P VNW:P VPW:P VSS:G
-M_n_tran_1 VSS A A VPW nmos_5p0 W=0.660000U L=0.600000U
-M_p_tran_2 VDD A Z VNW pmos_5p0 W=0.900000U L=0.500000U
+M_n_tran_1 VSS A A VPW nfet_05v0 W=0.660000U L=0.600000U
+M_p_tran_2 VDD A Z VNW pfet_05v0 W=0.900000U L=0.500000U
.ENDS
diff --git a/cells/tiel/gf180mcu_fd_sc_mcu9t5v0__tiel.cdl b/cells/tiel/gf180mcu_fd_sc_mcu9t5v0__tiel.cdl
index 9176a56..f2b6a1e 100644
--- a/cells/tiel/gf180mcu_fd_sc_mcu9t5v0__tiel.cdl
+++ b/cells/tiel/gf180mcu_fd_sc_mcu9t5v0__tiel.cdl
@@ -14,6 +14,6 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__tiel ZN VDD VNW VPW VSS
*.PININFO ZN:O VDD:P VNW:P VPW:P VSS:G
-M_n_tran_1 VSS A ZN VPW nmos_5p0 W=0.660000U L=0.600000U
-M_transistor_0 VDD A A VNW pmos_5p0 W=0.900000U L=0.500000U
+M_n_tran_1 VSS A ZN VPW nfet_05v0 W=0.660000U L=0.600000U
+M_transistor_0 VDD A A VNW pfet_05v0 W=0.900000U L=0.500000U
.ENDS
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.cdl b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.cdl
index 4dad6d3..1397508 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.cdl
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.cdl
@@ -15,14 +15,14 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xnor2_1 A1 A2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(!((A1 * A2) + !(A1 + A2)))
-M_i_6 net_2 A2 I VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_7 VSS A1 net_2 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_2 net_0 I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 ZN A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 net_0 A2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_8 I A2 VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_9 VDD A1 I VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_5 ZN I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3 net_1 A1 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4 VDD A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_6 net_2 A2 I VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_7 VSS A1 net_2 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_2 net_0 I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 ZN A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 net_0 A2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_8 I A2 VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_9 VDD A1 I VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_5 ZN I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3 net_1 A1 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4 VDD A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_2.cdl b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_2.cdl
index 22e68bb..f399298 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_2.cdl
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_2.cdl
@@ -15,18 +15,18 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xnor2_2 A1 A2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(!((A1 * A2) + !(A1 + A2)))
-M_i_8 I A2 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_9 VSS A1 I VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_4 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 net_0 A1 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 VSS A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_10 net_2 A2 I VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_11 VDD A1 net_2 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_7 net_1 I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 Z_neg A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 net_1 A2 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 ZN Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_8 I A2 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_9 VSS A1 I VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_4 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 net_0 A1 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 VSS A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_10 net_2 A2 I VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_11 VDD A1 net_2 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_7 net_1 I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 Z_neg A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 net_1 A2 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 ZN Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.cdl b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.cdl
index e501a9e..5ef26e0 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.cdl
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.cdl
@@ -15,22 +15,22 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xnor2_4 A1 A2 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(!((A1 * A2) + !(A1 + A2)))
-M_i_8 I A2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_9 VSS A1 I VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_4 Z_neg I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 net_0 A1 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 VSS A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 ZN Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 ZN Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 VSS Z_neg ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_10 net_2 A2 I VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_11 VDD A1 net_2 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_7 net_1 I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 Z_neg A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 net_1 A2 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 ZN Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 ZN Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg ZN VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_8 I A2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_9 VSS A1 I VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_4 Z_neg I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 net_0 A1 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 VSS A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 ZN Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 ZN Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 VSS Z_neg ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_10 net_2 A2 I VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_11 VDD A1 net_2 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_7 net_1 I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 Z_neg A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 net_1 A2 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 ZN Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 ZN Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg ZN VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.cdl b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.cdl
index 1c9be8f..60dbd6f 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.cdl
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.cdl
@@ -15,24 +15,24 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xnor3_1 A1 A2 A3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(!((!((A1 * A2) + !(A1 + A2)) * A3) + !(!((A1 * A2) + !(A1 + A2)) + A3)))
-M_i_12 I A2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_13 VSS A1 I VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 I2 I VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0 net_0 A1 I2 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_1 VSS A2 net_0 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_16 net_5 I2 I3 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_17 VSS A3 net_5 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_8 net_2 I3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6 ZN A3 net_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7 net_2 I2 ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_14 net_4 A2 I VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_15 VDD A1 net_4 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_5 net_1 I VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_3 I2 A1 net_1 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_4 net_1 A2 I2 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_18 I3 I2 VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_19 VDD A3 I3 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_11 ZN I3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9 net_3 A3 ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10 VDD I2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_12 I A2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_13 VSS A1 I VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 I2 I VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0 net_0 A1 I2 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_1 VSS A2 net_0 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_16 net_5 I2 I3 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_17 VSS A3 net_5 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_8 net_2 I3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6 ZN A3 net_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7 net_2 I2 ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_14 net_4 A2 I VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_15 VDD A1 net_4 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_5 net_1 I VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_3 I2 A1 net_1 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_4 net_1 A2 I2 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_18 I3 I2 VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_19 VDD A3 I3 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_11 ZN I3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9 net_3 A3 ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10 VDD I2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_2.cdl b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_2.cdl
index 4f38b45..6e4385b 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_2.cdl
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_2.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xnor3_2 A1 A2 A3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(!((!((A1 * A2) + !(A1 + A2)) * A3) + !(!((A1 * A2) + !(A1 + A2)) + A3)))
-M_i_14 I A2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_15 VSS A1 I VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 I2 I VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0 net_0 A1 I2 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_1 VSS A2 net_0 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_18 I3 I2 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_19 VSS A3 I3 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_10 Z_neg I3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_8 net_2 A3 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_9 VSS I2 net_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_1 VSS Z_neg ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_0 ZN Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_16 net_4 A2 I VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_17 VDD A1 net_4 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_5 net_1 I VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_3 I2 A1 net_1 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_4 net_1 A2 I2 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_20 net_5 I2 I3 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_21 VDD A3 net_5 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_13 net_3 I3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11 Z_neg A3 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_12 net_3 I2 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 VDD Z_neg ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 ZN Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_14 I A2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_15 VSS A1 I VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 I2 I VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0 net_0 A1 I2 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_1 VSS A2 net_0 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_18 I3 I2 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_19 VSS A3 I3 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_10 Z_neg I3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_8 net_2 A3 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_9 VSS I2 net_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_1 VSS Z_neg ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_0 ZN Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_16 net_4 A2 I VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_17 VDD A1 net_4 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_5 net_1 I VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_3 I2 A1 net_1 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_4 net_1 A2 I2 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_20 net_5 I2 I3 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_21 VDD A3 net_5 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_13 net_3 I3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11 Z_neg A3 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_12 net_3 I2 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 VDD Z_neg ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 ZN Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_4.cdl b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_4.cdl
index 2f28998..eab20b2 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_4.cdl
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_4.cdl
@@ -15,32 +15,32 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xnor3_4 A1 A2 A3 ZN VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VNW:P VPW:P VSS:G
*.EQN ZN=!(!((!((A1 * A2) + !(A1 + A2)) * A3) + !(!((A1 * A2) + !(A1 + A2)) + A3)))
-M_i_14 I A2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_15 VSS A1 I VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 I2 I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_0 net_0 A1 I2 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_1 VSS A2 net_0 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_18 I3 I2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_19 VSS A3 I3 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_10 Z_neg I3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_8 net_2 A3 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_9 VSS I2 net_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_3 VSS Z_neg ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_2 ZN Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_1 VSS Z_neg ZN VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_0 ZN Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_16 net_4 A2 I VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_17 VDD A1 net_4 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_5 net_1 I VDD VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_3 I2 A1 net_1 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_4 net_1 A2 I2 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_20 net_5 I2 I3 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_21 VDD A3 net_5 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_13 net_3 I3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11 Z_neg A3 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_12 net_3 I2 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_3 VDD Z_neg ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_2 ZN Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 VDD Z_neg ZN VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 ZN Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_14 I A2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_15 VSS A1 I VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 I2 I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_0 net_0 A1 I2 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_1 VSS A2 net_0 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_18 I3 I2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_19 VSS A3 I3 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_10 Z_neg I3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_8 net_2 A3 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_9 VSS I2 net_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_3 VSS Z_neg ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_2 ZN Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_1 VSS Z_neg ZN VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_0 ZN Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_16 net_4 A2 I VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_17 VDD A1 net_4 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_5 net_1 I VDD VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_3 I2 A1 net_1 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_4 net_1 A2 I2 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_20 net_5 I2 I3 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_21 VDD A3 net_5 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_13 net_3 I3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11 Z_neg A3 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_12 net_3 I2 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_3 VDD Z_neg ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_2 ZN Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 VDD Z_neg ZN VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 ZN Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.cdl b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.cdl
index 83857fd..89a0a3e 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.cdl
+++ b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.cdl
@@ -15,14 +15,14 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xor2_1 A1 A2 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=!((A1 * A2) + !(A1 + A2))
-M_i_6 I A2 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_7 VSS A1 I VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_2 Z I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0 net_0 A1 Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_1 VSS A2 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_8 net_2 A2 I VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_9 VDD A1 net_2 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_5 net_1 I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_3 Z A1 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_4 net_1 A2 Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_6 I A2 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_7 VSS A1 I VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_2 Z I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0 net_0 A1 Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_1 VSS A2 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_8 net_2 A2 I VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_9 VDD A1 net_2 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_5 net_1 I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_3 Z A1 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_4 net_1 A2 Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_2.cdl b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_2.cdl
index dad11cb..87cc6f6 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_2.cdl
+++ b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_2.cdl
@@ -15,18 +15,18 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xor2_2 A1 A2 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=!((A1 * A2) + !(A1 + A2))
-M_i_8 net_2 A2 I VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_9 VSS A1 net_2 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_4 net_0 I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 Z_neg A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 net_0 A2 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_10 I A2 VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_11 VDD A1 I VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_7 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 net_1 A1 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 VDD A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_8 net_2 A2 I VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_9 VSS A1 net_2 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_4 net_0 I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 Z_neg A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 net_0 A2 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_10 I A2 VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_11 VDD A1 I VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_7 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 net_1 A1 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 VDD A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.cdl b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.cdl
index d7f0cad..ed5d028 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.cdl
+++ b/cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.cdl
@@ -15,22 +15,22 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xor2_4 A1 A2 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=!((A1 * A2) + !(A1 + A2))
-M_i_8 net_2 A2 I VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_9 VSS A1 net_2 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_4 net_0 I VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_2 Z_neg A1 net_0 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_3 net_0 A2 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_2 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_0_3 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_10 I A2 VDD VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_11 VDD A1 I VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_7 Z_neg I VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_5 net_1 A1 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_6 VDD A2 net_1 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_1_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_8 net_2 A2 I VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_9 VSS A1 net_2 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_4 net_0 I VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_2 Z_neg A1 net_0 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_3 net_0 A2 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_2 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_0_3 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_10 I A2 VDD VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_11 VDD A1 I VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_7 Z_neg I VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_5 net_1 A1 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_6 VDD A2 net_1 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_1_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.cdl b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.cdl
index 7174e6e..066574b 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.cdl
+++ b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.cdl
@@ -15,24 +15,24 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xor3_1 A1 A2 A3 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=!((!((A1 * A2) + !(A1 + A2)) * A3) + !(!((A1 * A2) + !(A1 + A2)) + A3))
-M_i_12 I A2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_13 VSS A1 I VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 I2 I VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0 net_0 A1 I2 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_1 VSS A2 net_0 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_16 I3 I2 VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_17 VSS A3 I3 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_8 Z I3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6 net_2 A3 Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_7 VSS I2 net_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_14 net_4 A2 I VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_15 VDD A1 net_4 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_5 net_1 I VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_3 I2 A1 net_1 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_4 net_1 A2 I2 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_18 net_5 I2 I3 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_19 VDD A3 net_5 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_11 net_3 I3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_9 Z A3 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_10 net_3 I2 Z VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_12 I A2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_13 VSS A1 I VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 I2 I VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0 net_0 A1 I2 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_1 VSS A2 net_0 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_16 I3 I2 VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_17 VSS A3 I3 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_8 Z I3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6 net_2 A3 Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_7 VSS I2 net_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_14 net_4 A2 I VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_15 VDD A1 net_4 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_5 net_1 I VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_3 I2 A1 net_1 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_4 net_1 A2 I2 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_18 net_5 I2 I3 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_19 VDD A3 net_5 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_11 net_3 I3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_9 Z A3 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_10 net_3 I2 Z VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.cdl b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.cdl
index 0273ae7..1216d7c 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.cdl
+++ b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.cdl
@@ -15,28 +15,28 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xor3_2 A1 A2 A3 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=!((!((A1 * A2) + !(A1 + A2)) * A3) + !(!((A1 * A2) + !(A1 + A2)) + A3))
-M_i_14 I A2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_15 VSS A1 I VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 I2 I VSS VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_0 net_0 A1 I2 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_1 VSS A2 net_0 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_18 net_5 I2 I3 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_19 VSS A3 net_5 VPW nmos_5p0 W=0.660000U L=0.600000U
-M_i_10 net_2 I3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_8 Z_neg A3 net_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_9 net_2 I2 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_16 net_4 A2 I VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_17 VDD A1 net_4 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_5 net_1 I VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_3 I2 A1 net_1 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_4 net_1 A2 I2 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_20 I3 I2 VDD VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_21 VDD A3 I3 VNW pmos_5p0 W=0.915000U L=0.500000U
-M_i_13 Z_neg I3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11 net_3 A3 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_12 VDD I2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_14 I A2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_15 VSS A1 I VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 I2 I VSS VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_0 net_0 A1 I2 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_1 VSS A2 net_0 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_18 net_5 I2 I3 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_19 VSS A3 net_5 VPW nfet_05v0 W=0.660000U L=0.600000U
+M_i_10 net_2 I3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_8 Z_neg A3 net_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_9 net_2 I2 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_16 net_4 A2 I VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_17 VDD A1 net_4 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_5 net_1 I VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_3 I2 A1 net_1 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_4 net_1 A2 I2 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_20 I3 I2 VDD VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_21 VDD A3 I3 VNW pfet_05v0 W=0.915000U L=0.500000U
+M_i_13 Z_neg I3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11 net_3 A3 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_12 VDD I2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_4.cdl b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_4.cdl
index 60e5d5c..f3149f2 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_4.cdl
+++ b/cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_4.cdl
@@ -15,32 +15,32 @@
.SUBCKT gf180mcu_fd_sc_mcu9t5v0__xor3_4 A1 A2 A3 Z VDD VNW VPW VSS
*.PININFO A1:I A2:I A3:I Z:O VDD:P VNW:P VPW:P VSS:G
*.EQN Z=!((!((A1 * A2) + !(A1 + A2)) * A3) + !(!((A1 * A2) + !(A1 + A2)) + A3))
-M_i_14 I A2 VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_15 VSS A1 I VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_2 I2 I VSS VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_0 net_0 A1 I2 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_1 VSS A2 net_0 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_18 net_5 I2 I3 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_19 VSS A3 net_5 VPW nmos_5p0 W=0.360000U L=0.600000U
-M_i_10 net_2 I3 VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_8 Z_neg A3 net_2 VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_9 net_2 I2 Z_neg VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_3 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_2 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_1 VSS Z_neg Z VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_6_0 Z Z_neg VSS VPW nmos_5p0 W=1.320000U L=0.600000U
-M_i_16 net_4 A2 I VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_17 VDD A1 net_4 VNW pmos_5p0 W=0.360000U L=0.500000U
-M_i_5 net_1 I VDD VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_3 I2 A1 net_1 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_4 net_1 A2 I2 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_20 I3 I2 VDD VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_21 VDD A3 I3 VNW pmos_5p0 W=0.495000U L=0.500000U
-M_i_13 Z_neg I3 VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_11 net_3 A3 Z_neg VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_12 VDD I2 net_3 VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_3 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_2 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_1 VDD Z_neg Z VNW pmos_5p0 W=1.830000U L=0.500000U
-M_i_7_0 Z Z_neg VDD VNW pmos_5p0 W=1.830000U L=0.500000U
+M_i_14 I A2 VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_15 VSS A1 I VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_2 I2 I VSS VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_0 net_0 A1 I2 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_1 VSS A2 net_0 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_18 net_5 I2 I3 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_19 VSS A3 net_5 VPW nfet_05v0 W=0.360000U L=0.600000U
+M_i_10 net_2 I3 VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_8 Z_neg A3 net_2 VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_9 net_2 I2 Z_neg VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_3 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_2 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_1 VSS Z_neg Z VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_6_0 Z Z_neg VSS VPW nfet_05v0 W=1.320000U L=0.600000U
+M_i_16 net_4 A2 I VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_17 VDD A1 net_4 VNW pfet_05v0 W=0.360000U L=0.500000U
+M_i_5 net_1 I VDD VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_3 I2 A1 net_1 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_4 net_1 A2 I2 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_20 I3 I2 VDD VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_21 VDD A3 I3 VNW pfet_05v0 W=0.495000U L=0.500000U
+M_i_13 Z_neg I3 VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_11 net_3 A3 Z_neg VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_12 VDD I2 net_3 VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_3 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_2 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_1 VDD Z_neg Z VNW pfet_05v0 W=1.830000U L=0.500000U
+M_i_7_0 Z Z_neg VDD VNW pfet_05v0 W=1.830000U L=0.500000U
.ENDS
diff --git a/tech/gf180mcu_2LM_1TM_30K_9t_tech.lef b/tech/gf180mcu_2LM_1TM_30K_9t_tech.lef
new file mode 100755
index 0000000..2708716
--- /dev/null
+++ b/tech/gf180mcu_2LM_1TM_30K_9t_tech.lef
@@ -0,0 +1,486 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 2LM_1TM_30K
+# Preferred routing directions:
+# vertical: Metal2
+# horizontal: Metal1
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.12 0.25 ;
+ ENCLOSURE ABOVE 0.12 0.12 WIDTH 2.5 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 2.5 ABOVE 0.250 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 4.000 ;
+ MINWIDTH 2.200 ; # MT30.1
+ WIDTH 2.200 ; # MT30.1
+ SPACING 1.800 ; # MT30.2, MT30.3
+ MINIMUMCUT 4 WIDTH 1.790 FROMBELOW ; # MT30.8b
+
+ DCCURRENTDENSITY AVERAGE 5.37 ;
+ ACCURRENTDENSITY AVERAGE 8.06 ;
+ RESISTANCE RPERSQ 0.01000 ;
+
+ THICKNESS 3.035 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.250 0.120 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.120 0.250 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.250 0.120 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.120 0.250 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+VIARULE Via1_0 GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.120 0.120 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_0
+
+ VIA Via1_2X2_0_60_120_120_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.510 -0.510 0.510 0.510 ;
+ END Via1_2X2_0_60_120_120_H_H
+
+ VIA Via1_2X2_0_60_120_120_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.510 -0.510 0.510 0.510 ;
+ END Via1_2X2_0_60_120_120_V_H
+
+ VIA Via1_2X2_0_60_120_250_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.640 -0.510 0.640 0.510 ;
+ END Via1_2X2_0_60_120_250_H_H
+
+ VIA Via1_2X2_0_60_120_250_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.510 -0.640 0.510 0.640 ;
+ END Via1_2X2_0_60_120_250_H_V
+
+ VIA Via1_2X2_0_60_120_250_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.640 -0.510 0.640 0.510 ;
+ END Via1_2X2_0_60_120_250_V_H
+
+ VIA Via1_2X2_0_60_120_250_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.510 -0.640 0.510 0.640 ;
+ END Via1_2X2_0_60_120_250_V_V
+
+ VIA Via1_2X3_0_60_120_120_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.650 -0.130 -0.390 ;
+ RECT 0.130 -0.650 0.390 -0.390 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ RECT -0.390 0.390 -0.130 0.650 ;
+ RECT 0.130 0.390 0.390 0.650 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.650 0.450 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.510 -0.770 0.510 0.770 ;
+ END Via1_2X3_0_60_120_120_H_H
+
+ VIA Via1_2X3_0_60_120_120_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.650 -0.130 -0.390 ;
+ RECT 0.130 -0.650 0.390 -0.390 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ RECT -0.390 0.390 -0.130 0.650 ;
+ RECT 0.130 0.390 0.390 0.650 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.710 0.390 0.710 ;
+ LAYER Metal2 ;
+ RECT -0.510 -0.770 0.510 0.770 ;
+ END Via1_2X3_0_60_120_120_V_H
+
+ VIA Via1_3X3_0_60_120_120_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal1 ;
+ RECT -0.710 -0.650 0.710 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.770 -0.770 0.770 0.770 ;
+ END Via1_3X3_0_60_120_120_H_H
+
+ VIA Via1_3X3_0_60_120_120_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal1 ;
+ RECT -0.650 -0.710 0.650 0.710 ;
+ LAYER Metal2 ;
+ RECT -0.770 -0.770 0.770 0.770 ;
+ END Via1_3X3_0_60_120_120_V_H
+
+ VIA Via1_3X3_0_60_120_250_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal1 ;
+ RECT -0.710 -0.650 0.710 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.900 -0.770 0.900 0.770 ;
+ END Via1_3X3_0_60_120_250_H_H
+
+ VIA Via1_3X3_0_60_120_250_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal1 ;
+ RECT -0.710 -0.650 0.710 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.770 -0.900 0.770 0.900 ;
+ END Via1_3X3_0_60_120_250_H_V
+
+ VIA Via1_3X3_0_60_120_250_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal1 ;
+ RECT -0.650 -0.710 0.650 0.710 ;
+ LAYER Metal2 ;
+ RECT -0.900 -0.770 0.900 0.770 ;
+ END Via1_3X3_0_60_120_250_V_H
+
+ VIA Via1_3X3_0_60_120_250_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal1 ;
+ RECT -0.650 -0.710 0.650 0.710 ;
+ LAYER Metal2 ;
+ RECT -0.770 -0.900 0.770 0.900 ;
+ END Via1_3X3_0_60_120_250_V_V
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.180 -1.180 1.180 1.180 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.180 -1.180 1.180 1.180 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT1 DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.180 -1.310 1.180 1.310 ;
+ END Via1_4X4H_HV_DEFAULT1
+
+
+END LIBRARY
diff --git a/tech/gf180mcu_3LM_1TM_11K_9t_tech.lef b/tech/gf180mcu_3LM_1TM_11K_9t_tech.lef
new file mode 100755
index 0000000..dac9db1
--- /dev/null
+++ b/tech/gf180mcu_3LM_1TM_11K_9t_tech.lef
@@ -0,0 +1,704 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 3LM_1TM_11K
+# Preferred routing directions:
+# vertical: Metal2
+# horizontal: Metal1 Metal3
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 0.34 0.06 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+LAYER Via2
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via2
+
+
+
+LAYER Metal3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 0.9 ;
+ MINWIDTH 0.440 ;
+ WIDTH 0.440 ; # MT.1
+ AREA 0.5625 ; # MT.4
+ SPACING 0.460 ; # MT.2a
+ SPACING 0.600 RANGE 10.005 999.00 ; # MT.2b
+
+ DCCURRENTDENSITY AVERAGE 1.5 ;
+ ACCURRENTDENSITY AVERAGE 2.2 ;
+ RESISTANCE RPERSQ 0.04000 ;
+
+ THICKNESS 1.19 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal3
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+ VIA Via1_HH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_HH
+
+ VIA Via1_HV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_HV
+
+ VIA Via1_VH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_VH
+
+ VIA Via1_VV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_VV
+
+ VIA Via1_2CUT_H
+ LAYER Via1 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via1_2CUT_H
+
+ VIA Via1_2CUT_V
+ LAYER Via1 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via1_2CUT_V
+
+ VIA Via1_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_H_H
+
+ VIA Via1_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_H_V
+
+ VIA Via1_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_V_H
+
+ VIA Via1_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_V_V
+
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_HV_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via2 VIA SECTION
+#------------------------------------------------------------
+ VIA Via2_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_HH
+
+ VIA Via2_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_HV
+
+ VIA Via2_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_VH
+
+ VIA Via2_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_VV
+
+ VIA Via2_2CUT_H
+ LAYER Via2 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via2_2CUT_H
+
+ VIA Via2_2CUT_V
+ LAYER Via2 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via2_2CUT_V
+
+ VIA Via2_2X2_10_60_10_60_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_10_60_10_60_H_H
+
+ VIA Via2_2X2_10_60_10_60_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_10_60_10_60_H_V
+
+ VIA Via2_2X2_10_60_10_60_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_10_60_10_60_V_H
+
+ VIA Via2_2X2_10_60_10_60_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_10_60_10_60_V_V
+
+VIARULE Via2_GEN_HH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HH
+
+VIARULE Via2_GEN_HV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HV
+
+VIARULE Via2_GEN_VH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VH
+
+VIARULE Via2_GEN_VV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VV
+
+ VIA Via2_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_HH_DEFAULT
+
+ VIA Via2_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_HV_DEFAULT
+
+ VIA Via2_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_VH_DEFAULT
+
+ VIA Via2_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_VV_DEFAULT
+
+
+END LIBRARY
diff --git a/tech/gf180mcu_3LM_1TM_30K_9t_tech.lef b/tech/gf180mcu_3LM_1TM_30K_9t_tech.lef
new file mode 100755
index 0000000..66eb870
--- /dev/null
+++ b/tech/gf180mcu_3LM_1TM_30K_9t_tech.lef
@@ -0,0 +1,783 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 3LM_1TM_30K
+# Preferred routing directions:
+# vertical: Metal2
+# horizontal: Metal1 Metal3
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 0.34 0.06 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+LAYER Via2
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.12 0.25 ;
+ ENCLOSURE ABOVE 0.12 0.12 WIDTH 2.5 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 2.5 ABOVE 0.250 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via2
+
+
+
+LAYER Metal3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 4.000 ;
+ MINWIDTH 2.200 ; # MT30.1
+ WIDTH 2.200 ; # MT30.1
+ SPACING 1.800 ; # MT30.2, MT30.3
+ MINIMUMCUT 4 WIDTH 1.790 FROMBELOW ; # MT30.8b
+
+ DCCURRENTDENSITY AVERAGE 5.37 ;
+ ACCURRENTDENSITY AVERAGE 8.06 ;
+ RESISTANCE RPERSQ 0.01000 ;
+
+ THICKNESS 3.035 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal3
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+ VIA Via1_HH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_HH
+
+ VIA Via1_HV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_HV
+
+ VIA Via1_VH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_VH
+
+ VIA Via1_VV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_VV
+
+ VIA Via1_2CUT_H
+ LAYER Via1 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via1_2CUT_H
+
+ VIA Via1_2CUT_V
+ LAYER Via1 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via1_2CUT_V
+
+ VIA Via1_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_H_H
+
+ VIA Via1_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_H_V
+
+ VIA Via1_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_V_H
+
+ VIA Via1_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_V_V
+
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_HV_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via2 VIA SECTION
+#------------------------------------------------------------
+VIARULE Via2_GEN_HH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.250 0.120 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HH
+
+VIARULE Via2_GEN_HV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.120 0.250 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HV
+
+VIARULE Via2_GEN_VH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.250 0.120 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VH
+
+VIARULE Via2_GEN_VV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.120 0.250 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VV
+
+VIARULE Via2_0 GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.120 0.120 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_0
+
+ VIA Via2_2X2_10_60_120_120_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal3 ;
+ RECT -0.510 -0.510 0.510 0.510 ;
+ END Via2_2X2_10_60_120_120_H_H
+
+ VIA Via2_2X2_10_60_120_120_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.510 -0.510 0.510 0.510 ;
+ END Via2_2X2_10_60_120_120_V_H
+
+ VIA Via2_2X2_10_60_120_250_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal3 ;
+ RECT -0.640 -0.510 0.640 0.510 ;
+ END Via2_2X2_10_60_120_250_H_H
+
+ VIA Via2_2X2_10_60_120_250_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal3 ;
+ RECT -0.510 -0.640 0.510 0.640 ;
+ END Via2_2X2_10_60_120_250_H_V
+
+ VIA Via2_2X2_10_60_120_250_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.640 -0.510 0.640 0.510 ;
+ END Via2_2X2_10_60_120_250_V_H
+
+ VIA Via2_2X2_10_60_120_250_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.510 -0.640 0.510 0.640 ;
+ END Via2_2X2_10_60_120_250_V_V
+
+ VIA Via2_2X3_10_60_120_120_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.650 -0.130 -0.390 ;
+ RECT 0.130 -0.650 0.390 -0.390 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ RECT -0.390 0.390 -0.130 0.650 ;
+ RECT 0.130 0.390 0.390 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.660 0.450 0.660 ;
+ LAYER Metal3 ;
+ RECT -0.510 -0.770 0.510 0.770 ;
+ END Via2_2X3_10_60_120_120_H_H
+
+ VIA Via2_2X3_10_60_120_120_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.650 -0.130 -0.390 ;
+ RECT 0.130 -0.650 0.390 -0.390 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ RECT -0.390 0.390 -0.130 0.650 ;
+ RECT 0.130 0.390 0.390 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.710 0.400 0.710 ;
+ LAYER Metal3 ;
+ RECT -0.510 -0.770 0.510 0.770 ;
+ END Via2_2X3_10_60_120_120_V_H
+
+ VIA Via2_3X3_10_60_120_120_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.710 -0.660 0.710 0.660 ;
+ LAYER Metal3 ;
+ RECT -0.770 -0.770 0.770 0.770 ;
+ END Via2_3X3_10_60_120_120_H_H
+
+ VIA Via2_3X3_10_60_120_120_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.660 -0.710 0.660 0.710 ;
+ LAYER Metal3 ;
+ RECT -0.770 -0.770 0.770 0.770 ;
+ END Via2_3X3_10_60_120_120_V_H
+
+ VIA Via2_3X3_10_60_120_250_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.710 -0.660 0.710 0.660 ;
+ LAYER Metal3 ;
+ RECT -0.900 -0.770 0.900 0.770 ;
+ END Via2_3X3_10_60_120_250_H_H
+
+ VIA Via2_3X3_10_60_120_250_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.710 -0.660 0.710 0.660 ;
+ LAYER Metal3 ;
+ RECT -0.770 -0.900 0.770 0.900 ;
+ END Via2_3X3_10_60_120_250_H_V
+
+ VIA Via2_3X3_10_60_120_250_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.660 -0.710 0.660 0.710 ;
+ LAYER Metal3 ;
+ RECT -0.900 -0.770 0.900 0.770 ;
+ END Via2_3X3_10_60_120_250_V_H
+
+ VIA Via2_3X3_10_60_120_250_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal2 ;
+ RECT -0.660 -0.710 0.660 0.710 ;
+ LAYER Metal3 ;
+ RECT -0.770 -0.900 0.770 0.900 ;
+ END Via2_3X3_10_60_120_250_V_V
+
+ VIA Via2_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.180 -1.180 1.180 1.180 ;
+ END Via2_4X4H_HH_DEFAULT
+
+ VIA Via2_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.180 -1.180 1.180 1.180 ;
+ END Via2_4X4H_VH_DEFAULT
+
+ VIA Via2_4X4V_VH_DEFAULT1 DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.310 -1.180 1.310 1.180 ;
+ END Via2_4X4V_VH_DEFAULT1
+
+
+END LIBRARY
diff --git a/tech/gf180mcu_3LM_1TM_6K_9t_tech.lef b/tech/gf180mcu_3LM_1TM_6K_9t_tech.lef
new file mode 100755
index 0000000..7a4f57b
--- /dev/null
+++ b/tech/gf180mcu_3LM_1TM_6K_9t_tech.lef
@@ -0,0 +1,744 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 3LM_1TM_6K
+# Preferred routing directions:
+# vertical: Metal3
+# horizontal: Metal1 Metal2
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 0.34 0.06 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+LAYER Via2
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via2
+
+
+
+LAYER Metal3
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 0.74 ;
+ MINWIDTH 0.360 ;
+ WIDTH 0.360 ; # MT.1
+ AREA 0.5625 ; # MT.4
+ SPACING 0.380 ; # MT.2a
+ SPACING 0.500 RANGE 10.005 999.00 ; # MT.2b
+
+ DCCURRENTDENSITY AVERAGE 1.07 ;
+ ACCURRENTDENSITY AVERAGE 1.60 ;
+ RESISTANCE RPERSQ 0.06000 ;
+
+ THICKNESS 0.69 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal3
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+ VIA Via1_HH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_HH
+
+ VIA Via1_HV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_HV
+
+ VIA Via1_VH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_VH
+
+ VIA Via1_VV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_VV
+
+ VIA Via1_2CUT_H
+ LAYER Via1 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via1_2CUT_H
+
+ VIA Via1_2CUT_V
+ LAYER Via1 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via1_2CUT_V
+
+ VIA Via1_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_H_H
+
+ VIA Via1_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_H_V
+
+ VIA Via1_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_V_H
+
+ VIA Via1_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_V_V
+
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_HV_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via2 VIA SECTION
+#------------------------------------------------------------
+ VIA Via2_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.180 0.190 0.180 ;
+ RESISTANCE 4.500 ;
+ END Via2_HH
+
+ VIA Via2_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.180 -0.190 0.180 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_HV
+
+ VIA Via2_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.180 0.190 0.180 ;
+ RESISTANCE 4.500 ;
+ END Via2_VH
+
+ VIA Via2_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.180 -0.190 0.180 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_VV
+
+ VIA Via2_1_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_1_HH
+
+ VIA Via2_1_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_1_HV
+
+ VIA Via2_1_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_1_VH
+
+ VIA Via2_1_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_1_VV
+
+ VIA Via2_2CUT_H
+ LAYER Via2 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via2_2CUT_H
+
+ VIA Via2_2CUT_V
+ LAYER Via2 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via2_2CUT_V
+
+ VIA Via2_2X2_10_60_10_60_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_10_60_10_60_H_H
+
+ VIA Via2_2X2_10_60_10_60_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_10_60_10_60_H_V
+
+ VIA Via2_2X2_10_60_10_60_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_10_60_10_60_V_H
+
+ VIA Via2_2X2_10_60_10_60_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_10_60_10_60_V_V
+
+VIARULE Via2_GEN_HH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HH
+
+VIARULE Via2_GEN_HV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HV
+
+VIARULE Via2_GEN_VH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VH
+
+VIARULE Via2_GEN_VV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VV
+
+ VIA Via2_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_HH_DEFAULT
+
+ VIA Via2_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_HV_DEFAULT
+
+ VIA Via2_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_VH_DEFAULT
+
+ VIA Via2_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_VV_DEFAULT
+
+
+END LIBRARY
diff --git a/tech/gf180mcu_3LM_1TM_9K_9t_tech.lef b/tech/gf180mcu_3LM_1TM_9K_9t_tech.lef
new file mode 100755
index 0000000..ed71d23
--- /dev/null
+++ b/tech/gf180mcu_3LM_1TM_9K_9t_tech.lef
@@ -0,0 +1,765 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 3LM_1TM_9K
+# Preferred routing directions:
+# vertical: Metal3
+# horizontal: Metal1 Metal2
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 0.34 0.06 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+LAYER Via2
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ # ENCLOSURE ABOVE 0.01 0.09 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via2
+
+
+
+LAYER Metal3
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 0.9 ;
+ MINWIDTH 0.440 ;
+ WIDTH 0.440 ; # MT.1
+ AREA 0.5625 ; # MT.4
+ SPACING 0.460 ; # MT.2a
+ SPACING 0.600 RANGE 10.005 999.00 ; # MT.2b
+
+ DCCURRENTDENSITY AVERAGE 1.21 ;
+ ACCURRENTDENSITY AVERAGE 1.82 ;
+ RESISTANCE RPERSQ 0.04000 ;
+
+ THICKNESS 0.99 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal3
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+ VIA Via1_HH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_HH
+
+ VIA Via1_HV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_HV
+
+ VIA Via1_VH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_VH
+
+ VIA Via1_VV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_VV
+
+ VIA Via1_2CUT_H
+ LAYER Via1 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via1_2CUT_H
+
+ VIA Via1_2CUT_V
+ LAYER Via1 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via1_2CUT_V
+
+ VIA Via1_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_H_H
+
+ VIA Via1_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_H_V
+
+ VIA Via1_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_V_H
+
+ VIA Via1_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_V_V
+
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_HV_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via2 VIA SECTION
+#------------------------------------------------------------
+ VIA Via2_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.220 -0.140 0.220 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_HH
+
+ VIA Via2_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.220 0.140 0.220 ;
+ RESISTANCE 4.500 ;
+ END Via2_HV
+
+ VIA Via2_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.220 -0.140 0.220 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_VH
+
+ VIA Via2_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.220 0.140 0.220 ;
+ RESISTANCE 4.500 ;
+ END Via2_VV
+
+ VIA Via2_1_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_1_HH
+
+ VIA Via2_1_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_1_HV
+
+ VIA Via2_1_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_1_VH
+
+ VIA Via2_1_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_1_VV
+
+ VIA Via2_2CUT_H
+ LAYER Via2 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via2_2CUT_H
+
+ VIA Via2_2CUT_V
+ LAYER Via2 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via2_2CUT_V
+
+ VIA Via2_2X2_10_60_10_60_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_10_60_10_60_H_H
+
+ VIA Via2_2X2_10_60_10_60_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_10_60_10_60_H_V
+
+ VIA Via2_2X2_10_60_10_60_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_10_60_10_60_V_H
+
+ VIA Via2_2X2_10_60_10_60_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_10_60_10_60_V_V
+
+VIARULE Via2_GEN_HH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.090 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HH
+
+VIARULE Via2_GEN_HV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.090 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HV
+
+VIARULE Via2_GEN_VH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.090 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VH
+
+VIARULE Via2_GEN_VV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.090 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VV
+
+VIARULE Via2_0_RULE GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_0_RULE
+
+VIARULE Via2_0 GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_0
+
+ VIA Via2_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_HH_DEFAULT
+
+ VIA Via2_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_HV_DEFAULT
+
+ VIA Via2_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_VH_DEFAULT
+
+ VIA Via2_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_VV_DEFAULT
+
+
+END LIBRARY
diff --git a/tech/gf180mcu_4LM_1TM_11K_9t_tech.lef b/tech/gf180mcu_4LM_1TM_11K_9t_tech.lef
new file mode 100755
index 0000000..32d5e2c
--- /dev/null
+++ b/tech/gf180mcu_4LM_1TM_11K_9t_tech.lef
@@ -0,0 +1,1002 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 4LM_1TM_11K
+# Preferred routing directions:
+# vertical: Metal2 Metal4
+# horizontal: Metal1 Metal3
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 0.34 0.06 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+LAYER Via2
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via2
+
+
+LAYER Metal3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal3
+
+
+LAYER Via3
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via3
+
+
+
+LAYER Metal4
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 0.9 ;
+ MINWIDTH 0.440 ;
+ WIDTH 0.440 ; # MT.1
+ AREA 0.5625 ; # MT.4
+ SPACING 0.460 ; # MT.2a
+ SPACING 0.600 RANGE 10.005 999.00 ; # MT.2b
+
+ DCCURRENTDENSITY AVERAGE 1.5 ;
+ ACCURRENTDENSITY AVERAGE 2.2 ;
+ RESISTANCE RPERSQ 0.04000 ;
+
+ THICKNESS 1.19 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal4
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+ VIA Via1_HH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_HH
+
+ VIA Via1_HV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_HV
+
+ VIA Via1_VH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_VH
+
+ VIA Via1_VV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_VV
+
+ VIA Via1_2CUT_H
+ LAYER Via1 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via1_2CUT_H
+
+ VIA Via1_2CUT_V
+ LAYER Via1 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via1_2CUT_V
+
+ VIA Via1_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_H_H
+
+ VIA Via1_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_H_V
+
+ VIA Via1_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_V_H
+
+ VIA Via1_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_V_V
+
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_HV_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via2 VIA SECTION
+#------------------------------------------------------------
+ VIA Via2_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_HH
+
+ VIA Via2_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_HV
+
+ VIA Via2_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_VH
+
+ VIA Via2_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_VV
+
+ VIA Via2_2CUT_H
+ LAYER Via2 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.190 0.390 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via2_2CUT_H
+
+ VIA Via2_2CUT_V
+ LAYER Via2 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.130 -0.450 0.130 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via2_2CUT_V
+
+ VIA Via2_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_H_H
+
+ VIA Via2_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_H_V
+
+ VIA Via2_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_V_H
+
+ VIA Via2_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_V_V
+
+VIARULE Via2_GEN_HH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HH
+
+VIARULE Via2_GEN_HV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HV
+
+VIARULE Via2_GEN_VH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VH
+
+VIARULE Via2_GEN_VV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VV
+
+ VIA Via2_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_HH_DEFAULT
+
+ VIA Via2_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_HV_DEFAULT
+
+ VIA Via2_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_VH_DEFAULT
+
+ VIA Via2_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via3 VIA SECTION
+#------------------------------------------------------------
+ VIA Via3_HH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_HH
+
+ VIA Via3_HV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_HV
+
+ VIA Via3_VH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_VH
+
+ VIA Via3_VV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_VV
+
+ VIA Via3_2CUT_H
+ LAYER Via3 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via3_2CUT_H
+
+ VIA Via3_2CUT_V
+ LAYER Via3 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via3_2CUT_V
+
+ VIA Via3_2X2_10_60_10_60_H_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_10_60_10_60_H_H
+
+ VIA Via3_2X2_10_60_10_60_H_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_10_60_10_60_H_V
+
+ VIA Via3_2X2_10_60_10_60_V_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_10_60_10_60_V_H
+
+ VIA Via3_2X2_10_60_10_60_V_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_10_60_10_60_V_V
+
+VIARULE Via3_GEN_HH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HH
+
+VIARULE Via3_GEN_HV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HV
+
+VIARULE Via3_GEN_VH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VH
+
+VIARULE Via3_GEN_VV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VV
+
+ VIA Via3_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_HH_DEFAULT
+
+ VIA Via3_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_HV_DEFAULT
+
+ VIA Via3_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_VH_DEFAULT
+
+ VIA Via3_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_VV_DEFAULT
+
+
+END LIBRARY
diff --git a/tech/gf180mcu_4LM_1TM_30K_9t_tech.lef b/tech/gf180mcu_4LM_1TM_30K_9t_tech.lef
new file mode 100755
index 0000000..c56cd4b
--- /dev/null
+++ b/tech/gf180mcu_4LM_1TM_30K_9t_tech.lef
@@ -0,0 +1,1081 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 4LM_1TM_30K
+# Preferred routing directions:
+# vertical: Metal2 Metal4
+# horizontal: Metal1 Metal3
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 0.34 0.06 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+LAYER Via2
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via2
+
+
+LAYER Metal3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal3
+
+
+LAYER Via3
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.12 0.25 ;
+ ENCLOSURE ABOVE 0.12 0.12 WIDTH 2.5 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 2.5 ABOVE 0.250 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via3
+
+
+
+LAYER Metal4
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 4.000 ;
+ MINWIDTH 2.200 ; # MT30.1
+ WIDTH 2.200 ; # MT30.1
+ SPACING 1.800 ; # MT30.2, MT30.3
+ MINIMUMCUT 4 WIDTH 1.790 FROMBELOW ; # MT30.8b
+
+ DCCURRENTDENSITY AVERAGE 5.37 ;
+ ACCURRENTDENSITY AVERAGE 8.06 ;
+ RESISTANCE RPERSQ 0.01000 ;
+
+ THICKNESS 3.035 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal4
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+ VIA Via1_HH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_HH
+
+ VIA Via1_HV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_HV
+
+ VIA Via1_VH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_VH
+
+ VIA Via1_VV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_VV
+
+ VIA Via1_2CUT_H
+ LAYER Via1 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via1_2CUT_H
+
+ VIA Via1_2CUT_V
+ LAYER Via1 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via1_2CUT_V
+
+ VIA Via1_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_H_H
+
+ VIA Via1_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_H_V
+
+ VIA Via1_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_V_H
+
+ VIA Via1_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_V_V
+
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_HV_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via2 VIA SECTION
+#------------------------------------------------------------
+ VIA Via2_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_HH
+
+ VIA Via2_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_HV
+
+ VIA Via2_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_VH
+
+ VIA Via2_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_VV
+
+ VIA Via2_2CUT_H
+ LAYER Via2 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.190 0.390 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via2_2CUT_H
+
+ VIA Via2_2CUT_V
+ LAYER Via2 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.130 -0.450 0.130 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via2_2CUT_V
+
+ VIA Via2_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_H_H
+
+ VIA Via2_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_H_V
+
+ VIA Via2_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_V_H
+
+ VIA Via2_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_V_V
+
+VIARULE Via2_GEN_HH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HH
+
+VIARULE Via2_GEN_HV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HV
+
+VIARULE Via2_GEN_VH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VH
+
+VIARULE Via2_GEN_VV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VV
+
+ VIA Via2_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_HH_DEFAULT
+
+ VIA Via2_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_HV_DEFAULT
+
+ VIA Via2_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_VH_DEFAULT
+
+ VIA Via2_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via3 VIA SECTION
+#------------------------------------------------------------
+VIARULE Via3_GEN_HH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.250 0.120 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HH
+
+VIARULE Via3_GEN_HV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.120 0.250 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HV
+
+VIARULE Via3_GEN_VH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.250 0.120 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VH
+
+VIARULE Via3_GEN_VV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.120 0.250 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VV
+
+VIARULE Via3_0 GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.120 0.120 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_0
+
+ VIA Via3_2X2_10_60_120_120_H_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.510 -0.510 0.510 0.510 ;
+ END Via3_2X2_10_60_120_120_H_H
+
+ VIA Via3_2X2_10_60_120_120_V_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.510 -0.510 0.510 0.510 ;
+ END Via3_2X2_10_60_120_120_V_H
+
+ VIA Via3_2X2_10_60_120_250_H_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.640 -0.510 0.640 0.510 ;
+ END Via3_2X2_10_60_120_250_H_H
+
+ VIA Via3_2X2_10_60_120_250_H_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.510 -0.640 0.510 0.640 ;
+ END Via3_2X2_10_60_120_250_H_V
+
+ VIA Via3_2X2_10_60_120_250_V_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.640 -0.510 0.640 0.510 ;
+ END Via3_2X2_10_60_120_250_V_H
+
+ VIA Via3_2X2_10_60_120_250_V_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.510 -0.640 0.510 0.640 ;
+ END Via3_2X2_10_60_120_250_V_V
+
+ VIA Via3_2X3_10_60_120_120_H_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.650 -0.130 -0.390 ;
+ RECT 0.130 -0.650 0.390 -0.390 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ RECT -0.390 0.390 -0.130 0.650 ;
+ RECT 0.130 0.390 0.390 0.650 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.660 0.450 0.660 ;
+ LAYER Metal4 ;
+ RECT -0.510 -0.770 0.510 0.770 ;
+ END Via3_2X3_10_60_120_120_H_H
+
+ VIA Via3_2X3_10_60_120_120_V_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.650 -0.130 -0.390 ;
+ RECT 0.130 -0.650 0.390 -0.390 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ RECT -0.390 0.390 -0.130 0.650 ;
+ RECT 0.130 0.390 0.390 0.650 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.710 0.400 0.710 ;
+ LAYER Metal4 ;
+ RECT -0.510 -0.770 0.510 0.770 ;
+ END Via3_2X3_10_60_120_120_V_H
+
+ VIA Via3_3X3_10_60_120_120_H_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal3 ;
+ RECT -0.710 -0.660 0.710 0.660 ;
+ LAYER Metal4 ;
+ RECT -0.770 -0.770 0.770 0.770 ;
+ END Via3_3X3_10_60_120_120_H_H
+
+ VIA Via3_3X3_10_60_120_120_V_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal3 ;
+ RECT -0.660 -0.710 0.660 0.710 ;
+ LAYER Metal4 ;
+ RECT -0.770 -0.770 0.770 0.770 ;
+ END Via3_3X3_10_60_120_120_V_H
+
+ VIA Via3_3X3_10_60_120_250_H_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal3 ;
+ RECT -0.710 -0.660 0.710 0.660 ;
+ LAYER Metal4 ;
+ RECT -0.900 -0.770 0.900 0.770 ;
+ END Via3_3X3_10_60_120_250_H_H
+
+ VIA Via3_3X3_10_60_120_250_H_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal3 ;
+ RECT -0.710 -0.660 0.710 0.660 ;
+ LAYER Metal4 ;
+ RECT -0.770 -0.900 0.770 0.900 ;
+ END Via3_3X3_10_60_120_250_H_V
+
+ VIA Via3_3X3_10_60_120_250_V_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal3 ;
+ RECT -0.660 -0.710 0.660 0.710 ;
+ LAYER Metal4 ;
+ RECT -0.900 -0.770 0.900 0.770 ;
+ END Via3_3X3_10_60_120_250_V_H
+
+ VIA Via3_3X3_10_60_120_250_V_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.650 -0.650 -0.390 -0.390 ;
+ RECT -0.130 -0.650 0.130 -0.390 ;
+ RECT 0.390 -0.650 0.650 -0.390 ;
+ RECT -0.650 -0.130 -0.390 0.130 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ RECT 0.390 -0.130 0.650 0.130 ;
+ RECT -0.650 0.390 -0.390 0.650 ;
+ RECT -0.130 0.390 0.130 0.650 ;
+ RECT 0.390 0.390 0.650 0.650 ;
+ LAYER Metal3 ;
+ RECT -0.660 -0.710 0.660 0.710 ;
+ LAYER Metal4 ;
+ RECT -0.770 -0.900 0.770 0.900 ;
+ END Via3_3X3_10_60_120_250_V_V
+
+ VIA Via3_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.180 -1.180 1.180 1.180 ;
+ END Via3_4X4H_HH_DEFAULT
+
+ VIA Via3_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.180 -1.180 1.180 1.180 ;
+ END Via3_4X4H_VH_DEFAULT
+
+ VIA Via3_4X4H_HV_DEFAULT1 DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.180 -1.310 1.180 1.310 ;
+ END Via3_4X4H_HV_DEFAULT1
+
+
+END LIBRARY
diff --git a/tech/gf180mcu_4LM_1TM_6K_9t_tech.lef b/tech/gf180mcu_4LM_1TM_6K_9t_tech.lef
new file mode 100755
index 0000000..69d0b13
--- /dev/null
+++ b/tech/gf180mcu_4LM_1TM_6K_9t_tech.lef
@@ -0,0 +1,1042 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 4LM_1TM_6K
+# Preferred routing directions:
+# vertical: Metal2 Metal4
+# horizontal: Metal1 Metal3
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 0.34 0.06 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+LAYER Via2
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via2
+
+
+LAYER Metal3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal3
+
+
+LAYER Via3
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via3
+
+
+
+LAYER Metal4
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 0.74 ;
+ MINWIDTH 0.360 ;
+ WIDTH 0.360 ; # MT.1
+ AREA 0.5625 ; # MT.4
+ SPACING 0.380 ; # MT.2a
+ SPACING 0.500 RANGE 10.005 999.00 ; # MT.2b
+
+ DCCURRENTDENSITY AVERAGE 1.07 ;
+ ACCURRENTDENSITY AVERAGE 1.60 ;
+ RESISTANCE RPERSQ 0.06000 ;
+
+ THICKNESS 0.69 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal4
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+ VIA Via1_HH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_HH
+
+ VIA Via1_HV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_HV
+
+ VIA Via1_VH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_VH
+
+ VIA Via1_VV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_VV
+
+ VIA Via1_2CUT_H
+ LAYER Via1 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via1_2CUT_H
+
+ VIA Via1_2CUT_V
+ LAYER Via1 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via1_2CUT_V
+
+ VIA Via1_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_H_H
+
+ VIA Via1_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_H_V
+
+ VIA Via1_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_V_H
+
+ VIA Via1_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_V_V
+
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_HV_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via2 VIA SECTION
+#------------------------------------------------------------
+ VIA Via2_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_HH
+
+ VIA Via2_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_HV
+
+ VIA Via2_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_VH
+
+ VIA Via2_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_VV
+
+ VIA Via2_2CUT_H
+ LAYER Via2 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.190 0.390 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via2_2CUT_H
+
+ VIA Via2_2CUT_V
+ LAYER Via2 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.130 -0.450 0.130 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via2_2CUT_V
+
+ VIA Via2_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_H_H
+
+ VIA Via2_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_H_V
+
+ VIA Via2_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_V_H
+
+ VIA Via2_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_V_V
+
+VIARULE Via2_GEN_HH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HH
+
+VIARULE Via2_GEN_HV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HV
+
+VIARULE Via2_GEN_VH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VH
+
+VIARULE Via2_GEN_VV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VV
+
+ VIA Via2_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_HH_DEFAULT
+
+ VIA Via2_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_HV_DEFAULT
+
+ VIA Via2_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_VH_DEFAULT
+
+ VIA Via2_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via3 VIA SECTION
+#------------------------------------------------------------
+ VIA Via3_HH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.180 0.190 0.180 ;
+ RESISTANCE 4.500 ;
+ END Via3_HH
+
+ VIA Via3_HV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.180 -0.190 0.180 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_HV
+
+ VIA Via3_VH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.180 0.190 0.180 ;
+ RESISTANCE 4.500 ;
+ END Via3_VH
+
+ VIA Via3_VV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.180 -0.190 0.180 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_VV
+
+ VIA Via3_1_HH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_1_HH
+
+ VIA Via3_1_HV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_1_HV
+
+ VIA Via3_1_VH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_1_VH
+
+ VIA Via3_1_VV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_1_VV
+
+ VIA Via3_2CUT_H
+ LAYER Via3 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via3_2CUT_H
+
+ VIA Via3_2CUT_V
+ LAYER Via3 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via3_2CUT_V
+
+ VIA Via3_2X2_10_60_10_60_H_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_10_60_10_60_H_H
+
+ VIA Via3_2X2_10_60_10_60_H_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_10_60_10_60_H_V
+
+ VIA Via3_2X2_10_60_10_60_V_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_10_60_10_60_V_H
+
+ VIA Via3_2X2_10_60_10_60_V_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_10_60_10_60_V_V
+
+VIARULE Via3_GEN_HH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HH
+
+VIARULE Via3_GEN_HV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HV
+
+VIARULE Via3_GEN_VH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VH
+
+VIARULE Via3_GEN_VV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VV
+
+ VIA Via3_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_HH_DEFAULT
+
+ VIA Via3_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_HV_DEFAULT
+
+ VIA Via3_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_VH_DEFAULT
+
+ VIA Via3_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_VV_DEFAULT
+
+
+END LIBRARY
diff --git a/tech/gf180mcu_4LM_1TM_9K_9t_tech.lef b/tech/gf180mcu_4LM_1TM_9K_9t_tech.lef
new file mode 100755
index 0000000..c81af47
--- /dev/null
+++ b/tech/gf180mcu_4LM_1TM_9K_9t_tech.lef
@@ -0,0 +1,1063 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 4LM_1TM_9K
+# Preferred routing directions:
+# vertical: Metal2 Metal4
+# horizontal: Metal1 Metal3
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 0.34 0.06 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+LAYER Via2
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via2
+
+
+LAYER Metal3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal3
+
+
+LAYER Via3
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ # ENCLOSURE ABOVE 0.01 0.09 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via3
+
+
+
+LAYER Metal4
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 0.9 ;
+ MINWIDTH 0.440 ;
+ WIDTH 0.440 ; # MT.1
+ AREA 0.5625 ; # MT.4
+ SPACING 0.460 ; # MT.2a
+ SPACING 0.600 RANGE 10.005 999.00 ; # MT.2b
+
+ DCCURRENTDENSITY AVERAGE 1.21 ;
+ ACCURRENTDENSITY AVERAGE 1.82 ;
+ RESISTANCE RPERSQ 0.04000 ;
+
+ THICKNESS 0.99 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal4
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+ VIA Via1_HH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_HH
+
+ VIA Via1_HV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_HV
+
+ VIA Via1_VH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_VH
+
+ VIA Via1_VV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_VV
+
+ VIA Via1_2CUT_H
+ LAYER Via1 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via1_2CUT_H
+
+ VIA Via1_2CUT_V
+ LAYER Via1 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via1_2CUT_V
+
+ VIA Via1_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_H_H
+
+ VIA Via1_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_H_V
+
+ VIA Via1_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_V_H
+
+ VIA Via1_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_V_V
+
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_HV_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via2 VIA SECTION
+#------------------------------------------------------------
+ VIA Via2_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_HH
+
+ VIA Via2_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_HV
+
+ VIA Via2_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_VH
+
+ VIA Via2_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_VV
+
+ VIA Via2_2CUT_H
+ LAYER Via2 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.190 0.390 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via2_2CUT_H
+
+ VIA Via2_2CUT_V
+ LAYER Via2 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.130 -0.450 0.130 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via2_2CUT_V
+
+ VIA Via2_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_H_H
+
+ VIA Via2_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_H_V
+
+ VIA Via2_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_V_H
+
+ VIA Via2_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_V_V
+
+VIARULE Via2_GEN_HH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HH
+
+VIARULE Via2_GEN_HV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HV
+
+VIARULE Via2_GEN_VH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VH
+
+VIARULE Via2_GEN_VV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VV
+
+ VIA Via2_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_HH_DEFAULT
+
+ VIA Via2_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_HV_DEFAULT
+
+ VIA Via2_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_VH_DEFAULT
+
+ VIA Via2_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via3 VIA SECTION
+#------------------------------------------------------------
+ VIA Via3_HH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.220 -0.140 0.220 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_HH
+
+ VIA Via3_HV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.220 0.140 0.220 ;
+ RESISTANCE 4.500 ;
+ END Via3_HV
+
+ VIA Via3_VH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.220 -0.140 0.220 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_VH
+
+ VIA Via3_VV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.220 0.140 0.220 ;
+ RESISTANCE 4.500 ;
+ END Via3_VV
+
+ VIA Via3_1_HH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_1_HH
+
+ VIA Via3_1_HV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_1_HV
+
+ VIA Via3_1_VH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_1_VH
+
+ VIA Via3_1_VV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_1_VV
+
+ VIA Via3_2CUT_H
+ LAYER Via3 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via3_2CUT_H
+
+ VIA Via3_2CUT_V
+ LAYER Via3 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via3_2CUT_V
+
+ VIA Via3_2X2_10_60_10_60_H_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_10_60_10_60_H_H
+
+ VIA Via3_2X2_10_60_10_60_H_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_10_60_10_60_H_V
+
+ VIA Via3_2X2_10_60_10_60_V_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_10_60_10_60_V_H
+
+ VIA Via3_2X2_10_60_10_60_V_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_10_60_10_60_V_V
+
+VIARULE Via3_GEN_HH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.090 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HH
+
+VIARULE Via3_GEN_HV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.090 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HV
+
+VIARULE Via3_GEN_VH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.090 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VH
+
+VIARULE Via3_GEN_VV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.090 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VV
+
+VIARULE Via3_0_RULE GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_0_RULE
+
+VIARULE Via3_0 GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_0
+
+ VIA Via3_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_HH_DEFAULT
+
+ VIA Via3_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_HV_DEFAULT
+
+ VIA Via3_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_VH_DEFAULT
+
+ VIA Via3_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_VV_DEFAULT
+
+
+END LIBRARY
diff --git a/tech/gf180mcu_5LM_1TM_11K_9t_tech.lef b/tech/gf180mcu_5LM_1TM_11K_9t_tech.lef
new file mode 100755
index 0000000..3550e31
--- /dev/null
+++ b/tech/gf180mcu_5LM_1TM_11K_9t_tech.lef
@@ -0,0 +1,1300 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 5LM_1TM_11K
+# Preferred routing directions:
+# vertical: Metal2 Metal4
+# horizontal: Metal1 Metal3 Metal5
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 0.34 0.06 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+LAYER Via2
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via2
+
+
+LAYER Metal3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal3
+
+
+LAYER Via3
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via3
+
+
+LAYER Metal4
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal4
+
+
+LAYER Via4
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via4
+
+
+
+LAYER Metal5
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 0.9 ;
+ MINWIDTH 0.440 ;
+ WIDTH 0.440 ; # MT.1
+ AREA 0.5625 ; # MT.4
+ SPACING 0.460 ; # MT.2a
+ SPACING 0.600 RANGE 10.005 999.00 ; # MT.2b
+
+ DCCURRENTDENSITY AVERAGE 1.5 ;
+ ACCURRENTDENSITY AVERAGE 2.2 ;
+ RESISTANCE RPERSQ 0.04000 ;
+
+ THICKNESS 1.19 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal5
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+ VIA Via1_HH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_HH
+
+ VIA Via1_HV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_HV
+
+ VIA Via1_VH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_VH
+
+ VIA Via1_VV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_VV
+
+ VIA Via1_2CUT_H
+ LAYER Via1 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via1_2CUT_H
+
+ VIA Via1_2CUT_V
+ LAYER Via1 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via1_2CUT_V
+
+ VIA Via1_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_H_H
+
+ VIA Via1_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_H_V
+
+ VIA Via1_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_V_H
+
+ VIA Via1_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_V_V
+
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_HV_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via2 VIA SECTION
+#------------------------------------------------------------
+ VIA Via2_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_HH
+
+ VIA Via2_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_HV
+
+ VIA Via2_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_VH
+
+ VIA Via2_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_VV
+
+ VIA Via2_2CUT_H
+ LAYER Via2 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.190 0.390 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via2_2CUT_H
+
+ VIA Via2_2CUT_V
+ LAYER Via2 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.130 -0.450 0.130 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via2_2CUT_V
+
+ VIA Via2_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_H_H
+
+ VIA Via2_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_H_V
+
+ VIA Via2_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_V_H
+
+ VIA Via2_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_V_V
+
+VIARULE Via2_GEN_HH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HH
+
+VIARULE Via2_GEN_HV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HV
+
+VIARULE Via2_GEN_VH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VH
+
+VIARULE Via2_GEN_VV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VV
+
+ VIA Via2_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_HH_DEFAULT
+
+ VIA Via2_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_HV_DEFAULT
+
+ VIA Via2_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_VH_DEFAULT
+
+ VIA Via2_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via3 VIA SECTION
+#------------------------------------------------------------
+ VIA Via3_HH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_HH
+
+ VIA Via3_HV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_HV
+
+ VIA Via3_VH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_VH
+
+ VIA Via3_VV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_VV
+
+ VIA Via3_2CUT_H
+ LAYER Via3 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via3_2CUT_H
+
+ VIA Via3_2CUT_V
+ LAYER Via3 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via3_2CUT_V
+
+ VIA Via3_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_0_60_10_60_H_H
+
+ VIA Via3_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_0_60_10_60_H_V
+
+ VIA Via3_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_0_60_10_60_V_H
+
+ VIA Via3_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_0_60_10_60_V_V
+
+VIARULE Via3_GEN_HH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HH
+
+VIARULE Via3_GEN_HV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HV
+
+VIARULE Via3_GEN_VH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VH
+
+VIARULE Via3_GEN_VV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VV
+
+ VIA Via3_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_HH_DEFAULT
+
+ VIA Via3_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_HV_DEFAULT
+
+ VIA Via3_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_VH_DEFAULT
+
+ VIA Via3_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via4 VIA SECTION
+#------------------------------------------------------------
+ VIA Via4_HH DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via4_HH
+
+ VIA Via4_HV DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via4_HV
+
+ VIA Via4_VH DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via4_VH
+
+ VIA Via4_VV DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via4_VV
+
+ VIA Via4_2CUT_H
+ LAYER Via4 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via4_2CUT_H
+
+ VIA Via4_2CUT_V
+ LAYER Via4 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via4_2CUT_V
+
+ VIA Via4_2X2_10_60_10_60_H_H DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via4_2X2_10_60_10_60_H_H
+
+ VIA Via4_2X2_10_60_10_60_H_V DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal5 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via4_2X2_10_60_10_60_H_V
+
+ VIA Via4_2X2_10_60_10_60_V_H DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via4_2X2_10_60_10_60_V_H
+
+ VIA Via4_2X2_10_60_10_60_V_V DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal5 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via4_2X2_10_60_10_60_V_V
+
+VIARULE Via4_GEN_HH GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_HH
+
+VIARULE Via4_GEN_HV GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_HV
+
+VIARULE Via4_GEN_VH GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_VH
+
+VIARULE Via4_GEN_VV GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_VV
+
+ VIA Via4_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal5 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via4_4X4H_HH_DEFAULT
+
+ VIA Via4_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal5 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via4_4X4H_HV_DEFAULT
+
+ VIA Via4_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal5 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via4_4X4H_VH_DEFAULT
+
+ VIA Via4_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal5 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via4_4X4H_VV_DEFAULT
+
+
+END LIBRARY
diff --git a/tech/gf180mcu_5LM_1TM_9K_9t_tech.lef b/tech/gf180mcu_5LM_1TM_9K_9t_tech.lef
new file mode 100755
index 0000000..9d83148
--- /dev/null
+++ b/tech/gf180mcu_5LM_1TM_9K_9t_tech.lef
@@ -0,0 +1,1361 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 5LM_1TM_9K
+# Preferred routing directions:
+# vertical: Metal2 Metal4
+# horizontal: Metal1 Metal3 Metal5
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 0.34 0.06 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+LAYER Via2
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via2
+
+
+LAYER Metal3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal3
+
+
+LAYER Via3
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via3
+
+
+LAYER Metal4
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal4
+
+
+LAYER Via4
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ # ENCLOSURE ABOVE 0.01 0.09 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via4
+
+
+
+LAYER Metal5
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 0.9 ;
+ MINWIDTH 0.440 ;
+ WIDTH 0.440 ; # MT.1
+ AREA 0.5625 ; # MT.4
+ SPACING 0.460 ; # MT.2a
+ SPACING 0.600 RANGE 10.005 999.00 ; # MT.2b
+
+ DCCURRENTDENSITY AVERAGE 1.21 ;
+ ACCURRENTDENSITY AVERAGE 1.82 ;
+ RESISTANCE RPERSQ 0.04000 ;
+
+ THICKNESS 0.99 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal5
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+ VIA Via1_HH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_HH
+
+ VIA Via1_HV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_HV
+
+ VIA Via1_VH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_VH
+
+ VIA Via1_VV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_VV
+
+ VIA Via1_2CUT_H
+ LAYER Via1 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via1_2CUT_H
+
+ VIA Via1_2CUT_V
+ LAYER Via1 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via1_2CUT_V
+
+ VIA Via1_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_H_H
+
+ VIA Via1_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_H_V
+
+ VIA Via1_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_V_H
+
+ VIA Via1_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_V_V
+
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_HV_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via2 VIA SECTION
+#------------------------------------------------------------
+ VIA Via2_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_HH
+
+ VIA Via2_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_HV
+
+ VIA Via2_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_VH
+
+ VIA Via2_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_VV
+
+ VIA Via2_2CUT_H
+ LAYER Via2 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.190 0.390 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via2_2CUT_H
+
+ VIA Via2_2CUT_V
+ LAYER Via2 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.130 -0.450 0.130 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via2_2CUT_V
+
+ VIA Via2_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_H_H
+
+ VIA Via2_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_H_V
+
+ VIA Via2_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_V_H
+
+ VIA Via2_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_V_V
+
+VIARULE Via2_GEN_HH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HH
+
+VIARULE Via2_GEN_HV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HV
+
+VIARULE Via2_GEN_VH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VH
+
+VIARULE Via2_GEN_VV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VV
+
+ VIA Via2_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_HH_DEFAULT
+
+ VIA Via2_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_HV_DEFAULT
+
+ VIA Via2_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_VH_DEFAULT
+
+ VIA Via2_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via3 VIA SECTION
+#------------------------------------------------------------
+ VIA Via3_HH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_HH
+
+ VIA Via3_HV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_HV
+
+ VIA Via3_VH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_VH
+
+ VIA Via3_VV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_VV
+
+ VIA Via3_2CUT_H
+ LAYER Via3 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via3_2CUT_H
+
+ VIA Via3_2CUT_V
+ LAYER Via3 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via3_2CUT_V
+
+ VIA Via3_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_0_60_10_60_H_H
+
+ VIA Via3_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_0_60_10_60_H_V
+
+ VIA Via3_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_0_60_10_60_V_H
+
+ VIA Via3_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_0_60_10_60_V_V
+
+VIARULE Via3_GEN_HH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HH
+
+VIARULE Via3_GEN_HV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HV
+
+VIARULE Via3_GEN_VH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VH
+
+VIARULE Via3_GEN_VV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VV
+
+ VIA Via3_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_HH_DEFAULT
+
+ VIA Via3_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_HV_DEFAULT
+
+ VIA Via3_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_VH_DEFAULT
+
+ VIA Via3_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via4 VIA SECTION
+#------------------------------------------------------------
+ VIA Via4_HH DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal5 ;
+ RECT -0.220 -0.140 0.220 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via4_HH
+
+ VIA Via4_HV DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.220 0.140 0.220 ;
+ RESISTANCE 4.500 ;
+ END Via4_HV
+
+ VIA Via4_VH DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal5 ;
+ RECT -0.220 -0.140 0.220 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via4_VH
+
+ VIA Via4_VV DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.220 0.140 0.220 ;
+ RESISTANCE 4.500 ;
+ END Via4_VV
+
+ VIA Via4_1_HH DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via4_1_HH
+
+ VIA Via4_1_HV DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via4_1_HV
+
+ VIA Via4_1_VH DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via4_1_VH
+
+ VIA Via4_1_VV DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via4_1_VV
+
+ VIA Via4_2CUT_H
+ LAYER Via4 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via4_2CUT_H
+
+ VIA Via4_2CUT_V
+ LAYER Via4 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via4_2CUT_V
+
+ VIA Via4_2X2_10_60_10_60_H_H DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via4_2X2_10_60_10_60_H_H
+
+ VIA Via4_2X2_10_60_10_60_H_V DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER Metal5 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via4_2X2_10_60_10_60_H_V
+
+ VIA Via4_2X2_10_60_10_60_V_H DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via4_2X2_10_60_10_60_V_H
+
+ VIA Via4_2X2_10_60_10_60_V_V DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER Metal5 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via4_2X2_10_60_10_60_V_V
+
+VIARULE Via4_GEN_HH GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.090 0.010 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_HH
+
+VIARULE Via4_GEN_HV GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.010 0.090 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_HV
+
+VIARULE Via4_GEN_VH GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.090 0.010 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_VH
+
+VIARULE Via4_GEN_VV GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.010 0.090 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_VV
+
+VIARULE Via4_0_RULE GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_0_RULE
+
+VIARULE Via4_0 GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_0
+
+ VIA Via4_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal5 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via4_4X4H_HH_DEFAULT
+
+ VIA Via4_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal5 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via4_4X4H_HV_DEFAULT
+
+ VIA Via4_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal5 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via4_4X4H_VH_DEFAULT
+
+ VIA Via4_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal5 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via4_4X4H_VV_DEFAULT
+
+
+END LIBRARY
diff --git a/tech/gf180mcu_6LM_1TM_9K_9t_tech.lef b/tech/gf180mcu_6LM_1TM_9K_9t_tech.lef
new file mode 100755
index 0000000..2b817d9
--- /dev/null
+++ b/tech/gf180mcu_6LM_1TM_9K_9t_tech.lef
@@ -0,0 +1,1659 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+##################################################################################
+#
+# GLOBALFOUNDRIES
+#
+##################################################################################
+#
+# 180MCU Tech LEF File
+# based on DRM DM-000013-01 Rev 13
+# TFG-Version: 2.1.9
+# Date: February 2018
+#-------------------------------------------------------
+# metal stack option: 6LM_1TM_9K
+# Preferred routing directions:
+# vertical: Metal2 Metal4 MetalTop
+# horizontal: Metal1 Metal3 Metal5
+#------------------------------------------------------
+# This Techfile contains not correct Parasitic Information.
+# USE Appropriate parasitic files for Parasitic Extraction.
+#------------------------------------------------------
+
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ DATABASE MICRONS 2000 ;
+ CAPACITANCE PICOFARADS 1 ;
+ CURRENT MILLIAMPS 1 ;
+ RESISTANCE OHMS 1 ;
+END UNITS
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_EOLENCLOSURE STRING ;
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+MANUFACTURINGGRID 0.0050 ;
+CLEARANCEMEASURE EUCLIDEAN ;
+USEMINSPACING OBS ON ;
+
+LAYER Poly2
+ TYPE MASTERSLICE ;
+END Poly2
+
+LAYER CON
+ TYPE CUT ;
+END CON
+
+
+
+LAYER Metal1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.230 ; # Mn.1 (n=1)
+ WIDTH 0.230 ; # Mn.1 (n=1)
+ SPACING 0.230 ; # Mn.2a (n=1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNASIDEAREARATIO 400 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal1
+
+
+LAYER Via1
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.00 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+ PROPERTY LEF58_EOLENCLOSURE "
+ EOLENCLOSURE 0.34 0.06 ;" ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via1
+
+
+LAYER Metal2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal2
+
+
+LAYER Via2
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via2
+
+
+LAYER Metal3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal3
+
+
+LAYER Via3
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via3
+
+
+LAYER Metal4
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal4
+
+
+LAYER Via4
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via4
+
+
+LAYER Metal5
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.56 ;
+ OFFSET 0.0 ;
+
+ MINWIDTH 0.280 ;
+ WIDTH 0.280 ; # Mn.1 (n>1)
+ SPACING 0.280 ; # Mn.2a (n>1)
+ SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
+ AREA 0.1444 ; # Mn.3
+
+ THICKNESS 0.54 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ DCCURRENTDENSITY AVERAGE 0.67 ;
+ ACCURRENTDENSITY AVERAGE 1.00 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+ RESISTANCE RPERSQ 0.090000 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END Metal5
+
+
+LAYER Via5
+ TYPE CUT ;
+ SPACING 0.26 ;
+ WIDTH 0.26 ;
+
+ ENCLOSURE BELOW 0.01 0.06 ;
+ # ENCLOSURE ABOVE 0.01 0.09 ;
+ ENCLOSURE ABOVE 0.01 0.06 ;
+
+ # a bit conservative for Vn.3/4a without considering the protrusion length of 0.28
+ PROPERTY LEF58_EOLENCLOSURE " EOLENCLOSURE 0.34 0.06 ; " ;
+
+ ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b
+
+ ACCURRENTDENSITY AVERAGE 0.28 ;
+ DCCURRENTDENSITY AVERAGE 0.18 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAAREARATIO 20.0 ;
+END Via5
+
+
+
+LAYER MetalTop
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ OFFSET 0.0 ;
+
+
+ PITCH 0.9 ;
+ MINWIDTH 0.440 ;
+ WIDTH 0.440 ; # MT.1
+ AREA 0.5625 ; # MT.4
+ SPACING 0.460 ; # MT.2a
+ SPACING 0.600 RANGE 10.005 999.00 ; # MT.2b
+
+ DCCURRENTDENSITY AVERAGE 1.21 ;
+ ACCURRENTDENSITY AVERAGE 1.82 ;
+ RESISTANCE RPERSQ 0.04000 ;
+
+ THICKNESS 0.99 ;
+
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNADIFFSIDEAREARATIO 400 ;
+ ANTENNAGATEPLUSDIFF 2 ;
+
+ CAPACITANCE CPERSQDIST 0.0000394 ;
+
+ MINIMUMDENSITY 30.0 ;
+ DENSITYCHECKWINDOW 200.0 200.0 ;
+ DENSITYCHECKSTEP 100.0 ;
+
+END MetalTop
+
+
+
+LAYER OVERLAP
+ TYPE OVERLAP ;
+END OVERLAP
+
+LAYER PR_bndry
+ TYPE MASTERSLICE ;
+END PR_bndry
+
+
+#------------------------------------------------------------
+# Via1 VIA SECTION
+#------------------------------------------------------------
+ VIA Via1_HH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_HH
+
+ VIA Via1_HV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.130 0.190 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_HV
+
+ VIA Via1_VH DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via1_VH
+
+ VIA Via1_VV DEFAULT
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.130 -0.190 0.130 0.190 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via1_VV
+
+ VIA Via1_2CUT_H
+ LAYER Via1 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via1_2CUT_H
+
+ VIA Via1_2CUT_V
+ LAYER Via1 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via1_2CUT_V
+
+ VIA Via1_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_H_H
+
+ VIA Via1_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_H_V
+
+ VIA Via1_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via1_2X2_0_60_10_60_V_H
+
+ VIA Via1_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via1 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal1 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal2 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via1_2X2_0_60_10_60_V_V
+
+VIARULE Via1_GEN_HH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HH
+
+VIARULE Via1_GEN_HV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.060 0.000 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_HV
+
+VIARULE Via1_GEN_VH GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VH
+
+VIARULE Via1_GEN_VV GENERATE
+ LAYER Metal1 ;
+ ENCLOSURE 0.000 0.060 ;
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via1 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via1_GEN_VV
+
+ VIA Via1_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_HH_DEFAULT
+
+ VIA Via1_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.120 -1.060 1.120 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_HV_DEFAULT
+
+ VIA Via1_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via1_4X4H_VH_DEFAULT
+
+ VIA Via1_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via1 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal1 ;
+ RECT -1.060 -1.120 1.060 1.120 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via1_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via2 VIA SECTION
+#------------------------------------------------------------
+ VIA Via2_HH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_HH
+
+ VIA Via2_HV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_HV
+
+ VIA Via2_VH DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via2_VH
+
+ VIA Via2_VV DEFAULT
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via2_VV
+
+ VIA Via2_2CUT_H
+ LAYER Via2 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.190 0.390 0.190 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via2_2CUT_H
+
+ VIA Via2_2CUT_V
+ LAYER Via2 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.130 -0.450 0.130 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via2_2CUT_V
+
+ VIA Via2_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_H_H
+
+ VIA Via2_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_H_V
+
+ VIA Via2_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via2_2X2_0_60_10_60_V_H
+
+ VIA Via2_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via2 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal2 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal3 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via2_2X2_0_60_10_60_V_V
+
+VIARULE Via2_GEN_HH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HH
+
+VIARULE Via2_GEN_HV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_HV
+
+VIARULE Via2_GEN_VH GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VH
+
+VIARULE Via2_GEN_VV GENERATE
+ LAYER Metal2 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via2 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via2_GEN_VV
+
+ VIA Via2_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_HH_DEFAULT
+
+ VIA Via2_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_HV_DEFAULT
+
+ VIA Via2_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via2_4X4H_VH_DEFAULT
+
+ VIA Via2_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via2 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal2 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via2_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via3 VIA SECTION
+#------------------------------------------------------------
+ VIA Via3_HH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_HH
+
+ VIA Via3_HV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_HV
+
+ VIA Via3_VH DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via3_VH
+
+ VIA Via3_VV DEFAULT
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via3_VV
+
+ VIA Via3_2CUT_H
+ LAYER Via3 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.130 0.450 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via3_2CUT_H
+
+ VIA Via3_2CUT_V
+ LAYER Via3 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.190 -0.390 0.190 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via3_2CUT_V
+
+ VIA Via3_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_0_60_10_60_H_H
+
+ VIA Via3_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_0_60_10_60_H_V
+
+ VIA Via3_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via3_2X2_0_60_10_60_V_H
+
+ VIA Via3_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via3 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal3 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal4 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via3_2X2_0_60_10_60_V_V
+
+VIARULE Via3_GEN_HH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HH
+
+VIARULE Via3_GEN_HV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_HV
+
+VIARULE Via3_GEN_VH GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VH
+
+VIARULE Via3_GEN_VV GENERATE
+ LAYER Metal3 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via3 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via3_GEN_VV
+
+ VIA Via3_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_HH_DEFAULT
+
+ VIA Via3_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_HV_DEFAULT
+
+ VIA Via3_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via3_4X4H_VH_DEFAULT
+
+ VIA Via3_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via3 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal3 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via3_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via4 VIA SECTION
+#------------------------------------------------------------
+ VIA Via4_HH DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via4_HH
+
+ VIA Via4_HV DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via4_HV
+
+ VIA Via4_VH DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via4_VH
+
+ VIA Via4_VV DEFAULT
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via4_VV
+
+ VIA Via4_2CUT_H
+ LAYER Via4 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal4 ;
+ RECT -0.390 -0.190 0.390 0.190 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ END Via4_2CUT_H
+
+ VIA Via4_2CUT_V
+ LAYER Via4 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.130 -0.450 0.130 0.450 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ END Via4_2CUT_V
+
+ VIA Via4_2X2_0_60_10_60_H_H DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via4_2X2_0_60_10_60_H_H
+
+ VIA Via4_2X2_0_60_10_60_H_V DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.450 -0.390 0.450 0.390 ;
+ LAYER Metal5 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via4_2X2_0_60_10_60_H_V
+
+ VIA Via4_2X2_0_60_10_60_V_H DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via4_2X2_0_60_10_60_V_H
+
+ VIA Via4_2X2_0_60_10_60_V_V DEFAULT
+ LAYER Via4 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal4 ;
+ RECT -0.390 -0.450 0.390 0.450 ;
+ LAYER Metal5 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via4_2X2_0_60_10_60_V_V
+
+VIARULE Via4_GEN_HH GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_HH
+
+VIARULE Via4_GEN_HV GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_HV
+
+VIARULE Via4_GEN_VH GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_VH
+
+VIARULE Via4_GEN_VV GENERATE
+ LAYER Metal4 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Metal5 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via4 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via4_GEN_VV
+
+ VIA Via4_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal5 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via4_4X4H_HH_DEFAULT
+
+ VIA Via4_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER Metal5 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via4_4X4H_HV_DEFAULT
+
+ VIA Via4_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal5 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via4_4X4H_VH_DEFAULT
+
+ VIA Via4_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via4 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal4 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER Metal5 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via4_4X4H_VV_DEFAULT
+
+#------------------------------------------------------------
+# Via5 VIA SECTION
+#------------------------------------------------------------
+ VIA Via5_HH DEFAULT
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER MetalTop ;
+ RECT -0.220 -0.140 0.220 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via5_HH
+
+ VIA Via5_HV DEFAULT
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER MetalTop ;
+ RECT -0.140 -0.220 0.140 0.220 ;
+ RESISTANCE 4.500 ;
+ END Via5_HV
+
+ VIA Via5_VH DEFAULT
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER MetalTop ;
+ RECT -0.220 -0.140 0.220 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via5_VH
+
+ VIA Via5_VV DEFAULT
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER MetalTop ;
+ RECT -0.140 -0.220 0.140 0.220 ;
+ RESISTANCE 4.500 ;
+ END Via5_VV
+
+ VIA Via5_1_HH DEFAULT
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER MetalTop ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via5_1_HH
+
+ VIA Via5_1_HV DEFAULT
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ LAYER MetalTop ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via5_1_HV
+
+ VIA Via5_1_VH DEFAULT
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER MetalTop ;
+ RECT -0.190 -0.140 0.190 0.140 ;
+ RESISTANCE 4.500 ;
+ END Via5_1_VH
+
+ VIA Via5_1_VV DEFAULT
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ LAYER Metal5 ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ LAYER MetalTop ;
+ RECT -0.140 -0.190 0.140 0.190 ;
+ RESISTANCE 4.500 ;
+ END Via5_1_VV
+
+ VIA Via5_2CUT_H
+ LAYER Via5 ;
+ RECT -0.390 -0.130 -0.130 0.130 ;
+ RECT 0.130 -0.130 0.390 0.130 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.140 0.450 0.140 ;
+ LAYER MetalTop ;
+ RECT -0.400 -0.190 0.400 0.190 ;
+ END Via5_2CUT_H
+
+ VIA Via5_2CUT_V
+ LAYER Via5 ;
+ RECT -0.130 -0.390 0.130 -0.130 ;
+ RECT -0.130 0.130 0.130 0.390 ;
+ LAYER Metal5 ;
+ RECT -0.190 -0.400 0.190 0.400 ;
+ LAYER MetalTop ;
+ RECT -0.140 -0.450 0.140 0.450 ;
+ END Via5_2CUT_V
+
+ VIA Via5_2X2_10_60_10_60_H_H DEFAULT
+ LAYER Via5 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER MetalTop ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via5_2X2_10_60_10_60_H_H
+
+ VIA Via5_2X2_10_60_10_60_H_V DEFAULT
+ LAYER Via5 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal5 ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ LAYER MetalTop ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via5_2X2_10_60_10_60_H_V
+
+ VIA Via5_2X2_10_60_10_60_V_H DEFAULT
+ LAYER Via5 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal5 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER MetalTop ;
+ RECT -0.450 -0.400 0.450 0.400 ;
+ END Via5_2X2_10_60_10_60_V_H
+
+ VIA Via5_2X2_10_60_10_60_V_V DEFAULT
+ LAYER Via5 ;
+ RECT -0.390 -0.390 -0.130 -0.130 ;
+ RECT 0.130 -0.390 0.390 -0.130 ;
+ RECT -0.390 0.130 -0.130 0.390 ;
+ RECT 0.130 0.130 0.390 0.390 ;
+ LAYER Metal5 ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ LAYER MetalTop ;
+ RECT -0.400 -0.450 0.400 0.450 ;
+ END Via5_2X2_10_60_10_60_V_V
+
+VIARULE Via5_GEN_HH GENERATE
+ LAYER Metal5 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER MetalTop ;
+ ENCLOSURE 0.090 0.010 ;
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via5_GEN_HH
+
+VIARULE Via5_GEN_HV GENERATE
+ LAYER Metal5 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER MetalTop ;
+ ENCLOSURE 0.010 0.090 ;
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via5_GEN_HV
+
+VIARULE Via5_GEN_VH GENERATE
+ LAYER Metal5 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER MetalTop ;
+ ENCLOSURE 0.090 0.010 ;
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via5_GEN_VH
+
+VIARULE Via5_GEN_VV GENERATE
+ LAYER Metal5 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER MetalTop ;
+ ENCLOSURE 0.010 0.090 ;
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via5_GEN_VV
+
+VIARULE Via5_0_RULE GENERATE
+ LAYER Metal5 ;
+ ENCLOSURE 0.060 0.010 ;
+ LAYER MetalTop ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via5_0_RULE
+
+VIARULE Via5_0 GENERATE
+ LAYER Metal5 ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER MetalTop ;
+ ENCLOSURE 0.010 0.060 ;
+ LAYER Via5 ;
+ RECT -0.130 -0.130 0.130 0.130 ;
+ SPACING 0.520 BY 0.520 ;
+END Via5_0
+
+ VIA Via5_4X4H_HH_DEFAULT DEFAULT
+ LAYER Via5 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal5 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER MetalTop ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via5_4X4H_HH_DEFAULT
+
+ VIA Via5_4X4H_HV_DEFAULT DEFAULT
+ LAYER Via5 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal5 ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ LAYER MetalTop ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via5_4X4H_HV_DEFAULT
+
+ VIA Via5_4X4H_VH_DEFAULT DEFAULT
+ LAYER Via5 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal5 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER MetalTop ;
+ RECT -1.120 -1.070 1.120 1.070 ;
+ END Via5_4X4H_VH_DEFAULT
+
+ VIA Via5_4X4H_VV_DEFAULT DEFAULT
+ LAYER Via5 ;
+ RECT -1.060 -1.060 -0.800 -0.800 ;
+ RECT -0.440 -1.060 -0.180 -0.800 ;
+ RECT 0.180 -1.060 0.440 -0.800 ;
+ RECT 0.800 -1.060 1.060 -0.800 ;
+ RECT -1.060 -0.440 -0.800 -0.180 ;
+ RECT -0.440 -0.440 -0.180 -0.180 ;
+ RECT 0.180 -0.440 0.440 -0.180 ;
+ RECT 0.800 -0.440 1.060 -0.180 ;
+ RECT -1.060 0.180 -0.800 0.440 ;
+ RECT -0.440 0.180 -0.180 0.440 ;
+ RECT 0.180 0.180 0.440 0.440 ;
+ RECT 0.800 0.180 1.060 0.440 ;
+ RECT -1.060 0.800 -0.800 1.060 ;
+ RECT -0.440 0.800 -0.180 1.060 ;
+ RECT 0.180 0.800 0.440 1.060 ;
+ RECT 0.800 0.800 1.060 1.060 ;
+ LAYER Metal5 ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ LAYER MetalTop ;
+ RECT -1.070 -1.120 1.070 1.120 ;
+ END Via5_4X4H_VV_DEFAULT
+
+
+END LIBRARY
