cells/addh/definition.json

{
    "description": "1 bit Half Adder",
    "file_prefix": "gf180mcu_fd_sc_mcu9t5v0__addh",
    "library": "gf180mcu_fd_sc_mcu9t5v0",
    "name": "addh",
    "parameters": [],
    "ports": [
        [
            "signal",
            "A",
            "input",
            ""
        ],
        [
            "signal",
            "B",
            "input",
            ""
        ],
        [
            "signal",
            "CO",
            "output",
            ""
        ],
        [
            "signal",
            "S",
            "output",
            ""
        ],
        [
            "power",
            "VDD",
            "input",
            "supply1"
        ],
        [
            "power",
            "VSS",
            "input",
            "supply0"
        ]
    ],
    "type": "cell",
    "verilog_name": "gf180mcu_fd_sc_mcu9t5v0__addh"
}