diff --git a/cells/addf/definition.json b/cells/addf/definition.json
new file mode 100644
index 0000000..050ff93
--- /dev/null
+++ b/cells/addf/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "Full Adder",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__addf",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "addf",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "CI",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "CO",
+            "output",
+            ""
+        ],
+        [
+            "signal",
+            "S",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__addf"
+}
\ No newline at end of file
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new file mode 100644
index 0000000..1c1bdc1
--- /dev/null
+++ b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf.schematic.svg
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diff --git a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_1.rst b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_1.rst
index debf07b..3d191eb 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_1.rst
+++ b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__addf_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__addf_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__addf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__addf_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__addf_1 layout**
diff --git a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_1.schematic.png b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_1.schematic.png
deleted file mode 100644
index d27f5c7..0000000
--- a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_2.rst b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_2.rst
index ee6ff91..942fb4a 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_2.rst
+++ b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__addf_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__addf_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__addf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__addf_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__addf_2 layout**
diff --git a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_2.schematic.png b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_2.schematic.png
deleted file mode 100644
index d27f5c7..0000000
--- a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_4.rst b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_4.rst
index 20214c6..92aed61 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_4.rst
+++ b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__addf_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__addf_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__addf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__addf_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__addf_4 layout**
diff --git a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_4.schematic.png b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_4.schematic.png
deleted file mode 100644
index d27f5c7..0000000
--- a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/addh/definition.json b/cells/addh/definition.json
new file mode 100644
index 0000000..062184b
--- /dev/null
+++ b/cells/addh/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "Half Adder",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__addh",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "addh",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "CO",
+            "output",
+            ""
+        ],
+        [
+            "signal",
+            "S",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__addh"
+}
\ No newline at end of file
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh.schematic.svg b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh.schematic.svg
new file mode 100644
index 0000000..0a81fea
--- /dev/null
+++ b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="315" height="188.5"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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\ No newline at end of file
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_1.rst b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_1.rst
index 3f82f3b..941edd6 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_1.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__addh_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__addh_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__addh.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__addh_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__addh_1 layout**
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_1.schematic.png b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_1.schematic.png
deleted file mode 100644
index e988407..0000000
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_2.rst b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_2.rst
index 70ad587..363c22d 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_2.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__addh_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__addh_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__addh.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__addh_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__addh_2 layout**
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_2.schematic.png b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_2.schematic.png
deleted file mode 100644
index e988407..0000000
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_4.rst b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_4.rst
index 10d23c4..e7ca334 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_4.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__addh_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__addh_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__addh.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__addh_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__addh_4 layout**
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_4.schematic.png b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_4.schematic.png
deleted file mode 100644
index e988407..0000000
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/and2/definition.json b/cells/and2/definition.json
new file mode 100644
index 0000000..1077ae4
--- /dev/null
+++ b/cells/and2/definition.json
@@ -0,0 +1,41 @@
+{
+    "description": "2-input AND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__and2",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "and2",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__and2"
+}
\ No newline at end of file
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2.schematic.svg b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2.schematic.svg
new file mode 100644
index 0000000..0b475fd
--- /dev/null
+++ b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="184" height="119"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(77,27)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and2.v:22$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and2.v:22$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(142,29.5)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="42" x2="52" y1="97" y2="97" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="97" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="77" y1="47" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="107" x2="142" y1="39.5" y2="39.5" class="net_4 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_1.rst b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_1.rst
index f0788ce..19398af 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_1.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__and2_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__and2_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__and2_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__and2_1 layout**
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_1.schematic.png b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_1.schematic.png
deleted file mode 100644
index ac70987..0000000
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_2.rst b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_2.rst
index 2abeb10..f34ae6a 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_2.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__and2_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__and2_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__and2_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__and2_2 layout**
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_2.schematic.png b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_2.schematic.png
deleted file mode 100644
index ac70987..0000000
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_4.rst b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_4.rst
index 9468d6c..358f28a 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_4.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__and2_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__and2_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__and2_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__and2_4 layout**
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_4.schematic.png b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_4.schematic.png
deleted file mode 100644
index ac70987..0000000
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/and3/definition.json b/cells/and3/definition.json
new file mode 100644
index 0000000..bcbdcf2
--- /dev/null
+++ b/cells/and3/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "3-input AND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__and3",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "and3",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__and3"
+}
\ No newline at end of file
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3.schematic.svg b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3.schematic.svg
new file mode 100644
index 0000000..e672cf6
--- /dev/null
+++ b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="249" height="129"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(77,27)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and3.v:22$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and3.v:22$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(142,34.5)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and3.v:22$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and3.v:22$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(77,97)" s:width="30" s:height="20" id="cell_A3"><text x="15" y="-4" class="nodelabel cell_A3" s:attribute="ref">A3</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A3"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(207,37)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="42" x2="52" y1="97" y2="97" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="97" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="77" y1="47" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="107" x2="142" y1="39.5" y2="39.5" class="net_6 width_1" style="stroke-width: 1"/><line x1="107" x2="117" y1="107" y2="107" class="net_4 width_1" style="stroke-width: 1"/><line x1="117" x2="117" y1="107" y2="54.5" class="net_4 width_1" style="stroke-width: 1"/><line x1="117" x2="142" y1="54.5" y2="54.5" class="net_4 width_1" style="stroke-width: 1"/><line x1="172" x2="207" y1="47" y2="47" class="net_5 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_1.rst b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_1.rst
index 9dec8ee..4b669b8 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_1.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__and3_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__and3_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__and3_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__and3_1 layout**
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_1.schematic.png b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_1.schematic.png
deleted file mode 100644
index 53b37c6..0000000
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_2.rst b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_2.rst
index 53ed6b8..f651338 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_2.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__and3_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__and3_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__and3_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__and3_2 layout**
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_2.schematic.png b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_2.schematic.png
deleted file mode 100644
index 53b37c6..0000000
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_4.rst b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_4.rst
index 6464766..bf2d719 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_4.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__and3_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__and3_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__and3_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__and3_4 layout**
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_4.schematic.png b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_4.schematic.png
deleted file mode 100644
index 53b37c6..0000000
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/and4/definition.json b/cells/and4/definition.json
new file mode 100644
index 0000000..8a3a96a
--- /dev/null
+++ b/cells/and4/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "4-input AND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__and4",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "and4",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A4",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__and4"
+}
\ No newline at end of file
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4.schematic.svg b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4.schematic.svg
new file mode 100644
index 0000000..04db3bf
--- /dev/null
+++ b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="314" height="136.5"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(77,27)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and4.v:22$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and4.v:22$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(142,34.5)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and4.v:22$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and4.v:22$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(207,42)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and4.v:22$3"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__and4.v:22$3"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(77,97)" s:width="30" s:height="20" id="cell_A3"><text x="15" y="-4" class="nodelabel cell_A3" s:attribute="ref">A3</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A3"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(142,104.5)" s:width="30" s:height="20" id="cell_A4"><text x="15" y="-4" class="nodelabel cell_A4" s:attribute="ref">A4</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A4"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(272,44.5)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="42" x2="52" y1="97" y2="97" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="97" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="77" y1="47" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="107" x2="142" y1="39.5" y2="39.5" class="net_7 width_1" style="stroke-width: 1"/><line x1="107" x2="117" y1="107" y2="107" class="net_4 width_1" style="stroke-width: 1"/><line x1="117" x2="117" y1="107" y2="54.5" class="net_4 width_1" style="stroke-width: 1"/><line x1="117" x2="142" y1="54.5" y2="54.5" class="net_4 width_1" style="stroke-width: 1"/><line x1="172" x2="207" y1="47" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="172" x2="182" y1="114.5" y2="114.5" class="net_5 width_1" style="stroke-width: 1"/><line x1="182" x2="182" y1="114.5" y2="62" class="net_5 width_1" style="stroke-width: 1"/><line x1="182" x2="207" y1="62" y2="62" class="net_5 width_1" style="stroke-width: 1"/><line x1="237" x2="272" y1="54.5" y2="54.5" class="net_6 width_1" style="stroke-width: 1"/></svg>
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diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_1.rst b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_1.rst
index 511adf5..f9aac4f 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_1.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__and4_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__and4_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__and4_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__and4_1 layout**
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_1.schematic.png b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_1.schematic.png
deleted file mode 100644
index d29a8b1..0000000
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_2.rst b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_2.rst
index f85a8e5..a9b4ecb 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_2.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__and4_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__and4_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__and4_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__and4_2 layout**
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_2.schematic.png b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_2.schematic.png
deleted file mode 100644
index d29a8b1..0000000
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_4.rst b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_4.rst
index 36822d3..627e152 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_4.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__and4_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__and4_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__and4_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__and4_4 layout**
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_4.schematic.png b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_4.schematic.png
deleted file mode 100644
index d29a8b1..0000000
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/antenna/definition.json b/cells/antenna/definition.json
new file mode 100644
index 0000000..f8e8fa4
--- /dev/null
+++ b/cells/antenna/definition.json
@@ -0,0 +1,29 @@
+{
+    "description": "antenna cell",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__antenna",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "antenna",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "I",
+            "input",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__antenna"
+}
\ No newline at end of file
diff --git a/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst b/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst
index fd8130c..2f76d18 100644
--- a/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst
+++ b/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__antenna schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__antenna.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__antenna.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__antenna schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__antenna layout**
diff --git a/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.schematic.png b/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.schematic.png
deleted file mode 100644
index 9a5f56c..0000000
--- a/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.schematic.svg b/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.schematic.svg
new file mode 100644
index 0000000..4bb6a24
--- /dev/null
+++ b/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="54" height="54"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
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+.splitjoinBody {
+  fill:#000;
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\ No newline at end of file
diff --git a/cells/aoi21/definition.json b/cells/aoi21/definition.json
new file mode 100644
index 0000000..a955143
--- /dev/null
+++ b/cells/aoi21/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "2-input AND into 2-input NOR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi21",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "aoi21",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__aoi21"
+}
\ No newline at end of file
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21.schematic.svg b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21.schematic.svg
new file mode 100644
index 0000000..17cff35
--- /dev/null
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="315" height="194"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
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+  text-anchor: middle;
+}
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+  text-anchor: end;
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+.splitjoinBody {
+  fill:#000;
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\ No newline at end of file
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.rst b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.rst
index 1f557e2..d3795cd 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi21_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi21_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi21.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi21_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi21_1 layout**
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.schematic.png b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.schematic.png
deleted file mode 100644
index da351df..0000000
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_2.rst b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_2.rst
index d72d41e..8a41635 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_2.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi21_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi21_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi21.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi21_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi21_2 layout**
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_2.schematic.png b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_2.schematic.png
deleted file mode 100644
index da351df..0000000
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.rst b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.rst
index 55d88ee..f3c0c7a 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi21_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi21_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi21.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi21_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi21_4 layout**
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.schematic.png b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.schematic.png
deleted file mode 100644
index da351df..0000000
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi211/definition.json b/cells/aoi211/definition.json
new file mode 100644
index 0000000..9cb39f4
--- /dev/null
+++ b/cells/aoi211/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "2-input AND into 3-input NOR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi211",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "aoi211",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "C",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__aoi211"
+}
\ No newline at end of file
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211.schematic.svg b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211.schematic.svg
new file mode 100644
index 0000000..b1cf88f
--- /dev/null
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="381" height="249"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(143.66666666666666,77)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:36$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:36$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(209,84.5)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:36$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:36$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(143.66666666666666,157)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:44$3"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:44$3"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(209,207)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:44$4"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:44$4"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:0$6"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:0$6"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:0$6"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:0$7"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:0$7"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:0$7"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(144,217)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:0$8"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi211.v:0$8"/><circle cx="24" cy="10" r="3" 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s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,152)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(339,202)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_B"><text x="15" y="-4" class="nodelabel cell_B" s:attribute="ref">B</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_B"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(78,217)" s:width="30" s:height="20" id="cell_C"><text x="15" y="-4" class="nodelabel cell_C" s:attribute="ref">C</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_C"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="105" x2="118" y1="32" y2="32" class="net_7 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="32" y2="82" class="net_7 width_1" style="stroke-width: 1"/><line x1="118" x2="143.66666666666666" y1="82" y2="82" class="net_7 width_1" style="stroke-width: 1"/><line x1="105" x2="143.66666666666666" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="97" y2="177" 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\ No newline at end of file
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_1.rst b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_1.rst
index d728d1d..24df471 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_1.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi211_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi211_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi211.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi211_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi211_1 layout**
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_1.schematic.png b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_1.schematic.png
deleted file mode 100644
index e14de5c..0000000
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.rst b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.rst
index a98a716..083acad 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi211_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi211_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi211.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi211_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi211_2 layout**
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.schematic.png b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.schematic.png
deleted file mode 100644
index e14de5c..0000000
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.rst b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.rst
index 08cc282..b0ab6f1 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi211_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi211_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi211.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi211_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi211_4 layout**
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.schematic.png b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.schematic.png
deleted file mode 100644
index e14de5c..0000000
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi22/definition.json b/cells/aoi22/definition.json
new file mode 100644
index 0000000..6804d73
--- /dev/null
+++ b/cells/aoi22/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "two 2-input AND into 2-input NOR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi22",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "aoi22",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__aoi22"
+}
\ No newline at end of file
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22.schematic.svg b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22.schematic.svg
new file mode 100644
index 0000000..71f3e26
--- /dev/null
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="451" height="260"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(148.66666666666666,27)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:32$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:32$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(148.66666666666666,142)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:40$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:40$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(214,157)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:48$3"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:48$3"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(279,222)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:52$4"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:52$4"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,152)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$10"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$10"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$10"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(149,217)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$11"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$11"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$11"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$8"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$8"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$8"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$9"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$9"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:0$9"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(214,34.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:54$5"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:54$5"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(279,42)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:54$6"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:54$6"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(344,49.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:54$7"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__aoi22.v:54$7"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,152)" s:width="30" s:height="20" id="cell_B2"><text x="15" y="-4" class="nodelabel cell_B2" s:attribute="ref">B2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_B2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_B1"><text x="15" y="-4" class="nodelabel cell_B1" s:attribute="ref">B1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_B1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(409,52)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(78,217)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="105" x2="148.66666666666666" y1="32" y2="32" class="net_7 width_1" style="stroke-width: 1"/><line x1="105" x2="138" y1="32" y2="32" class="net_7 width_1" style="stroke-width: 1"/><line x1="138" x2="138" y1="32" y2="147" class="net_7 width_1" style="stroke-width: 1"/><circle cx="138" cy="32" r="2" style="fill:#000" class="net_7 width_1"/><line x1="138" x2="148.66666666666666" y1="147" y2="147" class="net_7 width_1" style="stroke-width: 1"/><line x1="105" x2="128" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="128" x2="128" y1="97" y2="47" class="net_8 width_1" style="stroke-width: 1"/><circle cx="128" cy="97" r="2" style="fill:#000" class="net_8 width_1"/><line x1="128" x2="148.66666666666666" y1="47" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="105" x2="128" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="128" x2="128" y1="97" y2="177" class="net_8 width_1" style="stroke-width: 1"/><line x1="128" x2="214" y1="177" y2="177" class="net_8 width_1" style="stroke-width: 1"/><line x1="105" x2="148.66666666666666" y1="162" y2="162" class="net_10 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="162" y2="162" class="net_10 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="162" y2="247" class="net_10 width_1" style="stroke-width: 1"/><line x1="118" x2="254" y1="247" y2="247" class="net_10 width_1" style="stroke-width: 1"/><line x1="254" x2="254" y1="247" y2="242" class="net_10 width_1" style="stroke-width: 1"/><circle cx="118" cy="162" r="2" style="fill:#000" class="net_10 width_1"/><line x1="254" x2="279" y1="242" y2="242" class="net_10 width_1" style="stroke-width: 1"/><line x1="176" x2="189" y1="227" y2="227" class="net_12 width_1" style="stroke-width: 1"/><line x1="189" x2="189" y1="227" y2="162" class="net_12 width_1" style="stroke-width: 1"/><circle cx="189" cy="227" r="2" style="fill:#000" class="net_12 width_1"/><line x1="189" x2="214" y1="162" y2="162" class="net_12 width_1" style="stroke-width: 1"/><line x1="176" x2="279" y1="227" y2="227" class="net_12 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="162" y2="162" class="net_2 width_1" style="stroke-width: 1"/><line x1="108" x2="148" y1="227" y2="227" class="net_6 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="32" y2="32" class="net_5 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="97" y2="97" class="net_3 width_1" style="stroke-width: 1"/><line x1="178.66666666666666" x2="216" y1="39.5" y2="39.5" class="net_9 width_1" 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y2="69.5" class="net_14 width_1" style="stroke-width: 1"/><line x1="374" x2="409" y1="62" y2="62" class="net_4 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.rst b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.rst
index fe51c2c..a3ac158 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi22_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi22_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi22.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi22_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi22_1 layout**
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.schematic.png b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.schematic.png
deleted file mode 100644
index 29a9b3b..0000000
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_2.rst b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_2.rst
index ae3dda8..dc0d4cb 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_2.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi22_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi22_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi22.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi22_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi22_2 layout**
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_2.schematic.png b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_2.schematic.png
deleted file mode 100644
index 29a9b3b..0000000
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.rst b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.rst
index b893a09..ae1bcdd 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi22_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi22_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi22.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi22_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi22_4 layout**
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.schematic.png b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.schematic.png
deleted file mode 100644
index 29a9b3b..0000000
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi221/definition.json b/cells/aoi221/definition.json
new file mode 100644
index 0000000..920aa2d
--- /dev/null
+++ b/cells/aoi221/definition.json
@@ -0,0 +1,59 @@
+{
+    "description": "two 2-input AND into 3-input NOR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi221",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "aoi221",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "C",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__aoi221"
+}
\ No newline at end of file
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new file mode 100644
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diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_1.rst b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_1.rst
index 08f5f7a..a89fa6c 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_1.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi221_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi221_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi221.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi221_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi221_1 layout**
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_1.schematic.png b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_1.schematic.png
deleted file mode 100644
index c1e6eaa..0000000
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_2.rst b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_2.rst
index 816a179..14d8608 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_2.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi221_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi221_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi221.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi221_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi221_2 layout**
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_2.schematic.png b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_2.schematic.png
deleted file mode 100644
index c1e6eaa..0000000
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.rst b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.rst
index 3f6d7d6..daca93f 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi221_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi221_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi221.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi221_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi221_4 layout**
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.schematic.png b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.schematic.png
deleted file mode 100644
index c1e6eaa..0000000
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi222/definition.json b/cells/aoi222/definition.json
new file mode 100644
index 0000000..0840655
--- /dev/null
+++ b/cells/aoi222/definition.json
@@ -0,0 +1,65 @@
+{
+    "description": "three 2-input AND into 3-input NOR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi222",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "aoi222",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "C1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "C2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__aoi222"
+}
\ No newline at end of file
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222.schematic.svg b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222.schematic.svg
new file mode 100644
index 0000000..90bde54
--- /dev/null
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="777" height="422"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_1.rst b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_1.rst
index 732ed53..bba8f41 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_1.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi222_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi222_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi222.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi222_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi222_1 layout**
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_1.schematic.png b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_1.schematic.png
deleted file mode 100644
index 5c3c1e1..0000000
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_2.rst b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_2.rst
index 583fc54..cd9f4d0 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_2.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi222_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi222_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi222.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi222_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi222_2 layout**
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_2.schematic.png b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_2.schematic.png
deleted file mode 100644
index 5c3c1e1..0000000
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.rst b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.rst
index d535129..690cf84 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi222_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi222_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi222.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__aoi222_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__aoi222_4 layout**
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.schematic.png b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.schematic.png
deleted file mode 100644
index 5c3c1e1..0000000
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/buf/definition.json b/cells/buf/definition.json
new file mode 100644
index 0000000..56b808a
--- /dev/null
+++ b/cells/buf/definition.json
@@ -0,0 +1,35 @@
+{
+    "description": "buffer",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__buf",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "buf",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "I",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__buf"
+}
\ No newline at end of file
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf.schematic.svg b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf.schematic.svg
new file mode 100644
index 0000000..72e18ad
--- /dev/null
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_I"><text x="15" y="-4" class="nodelabel cell_I" s:attribute="ref">I</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_I"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(77,22)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_1.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_1.rst
index 9183461..32b1ee4 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_1.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__buf_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_1 layout**
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_1.schematic.png b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_1.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_12.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_12.rst
index a32e2c8..0a8a637 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_12.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_12.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_x12 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_12.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__buf_x12 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_x12 layout**
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_12.schematic.png b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_12.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_12.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_16.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_16.rst
index 7dd4847..0bfef6e 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_16.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_16.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_x16 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_16.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__buf_x16 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_x16 layout**
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_16.schematic.png b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_16.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_16.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_2.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_2.rst
index 7288e99..738ba88 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_2.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__buf_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_2 layout**
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_2.schematic.png b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_2.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_20.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_20.rst
index adb9384..653e86f 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_20.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_20.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_x20 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_20.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__buf_x20 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_x20 layout**
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_20.schematic.png b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_20.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_20.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_3.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_3.rst
index a62fd9d..216cacb 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_3.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_3.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_3 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_3.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__buf_3 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_3 layout**
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_3.schematic.png b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_3.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_3.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_4.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_4.rst
index 3c8a9ef..c549427 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_4.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__buf_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_4 layout**
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_4.schematic.png b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_4.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_8.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_8.rst
index 76ace19..4a7212f 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_8.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_8.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_8 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_8.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__buf_8 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__buf_8 layout**
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_8.schematic.png b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_8.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_8.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/bufz/definition.json b/cells/bufz/definition.json
new file mode 100644
index 0000000..e8547d9
--- /dev/null
+++ b/cells/bufz/definition.json
@@ -0,0 +1,41 @@
+{
+    "description": "tri-state buffer",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__bufz",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "bufz",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "EN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "I",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__bufz"
+}
\ No newline at end of file
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz.schematic.svg b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz.schematic.svg
new file mode 100644
index 0000000..c8d372b
--- /dev/null
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="239" height="121.5"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(77,29.5)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__bufz.v:26$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__bufz.v:26$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="mux" transform="translate(142,12)" s:width="20" s:height="40" id="cell_$ternary$gf180mcu_fd_sc_mcu7t5v0__bufz.v:0$2"><s:alias val="$pmux"/><s:alias val="$mux"/><s:alias val="$_MUX_"/><path d="M0,0 L20,10 L20,30 L0,40 Z" class="cell_$ternary$gf180mcu_fd_sc_mcu7t5v0__bufz.v:0$2"/><text x="5" y="32" class="nodelabel cell_$ternary$gf180mcu_fd_sc_mcu7t5v0__bufz.v:0$2" s:attribute="">1</text><text x="5" y="13" class="nodelabel cell_$ternary$gf180mcu_fd_sc_mcu7t5v0__bufz.v:0$2" s:attribute="">0</text><g s:x="0" s:y="10" s:pid="A"/><g s:x="0" s:y="30" s:pid="B"/><g s:x="10" s:y="35" s:pid="S"/><g s:x="20" s:y="20" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,24.5)" s:width="30" s:height="20" id="cell_EN"><text x="15" y="-4" class="nodelabel cell_EN" s:attribute="ref">EN</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_EN"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,89.5)" s:width="30" s:height="20" id="cell_I"><text x="15" y="-4" class="nodelabel cell_I" s:attribute="ref">I</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_I"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(197,22)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="34.5" y2="34.5" class="net_2 width_1" style="stroke-width: 1"/><line x1="42" x2="62" y1="34.5" y2="34.5" class="net_2 width_1" style="stroke-width: 1"/><line x1="62" x2="62" y1="34.5" y2="64.5" class="net_2 width_1" style="stroke-width: 1"/><line x1="62" x2="152" y1="64.5" y2="64.5" class="net_2 width_1" style="stroke-width: 1"/><circle cx="62" cy="34.5" r="2" style="fill:#000" class="net_2 width_1"/><line x1="152" x2="152" y1="64.5" y2="47" class="net_2 width_1" style="stroke-width: 1"/><line x1="42" x2="52" y1="99.5" y2="99.5" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="99.5" y2="49.5" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="77" y1="49.5" y2="49.5" class="net_3 width_1" style="stroke-width: 1"/><line x1="107" x2="142" y1="42" y2="42" class="net_5 width_1" style="stroke-width: 1"/><line x1="162" x2="197" y1="32" y2="32" class="net_4 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_1.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_1.rst
index 2970ea4..c24e7d0 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_1.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__bufz_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_1 layout**
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_12.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_12.rst
index d9e093c..f5b0710 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_12.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_12.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_x12 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_12.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__bufz_x12 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_x12 layout**
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_16.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_16.rst
index b57f22f..15795ed 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_16.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_16.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_x16 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_16.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__bufz_x16 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_x16 layout**
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_2.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_2.rst
index 5564937..8b52c2f 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_2.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__bufz_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_2 layout**
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_3.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_3.rst
index 20b23c8..1c78700 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_3.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_3.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_3 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_3.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__bufz_3 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_3 layout**
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_4.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_4.rst
index 15f2b12..b4b21a2 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_4.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__bufz_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_4 layout**
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_8.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_8.rst
index fc4ea63..df863f0 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_8.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_8.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_8 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_8.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__bufz_8 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__bufz_8 layout**
diff --git a/cells/clkbuf/definition.json b/cells/clkbuf/definition.json
new file mode 100644
index 0000000..f8497d4
--- /dev/null
+++ b/cells/clkbuf/definition.json
@@ -0,0 +1,35 @@
+{
+    "description": "clock buffer",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__clkbuf",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "clkbuf",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "I",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__clkbuf"
+}
\ No newline at end of file
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf.schematic.svg b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf.schematic.svg
new file mode 100644
index 0000000..72e18ad
--- /dev/null
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="119" height="54"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_I"><text x="15" y="-4" class="nodelabel cell_I" s:attribute="ref">I</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_I"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(77,22)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.rst
index 539b063..94b20bb 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 layout**
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.schematic.png b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.rst
index ac0e62f..08fab3f 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12 layout**
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.schematic.png b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.rst
index e00e045..8a036ff 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16 layout**
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.schematic.png b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.rst
index 786833b..400727c 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 layout**
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.schematic.png b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_20.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_20.rst
index 59df858..f9ed321 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_20.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_20.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_20.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20 layout**
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_20.schematic.png b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_20.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_20.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.rst
index 49a4f09..ad83032 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 layout**
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.schematic.png b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.rst
index 13d9956..b54b9bf 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 layout**
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.schematic.png b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.rst
index 94f875e..0a5ee3e 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 layout**
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.schematic.png b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkinv/definition.json b/cells/clkinv/definition.json
new file mode 100644
index 0000000..e026702
--- /dev/null
+++ b/cells/clkinv/definition.json
@@ -0,0 +1,35 @@
+{
+    "description": "clock inverter",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__clkinv",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "clkinv",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "I",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__clkinv"
+}
\ No newline at end of file
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv.schematic.svg b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv.schematic.svg
new file mode 100644
index 0000000..aebfaa0
--- /dev/null
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="185" height="54"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__clkinv.v:0$1"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__clkinv.v:0$1"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__clkinv.v:0$1"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_I"><text x="15" y="-4" class="nodelabel cell_I" s:attribute="ref">I</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_I"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(143,22)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="105" x2="143" y1="32" y2="32" class="net_3 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.rst
index 48c1d6f..cec4210 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_1 layout**
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.schematic.png b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_12.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_12.rst
index 9083000..61fc7a4 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_12.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_12.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_x12 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_12.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_x12 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_x12 layout**
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_12.schematic.png b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_12.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_12.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_16.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_16.rst
index e060ae5..d883763 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_16.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_16.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_x16 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_16.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_x16 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_x16 layout**
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_16.schematic.png b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_16.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_16.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.rst
index 7d8cfb5..ace0373 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_2 layout**
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.schematic.png b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_20.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_20.rst
index b0b743a..6a1a3c7 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_20.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_20.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_x20 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_20.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_x20 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_x20 layout**
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_20.schematic.png b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_20.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_20.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.rst
index 3d76d31..1587710 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_3 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_3.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_3 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_3 layout**
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.schematic.png b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.rst
index e8e820c..074662d 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_4 layout**
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.schematic.png b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.rst
index 705ac75..cfa85ba 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_8 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_8.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_8 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__clkinv_8 layout**
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.schematic.png b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dffnq/definition.json b/cells/dffnq/definition.json
new file mode 100644
index 0000000..f643022
--- /dev/null
+++ b/cells/dffnq/definition.json
@@ -0,0 +1,41 @@
+{
+    "description": "negative edge triggered D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dffnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLKN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffnq"
+}
\ No newline at end of file
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq.schematic.svg b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq.schematic.svg
new file mode 100644
index 0000000..5231d02
--- /dev/null
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="359" height="239"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(86,77)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnq.v:0$1"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnq.v:0$1"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnq.v:0$1"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(86,142)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnq.v:0$2"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnq.v:0$2"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnq.v:0$2"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(252,57)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnq.v:0$3"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnq.v:0$3"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnq.v:0$3"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="generic" transform="translate(178,56.5)" s:width="30" s:height="40" id="cell_x0"><text x="15" y="-4" class="nodelabel cell_x0" s:attribute="ref">udp_gf180mcu_fd_sc_mcu7t5v0_tt_25c_1v80_verilog_mgm_n_iq_ff_udp</text><rect width="30" height="100" s:generic="body" class="cell_x0"/><g transform="translate(0,10)" s:x="0" s:y="10" s:pid="in0" id="port_x0~C"><text x="-3" y="-4" class="inputPortLabel cell_x0">C</text></g><g transform="translate(0,30)" s:x="0" s:y="10" s:pid="in0" id="port_x0~CK"><text x="-3" y="-4" class="inputPortLabel cell_x0">CK</text></g><g transform="translate(0,50)" s:x="0" s:y="10" s:pid="in0" id="port_x0~D"><text x="-3" y="-4" class="inputPortLabel cell_x0">D</text></g><g transform="translate(0,70)" s:x="0" s:y="10" s:pid="in0" id="port_x0~N"><text x="-3" y="-4" class="inputPortLabel cell_x0">N</text></g><g transform="translate(0,90)" s:x="0" s:y="10" s:pid="in0" id="port_x0~P"><text x="-3" y="-4" class="inputPortLabel cell_x0">P</text></g><g transform="translate(30,10)" s:x="30" s:y="10" s:pid="out0" id="port_x0~Q"><text x="5" y="-4" style="fill:#000; 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\ No newline at end of file
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_1.rst b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_1.rst
index 13cb7fb..0f58d6d 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_1.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnq_1 layout**
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_2.rst b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_2.rst
index 2531d34..17a4547 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_2.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnq_2 layout**
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_4.rst b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_4.rst
index 39f4524..e220dd3 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_4.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnq_4 layout**
diff --git a/cells/dffnrnq/definition.json b/cells/dffnrnq/definition.json
new file mode 100644
index 0000000..269eb7b
--- /dev/null
+++ b/cells/dffnrnq/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "negative edge triggered D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffnrnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dffnrnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLKN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "RN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffnrnq"
+}
\ No newline at end of file
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq.schematic.svg b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq.schematic.svg
new file mode 100644
index 0000000..b9dbc58
--- /dev/null
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.rst
index 93bba72..5950727 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1 layout**
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2.rst
index 2252208..b5665d5 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2 layout**
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4.rst
index 986554e..67daa13 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4 layout**
diff --git a/cells/dffnrsnq/definition.json b/cells/dffnrsnq/definition.json
new file mode 100644
index 0000000..328307f
--- /dev/null
+++ b/cells/dffnrsnq/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "negative edge triggered D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dffnrsnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLKN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "RN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SETN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq"
+}
\ No newline at end of file
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq.schematic.svg b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq.schematic.svg
new file mode 100644
index 0000000..1fc51cb
--- /dev/null
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
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+  fill:#000;
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\ No newline at end of file
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1.rst
index 0ed0846..9895c9d 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1 layout**
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2.rst
index 4649dd1..24adc89 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2 layout**
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4.rst
index 97f0a1c..5849b10 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4 layout**
diff --git a/cells/dffnsnq/definition.json b/cells/dffnsnq/definition.json
new file mode 100644
index 0000000..f60624c
--- /dev/null
+++ b/cells/dffnsnq/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "negative edge triggered D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffnsnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dffnsnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLKN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SETN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffnsnq"
+}
\ No newline at end of file
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq.schematic.svg b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq.schematic.svg
new file mode 100644
index 0000000..45a88e8
--- /dev/null
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="354" height="314"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(86,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$1"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$1"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$1"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(86,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$2"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$2"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$2"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(86,152)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$3"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$3"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$3"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(247,112)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$4"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$4"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffnsnq.v:0$4"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="generic" transform="translate(173,111.5)" s:width="30" s:height="40" id="cell_x0"><text x="15" y="-4" class="nodelabel cell_x0" s:attribute="ref">udp_gf180mcu_fd_sc_mcu7t5v0_tt_25c_1v80_verilog_mgm_n_iq_ff_udp</text><rect width="30" height="100" s:generic="body" class="cell_x0"/><g transform="translate(0,10)" s:x="0" s:y="10" s:pid="in0" id="port_x0~C"><text x="-3" y="-4" class="inputPortLabel cell_x0">C</text></g><g transform="translate(0,30)" s:x="0" s:y="10" s:pid="in0" id="port_x0~CK"><text x="-3" y="-4" class="inputPortLabel cell_x0">CK</text></g><g transform="translate(0,50)" s:x="0" s:y="10" s:pid="in0" id="port_x0~D"><text x="-3" y="-4" class="inputPortLabel cell_x0">D</text></g><g transform="translate(0,70)" s:x="0" s:y="10" s:pid="in0" id="port_x0~N"><text x="-3" y="-4" class="inputPortLabel cell_x0">N</text></g><g transform="translate(0,90)" s:x="0" s:y="10" s:pid="in0" id="port_x0~P"><text x="-3" y="-4" class="inputPortLabel cell_x0">P</text></g><g transform="translate(30,10)" s:x="30" s:y="10" s:pid="out0" id="port_x0~Q"><text x="5" y="-4" style="fill:#000; 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\ No newline at end of file
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.rst
index 033fbf6..867f749 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1 layout**
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2.rst
index a625f04..b5076b1 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2 layout**
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4.rst
index bdee9f7..c869063 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4 layout**
diff --git a/cells/dffq/definition.json b/cells/dffq/definition.json
new file mode 100644
index 0000000..465a536
--- /dev/null
+++ b/cells/dffq/definition.json
@@ -0,0 +1,41 @@
+{
+    "description": "poistive edge triggered D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dffq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLK",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffq"
+}
\ No newline at end of file
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq.schematic.svg b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq.schematic.svg
new file mode 100644
index 0000000..939ac73
--- /dev/null
+++ b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="354" height="239"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(86,142)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffq.v:0$1"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffq.v:0$1"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffq.v:0$1"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(247,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffq.v:0$2"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffq.v:0$2"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffq.v:0$2"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="generic" transform="translate(173,86.5)" s:width="30" s:height="40" id="cell_x0"><text x="15" y="-4" class="nodelabel cell_x0" s:attribute="ref">udp_gf180mcu_fd_sc_mcu7t5v0_tt_25c_1v80_verilog_mgm_n_iq_ff_udp</text><rect width="30" height="100" s:generic="body" class="cell_x0"/><g transform="translate(0,10)" s:x="0" s:y="10" s:pid="in0" id="port_x0~C"><text x="-3" y="-4" class="inputPortLabel cell_x0">C</text></g><g transform="translate(0,30)" s:x="0" s:y="10" s:pid="in0" id="port_x0~CK"><text x="-3" y="-4" class="inputPortLabel cell_x0">CK</text></g><g transform="translate(0,50)" s:x="0" s:y="10" s:pid="in0" id="port_x0~D"><text x="-3" y="-4" class="inputPortLabel cell_x0">D</text></g><g transform="translate(0,70)" s:x="0" s:y="10" s:pid="in0" id="port_x0~N"><text x="-3" y="-4" class="inputPortLabel cell_x0">N</text></g><g transform="translate(0,90)" s:x="0" s:y="10" s:pid="in0" id="port_x0~P"><text x="-3" y="-4" class="inputPortLabel cell_x0">P</text></g><g transform="translate(30,10)" s:x="30" s:y="10" s:pid="out0" id="port_x0~Q"><text x="5" y="-4" style="fill:#000; stroke:none" class="cell_x0">Q</text></g></g><g s:type="inputExt" transform="translate(77,22)" s:width="30" s:height="20" id="cell_CLK"><text x="15" y="-4" class="nodelabel cell_CLK" s:attribute="ref">CLK</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_CLK"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,142)" s:width="30" s:height="20" id="cell_D"><text x="15" y="-4" class="nodelabel cell_D" s:attribute="ref">D</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_D"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(312,87)" s:width="30" s:height="20" id="cell_Q"><text x="15" y="-4" class="nodelabel cell_Q" s:attribute="ref">Q</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Q"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(77,207)" s:width="30" s:height="20" id="cell_notifier"><text x="15" y="-4" class="nodelabel cell_notifier" s:attribute="ref">notifier</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_notifier"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="constant" transform="translate(77,87)" s:width="30" s:height="20" id="cell_0"><text x="15" y="-4" class="nodelabel cell_0" s:attribute="ref">0</text><s:alias val="$_constant_"/><rect width="30" height="20" class="cell_0"/><g s:x="31" s:y="10" s:pid="Y"/></g><line x1="42" x2="85" y1="152" y2="152" class="net_3 width_1" style="stroke-width: 1"/><line x1="204" x2="246" y1="97" y2="97" class="net_7 width_1" style="stroke-width: 1"/><line x1="108" x2="173" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="108" x2="135" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="97" y2="177" class="net_8 width_1" style="stroke-width: 1"/><circle cx="135" cy="97" r="2" style="fill:#000" class="net_8 width_1"/><line x1="135" x2="173" y1="177" y2="177" class="net_8 width_1" style="stroke-width: 1"/><line x1="107" x2="145" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="32" y2="117" class="net_2 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="117" y2="117" class="net_2 width_1" style="stroke-width: 1"/><line x1="113" x2="145" y1="152" y2="152" class="net_6 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="152" y2="137" class="net_6 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="137" y2="137" class="net_6 width_1" style="stroke-width: 1"/><line x1="107" x2="145" y1="217" y2="217" class="net_5 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="217" y2="157" class="net_5 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="157" y2="157" class="net_5 width_1" style="stroke-width: 1"/><line x1="274" x2="312" y1="97" y2="97" class="net_4 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_1.rst b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_1.rst
index 104ecbe..01634ed 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_1.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffq_1 layout**
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_2.rst b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_2.rst
index 9f6b5ff..6659c12 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_2.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffq_2 layout**
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_4.rst b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_4.rst
index 950829d..a598da4 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_4.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffq_4 layout**
diff --git a/cells/dffrnq/definition.json b/cells/dffrnq/definition.json
new file mode 100644
index 0000000..1e3fa6c
--- /dev/null
+++ b/cells/dffrnq/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "positive edge triggered D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffrnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dffrnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLK",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "RN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffrnq"
+}
\ No newline at end of file
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq.schematic.svg b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq.schematic.svg
new file mode 100644
index 0000000..0511f03
--- /dev/null
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="354" height="294"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(86,262)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffrnq.v:0$1"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffrnq.v:0$1"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffrnq.v:0$1"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(86,142)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffrnq.v:0$2"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffrnq.v:0$2"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffrnq.v:0$2"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(247,102)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffrnq.v:0$3"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffrnq.v:0$3"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__dffrnq.v:0$3"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="generic" transform="translate(173,101.5)" s:width="30" s:height="40" id="cell_x0"><text x="15" y="-4" class="nodelabel cell_x0" s:attribute="ref">udp_gf180mcu_fd_sc_mcu7t5v0_tt_25c_1v80_verilog_mgm_n_iq_ff_udp</text><rect width="30" height="100" s:generic="body" class="cell_x0"/><g transform="translate(0,10)" s:x="0" s:y="10" s:pid="in0" id="port_x0~C"><text x="-3" y="-4" class="inputPortLabel cell_x0">C</text></g><g transform="translate(0,30)" s:x="0" s:y="10" s:pid="in0" id="port_x0~CK"><text x="-3" y="-4" class="inputPortLabel cell_x0">CK</text></g><g transform="translate(0,50)" s:x="0" s:y="10" s:pid="in0" id="port_x0~D"><text x="-3" y="-4" class="inputPortLabel cell_x0">D</text></g><g transform="translate(0,70)" s:x="0" s:y="10" s:pid="in0" id="port_x0~N"><text x="-3" y="-4" class="inputPortLabel cell_x0">N</text></g><g transform="translate(0,90)" s:x="0" s:y="10" s:pid="in0" id="port_x0~P"><text x="-3" y="-4" class="inputPortLabel cell_x0">P</text></g><g transform="translate(30,10)" s:x="30" s:y="10" s:pid="out0" id="port_x0~Q"><text x="5" y="-4" style="fill:#000; stroke:none" class="cell_x0">Q</text></g></g><g s:type="inputExt" transform="translate(77,87)" s:width="30" s:height="20" id="cell_CLK"><text x="15" y="-4" class="nodelabel cell_CLK" s:attribute="ref">CLK</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_CLK"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,142)" s:width="30" s:height="20" id="cell_D"><text x="15" y="-4" class="nodelabel cell_D" s:attribute="ref">D</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_D"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,262)" s:width="30" s:height="20" id="cell_RN"><text x="15" y="-4" class="nodelabel cell_RN" s:attribute="ref">RN</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_RN"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(312,102)" s:width="30" s:height="20" id="cell_Q"><text x="15" y="-4" class="nodelabel cell_Q" s:attribute="ref">Q</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Q"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(77,207)" s:width="30" s:height="20" id="cell_notifier"><text x="15" y="-4" class="nodelabel cell_notifier" s:attribute="ref">notifier</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_notifier"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="constant" transform="translate(77,22)" s:width="30" s:height="20" id="cell_0"><text x="15" y="-4" class="nodelabel cell_0" s:attribute="ref">0</text><s:alias val="$_constant_"/><rect width="30" height="20" class="cell_0"/><g s:x="31" s:y="10" s:pid="Y"/></g><line x1="42" x2="85" y1="272" y2="272" class="net_4 width_1" style="stroke-width: 1"/><line x1="42" x2="85" y1="152" y2="152" class="net_3 width_1" style="stroke-width: 1"/><line x1="204" x2="246" y1="112" y2="112" class="net_9 width_1" style="stroke-width: 1"/><line x1="108" x2="145" y1="32" y2="32" class="net_10 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="32" y2="112" class="net_10 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="112" y2="112" class="net_10 width_1" style="stroke-width: 1"/><line x1="107" x2="135" y1="97" y2="97" class="net_2 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="97" y2="132" class="net_2 width_1" style="stroke-width: 1"/><line x1="135" x2="173" y1="132" y2="132" class="net_2 width_1" style="stroke-width: 1"/><line x1="113" x2="173" y1="152" y2="152" class="net_8 width_1" style="stroke-width: 1"/><line x1="107" x2="135" y1="217" y2="217" class="net_6 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="217" y2="172" class="net_6 width_1" style="stroke-width: 1"/><line x1="135" x2="173" y1="172" y2="172" class="net_6 width_1" style="stroke-width: 1"/><line x1="113" x2="145" y1="272" y2="272" class="net_7 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="272" y2="192" class="net_7 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="192" y2="192" class="net_7 width_1" style="stroke-width: 1"/><line x1="274" x2="312" y1="112" y2="112" class="net_5 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.rst
index 95f3a30..b3747a1 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 layout**
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.rst
index 76e2518..c863429 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffrnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrnq_2 layout**
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_4.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_4.rst
index 1f212b1..46f56a4 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_4.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffrnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrnq_4 layout**
diff --git a/cells/dffrsnq/definition.json b/cells/dffrsnq/definition.json
new file mode 100644
index 0000000..0768fad
--- /dev/null
+++ b/cells/dffrsnq/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "positive edge triggered D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffrsnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dffrsnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLK",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "RN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SETN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffrsnq"
+}
\ No newline at end of file
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq.schematic.svg b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq.schematic.svg
new file mode 100644
index 0000000..8dfe8a3
--- /dev/null
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="354" height="294"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
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+  text-anchor: end;
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+  fill:#000;
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\ No newline at end of file
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1.rst
index 283a7e9..3fe7be8 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1 layout**
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2.rst
index 4d2f878..2dda73e 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2 layout**
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4.rst
index 64e8151..6265814 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4 layout**
diff --git a/cells/dffsnq/definition.json b/cells/dffsnq/definition.json
new file mode 100644
index 0000000..ec33723
--- /dev/null
+++ b/cells/dffsnq/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "positive edge triggered D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffsnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dffsnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLK",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SETN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffsnq"
+}
\ No newline at end of file
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq.schematic.svg b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq.schematic.svg
new file mode 100644
index 0000000..8d51a1b
--- /dev/null
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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\ No newline at end of file
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.rst
index 7508280..ec669ab 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 layout**
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_2.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_2.rst
index 444c613..def03cb 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_2.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffsnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffsnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffsnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffsnq_2 layout**
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.rst
index 200fd30..bbe9f21 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dffsnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dffsnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dffsnq_4 layout**
diff --git a/cells/dlya/definition.json b/cells/dlya/definition.json
new file mode 100644
index 0000000..35f3b09
--- /dev/null
+++ b/cells/dlya/definition.json
@@ -0,0 +1,35 @@
+{
+    "description": "2 buffer delay cell",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dlya",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dlya",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "I",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dlya"
+}
\ No newline at end of file
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya.schematic.svg b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya.schematic.svg
new file mode 100644
index 0000000..72e18ad
--- /dev/null
+++ b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="119" height="54"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_I"><text x="15" y="-4" class="nodelabel cell_I" s:attribute="ref">I</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_I"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(77,22)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_1.rst b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_1.rst
index a0d0054..af37811 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_1.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlya_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlya_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlya.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlya_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlya_1 layout**
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_1.schematic.png b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_1.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_2.rst b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_2.rst
index 1e1e2dc..da837af 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_2.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlya_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlya_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlya.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlya_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlya_2 layout**
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_2.schematic.png b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_2.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_4.rst b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_4.rst
index 2c7b186..43a0c2e 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_4.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlya_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlya_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlya.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlya_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlya_4 layout**
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_4.schematic.png b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_4.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dlyb/definition.json b/cells/dlyb/definition.json
new file mode 100644
index 0000000..25e76e3
--- /dev/null
+++ b/cells/dlyb/definition.json
@@ -0,0 +1,35 @@
+{
+    "description": "4 buffer delay cell",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dlyb",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dlyb",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "I",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dlyb"
+}
\ No newline at end of file
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb.schematic.svg b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb.schematic.svg
new file mode 100644
index 0000000..72e18ad
--- /dev/null
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="119" height="54"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_I"><text x="15" y="-4" class="nodelabel cell_I" s:attribute="ref">I</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_I"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(77,22)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_1.rst b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_1.rst
index f2d8e0a..0fc284e 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_1.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyb_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyb_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyb.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlyb_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyb_1 layout**
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_1.schematic.png b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_1.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_2.rst b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_2.rst
index c4961a1..1dd9e0b 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_2.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyb_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyb_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyb.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlyb_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyb_2 layout**
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_2.schematic.png b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_2.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.rst b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.rst
index 1799f38..f32a912 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyb_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyb_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyb.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlyb_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyb_4 layout**
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.schematic.png b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dlyc/definition.json b/cells/dlyc/definition.json
new file mode 100644
index 0000000..516977e
--- /dev/null
+++ b/cells/dlyc/definition.json
@@ -0,0 +1,35 @@
+{
+    "description": "8 buffer delay cell",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dlyc",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dlyc",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "I",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dlyc"
+}
\ No newline at end of file
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc.schematic.svg b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc.schematic.svg
new file mode 100644
index 0000000..72e18ad
--- /dev/null
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="119" height="54"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_I"><text x="15" y="-4" class="nodelabel cell_I" s:attribute="ref">I</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_I"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(77,22)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_1.rst b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_1.rst
index 5542380..890c806 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_1.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyc_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyc_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyc.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlyc_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyc_1 layout**
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_1.schematic.png b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_1.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_2.rst b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_2.rst
index eb1893c..ae385fe 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_2.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyc_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyc_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyc.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlyc_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyc_2 layout**
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_2.schematic.png b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_2.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_4.rst b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_4.rst
index e450d83..a14bdae 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_4.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyc_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyc_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyc.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlyc_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyc_4 layout**
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_4.schematic.png b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_4.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dlyd/definition.json b/cells/dlyd/definition.json
new file mode 100644
index 0000000..b4f11b8
--- /dev/null
+++ b/cells/dlyd/definition.json
@@ -0,0 +1,35 @@
+{
+    "description": "16 buffer delay cell",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dlyd",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "dlyd",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "I",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dlyd"
+}
\ No newline at end of file
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd.schematic.svg b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd.schematic.svg
new file mode 100644
index 0000000..72e18ad
--- /dev/null
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="119" height="54"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_I"><text x="15" y="-4" class="nodelabel cell_I" s:attribute="ref">I</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_I"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(77,22)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_1.rst b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_1.rst
index 06bf228..9895f75 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_1.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyd_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyd_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyd.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlyd_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyd_1 layout**
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_1.schematic.png b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_1.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_2.rst b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_2.rst
index 7387e18..bbaa644 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_2.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyd_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyd_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyd.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlyd_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyd_2 layout**
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_2.schematic.png b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_2.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_4.rst b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_4.rst
index 86903cf..c2bca69 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_4.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyd_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyd_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyd.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__dlyd_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__dlyd_4 layout**
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_4.schematic.png b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_4.schematic.png
deleted file mode 100644
index fb243ea..0000000
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/endcap/definition.json b/cells/endcap/definition.json
new file mode 100644
index 0000000..061d34a
--- /dev/null
+++ b/cells/endcap/definition.json
@@ -0,0 +1,23 @@
+{
+    "description": "row end closure cell",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__endcap",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "endcap",
+    "parameters": [],
+    "ports": [
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__endcap"
+}
\ No newline at end of file
diff --git a/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst b/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst
index aadaf74..ad701ee 100644
--- a/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst
+++ b/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__endcap schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__endcap.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__endcap.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__endcap schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__endcap layout**
diff --git a/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.schematic.svg b/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.schematic.svg
new file mode 100644
index 0000000..f8b5edc
--- /dev/null
+++ b/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="0" height="0"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style></svg>
\ No newline at end of file
diff --git a/cells/fill/definition.json b/cells/fill/definition.json
new file mode 100644
index 0000000..3677f8e
--- /dev/null
+++ b/cells/fill/definition.json
@@ -0,0 +1,23 @@
+{
+    "description": "filler whose cell width is 0.56um",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__fill",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "fill",
+    "parameters": [],
+    "ports": [
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__fill"
+}
\ No newline at end of file
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg
new file mode 100644
index 0000000..f8b5edc
--- /dev/null
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="0" height="0"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style></svg>
\ No newline at end of file
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_1.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_1.rst
index 3646f9f..c006bcc 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_1.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fill_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_1 layout**
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_16.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_16.rst
index 5086f3e..f9c173b 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_16.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_16.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_x16 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_16.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fill_x16 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_x16 layout**
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_2.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_2.rst
index 525466c..b82659e 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_2.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fill_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_2 layout**
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_32.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_32.rst
index 14f74d9..e3dcb3e 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_32.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_32.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_x32 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_32.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fill_x32 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_x32 layout**
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_4.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_4.rst
index 9ed0a14..024985d 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_4.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fill_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_4 layout**
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_64.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_64.rst
index 6cd0485..cd3e4b0 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_64.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_64.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_x64 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_64.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fill_x64 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_x64 layout**
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_8.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_8.rst
index b153637..f535870 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_8.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_8.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_8 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_8.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fill_8 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fill_8 layout**
diff --git a/cells/fillcap/definition.json b/cells/fillcap/definition.json
new file mode 100644
index 0000000..a7e3a2e
--- /dev/null
+++ b/cells/fillcap/definition.json
@@ -0,0 +1,23 @@
+{
+    "description": "filler whose cell width is 35.84um",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__fillcap",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "fillcap",
+    "parameters": [],
+    "ports": [
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__fillcap"
+}
\ No newline at end of file
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap.schematic.svg b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap.schematic.svg
new file mode 100644
index 0000000..f8b5edc
--- /dev/null
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="0" height="0"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style></svg>
\ No newline at end of file
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.rst
index 26f77a4..31b7b7e 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fillcap_x16 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap_16.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fillcap_x16 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fillcap_x16 layout**
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.rst
index 8f72ba6..9a5c2f6 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fillcap_x32 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap_32.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fillcap_x32 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fillcap_x32 layout**
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.rst
index 7a2575b..9bacf56 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fillcap_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fillcap_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fillcap_4 layout**
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.rst
index 31c8a95..bb00384 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fillcap_x64 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap_64.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fillcap_x64 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fillcap_x64 layout**
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.rst
index 605946e..d45e049 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__fillcap_8 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap_8.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__fillcap_8 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__fillcap_8 layout**
diff --git a/cells/filltie/definition.json b/cells/filltie/definition.json
new file mode 100644
index 0000000..e003680
--- /dev/null
+++ b/cells/filltie/definition.json
@@ -0,0 +1,23 @@
+{
+    "description": "filler",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__filltie",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "filltie",
+    "parameters": [],
+    "ports": [
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__filltie"
+}
\ No newline at end of file
diff --git a/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst b/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst
index bb7b4ee..95bde50 100644
--- a/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst
+++ b/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__filltie schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__filltie.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__filltie.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__filltie schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__filltie layout**
diff --git a/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.schematic.svg b/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.schematic.svg
new file mode 100644
index 0000000..f8b5edc
--- /dev/null
+++ b/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="0" height="0"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style></svg>
\ No newline at end of file
diff --git a/cells/hold/definition.json b/cells/hold/definition.json
new file mode 100644
index 0000000..06fc1b7
--- /dev/null
+++ b/cells/hold/definition.json
@@ -0,0 +1,23 @@
+{
+    "description": "state holder cell",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__hold",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "hold",
+    "parameters": [],
+    "ports": [
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__hold"
+}
\ No newline at end of file
diff --git a/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst b/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst
index c04c6a0..931ee51 100644
--- a/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst
+++ b/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__hold schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__hold.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__hold.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__hold schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__hold layout**
diff --git a/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.schematic.svg b/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.schematic.svg
new file mode 100644
index 0000000..f8b5edc
--- /dev/null
+++ b/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="0" height="0"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style></svg>
\ No newline at end of file
diff --git a/cells/icgtn/definition.json b/cells/icgtn/definition.json
new file mode 100644
index 0000000..1e7fe70
--- /dev/null
+++ b/cells/icgtn/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "negative-edge triggered clock-gating latch",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__icgtn",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "icgtn",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLKN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "E",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "TE",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__icgtn"
+}
\ No newline at end of file
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn.schematic.svg b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn.schematic.svg
new file mode 100644
index 0000000..d77e111
--- /dev/null
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="424" height="244"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(252,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__icgtn.v:0$3"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__icgtn.v:0$3"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__icgtn.v:0$3"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(83,142)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__icgtn.v:22$1"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__icgtn.v:22$1"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(317,27)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__icgtn.v:30$2"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__icgtn.v:30$2"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="generic" transform="translate(178,86.5)" s:width="30" s:height="40" id="cell_x0"><text x="15" y="-4" class="nodelabel cell_x0" s:attribute="ref">udp_gf180mcu_fd_sc_mcu7t5v0_tt_25c_1v80_verilog_mgm_n_iq_latch_udp</text><rect width="30" height="100" s:generic="body" class="cell_x0"/><g transform="translate(0,10)" s:x="0" s:y="10" s:pid="in0" id="port_x0~C"><text x="-3" y="-4" class="inputPortLabel cell_x0">C</text></g><g transform="translate(0,30)" s:x="0" s:y="10" s:pid="in0" id="port_x0~CK"><text x="-3" y="-4" class="inputPortLabel cell_x0">CK</text></g><g transform="translate(0,50)" s:x="0" s:y="10" s:pid="in0" id="port_x0~D"><text x="-3" y="-4" class="inputPortLabel cell_x0">D</text></g><g transform="translate(0,70)" s:x="0" s:y="10" s:pid="in0" id="port_x0~N"><text x="-3" y="-4" class="inputPortLabel cell_x0">N</text></g><g transform="translate(0,90)" s:x="0" s:y="10" s:pid="in0" id="port_x0~P"><text x="-3" y="-4" class="inputPortLabel cell_x0">P</text></g><g transform="translate(30,10)" s:x="30" s:y="10" s:pid="out0" id="port_x0~Q"><text x="5" y="-4" style="fill:#000; stroke:none" class="cell_x0">Q</text></g></g><g s:type="inputExt" transform="translate(12,202)" s:width="30" s:height="20" id="cell_TE"><text x="15" y="-4" class="nodelabel cell_TE" s:attribute="ref">TE</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_TE"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,137)" s:width="30" s:height="20" id="cell_E"><text x="15" y="-4" class="nodelabel cell_E" s:attribute="ref">E</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_E"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(77,22)" s:width="30" s:height="20" id="cell_CLKN"><text x="15" y="-4" class="nodelabel cell_CLKN" s:attribute="ref">CLKN</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_CLKN"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(382,29.5)" s:width="30" s:height="20" id="cell_Q"><text x="15" y="-4" class="nodelabel cell_Q" s:attribute="ref">Q</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Q"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(77,212)" s:width="30" s:height="20" id="cell_notifier"><text x="15" y="-4" class="nodelabel cell_notifier" s:attribute="ref">notifier</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_notifier"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="constant" transform="translate(77,87)" s:width="30" s:height="20" id="cell_0"><text x="15" y="-4" class="nodelabel cell_0" s:attribute="ref">0</text><s:alias val="$_constant_"/><rect width="30" height="20" class="cell_0"/><g s:x="31" s:y="10" s:pid="Y"/></g><line x1="209" x2="251" y1="97" y2="97" class="net_7 width_1" style="stroke-width: 1"/><line x1="42" x2="85" y1="147" y2="147" class="net_3 width_1" style="stroke-width: 1"/><line x1="42" x2="52" y1="212" y2="212" class="net_2 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="212" y2="162" class="net_2 width_1" style="stroke-width: 1"/><line x1="52" x2="85" y1="162" y2="162" class="net_2 width_1" style="stroke-width: 1"/><line x1="107" x2="319" y1="32" y2="32" class="net_4 width_1" style="stroke-width: 1"/><line x1="107" x2="145" y1="32" y2="32" class="net_4 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="32" y2="117" class="net_4 width_1" style="stroke-width: 1"/><circle cx="145" cy="32" r="2" style="fill:#000" class="net_4 width_1"/><line x1="145" x2="178" y1="117" y2="117" class="net_4 width_1" style="stroke-width: 1"/><line x1="279" x2="292" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="292" x2="292" y1="97" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="292" x2="319" y1="47" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="108" x2="178" y1="97" y2="97" class="net_10 width_1" style="stroke-width: 1"/><line x1="108" x2="135" y1="97" y2="97" class="net_10 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="97" y2="177" class="net_10 width_1" style="stroke-width: 1"/><circle cx="135" cy="97" r="2" style="fill:#000" class="net_10 width_1"/><line x1="135" x2="178" y1="177" y2="177" class="net_10 width_1" style="stroke-width: 1"/><line x1="113" x2="145" y1="154.5" y2="154.5" class="net_9 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="154.5" y2="137" class="net_9 width_1" style="stroke-width: 1"/><line x1="145" x2="178" y1="137" y2="137" class="net_9 width_1" style="stroke-width: 1"/><line x1="107" x2="155" y1="222" y2="222" class="net_6 width_1" style="stroke-width: 1"/><line x1="155" x2="155" y1="222" y2="157" class="net_6 width_1" style="stroke-width: 1"/><line x1="155" x2="178" y1="157" y2="157" class="net_6 width_1" style="stroke-width: 1"/><line x1="347" x2="382" y1="39.5" y2="39.5" class="net_5 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_1.rst b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_1.rst
index df35c69..a035e9e 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_1.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtn_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtn_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtn.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__icgtn_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtn_1 layout**
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_2.rst b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_2.rst
index 300be75..ec334c4 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_2.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtn_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtn_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtn.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__icgtn_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtn_2 layout**
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_4.rst b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_4.rst
index f79c60d..2b70649 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_4.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtn_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtn_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtn.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__icgtn_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtn_4 layout**
diff --git a/cells/icgtp/definition.json b/cells/icgtp/definition.json
new file mode 100644
index 0000000..2eea2ef
--- /dev/null
+++ b/cells/icgtp/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "positive-edge triggered clock-gating latch",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__icgtp",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "icgtp",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLK",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "E",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "TE",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__icgtp"
+}
\ No newline at end of file
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp.schematic.svg b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp.schematic.svg
new file mode 100644
index 0000000..8ca4641
--- /dev/null
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="358" height="245"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(251,78)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__icgtp.v:28$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__icgtp.v:28$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(86,23)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__icgtp.v:0$3"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__icgtp.v:0$3"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__icgtp.v:0$3"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(83.33333333333333,143)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__icgtp.v:24$1"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__icgtp.v:24$1"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="generic" transform="translate(178,87.5)" s:width="30" s:height="40" id="cell_x0"><text x="15" y="-4" class="nodelabel cell_x0" s:attribute="ref">udp_gf180mcu_fd_sc_mcu7t5v0_tt_25c_1v80_verilog_mgm_n_iq_latch_udp</text><rect width="30" height="100" s:generic="body" class="cell_x0"/><g transform="translate(0,10)" s:x="0" s:y="10" s:pid="in0" id="port_x0~C"><text x="-3" y="-4" class="inputPortLabel cell_x0">C</text></g><g transform="translate(0,30)" s:x="0" s:y="10" s:pid="in0" id="port_x0~CK"><text x="-3" y="-4" class="inputPortLabel cell_x0">CK</text></g><g transform="translate(0,50)" s:x="0" s:y="10" s:pid="in0" id="port_x0~D"><text x="-3" y="-4" class="inputPortLabel cell_x0">D</text></g><g transform="translate(0,70)" s:x="0" s:y="10" s:pid="in0" id="port_x0~N"><text x="-3" y="-4" class="inputPortLabel cell_x0">N</text></g><g transform="translate(0,90)" s:x="0" s:y="10" s:pid="in0" id="port_x0~P"><text x="-3" y="-4" class="inputPortLabel cell_x0">P</text></g><g transform="translate(30,10)" s:x="30" s:y="10" s:pid="out0" id="port_x0~Q"><text x="5" y="-4" style="fill:#000; stroke:none" class="cell_x0">Q</text></g></g><g s:type="inputExt" transform="translate(12,153)" s:width="30" s:height="20" id="cell_TE"><text x="15" y="-4" class="nodelabel cell_TE" s:attribute="ref">TE</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_TE"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,88)" s:width="30" s:height="20" id="cell_E"><text x="15" y="-4" class="nodelabel cell_E" s:attribute="ref">E</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_E"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,23)" s:width="30" s:height="20" id="cell_CLK"><text x="15" y="-4" class="nodelabel cell_CLK" s:attribute="ref">CLK</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_CLK"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(316,80.5)" s:width="30" s:height="20" id="cell_Q"><text x="15" y="-4" class="nodelabel cell_Q" s:attribute="ref">Q</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Q"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(77,213)" s:width="30" s:height="20" id="cell_notifier"><text x="15" y="-4" class="nodelabel cell_notifier" s:attribute="ref">notifier</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_notifier"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="constant" transform="translate(77,88)" s:width="30" s:height="20" id="cell_0"><text x="15" y="-4" class="nodelabel cell_0" s:attribute="ref">0</text><s:alias val="$_constant_"/><rect width="30" height="20" class="cell_0"/><g s:x="31" s:y="10" s:pid="Y"/></g><line x1="42" x2="52" y1="33" y2="33" class="net_4 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="33" y2="12" class="net_4 width_1" style="stroke-width: 1"/><line x1="52" x2="226" y1="12" y2="12" class="net_4 width_1" style="stroke-width: 1"/><line x1="226" x2="226" y1="12" y2="83" class="net_4 width_1" style="stroke-width: 1"/><circle cx="52" cy="33" r="2" style="fill:#000" class="net_4 width_1"/><line x1="226" x2="251" y1="83" y2="83" class="net_4 width_1" style="stroke-width: 1"/><line x1="42" x2="85" y1="33" y2="33" class="net_4 width_1" style="stroke-width: 1"/><line x1="209" x2="251" y1="98" y2="98" class="net_7 width_1" style="stroke-width: 1"/><line x1="42" x2="52" y1="98" y2="98" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="98" y2="148" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="85.33333333333333" y1="148" y2="148" class="net_3 width_1" style="stroke-width: 1"/><line x1="42" x2="85.33333333333333" y1="163" y2="163" class="net_2 width_1" style="stroke-width: 1"/><line x1="108" x2="178" y1="98" y2="98" class="net_10 width_1" style="stroke-width: 1"/><line x1="108" x2="135" y1="98" y2="98" class="net_10 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="98" y2="178" class="net_10 width_1" style="stroke-width: 1"/><circle cx="135" cy="98" r="2" style="fill:#000" class="net_10 width_1"/><line x1="135" x2="178" y1="178" y2="178" class="net_10 width_1" style="stroke-width: 1"/><line x1="113" x2="145" y1="33" y2="33" class="net_8 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="33" y2="118" class="net_8 width_1" style="stroke-width: 1"/><line x1="145" x2="178" y1="118" y2="118" class="net_8 width_1" style="stroke-width: 1"/><line x1="113.33333333333333" x2="145" y1="155.5" y2="155.5" class="net_9 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="155.5" y2="138" class="net_9 width_1" style="stroke-width: 1"/><line x1="145" x2="178" y1="138" y2="138" class="net_9 width_1" style="stroke-width: 1"/><line x1="107" x2="155" y1="223" y2="223" class="net_6 width_1" style="stroke-width: 1"/><line x1="155" x2="155" y1="223" y2="158" class="net_6 width_1" style="stroke-width: 1"/><line x1="155" x2="178" y1="158" y2="158" class="net_6 width_1" style="stroke-width: 1"/><line x1="281" x2="316" y1="90.5" y2="90.5" class="net_5 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_1.rst b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_1.rst
index 718b430..c58f2de 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_1.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtp_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtp_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtp.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__icgtp_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtp_1 layout**
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_2.rst b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_2.rst
index 1d3d551..8c5d25b 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_2.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtp_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtp_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtp.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__icgtp_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtp_2 layout**
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_4.rst b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_4.rst
index 439f3d0..c6ce7e8 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_4.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtp_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtp_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtp.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__icgtp_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__icgtp_4 layout**
diff --git a/cells/inv/definition.json b/cells/inv/definition.json
new file mode 100644
index 0000000..03b6e66
--- /dev/null
+++ b/cells/inv/definition.json
@@ -0,0 +1,35 @@
+{
+    "description": "inverter",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__inv",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "inv",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "I",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__inv"
+}
\ No newline at end of file
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv.schematic.svg b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv.schematic.svg
new file mode 100644
index 0000000..1d5516c
--- /dev/null
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="185" height="54"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__inv.v:0$1"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__inv.v:0$1"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__inv.v:0$1"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_I"><text x="15" y="-4" class="nodelabel cell_I" s:attribute="ref">I</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_I"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(143,22)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="105" x2="143" y1="32" y2="32" class="net_3 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_1.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_1.rst
index 8c42d7c..1b736ed 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_1.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__inv_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_1 layout**
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_1.schematic.png b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_1.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_12.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_12.rst
index cb3d840..e6c1867 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_12.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_12.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_x12 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_12.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__inv_x12 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_x12 layout**
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_12.schematic.png b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_12.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_12.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_16.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_16.rst
index 6876e4d..e74388a 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_16.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_16.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_x16 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_16.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__inv_x16 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_x16 layout**
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_16.schematic.png b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_16.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_16.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_2.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_2.rst
index 44f2539..0c55947 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_2.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__inv_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_2 layout**
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_2.schematic.png b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_2.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_20.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_20.rst
index c4820ea..0082774 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_20.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_20.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_x20 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_20.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__inv_x20 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_x20 layout**
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_20.schematic.png b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_20.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_20.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_3.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_3.rst
index 36fc0c1..495b630 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_3.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_3.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_3 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_3.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__inv_3 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_3 layout**
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_3.schematic.png b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_3.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_3.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_4.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_4.rst
index 0f5c694..d2da006 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_4.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__inv_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_4 layout**
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_4.schematic.png b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_4.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_8.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_8.rst
index bd6992d..295a0ed 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_8.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_8.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_8 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_8.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__inv_8 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__inv_8 layout**
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_8.schematic.png b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_8.schematic.png
deleted file mode 100644
index 68f2c8b..0000000
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_8.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/invz/definition.json b/cells/invz/definition.json
new file mode 100644
index 0000000..3a54018
--- /dev/null
+++ b/cells/invz/definition.json
@@ -0,0 +1,41 @@
+{
+    "description": "tri-state inverter",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__invz",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "invz",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "EN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "I",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__invz"
+}
\ No newline at end of file
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz.schematic.svg b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz.schematic.svg
new file mode 100644
index 0000000..8babacf
--- /dev/null
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="305" height="121.5"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(143,29.5)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__invz.v:30$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__invz.v:30$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,24.5)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__invz.v:0$3"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__invz.v:0$3"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__invz.v:0$3"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="mux" transform="translate(208,12)" s:width="20" s:height="40" id="cell_$ternary$gf180mcu_fd_sc_mcu7t5v0__invz.v:0$2"><s:alias val="$pmux"/><s:alias val="$mux"/><s:alias val="$_MUX_"/><path d="M0,0 L20,10 L20,30 L0,40 Z" class="cell_$ternary$gf180mcu_fd_sc_mcu7t5v0__invz.v:0$2"/><text x="5" y="32" class="nodelabel cell_$ternary$gf180mcu_fd_sc_mcu7t5v0__invz.v:0$2" s:attribute="">1</text><text x="5" y="13" class="nodelabel cell_$ternary$gf180mcu_fd_sc_mcu7t5v0__invz.v:0$2" s:attribute="">0</text><g s:x="0" s:y="10" s:pid="A"/><g s:x="0" s:y="30" s:pid="B"/><g s:x="10" s:y="35" s:pid="S"/><g s:x="20" s:y="20" s:pid="Y"/></g><g s:type="inputExt" transform="translate(78,89.5)" s:width="30" s:height="20" id="cell_EN"><text x="15" y="-4" class="nodelabel cell_EN" s:attribute="ref">EN</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_EN"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(263,22)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(12,24.5)" s:width="30" s:height="20" id="cell_I"><text x="15" y="-4" class="nodelabel cell_I" s:attribute="ref">I</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_I"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="105" x2="143" y1="34.5" y2="34.5" class="net_5 width_1" style="stroke-width: 1"/><line x1="108" x2="118" y1="99.5" y2="99.5" class="net_2 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="99.5" y2="49.5" class="net_2 width_1" style="stroke-width: 1"/><circle cx="118" cy="99.5" r="2" style="fill:#000" class="net_2 width_1"/><line x1="118" x2="143" y1="49.5" y2="49.5" class="net_2 width_1" style="stroke-width: 1"/><line x1="108" x2="218" y1="99.5" y2="99.5" class="net_2 width_1" style="stroke-width: 1"/><line x1="218" x2="218" y1="99.5" y2="47" class="net_2 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="34.5" y2="34.5" class="net_4 width_1" style="stroke-width: 1"/><line x1="173" x2="208" y1="42" y2="42" class="net_6 width_1" style="stroke-width: 1"/><line x1="228" x2="263" y1="32" y2="32" class="net_3 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_1.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_1.rst
index 57d69c3..dca4feb 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_1.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__invz_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_1 layout**
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_12.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_12.rst
index 8021ce2..1f29652 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_12.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_12.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_x12 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_12.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__invz_x12 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_x12 layout**
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_16.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_16.rst
index 4a5fb48..b993ceb 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_16.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_16.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_x16 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_16.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__invz_x16 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_x16 layout**
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_2.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_2.rst
index 0863118..5c16ca3 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_2.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__invz_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_2 layout**
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_3.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_3.rst
index 322a213..e457927 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_3.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_3.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_3 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_3.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__invz_3 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_3 layout**
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_4.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_4.rst
index e9da3f7..d746fa1 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_4.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__invz_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_4 layout**
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_8.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_8.rst
index b97397e..ffbd7ee 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_8.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_8.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_8 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_8.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__invz_8 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__invz_8 layout**
diff --git a/cells/latq/definition.json b/cells/latq/definition.json
new file mode 100644
index 0000000..36a5a6e
--- /dev/null
+++ b/cells/latq/definition.json
@@ -0,0 +1,41 @@
+{
+    "description": "positive D-latch",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__latq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "latq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "E",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__latq"
+}
\ No newline at end of file
diff --git a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq.schematic.svg b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq.schematic.svg
new file mode 100644
index 0000000..3e2de3b
--- /dev/null
+++ b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="354" height="239"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(86,142)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latq.v:0$1"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latq.v:0$1"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latq.v:0$1"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(247,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latq.v:0$2"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latq.v:0$2"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latq.v:0$2"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="generic" transform="translate(173,86.5)" s:width="30" s:height="40" id="cell_x0"><text x="15" y="-4" class="nodelabel cell_x0" s:attribute="ref">udp_gf180mcu_fd_sc_mcu7t5v0_tt_25c_1v80_verilog_mgm_n_iq_latch_udp</text><rect width="30" height="100" s:generic="body" class="cell_x0"/><g transform="translate(0,10)" s:x="0" s:y="10" s:pid="in0" id="port_x0~C"><text x="-3" y="-4" class="inputPortLabel cell_x0">C</text></g><g transform="translate(0,30)" s:x="0" s:y="10" s:pid="in0" id="port_x0~CK"><text x="-3" y="-4" class="inputPortLabel cell_x0">CK</text></g><g transform="translate(0,50)" s:x="0" s:y="10" s:pid="in0" id="port_x0~D"><text x="-3" y="-4" class="inputPortLabel cell_x0">D</text></g><g transform="translate(0,70)" s:x="0" s:y="10" s:pid="in0" id="port_x0~N"><text x="-3" y="-4" class="inputPortLabel cell_x0">N</text></g><g transform="translate(0,90)" s:x="0" s:y="10" s:pid="in0" id="port_x0~P"><text x="-3" y="-4" class="inputPortLabel cell_x0">P</text></g><g transform="translate(30,10)" s:x="30" s:y="10" s:pid="out0" id="port_x0~Q"><text x="5" y="-4" style="fill:#000; stroke:none" class="cell_x0">Q</text></g></g><g s:type="inputExt" transform="translate(77,22)" s:width="30" s:height="20" id="cell_E"><text x="15" y="-4" class="nodelabel cell_E" s:attribute="ref">E</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_E"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,142)" s:width="30" s:height="20" id="cell_D"><text x="15" y="-4" class="nodelabel cell_D" s:attribute="ref">D</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_D"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(312,87)" s:width="30" s:height="20" id="cell_Q"><text x="15" y="-4" class="nodelabel cell_Q" s:attribute="ref">Q</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Q"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(77,207)" s:width="30" s:height="20" id="cell_notifier"><text x="15" y="-4" class="nodelabel cell_notifier" s:attribute="ref">notifier</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_notifier"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="constant" transform="translate(77,87)" s:width="30" s:height="20" id="cell_0"><text x="15" y="-4" class="nodelabel cell_0" s:attribute="ref">0</text><s:alias val="$_constant_"/><rect width="30" height="20" class="cell_0"/><g s:x="31" s:y="10" s:pid="Y"/></g><line x1="42" x2="85" y1="152" y2="152" class="net_3 width_1" style="stroke-width: 1"/><line x1="204" x2="246" y1="97" y2="97" class="net_7 width_1" style="stroke-width: 1"/><line x1="108" x2="173" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="108" x2="135" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="97" y2="177" class="net_8 width_1" style="stroke-width: 1"/><circle cx="135" cy="97" r="2" style="fill:#000" class="net_8 width_1"/><line x1="135" x2="173" y1="177" y2="177" class="net_8 width_1" style="stroke-width: 1"/><line x1="107" x2="145" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="32" y2="117" class="net_2 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="117" y2="117" class="net_2 width_1" style="stroke-width: 1"/><line x1="113" x2="145" y1="152" y2="152" class="net_6 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="152" y2="137" class="net_6 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="137" y2="137" class="net_6 width_1" style="stroke-width: 1"/><line x1="107" x2="145" y1="217" y2="217" class="net_5 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="217" y2="157" class="net_5 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="157" y2="157" class="net_5 width_1" style="stroke-width: 1"/><line x1="274" x2="312" y1="97" y2="97" class="net_4 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_1.rst b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_1.rst
index c837a21..afc12d0 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_1.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latq_1 layout**
diff --git a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_2.rst b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_2.rst
index 307f0c4..b352911 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_2.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latq_2 layout**
diff --git a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_4.rst b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_4.rst
index 1df1657..8c78f80 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_4.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latq_4 layout**
diff --git a/cells/latrnq/definition.json b/cells/latrnq/definition.json
new file mode 100644
index 0000000..d2658f8
--- /dev/null
+++ b/cells/latrnq/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "positive D-latch",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__latrnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "latrnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "E",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "RN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__latrnq"
+}
\ No newline at end of file
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq.schematic.svg b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq.schematic.svg
new file mode 100644
index 0000000..f9af348
--- /dev/null
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="288" height="314"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(86,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latrnq.v:0$1"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latrnq.v:0$1"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latrnq.v:0$1"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="generic" transform="translate(173,111.5)" s:width="30" s:height="40" id="cell_x0"><text x="15" y="-4" class="nodelabel cell_x0" s:attribute="ref">udp_gf180mcu_fd_sc_mcu7t5v0_tt_25c_1v80_verilog_mgm_n_iq_latch_udp</text><rect width="30" height="100" s:generic="body" class="cell_x0"/><g transform="translate(0,10)" s:x="0" s:y="10" s:pid="in0" id="port_x0~C"><text x="-3" y="-4" class="inputPortLabel cell_x0">C</text></g><g transform="translate(0,30)" s:x="0" s:y="10" s:pid="in0" id="port_x0~CK"><text x="-3" y="-4" class="inputPortLabel cell_x0">CK</text></g><g transform="translate(0,50)" s:x="0" s:y="10" s:pid="in0" id="port_x0~D"><text x="-3" y="-4" class="inputPortLabel cell_x0">D</text></g><g transform="translate(0,70)" s:x="0" s:y="10" s:pid="in0" id="port_x0~N"><text x="-3" y="-4" class="inputPortLabel cell_x0">N</text></g><g transform="translate(0,90)" s:x="0" s:y="10" s:pid="in0" id="port_x0~P"><text x="-3" y="-4" class="inputPortLabel cell_x0">P</text></g><g transform="translate(30,10)" s:x="30" s:y="10" s:pid="out0" id="port_x0~Q"><text x="5" y="-4" style="fill:#000; stroke:none" class="cell_x0">Q</text></g></g><g s:type="inputExt" transform="translate(77,87)" s:width="30" s:height="20" id="cell_E"><text x="15" y="-4" class="nodelabel cell_E" s:attribute="ref">E</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_E"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(77,152)" s:width="30" s:height="20" id="cell_D"><text x="15" y="-4" class="nodelabel cell_D" s:attribute="ref">D</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_D"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_RN"><text x="15" y="-4" class="nodelabel cell_RN" s:attribute="ref">RN</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_RN"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(246,112)" s:width="30" s:height="20" id="cell_Q"><text x="15" y="-4" class="nodelabel cell_Q" s:attribute="ref">Q</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Q"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(77,217)" s:width="30" s:height="20" id="cell_notifier"><text x="15" y="-4" class="nodelabel cell_notifier" s:attribute="ref">notifier</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_notifier"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="constant" transform="translate(77,282)" s:width="30" s:height="20" id="cell_0"><text x="15" y="-4" class="nodelabel cell_0" s:attribute="ref">0</text><s:alias val="$_constant_"/><rect width="30" height="20" class="cell_0"/><g s:x="31" s:y="10" s:pid="Y"/></g><line x1="42" x2="85" y1="32" y2="32" class="net_4 width_1" style="stroke-width: 1"/><line x1="113" x2="145" y1="32" y2="32" class="net_7 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="32" y2="122" class="net_7 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="122" y2="122" class="net_7 width_1" style="stroke-width: 1"/><line x1="107" x2="135" y1="97" y2="97" class="net_2 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="97" y2="142" class="net_2 width_1" style="stroke-width: 1"/><line x1="135" x2="173" y1="142" y2="142" class="net_2 width_1" style="stroke-width: 1"/><line x1="107" x2="173" y1="162" y2="162" class="net_3 width_1" style="stroke-width: 1"/><line x1="107" x2="135" y1="227" y2="227" class="net_6 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="227" y2="182" class="net_6 width_1" style="stroke-width: 1"/><line x1="135" x2="173" y1="182" y2="182" class="net_6 width_1" style="stroke-width: 1"/><line x1="108" x2="145" y1="292" y2="292" class="net_8 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="292" y2="202" class="net_8 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="202" y2="202" class="net_8 width_1" style="stroke-width: 1"/><line x1="204" x2="246" y1="122" y2="122" class="net_5 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_1.rst b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_1.rst
index ede3bd7..9b52425 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_1.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latrnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latrnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latrnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latrnq_1 layout**
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_2.rst b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_2.rst
index 11be322..490ecaf 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_2.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latrnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latrnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latrnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latrnq_2 layout**
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_4.rst b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_4.rst
index 1b05280..721eb4a 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_4.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latrnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latrnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latrnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latrnq_4 layout**
diff --git a/cells/latrsnq/definition.json b/cells/latrsnq/definition.json
new file mode 100644
index 0000000..5cf7c07
--- /dev/null
+++ b/cells/latrsnq/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "positive D-latch",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__latrsnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "latrsnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "E",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "RN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SETN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__latrsnq"
+}
\ No newline at end of file
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq.schematic.svg b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq.schematic.svg
new file mode 100644
index 0000000..7a56053
--- /dev/null
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="288" height="304"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(86,272)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latrsnq.v:0$1"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latrsnq.v:0$1"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latrsnq.v:0$1"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(86,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latrsnq.v:0$2"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latrsnq.v:0$2"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latrsnq.v:0$2"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="generic" transform="translate(173,111.5)" s:width="30" s:height="40" id="cell_x0"><text x="15" y="-4" class="nodelabel cell_x0" s:attribute="ref">udp_gf180mcu_fd_sc_mcu7t5v0_tt_25c_1v80_verilog_mgm_hn_iq_latch_udp</text><rect width="30" height="100" s:generic="body" class="cell_x0"/><g transform="translate(0,10)" s:x="0" s:y="10" s:pid="in0" id="port_x0~C"><text x="-3" y="-4" class="inputPortLabel cell_x0">C</text></g><g transform="translate(0,30)" s:x="0" s:y="10" s:pid="in0" id="port_x0~CK"><text x="-3" y="-4" class="inputPortLabel cell_x0">CK</text></g><g transform="translate(0,50)" s:x="0" s:y="10" s:pid="in0" id="port_x0~D"><text x="-3" y="-4" class="inputPortLabel cell_x0">D</text></g><g transform="translate(0,70)" s:x="0" s:y="10" s:pid="in0" id="port_x0~N"><text x="-3" y="-4" class="inputPortLabel cell_x0">N</text></g><g transform="translate(0,90)" s:x="0" s:y="10" s:pid="in0" id="port_x0~P"><text x="-3" y="-4" class="inputPortLabel cell_x0">P</text></g><g transform="translate(30,10)" s:x="30" s:y="10" s:pid="out0" id="port_x0~Q"><text x="5" y="-4" style="fill:#000; stroke:none" class="cell_x0">Q</text></g></g><g s:type="inputExt" transform="translate(77,87)" s:width="30" s:height="20" id="cell_E"><text x="15" y="-4" class="nodelabel cell_E" s:attribute="ref">E</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_E"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(77,152)" s:width="30" s:height="20" id="cell_D"><text x="15" y="-4" class="nodelabel cell_D" s:attribute="ref">D</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_D"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_RN"><text x="15" y="-4" class="nodelabel cell_RN" s:attribute="ref">RN</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_RN"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,272)" s:width="30" s:height="20" id="cell_SETN"><text x="15" y="-4" class="nodelabel cell_SETN" s:attribute="ref">SETN</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_SETN"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(246,112)" s:width="30" s:height="20" id="cell_Q"><text x="15" y="-4" class="nodelabel cell_Q" s:attribute="ref">Q</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Q"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(77,217)" s:width="30" s:height="20" id="cell_notifier"><text x="15" y="-4" class="nodelabel cell_notifier" s:attribute="ref">notifier</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_notifier"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="42" x2="85" y1="282" y2="282" class="net_5 width_1" style="stroke-width: 1"/><line x1="42" x2="85" y1="32" y2="32" class="net_4 width_1" style="stroke-width: 1"/><line x1="113" x2="145" y1="32" y2="32" class="net_9 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="32" y2="122" class="net_9 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="122" y2="122" class="net_9 width_1" style="stroke-width: 1"/><line x1="107" x2="135" y1="97" y2="97" class="net_2 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="97" y2="142" class="net_2 width_1" style="stroke-width: 1"/><line x1="135" x2="173" y1="142" y2="142" class="net_2 width_1" style="stroke-width: 1"/><line x1="107" x2="173" y1="162" y2="162" class="net_3 width_1" style="stroke-width: 1"/><line x1="107" x2="135" y1="227" y2="227" class="net_7 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="227" y2="182" class="net_7 width_1" style="stroke-width: 1"/><line x1="135" x2="173" y1="182" y2="182" class="net_7 width_1" style="stroke-width: 1"/><line x1="113" x2="145" y1="282" y2="282" class="net_8 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="282" y2="202" class="net_8 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="202" y2="202" class="net_8 width_1" style="stroke-width: 1"/><line x1="204" x2="246" y1="122" y2="122" class="net_6 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_1.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_1.rst
index 76ba4a0..08b1183 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_1.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latrsnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latrsnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latrsnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latrsnq_1 layout**
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_2.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_2.rst
index 5789b3a..7b2e962 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_2.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latrsnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latrsnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latrsnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latrsnq_2 layout**
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_4.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_4.rst
index 8034539..d8d66ed 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_4.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latrsnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latrsnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latrsnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latrsnq_4 layout**
diff --git a/cells/latsnq/definition.json b/cells/latsnq/definition.json
new file mode 100644
index 0000000..995f32a
--- /dev/null
+++ b/cells/latsnq/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "positive D-latch",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__latsnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "latsnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "E",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SETN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__latsnq"
+}
\ No newline at end of file
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq.schematic.svg b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq.schematic.svg
new file mode 100644
index 0000000..3c715d7
--- /dev/null
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="288" height="304"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(86,272)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latsnq.v:0$1"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latsnq.v:0$1"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__latsnq.v:0$1"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="generic" transform="translate(173,111.5)" s:width="30" s:height="40" id="cell_x0"><text x="15" y="-4" class="nodelabel cell_x0" s:attribute="ref">udp_gf180mcu_fd_sc_mcu7t5v0_tt_25c_1v80_verilog_mgm_n_iq_latch_udp</text><rect width="30" height="100" s:generic="body" class="cell_x0"/><g transform="translate(0,10)" s:x="0" s:y="10" s:pid="in0" id="port_x0~C"><text x="-3" y="-4" class="inputPortLabel cell_x0">C</text></g><g transform="translate(0,30)" s:x="0" s:y="10" s:pid="in0" id="port_x0~CK"><text x="-3" y="-4" class="inputPortLabel cell_x0">CK</text></g><g transform="translate(0,50)" s:x="0" s:y="10" s:pid="in0" id="port_x0~D"><text x="-3" y="-4" class="inputPortLabel cell_x0">D</text></g><g transform="translate(0,70)" s:x="0" s:y="10" s:pid="in0" id="port_x0~N"><text x="-3" y="-4" class="inputPortLabel cell_x0">N</text></g><g transform="translate(0,90)" s:x="0" s:y="10" s:pid="in0" id="port_x0~P"><text x="-3" y="-4" class="inputPortLabel cell_x0">P</text></g><g transform="translate(30,10)" s:x="30" s:y="10" s:pid="out0" id="port_x0~Q"><text x="5" y="-4" style="fill:#000; stroke:none" class="cell_x0">Q</text></g></g><g s:type="inputExt" transform="translate(77,87)" s:width="30" s:height="20" id="cell_E"><text x="15" y="-4" class="nodelabel cell_E" s:attribute="ref">E</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_E"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(77,152)" s:width="30" s:height="20" id="cell_D"><text x="15" y="-4" class="nodelabel cell_D" s:attribute="ref">D</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_D"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,272)" s:width="30" s:height="20" id="cell_SETN"><text x="15" y="-4" class="nodelabel cell_SETN" s:attribute="ref">SETN</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_SETN"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(246,112)" s:width="30" s:height="20" id="cell_Q"><text x="15" y="-4" class="nodelabel cell_Q" s:attribute="ref">Q</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Q"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(77,217)" s:width="30" s:height="20" id="cell_notifier"><text x="15" y="-4" class="nodelabel cell_notifier" s:attribute="ref">notifier</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_notifier"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="constant" transform="translate(77,22)" s:width="30" s:height="20" id="cell_0"><text x="15" y="-4" class="nodelabel cell_0" s:attribute="ref">0</text><s:alias val="$_constant_"/><rect width="30" height="20" class="cell_0"/><g s:x="31" s:y="10" s:pid="Y"/></g><line x1="42" x2="85" y1="282" y2="282" class="net_4 width_1" style="stroke-width: 1"/><line x1="108" x2="145" y1="32" y2="32" class="net_8 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="32" y2="122" class="net_8 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="122" y2="122" class="net_8 width_1" style="stroke-width: 1"/><line x1="107" x2="135" y1="97" y2="97" class="net_2 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="97" y2="142" class="net_2 width_1" style="stroke-width: 1"/><line x1="135" x2="173" y1="142" y2="142" class="net_2 width_1" style="stroke-width: 1"/><line x1="107" x2="173" y1="162" y2="162" class="net_3 width_1" style="stroke-width: 1"/><line x1="107" x2="135" y1="227" y2="227" class="net_6 width_1" style="stroke-width: 1"/><line x1="135" x2="135" y1="227" y2="182" class="net_6 width_1" style="stroke-width: 1"/><line x1="135" x2="173" y1="182" y2="182" class="net_6 width_1" style="stroke-width: 1"/><line x1="113" x2="145" y1="282" y2="282" class="net_7 width_1" style="stroke-width: 1"/><line x1="145" x2="145" y1="282" y2="202" class="net_7 width_1" style="stroke-width: 1"/><line x1="145" x2="173" y1="202" y2="202" class="net_7 width_1" style="stroke-width: 1"/><line x1="204" x2="246" y1="122" y2="122" class="net_5 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_1.rst b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_1.rst
index f8b45f6..d6da032 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_1.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latsnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latsnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latsnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latsnq_1 layout**
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_2.rst b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_2.rst
index 6b828a2..1978dcd 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_2.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latsnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latsnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latsnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latsnq_2 layout**
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_4.rst b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_4.rst
index fa204f1..094fbf1 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_4.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__latsnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__latsnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__latsnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__latsnq_4 layout**
diff --git a/cells/mux2/definition.json b/cells/mux2/definition.json
new file mode 100644
index 0000000..2a010e2
--- /dev/null
+++ b/cells/mux2/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "2-to-1 multiplexer",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__mux2",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "mux2",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "I0",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "I1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "S",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__mux2"
+}
\ No newline at end of file
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2.schematic.svg b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2.schematic.svg
new file mode 100644
index 0000000..e6fb4ba
--- /dev/null
+++ b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="380" height="194"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.rst b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.rst
index 5f5ad48..53e2a9b 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__mux2_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__mux2_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__mux2_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__mux2_1 layout**
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.schematic.png b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.schematic.png
deleted file mode 100644
index c1ec339..0000000
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_2.rst b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_2.rst
index cd186e1..dbcc551 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_2.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__mux2_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__mux2_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__mux2_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__mux2_2 layout**
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_2.schematic.png b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_2.schematic.png
deleted file mode 100644
index c1ec339..0000000
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_4.rst b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_4.rst
index dc91cb3..d6d631b 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_4.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__mux2_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__mux2_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__mux2_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__mux2_4 layout**
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_4.schematic.png b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_4.schematic.png
deleted file mode 100644
index c1ec339..0000000
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/mux4/definition.json b/cells/mux4/definition.json
new file mode 100644
index 0000000..fb8678d
--- /dev/null
+++ b/cells/mux4/definition.json
@@ -0,0 +1,65 @@
+{
+    "description": "4-to-1 multiplexer",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__mux4",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "mux4",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "I0",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "I1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "I2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "I3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "S0",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "S1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__mux4"
+}
\ No newline at end of file
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4.schematic.svg b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4.schematic.svg
new file mode 100644
index 0000000..c7da79a
--- /dev/null
+++ b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_1.rst b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_1.rst
index bf2915b..7b7ebfc 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_1.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__mux4_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__mux4_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__mux4_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__mux4_1 layout**
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_1.schematic.png b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_1.schematic.png
deleted file mode 100644
index 85de14a..0000000
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_2.rst b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_2.rst
index 2c05a00..ece6b9e 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_2.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__mux4_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__mux4_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__mux4_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__mux4_2 layout**
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_2.schematic.png b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_2.schematic.png
deleted file mode 100644
index 85de14a..0000000
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_4.rst b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_4.rst
index 3c234d5..8d29252 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_4.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__mux4_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__mux4_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__mux4_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__mux4_4 layout**
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_4.schematic.png b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_4.schematic.png
deleted file mode 100644
index 85de14a..0000000
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nand2/definition.json b/cells/nand2/definition.json
new file mode 100644
index 0000000..69c044a
--- /dev/null
+++ b/cells/nand2/definition.json
@@ -0,0 +1,41 @@
+{
+    "description": "2-input NAND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nand2",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "nand2",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nand2"
+}
\ No newline at end of file
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2.schematic.svg b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2.schematic.svg
new file mode 100644
index 0000000..46e5446
--- /dev/null
+++ b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="250" height="119"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand2.v:0$2"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand2.v:0$2"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand2.v:0$2"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand2.v:0$3"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand2.v:0$3"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand2.v:0$3"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(143,27)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand2.v:30$1"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand2.v:30$1"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(208,29.5)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_3 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="97" y2="97" class="net_2 width_1" style="stroke-width: 1"/><line x1="105" x2="145" y1="32" y2="32" class="net_5 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="97" y2="97" class="net_6 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="97" y2="47" class="net_6 width_1" style="stroke-width: 1"/><line x1="118" x2="145" y1="47" y2="47" class="net_6 width_1" style="stroke-width: 1"/><line x1="173" x2="208" y1="39.5" y2="39.5" class="net_4 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.rst b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.rst
index 1360aad..b87be07 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nand2_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nand2_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nand2_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nand2_1 layout**
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.schematic.png b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.schematic.png
deleted file mode 100644
index 12f8d31..0000000
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_2.rst b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_2.rst
index 6bf6f82..6f59137 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_2.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nand2_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nand2_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nand2_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nand2_2 layout**
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_2.schematic.png b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_2.schematic.png
deleted file mode 100644
index 12f8d31..0000000
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_4.rst b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_4.rst
index b03f9aa..5e7adf0 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_4.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nand2_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nand2_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nand2_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nand2_4 layout**
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_4.schematic.png b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_4.schematic.png
deleted file mode 100644
index 12f8d31..0000000
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nand3/definition.json b/cells/nand3/definition.json
new file mode 100644
index 0000000..66659e8
--- /dev/null
+++ b/cells/nand3/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "3-input NAND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nand3",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "nand3",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nand3"
+}
\ No newline at end of file
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3.schematic.svg b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3.schematic.svg
new file mode 100644
index 0000000..c6070a4
--- /dev/null
+++ b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="316" height="184"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand3.v:0$3"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand3.v:0$3"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand3.v:0$3"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand3.v:0$4"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand3.v:0$4"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand3.v:0$4"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(144,152)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand3.v:0$5"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand3.v:0$5"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand3.v:0$5"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(143.66666666666666,27)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand3.v:34$1"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand3.v:34$1"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(209,34.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand3.v:34$2"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand3.v:34$2"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(78,152)" s:width="30" s:height="20" id="cell_A3"><text x="15" y="-4" class="nodelabel cell_A3" s:attribute="ref">A3</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A3"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(274,37)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_5 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="97" y2="97" class="net_4 width_1" style="stroke-width: 1"/><line x1="108" x2="143" y1="162" y2="162" class="net_2 width_1" style="stroke-width: 1"/><line x1="105" x2="145.66666666666666" y1="32" y2="32" class="net_6 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="97" y2="97" class="net_7 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="97" y2="47" class="net_7 width_1" style="stroke-width: 1"/><line x1="118" x2="145.66666666666666" y1="47" y2="47" class="net_7 width_1" style="stroke-width: 1"/><line x1="173.66666666666666" x2="211" y1="39.5" y2="39.5" class="net_9 width_1" style="stroke-width: 1"/><line x1="171" x2="184" y1="162" y2="162" class="net_8 width_1" style="stroke-width: 1"/><line x1="184" x2="184" y1="162" y2="54.5" class="net_8 width_1" style="stroke-width: 1"/><line x1="184" x2="211" y1="54.5" y2="54.5" class="net_8 width_1" style="stroke-width: 1"/><line x1="239" x2="274" y1="47" y2="47" class="net_3 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_1.rst b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_1.rst
index 39f00bc..c448abc 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_1.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nand3_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nand3_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nand3_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nand3_1 layout**
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_1.schematic.png b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_1.schematic.png
deleted file mode 100644
index ef9d64c..0000000
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_2.rst b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_2.rst
index e8ef03a..e2fc06a 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_2.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nand3_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nand3_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nand3_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nand3_2 layout**
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_2.schematic.png b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_2.schematic.png
deleted file mode 100644
index ef9d64c..0000000
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_4.rst b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_4.rst
index ff04048..cb00623 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_4.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nand3_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nand3_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nand3_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nand3_4 layout**
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_4.schematic.png b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_4.schematic.png
deleted file mode 100644
index ef9d64c..0000000
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nand4/definition.json b/cells/nand4/definition.json
new file mode 100644
index 0000000..1342d84
--- /dev/null
+++ b/cells/nand4/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "4-input NAND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nand4",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "nand4",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A4",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nand4"
+}
\ No newline at end of file
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4.schematic.svg b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4.schematic.svg
new file mode 100644
index 0000000..763e41a
--- /dev/null
+++ b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="382" height="249"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$4"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$4"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$4"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$5"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$5"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$5"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(144,152)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$6"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$6"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$6"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(210,217)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$7"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$7"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nand4.v:0$7"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(143.66666666666666,27)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand4.v:38$1"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand4.v:38$1"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(209.66666666666666,34.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand4.v:38$2"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand4.v:38$2"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(275,42)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand4.v:38$3"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__nand4.v:38$3"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(144,217)" s:width="30" s:height="20" id="cell_A4"><text x="15" y="-4" class="nodelabel cell_A4" s:attribute="ref">A4</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A4"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(340,44.5)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(78,152)" s:width="30" s:height="20" id="cell_A3"><text x="15" y="-4" class="nodelabel cell_A3" s:attribute="ref">A3</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A3"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="42" x2="77" y1="32" y2="32" class="net_6 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="97" y2="97" class="net_5 width_1" style="stroke-width: 1"/><line x1="108" x2="143" y1="162" y2="162" class="net_4 width_1" style="stroke-width: 1"/><line x1="174" x2="209" y1="227" y2="227" class="net_2 width_1" style="stroke-width: 1"/><line x1="105" x2="145.66666666666666" y1="32" y2="32" class="net_7 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="97" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="118" x2="145.66666666666666" y1="47" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="173.66666666666666" x2="211.66666666666666" y1="39.5" y2="39.5" class="net_11 width_1" style="stroke-width: 1"/><line x1="171" x2="184" y1="162" y2="162" class="net_9 width_1" style="stroke-width: 1"/><line x1="184" x2="184" y1="162" y2="54.5" class="net_9 width_1" style="stroke-width: 1"/><line x1="184" x2="211.66666666666666" y1="54.5" y2="54.5" class="net_9 width_1" style="stroke-width: 1"/><line x1="239.66666666666666" x2="277" y1="47" y2="47" class="net_12 width_1" style="stroke-width: 1"/><line x1="237" x2="250" y1="227" y2="227" class="net_10 width_1" style="stroke-width: 1"/><line x1="250" x2="250" y1="227" y2="62" class="net_10 width_1" style="stroke-width: 1"/><line x1="250" x2="277" y1="62" y2="62" class="net_10 width_1" style="stroke-width: 1"/><line x1="305" x2="340" y1="54.5" y2="54.5" class="net_3 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_1.rst b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_1.rst
index 98b053f..f71db2d 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_1.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nand4_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nand4_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nand4_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nand4_1 layout**
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_1.schematic.png b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_1.schematic.png
deleted file mode 100644
index 2816b71..0000000
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.rst b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.rst
index 99037be..502b10a 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nand4_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nand4_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nand4_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nand4_2 layout**
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.schematic.png b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.schematic.png
deleted file mode 100644
index 2816b71..0000000
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_4.rst b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_4.rst
index 11e2962..94ea093 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_4.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nand4_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nand4_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nand4_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nand4_4 layout**
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_4.schematic.png b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_4.schematic.png
deleted file mode 100644
index 2816b71..0000000
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nor2/definition.json b/cells/nor2/definition.json
new file mode 100644
index 0000000..9c389f3
--- /dev/null
+++ b/cells/nor2/definition.json
@@ -0,0 +1,41 @@
+{
+    "description": "2-input NOR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nor2",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "nor2",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nor2"
+}
\ No newline at end of file
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2.schematic.svg b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2.schematic.svg
new file mode 100644
index 0000000..1539997
--- /dev/null
+++ b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="250" height="119"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(143,27)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor2.v:30$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor2.v:30$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor2.v:0$2"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor2.v:0$2"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor2.v:0$2"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor2.v:0$3"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor2.v:0$3"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor2.v:0$3"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(208,29.5)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="105" x2="143" y1="32" y2="32" class="net_5 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="97" y2="97" class="net_6 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="97" y2="47" class="net_6 width_1" style="stroke-width: 1"/><line x1="118" x2="143" y1="47" y2="47" class="net_6 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="32" y2="32" class="net_4 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="97" y2="97" class="net_2 width_1" style="stroke-width: 1"/><line x1="173" x2="208" y1="39.5" y2="39.5" class="net_3 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.rst b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.rst
index a135e57..3b02754 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nor2_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nor2_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nor2_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nor2_1 layout**
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.schematic.png b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.schematic.png
deleted file mode 100644
index cc8a0fc..0000000
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_2.rst b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_2.rst
index cd5f754..b2b204c 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_2.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nor2_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nor2_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nor2_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nor2_2 layout**
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_2.schematic.png b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_2.schematic.png
deleted file mode 100644
index cc8a0fc..0000000
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_4.rst b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_4.rst
index 190ca17..70b8c74 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_4.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nor2_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nor2_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nor2_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nor2_4 layout**
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_4.schematic.png b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_4.schematic.png
deleted file mode 100644
index cc8a0fc..0000000
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nor3/definition.json b/cells/nor3/definition.json
new file mode 100644
index 0000000..986c6e5
--- /dev/null
+++ b/cells/nor3/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "3-input NOR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nor3",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "nor3",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nor3"
+}
\ No newline at end of file
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3.schematic.svg b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3.schematic.svg
new file mode 100644
index 0000000..2abbedd
--- /dev/null
+++ b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="316" height="184"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(143.66666666666666,27)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor3.v:34$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor3.v:34$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(209,34.5)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor3.v:34$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor3.v:34$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor3.v:0$3"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor3.v:0$3"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor3.v:0$3"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor3.v:0$4"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor3.v:0$4"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor3.v:0$4"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(144,152)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor3.v:0$5"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor3.v:0$5"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor3.v:0$5"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(78,152)" s:width="30" s:height="20" id="cell_A3"><text x="15" y="-4" class="nodelabel cell_A3" s:attribute="ref">A3</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A3"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(274,37)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="105" x2="143.66666666666666" y1="32" y2="32" class="net_6 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="97" y2="97" class="net_7 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="97" y2="47" class="net_7 width_1" style="stroke-width: 1"/><line x1="118" x2="143.66666666666666" y1="47" y2="47" class="net_7 width_1" style="stroke-width: 1"/><line x1="173.66666666666666" x2="209" y1="39.5" y2="39.5" class="net_8 width_1" style="stroke-width: 1"/><line x1="171" x2="184" y1="162" y2="162" class="net_9 width_1" style="stroke-width: 1"/><line x1="184" x2="184" y1="162" y2="54.5" class="net_9 width_1" style="stroke-width: 1"/><line x1="184" x2="209" y1="54.5" y2="54.5" class="net_9 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="32" y2="32" class="net_5 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="97" y2="97" class="net_4 width_1" style="stroke-width: 1"/><line x1="108" x2="143" y1="162" y2="162" class="net_2 width_1" style="stroke-width: 1"/><line x1="239" x2="274" y1="47" y2="47" class="net_3 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_1.rst b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_1.rst
index c385060..a7a500c 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_1.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nor3_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nor3_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nor3_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nor3_1 layout**
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_1.schematic.png b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_1.schematic.png
deleted file mode 100644
index 40c2ac4..0000000
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.rst b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.rst
index 61c23cc..b0fa254 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nor3_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nor3_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nor3_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nor3_2 layout**
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.schematic.png b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.schematic.png
deleted file mode 100644
index 40c2ac4..0000000
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_4.rst b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_4.rst
index c4b2153..028c101 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_4.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nor3_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nor3_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nor3_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nor3_4 layout**
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_4.schematic.png b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_4.schematic.png
deleted file mode 100644
index 40c2ac4..0000000
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nor4/definition.json b/cells/nor4/definition.json
new file mode 100644
index 0000000..51902e0
--- /dev/null
+++ b/cells/nor4/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "4-input NOR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nor4",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "nor4",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A4",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nor4"
+}
\ No newline at end of file
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4.schematic.svg b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4.schematic.svg
new file mode 100644
index 0000000..a30202e
--- /dev/null
+++ b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="382" height="249"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(143.66666666666666,27)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor4.v:38$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor4.v:38$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(209.66666666666666,34.5)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor4.v:38$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor4.v:38$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(275,42)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor4.v:38$3"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__nor4.v:38$3"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor4.v:0$4"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor4.v:0$4"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor4.v:0$4"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor4.v:0$5"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor4.v:0$5"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor4.v:0$5"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(144,152)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor4.v:0$6"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor4.v:0$6"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor4.v:0$6"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(210,217)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor4.v:0$7"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__nor4.v:0$7"/><circle cx="24" cy="10" r="3" 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s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="105" x2="143.66666666666666" y1="32" y2="32" class="net_7 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="97" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="118" x2="143.66666666666666" y1="47" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="173.66666666666666" x2="209.66666666666666" y1="39.5" y2="39.5" class="net_9 width_1" style="stroke-width: 1"/><line x1="171" x2="184" y1="162" y2="162" class="net_10 width_1" style="stroke-width: 1"/><line x1="184" x2="184" y1="162" y2="54.5" class="net_10 width_1" style="stroke-width: 1"/><line x1="184" x2="209.66666666666666" y1="54.5" y2="54.5" class="net_10 width_1" style="stroke-width: 1"/><line x1="239.66666666666666" x2="275" y1="47" y2="47" class="net_11 width_1" style="stroke-width: 1"/><line x1="237" x2="250" y1="227" y2="227" class="net_12 width_1" style="stroke-width: 1"/><line x1="250" x2="250" y1="227" y2="62" class="net_12 width_1" style="stroke-width: 1"/><line x1="250" x2="275" y1="62" y2="62" class="net_12 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="32" y2="32" class="net_6 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="97" y2="97" class="net_5 width_1" style="stroke-width: 1"/><line x1="108" x2="143" y1="162" y2="162" class="net_4 width_1" style="stroke-width: 1"/><line x1="174" x2="209" y1="227" y2="227" class="net_2 width_1" style="stroke-width: 1"/><line x1="305" x2="340" y1="54.5" y2="54.5" class="net_3 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_1.rst b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_1.rst
index 5d5db69..5fdf556 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_1.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nor4_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nor4_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nor4_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nor4_1 layout**
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_1.schematic.png b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_1.schematic.png
deleted file mode 100644
index 314705d..0000000
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_2.rst b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_2.rst
index dbcfb32..5e5b94a 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_2.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nor4_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nor4_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nor4_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nor4_2 layout**
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_2.schematic.png b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_2.schematic.png
deleted file mode 100644
index 314705d..0000000
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_4.rst b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_4.rst
index 38f9bf9..a7120ed 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_4.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__nor4_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__nor4_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__nor4_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__nor4_4 layout**
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_4.schematic.png b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_4.schematic.png
deleted file mode 100644
index 314705d..0000000
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai21/definition.json b/cells/oai21/definition.json
new file mode 100644
index 0000000..cd14fcc
--- /dev/null
+++ b/cells/oai21/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "2-input OR into 2-input NAND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai21",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "oai21",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai21"
+}
\ No newline at end of file
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21.schematic.svg b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21.schematic.svg
new file mode 100644
index 0000000..58ce538
--- /dev/null
+++ b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="316" height="184"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(143.66666666666666,27)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai21.v:32$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai21.v:32$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai21.v:0$3"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai21.v:0$3"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai21.v:0$3"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai21.v:0$4"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai21.v:0$4"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai21.v:0$4"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(144,152)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai21.v:0$5"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai21.v:0$5"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai21.v:0$5"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(209,34.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__oai21.v:38$2"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__oai21.v:38$2"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(274,37)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(78,152)" s:width="30" s:height="20" id="cell_B"><text x="15" y="-4" class="nodelabel cell_B" s:attribute="ref">B</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_B"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="105" x2="143.66666666666666" y1="32" y2="32" class="net_6 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="97" y2="97" class="net_7 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="97" y2="47" class="net_7 width_1" style="stroke-width: 1"/><line x1="118" x2="143.66666666666666" y1="47" y2="47" class="net_7 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="32" y2="32" class="net_4 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="97" y2="97" class="net_2 width_1" style="stroke-width: 1"/><line x1="108" x2="143" y1="162" y2="162" class="net_5 width_1" style="stroke-width: 1"/><line x1="173.66666666666666" x2="211" y1="39.5" y2="39.5" class="net_8 width_1" style="stroke-width: 1"/><line x1="171" x2="184" y1="162" y2="162" class="net_9 width_1" style="stroke-width: 1"/><line x1="184" x2="184" y1="162" y2="54.5" class="net_9 width_1" style="stroke-width: 1"/><line x1="184" x2="211" y1="54.5" y2="54.5" class="net_9 width_1" style="stroke-width: 1"/><line x1="239" x2="274" y1="47" y2="47" class="net_3 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_1.rst b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_1.rst
index c575031..f7e18d2 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_1.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai21_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai21_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai21.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai21_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai21_1 layout**
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_1.schematic.png b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_1.schematic.png
deleted file mode 100644
index f95472c..0000000
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_2.rst b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_2.rst
index bd37233..13f12a5 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_2.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai21_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai21_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai21.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai21_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai21_2 layout**
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_2.schematic.png b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_2.schematic.png
deleted file mode 100644
index f95472c..0000000
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_4.rst b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_4.rst
index 158f142..6b1fac1 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_4.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai21_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai21_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai21.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai21_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai21_4 layout**
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_4.schematic.png b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_4.schematic.png
deleted file mode 100644
index f95472c..0000000
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai211/definition.json b/cells/oai211/definition.json
new file mode 100644
index 0000000..6a280cf
--- /dev/null
+++ b/cells/oai211/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "2-input OR into 3-input NAND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai211",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "oai211",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "C",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai211"
+}
\ No newline at end of file
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211.schematic.svg b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211.schematic.svg
new file mode 100644
index 0000000..1350209
--- /dev/null
+++ b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="382" height="249"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(143.66666666666666,27)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai211.v:32$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai211.v:32$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$4"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$4"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$4"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$5"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$5"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$5"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(144,152)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$6"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$6"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$6"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(210,217)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$7"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$7"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai211.v:0$7"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(209.66666666666666,34.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__oai211.v:42$2"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__oai211.v:42$2"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(275,42)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__oai211.v:42$3"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__oai211.v:42$3"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(340,44.5)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(78,152)" s:width="30" s:height="20" id="cell_B"><text x="15" y="-4" class="nodelabel cell_B" s:attribute="ref">B</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_B"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(144,217)" s:width="30" s:height="20" id="cell_C"><text x="15" y="-4" class="nodelabel cell_C" s:attribute="ref">C</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_C"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="105" x2="143.66666666666666" y1="32" y2="32" class="net_7 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="97" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="118" x2="143.66666666666666" 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style="stroke-width: 1"/><line x1="250" x2="250" y1="227" y2="62" class="net_11 width_1" style="stroke-width: 1"/><line x1="250" x2="277" y1="62" y2="62" class="net_11 width_1" style="stroke-width: 1"/><line x1="305" x2="340" y1="54.5" y2="54.5" class="net_3 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_1.rst b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_1.rst
index 330aa2d..80b6b21 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_1.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai211_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai211_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai211.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai211_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai211_1 layout**
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_1.schematic.png b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_1.schematic.png
deleted file mode 100644
index 0382fcc..0000000
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_2.rst b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_2.rst
index 6540da8..8231fbc 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_2.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai211_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai211_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai211.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai211_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai211_2 layout**
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_2.schematic.png b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_2.schematic.png
deleted file mode 100644
index 0382fcc..0000000
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_4.rst b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_4.rst
index c485ff2..8bd7f89 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_4.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai211_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai211_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai211.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai211_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai211_4 layout**
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_4.schematic.png b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_4.schematic.png
deleted file mode 100644
index 0382fcc..0000000
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai22/definition.json b/cells/oai22/definition.json
new file mode 100644
index 0000000..65ad00b
--- /dev/null
+++ b/cells/oai22/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "two 2-input OR into 2-input NAND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai22",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "oai22",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai22"
+}
\ No newline at end of file
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22.schematic.svg b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22.schematic.svg
new file mode 100644
index 0000000..e75fdf0
--- /dev/null
+++ b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="315" height="249"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(143,27)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai22.v:32$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai22.v:32$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(143,157)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai22.v:44$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai22.v:44$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$4"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$4"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$4"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$5"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$5"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$5"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,152)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$6"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$6"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$6"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,217)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$7"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$7"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai22.v:0$7"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(208,34.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__oai22.v:46$3"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" 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s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="105" x2="143" y1="32" y2="32" class="net_7 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="97" y2="97" class="net_8 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="97" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="118" x2="143" y1="47" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="105" x2="143" y1="162" y2="162" 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\ No newline at end of file
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_1.rst b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_1.rst
index 21b9d3b..23daa1b 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_1.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai22_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai22_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai22.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai22_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai22_1 layout**
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_1.schematic.png b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_1.schematic.png
deleted file mode 100644
index 76be4ee..0000000
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_2.rst b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_2.rst
index b80383a..e1f4146 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_2.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai22_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai22_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai22.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai22_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai22_2 layout**
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_2.schematic.png b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_2.schematic.png
deleted file mode 100644
index 76be4ee..0000000
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_4.rst b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_4.rst
index f569545..e1759d9 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_4.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai22_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai22_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai22.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai22_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai22_4 layout**
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_4.schematic.png b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_4.schematic.png
deleted file mode 100644
index 76be4ee..0000000
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai221/definition.json b/cells/oai221/definition.json
new file mode 100644
index 0000000..338ce4e
--- /dev/null
+++ b/cells/oai221/definition.json
@@ -0,0 +1,59 @@
+{
+    "description": "two 2-input OR into 3-input NAND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai221",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "oai221",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "C",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai221"
+}
\ No newline at end of file
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221.schematic.svg b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221.schematic.svg
new file mode 100644
index 0000000..d50ddc4
--- /dev/null
+++ b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="381" height="259"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(143,27)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai221.v:32$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai221.v:32$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(143,157)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai221.v:44$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__oai221.v:44$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$5"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$5"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$5"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$6"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$6"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$6"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,152)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$7"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$7"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$7"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,217)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$8"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$8"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$8"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(209,227)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$9"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$9"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__oai221.v:0$9"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(208.66666666666666,34.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__oai221.v:50$3"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__oai221.v:50$3"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(274,42)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__oai221.v:50$4"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__oai221.v:50$4"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,217)" s:width="30" s:height="20" id="cell_B2"><text x="15" y="-4" class="nodelabel cell_B2" s:attribute="ref">B2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_B2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,152)" s:width="30" s:height="20" id="cell_B1"><text x="15" y="-4" class="nodelabel cell_B1" s:attribute="ref">B1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_B1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(143,227)" s:width="30" s:height="20" id="cell_C"><text x="15" y="-4" class="nodelabel cell_C" s:attribute="ref">C</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_C"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(339,44.5)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><line x1="105" x2="143" y1="32" y2="32" class="net_8 width_1" style="stroke-width: 1"/><line x1="105" x2="118" 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\ No newline at end of file
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_1.rst b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_1.rst
index 18cb921..b3a5091 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_1.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai221_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai221_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai221.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai221_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai221_1 layout**
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_1.schematic.png b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_1.schematic.png
deleted file mode 100644
index c75021d..0000000
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.rst b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.rst
index 17713b9..59937e1 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai221_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai221_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai221.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai221_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai221_2 layout**
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.schematic.png b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.schematic.png
deleted file mode 100644
index c75021d..0000000
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_4.rst b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_4.rst
index e6fa947..01cf919 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_4.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai221_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai221_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai221.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai221_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai221_4 layout**
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_4.schematic.png b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_4.schematic.png
deleted file mode 100644
index c75021d..0000000
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai222/definition.json b/cells/oai222/definition.json
new file mode 100644
index 0000000..72f539e
--- /dev/null
+++ b/cells/oai222/definition.json
@@ -0,0 +1,65 @@
+{
+    "description": "three 2-input OR into 3-input NAND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai222",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "oai222",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "C1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "C2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai222"
+}
\ No newline at end of file
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222.schematic.svg b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222.schematic.svg
new file mode 100644
index 0000000..c53a153
--- /dev/null
+++ b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="381" height="379"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_1.rst b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_1.rst
index d8b65c6..bcbcd0e 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_1.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai222_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai222_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai222.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai222_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai222_1 layout**
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_1.schematic.png b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_1.schematic.png
deleted file mode 100644
index c67674b..0000000
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.rst b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.rst
index cd41646..848e2f7 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai222_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai222_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai222.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai222_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai222_2 layout**
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.schematic.png b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.schematic.png
deleted file mode 100644
index c67674b..0000000
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_4.rst b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_4.rst
index 25558e5..869e9f3 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_4.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai222_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai222_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai222.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai222_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai222_4 layout**
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_4.schematic.png b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_4.schematic.png
deleted file mode 100644
index c67674b..0000000
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai31/definition.json b/cells/oai31/definition.json
new file mode 100644
index 0000000..3d889f9
--- /dev/null
+++ b/cells/oai31/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "3-input OR into 2-input NAND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai31",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "oai31",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai31"
+}
\ No newline at end of file
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31.schematic.svg b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31.schematic.svg
new file mode 100644
index 0000000..a7a487e
--- /dev/null
+++ b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_1.rst b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_1.rst
index 8cb1dab..c4b801a 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_1.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai31_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai31_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai31.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai31_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai31_1 layout**
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_1.schematic.png b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_1.schematic.png
deleted file mode 100644
index f7bdfd6..0000000
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_2.rst b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_2.rst
index d4095df..168a306 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_2.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai31_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai31_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai31.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai31_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai31_2 layout**
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_2.schematic.png b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_2.schematic.png
deleted file mode 100644
index f7bdfd6..0000000
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_4.rst b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_4.rst
index 6993b19..27bbd8d 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_4.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai31_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai31_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai31.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai31_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai31_4 layout**
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_4.schematic.png b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_4.schematic.png
deleted file mode 100644
index f7bdfd6..0000000
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai32/definition.json b/cells/oai32/definition.json
new file mode 100644
index 0000000..5e57252
--- /dev/null
+++ b/cells/oai32/definition.json
@@ -0,0 +1,59 @@
+{
+    "description": "3-input OR and a 2-input OR into 2-input NAND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai32",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "oai32",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai32"
+}
\ No newline at end of file
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32.schematic.svg b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32.schematic.svg
new file mode 100644
index 0000000..ef1a0ae
--- /dev/null
+++ b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
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+  fill:#000;
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diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_1.rst b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_1.rst
index 8f2d82e..9072de3 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_1.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai32_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai32_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai32.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai32_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai32_1 layout**
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_1.schematic.png b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_1.schematic.png
deleted file mode 100644
index 55a96a4..0000000
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_2.rst b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_2.rst
index 387f032..1bb2365 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_2.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai32_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai32_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai32.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai32_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai32_2 layout**
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_2.schematic.png b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_2.schematic.png
deleted file mode 100644
index 55a96a4..0000000
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_4.rst b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_4.rst
index 141659c..b6ab2c5 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_4.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai32_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai32_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai32.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai32_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai32_4 layout**
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_4.schematic.png b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_4.schematic.png
deleted file mode 100644
index 55a96a4..0000000
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai33/definition.json b/cells/oai33/definition.json
new file mode 100644
index 0000000..ecfd623
--- /dev/null
+++ b/cells/oai33/definition.json
@@ -0,0 +1,65 @@
+{
+    "description": "two 3-input OR into 2-input NAND",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai33",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "oai33",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "B3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai33"
+}
\ No newline at end of file
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33.schematic.svg b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33.schematic.svg
new file mode 100644
index 0000000..11441f5
--- /dev/null
+++ b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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style="stroke-width: 1"/><line x1="239" x2="276" y1="47" y2="47" class="net_13 width_1" style="stroke-width: 1"/><line x1="239" x2="249" y1="232" y2="232" class="net_18 width_1" style="stroke-width: 1"/><line x1="249" x2="249" y1="232" y2="62" class="net_18 width_1" style="stroke-width: 1"/><line x1="249" x2="276" y1="62" y2="62" class="net_18 width_1" style="stroke-width: 1"/><line x1="304" x2="339" y1="54.5" y2="54.5" class="net_5 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_1.rst b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_1.rst
index be857d7..d28fcd6 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_1.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai33_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai33_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai33.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai33_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai33_1 layout**
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_1.schematic.png b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_1.schematic.png
deleted file mode 100644
index bfc83f1..0000000
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_2.rst b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_2.rst
index d094182..685ac35 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_2.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai33_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai33_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai33.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai33_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai33_2 layout**
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_2.schematic.png b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_2.schematic.png
deleted file mode 100644
index bfc83f1..0000000
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_4.rst b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_4.rst
index da1b0e7..ac2d3d2 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_4.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__oai33_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__oai33_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai33.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__oai33_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__oai33_4 layout**
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_4.schematic.png b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_4.schematic.png
deleted file mode 100644
index bfc83f1..0000000
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/or2/definition.json b/cells/or2/definition.json
new file mode 100644
index 0000000..4bd4a21
--- /dev/null
+++ b/cells/or2/definition.json
@@ -0,0 +1,41 @@
+{
+    "description": "2-input OR(A1",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__or2",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "or2",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__or2"
+}
\ No newline at end of file
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2.schematic.svg b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2.schematic.svg
new file mode 100644
index 0000000..2305996
--- /dev/null
+++ b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="184" height="119"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="or" transform="translate(77,27)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or2.v:22$1"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or2.v:22$1"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(142,29.5)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="79" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="42" x2="52" y1="97" y2="97" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="97" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="79" y1="47" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="107" x2="142" y1="39.5" y2="39.5" class="net_4 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_1.rst b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_1.rst
index 514d86e..9fda421 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_1.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__or2_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__or2_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__or2_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__or2_1 layout**
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_1.schematic.png b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_1.schematic.png
deleted file mode 100644
index 5451752..0000000
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_2.rst b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_2.rst
index f920fc5..2512be0 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_2.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__or2_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__or2_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__or2_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__or2_2 layout**
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_2.schematic.png b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_2.schematic.png
deleted file mode 100644
index 5451752..0000000
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_4.rst b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_4.rst
index c001686..e0d78a8 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_4.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__or2_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__or2_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__or2_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__or2_4 layout**
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_4.schematic.png b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_4.schematic.png
deleted file mode 100644
index 5451752..0000000
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/or3/definition.json b/cells/or3/definition.json
new file mode 100644
index 0000000..6da33e1
--- /dev/null
+++ b/cells/or3/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "3-input OR(A1",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__or3",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "or3",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__or3"
+}
\ No newline at end of file
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3.schematic.svg b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3.schematic.svg
new file mode 100644
index 0000000..cfdacbc
--- /dev/null
+++ b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="249" height="129"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="or" transform="translate(77,27)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or3.v:22$1"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or3.v:22$1"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(142,34.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or3.v:22$2"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or3.v:22$2"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(77,97)" s:width="30" s:height="20" id="cell_A3"><text x="15" y="-4" class="nodelabel cell_A3" s:attribute="ref">A3</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A3"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(207,37)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="79" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="42" x2="52" y1="97" y2="97" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="97" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="79" y1="47" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="107" x2="144" y1="39.5" y2="39.5" class="net_6 width_1" style="stroke-width: 1"/><line x1="107" x2="117" y1="107" y2="107" class="net_4 width_1" style="stroke-width: 1"/><line x1="117" x2="117" y1="107" y2="54.5" class="net_4 width_1" style="stroke-width: 1"/><line x1="117" x2="144" y1="54.5" y2="54.5" class="net_4 width_1" style="stroke-width: 1"/><line x1="172" x2="207" y1="47" y2="47" class="net_5 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_1.rst b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_1.rst
index 1a69a36..11ce579 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_1.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__or3_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__or3_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__or3_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__or3_1 layout**
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_1.schematic.png b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_1.schematic.png
deleted file mode 100644
index 5914186..0000000
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_2.rst b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_2.rst
index 5924240..f7485d0 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_2.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__or3_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__or3_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__or3_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__or3_2 layout**
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_2.schematic.png b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_2.schematic.png
deleted file mode 100644
index 5914186..0000000
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_4.rst b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_4.rst
index b41d535..ba2a0fe 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_4.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__or3_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__or3_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__or3_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__or3_4 layout**
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_4.schematic.png b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_4.schematic.png
deleted file mode 100644
index 5914186..0000000
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/or4/definition.json b/cells/or4/definition.json
new file mode 100644
index 0000000..1e19396
--- /dev/null
+++ b/cells/or4/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "4-input OR(A1",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__or4",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "or4",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A4",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__or4"
+}
\ No newline at end of file
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4.schematic.svg b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4.schematic.svg
new file mode 100644
index 0000000..5d573bb
--- /dev/null
+++ b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="314" height="136.5"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="or" transform="translate(77,27)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or4.v:22$1"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or4.v:22$1"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(142,34.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or4.v:22$2"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or4.v:22$2"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(207,42)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or4.v:22$3"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__or4.v:22$3"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(77,97)" s:width="30" s:height="20" id="cell_A3"><text x="15" y="-4" class="nodelabel cell_A3" s:attribute="ref">A3</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A3"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(142,104.5)" s:width="30" s:height="20" id="cell_A4"><text x="15" y="-4" class="nodelabel cell_A4" s:attribute="ref">A4</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A4"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(272,44.5)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="79" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="42" x2="52" y1="97" y2="97" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="97" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="79" y1="47" y2="47" class="net_3 width_1" style="stroke-width: 1"/><line x1="107" x2="144" y1="39.5" y2="39.5" class="net_7 width_1" style="stroke-width: 1"/><line x1="107" x2="117" y1="107" y2="107" class="net_4 width_1" style="stroke-width: 1"/><line x1="117" x2="117" y1="107" y2="54.5" class="net_4 width_1" style="stroke-width: 1"/><line x1="117" x2="144" y1="54.5" y2="54.5" class="net_4 width_1" style="stroke-width: 1"/><line x1="172" x2="209" y1="47" y2="47" class="net_8 width_1" style="stroke-width: 1"/><line x1="172" x2="182" y1="114.5" y2="114.5" class="net_5 width_1" style="stroke-width: 1"/><line x1="182" x2="182" y1="114.5" y2="62" class="net_5 width_1" style="stroke-width: 1"/><line x1="182" x2="209" y1="62" y2="62" class="net_5 width_1" style="stroke-width: 1"/><line x1="237" x2="272" y1="54.5" y2="54.5" class="net_6 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_1.rst b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_1.rst
index 5f7b1a4..b046428 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_1.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__or4_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__or4_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__or4_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__or4_1 layout**
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_1.schematic.png b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_1.schematic.png
deleted file mode 100644
index 0d4d547..0000000
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_2.rst b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_2.rst
index aa40f45..c40a10b 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_2.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__or4_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__or4_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__or4_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__or4_2 layout**
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_2.schematic.png b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_2.schematic.png
deleted file mode 100644
index 0d4d547..0000000
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_4.rst b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_4.rst
index fe8fa77..24daba4 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_4.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__or4_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__or4_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or4.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__or4_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__or4_4 layout**
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_4.schematic.png b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_4.schematic.png
deleted file mode 100644
index 0d4d547..0000000
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/sdffq/definition.json b/cells/sdffq/definition.json
new file mode 100644
index 0000000..91cb17e
--- /dev/null
+++ b/cells/sdffq/definition.json
@@ -0,0 +1,53 @@
+{
+    "description": "positive edge triggered scan D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__sdffq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "sdffq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLK",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SE",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SI",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__sdffq"
+}
\ No newline at end of file
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq.schematic.svg b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq.schematic.svg
new file mode 100644
index 0000000..c7bcd53
--- /dev/null
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="560" height="294"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_1.rst b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_1.rst
index bc52e44..1cb3fc9 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_1.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffq_1 layout**
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_2.rst b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_2.rst
index bda5183..6a26108 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_2.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffq_2 layout**
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_4.rst b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_4.rst
index 32cbae3..4bca7be 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_4.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffq_4 layout**
diff --git a/cells/sdffrnq/definition.json b/cells/sdffrnq/definition.json
new file mode 100644
index 0000000..c7f8869
--- /dev/null
+++ b/cells/sdffrnq/definition.json
@@ -0,0 +1,59 @@
+{
+    "description": "positive edge triggered scan D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__sdffrnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "sdffrnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLK",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "RN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SE",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SI",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__sdffrnq"
+}
\ No newline at end of file
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq.schematic.svg b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq.schematic.svg
new file mode 100644
index 0000000..1e3911d
--- /dev/null
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1.rst
index 588aeb1..759578a 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1 layout**
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2.rst
index b2b855c..b889c94 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2 layout**
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4.rst
index 1dd4e85..e2eebd7 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4 layout**
diff --git a/cells/sdffrsnq/definition.json b/cells/sdffrsnq/definition.json
new file mode 100644
index 0000000..96280ce
--- /dev/null
+++ b/cells/sdffrsnq/definition.json
@@ -0,0 +1,65 @@
+{
+    "description": "positive edge triggered scan D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__sdffrsnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "sdffrsnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLK",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "RN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SE",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SETN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SI",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__sdffrsnq"
+}
\ No newline at end of file
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq.schematic.svg b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq.schematic.svg
new file mode 100644
index 0000000..508b3ed
--- /dev/null
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_1.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_1.rst
index a154ea9..d0276e7 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_1.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_1 layout**
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_2.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_2.rst
index 1b20717..3d6a7ff 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_2.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_2 layout**
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_4.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_4.rst
index 709bc6b..a574280 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_4.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_4 layout**
diff --git a/cells/sdffsnq/definition.json b/cells/sdffsnq/definition.json
new file mode 100644
index 0000000..0a1385e
--- /dev/null
+++ b/cells/sdffsnq/definition.json
@@ -0,0 +1,59 @@
+{
+    "description": "positive edge triggered scan D-type flip flop",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__sdffsnq",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "sdffsnq",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "CLK",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "D",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SE",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SETN",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "SI",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Q",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__sdffsnq"
+}
\ No newline at end of file
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq.schematic.svg b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq.schematic.svg
new file mode 100644
index 0000000..7901da6
--- /dev/null
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
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+  fill:#000;
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diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_1.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_1.rst
index 266bfa6..d050f5e 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_1.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffsnq_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffsnq_1 layout**
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2.rst
index 83edbdf..60e4932 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2 layout**
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4.rst
index bcc1cc3..b9eb900 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffsnq.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4 layout**
diff --git a/cells/tieh/definition.json b/cells/tieh/definition.json
new file mode 100644
index 0000000..447c77d
--- /dev/null
+++ b/cells/tieh/definition.json
@@ -0,0 +1,29 @@
+{
+    "description": "high level generator",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__tieh",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "tieh",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__tieh"
+}
\ No newline at end of file
diff --git a/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst b/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst
index d77ae60..2465029 100644
--- a/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst
+++ b/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__tieh schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__tieh.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__tieh.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__tieh schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__tieh layout**
diff --git a/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.schematic.png b/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.schematic.png
deleted file mode 100644
index c119742..0000000
--- a/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.schematic.svg b/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.schematic.svg
new file mode 100644
index 0000000..95fdf51
--- /dev/null
+++ b/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.schematic.svg
@@ -0,0 +1,23 @@
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+  stroke:#000;
+  fill:none;
+}
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+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
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+}</style><g s:type="outputExt" transform="translate(78,22)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="constant" transform="translate(12,22)" s:width="30" s:height="20" id="cell_1"><text x="15" y="-4" class="nodelabel cell_1" s:attribute="ref">1</text><s:alias val="$_constant_"/><rect width="30" height="20" class="cell_1"/><g s:x="31" s:y="10" s:pid="Y"/></g><line x1="43" x2="78" y1="32" y2="32" class="net_0 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/tiel/definition.json b/cells/tiel/definition.json
new file mode 100644
index 0000000..0c7d89e
--- /dev/null
+++ b/cells/tiel/definition.json
@@ -0,0 +1,29 @@
+{
+    "description": "low level generator",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__tiel",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "tiel",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__tiel"
+}
\ No newline at end of file
diff --git a/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst b/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst
index e044866..5a40e8c 100644
--- a/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst
+++ b/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__tiel schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__tiel.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__tiel.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__tiel schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__tiel layout**
diff --git a/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.schematic.png b/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.schematic.png
deleted file mode 100644
index 80d1863..0000000
--- a/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.schematic.svg b/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.schematic.svg
new file mode 100644
index 0000000..11510dd
--- /dev/null
+++ b/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="120" height="54"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="outputExt" transform="translate(78,22)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><g s:type="constant" transform="translate(12,22)" s:width="30" s:height="20" id="cell_0"><text x="15" y="-4" class="nodelabel cell_0" s:attribute="ref">0</text><s:alias val="$_constant_"/><rect width="30" height="20" class="cell_0"/><g s:x="31" s:y="10" s:pid="Y"/></g><line x1="43" x2="78" y1="32" y2="32" class="net_0 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/xnor2/definition.json b/cells/xnor2/definition.json
new file mode 100644
index 0000000..49c49bf
--- /dev/null
+++ b/cells/xnor2/definition.json
@@ -0,0 +1,41 @@
+{
+    "description": "2-input exclusive NOR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__xnor2",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "xnor2",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__xnor2"
+}
\ No newline at end of file
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2.schematic.svg b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2.schematic.svg
new file mode 100644
index 0000000..5c5979b
--- /dev/null
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="315" height="140"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(143,12)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:24$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:24$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(143,98)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:36$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:36$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,43)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:0$4"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:0$4"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:0$4"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,108)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:0$5"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:0$5"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:0$5"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(208,90.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:38$3"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xnor2.v:38$3"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,108)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,43)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(273,93)" s:width="30" s:height="20" id="cell_ZN"><text x="15" y="-4" class="nodelabel cell_ZN" s:attribute="ref">ZN</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_ZN"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="42" x2="52" y1="53" y2="53" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="53" y2="21" class="net_3 width_1" style="stroke-width: 1"/><line x1="52" x2="118" y1="21" y2="21" class="net_3 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="21" y2="17" class="net_3 width_1" style="stroke-width: 1"/><circle cx="52" cy="53" r="2" style="fill:#000" class="net_3 width_1"/><line x1="118" x2="143" y1="17" y2="17" class="net_3 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="53" y2="53" class="net_3 width_1" style="stroke-width: 1"/><line x1="42" x2="62" y1="118" y2="118" class="net_2 width_1" style="stroke-width: 1"/><line x1="62" x2="62" y1="118" y2="32" class="net_2 width_1" style="stroke-width: 1"/><circle cx="62" cy="118" r="2" style="fill:#000" class="net_2 width_1"/><line x1="62" x2="143" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="118" y2="118" class="net_2 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="53" y2="53" class="net_6 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="53" y2="103" class="net_6 width_1" style="stroke-width: 1"/><line x1="118" x2="143" y1="103" y2="103" class="net_6 width_1" style="stroke-width: 1"/><line x1="105" x2="143" y1="118" y2="118" class="net_7 width_1" style="stroke-width: 1"/><line x1="173" x2="183" y1="24.5" y2="24.5" class="net_5 width_1" style="stroke-width: 1"/><line x1="183" x2="183" y1="24.5" y2="95.5" class="net_5 width_1" style="stroke-width: 1"/><line x1="183" x2="210" y1="95.5" y2="95.5" class="net_5 width_1" style="stroke-width: 1"/><line x1="173" x2="210" y1="110.5" y2="110.5" class="net_8 width_1" style="stroke-width: 1"/><line x1="238" x2="273" y1="103" y2="103" class="net_4 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.rst b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.rst
index 6ad8a75..359e283 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor2_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor2_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xnor2_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor2_1 layout**
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.schematic.png b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.schematic.png
deleted file mode 100644
index 16d11d5..0000000
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.rst b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.rst
index c6f44a8..32d3da2 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor2_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor2_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xnor2_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor2_2 layout**
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.schematic.png b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.schematic.png
deleted file mode 100644
index 16d11d5..0000000
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_4.rst b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_4.rst
index efc93bb..c537539 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_4.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor2_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor2_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xnor2_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor2_4 layout**
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_4.schematic.png b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_4.schematic.png
deleted file mode 100644
index 16d11d5..0000000
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/xnor3/definition.json b/cells/xnor3/definition.json
new file mode 100644
index 0000000..6bc11ae
--- /dev/null
+++ b/cells/xnor3/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "3-input exclusive NOR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__xnor3",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "xnor3",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "ZN",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__xnor3"
+}
\ No newline at end of file
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3.schematic.svg b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3.schematic.svg
new file mode 100644
index 0000000..2492772
--- /dev/null
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="516" height="324.5"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
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val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xnor3.v:50$10"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(409,34.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xnor3.v:50$11"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xnor3.v:50$11"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(279,19.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xnor3.v:50$9"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias 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diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_1.rst b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_1.rst
index 5156640..ada8e10 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_1.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor3_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor3_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xnor3_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor3_1 layout**
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_1.schematic.png b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_1.schematic.png
deleted file mode 100644
index a547030..0000000
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_2.rst b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_2.rst
index f77deba..c6d541a 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_2.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor3_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor3_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xnor3_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor3_2 layout**
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_2.schematic.png b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_2.schematic.png
deleted file mode 100644
index a547030..0000000
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.rst b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.rst
index ed16234..9d532d0 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor3_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor3_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xnor3_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xnor3_4 layout**
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.schematic.png b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.schematic.png
deleted file mode 100644
index a547030..0000000
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/xor2/definition.json b/cells/xor2/definition.json
new file mode 100644
index 0000000..844e26a
--- /dev/null
+++ b/cells/xor2/definition.json
@@ -0,0 +1,41 @@
+{
+    "description": "2-input exclusive OR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__xor2",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "xor2",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__xor2"
+}
\ No newline at end of file
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2.schematic.svg b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2.schematic.svg
new file mode 100644
index 0000000..bf31080
--- /dev/null
+++ b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="315" height="134"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(143,37)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor2.v:28$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor2.v:28$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(143,97)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor2.v:36$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor2.v:36$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="not" transform="translate(78,22)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xor2.v:0$4"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xor2.v:0$4"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xor2.v:0$4"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="not" transform="translate(78,87)" s:width="30" s:height="20" id="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xor2.v:0$5"><s:alias val="$_NOT_"/><s:alias val="$not"/><s:alias val="$logic_not"/><path d="M0,0 L0,20 L20,10 Z" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xor2.v:0$5"/><circle cx="24" cy="10" r="3" class="cell_$not$gf180mcu_fd_sc_mcu7t5v0__xor2.v:0$5"/><g s:x="-1" s:y="10" s:pid="A"/><g s:x="27" s:y="10" s:pid="Y"/></g><g s:type="or" transform="translate(208,89.5)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xor2.v:38$3"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xor2.v:38$3"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A2"><text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_A1"><text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text><s:alias val="$_inputExt_"/><path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/><g s:x="30" s:y="10" s:pid="Y"/></g><g s:type="outputExt" transform="translate(273,92)" s:width="30" s:height="20" id="cell_Z"><text x="15" y="-4" class="nodelabel cell_Z" s:attribute="ref">Z</text><s:alias val="$_outputExt_"/><path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_Z"/><g s:x="0" s:y="10" s:pid="A"/></g><line x1="105" x2="118" y1="32" y2="32" class="net_5 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="32" y2="42" class="net_5 width_1" style="stroke-width: 1"/><line x1="118" x2="143" y1="42" y2="42" class="net_5 width_1" style="stroke-width: 1"/><line x1="42" x2="62" y1="97" y2="97" class="net_3 width_1" style="stroke-width: 1"/><line x1="62" x2="62" y1="97" y2="57" class="net_3 width_1" style="stroke-width: 1"/><circle cx="62" cy="97" r="2" style="fill:#000" class="net_3 width_1"/><line x1="62" x2="143" y1="57" y2="57" class="net_3 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="97" y2="97" class="net_3 width_1" style="stroke-width: 1"/><line x1="105" x2="118" y1="97" y2="97" class="net_7 width_1" style="stroke-width: 1"/><line x1="118" x2="118" y1="97" y2="102" class="net_7 width_1" style="stroke-width: 1"/><line x1="118" x2="143" y1="102" y2="102" class="net_7 width_1" style="stroke-width: 1"/><line x1="42" x2="52" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="52" x2="52" y1="32" y2="117" class="net_2 width_1" style="stroke-width: 1"/><circle cx="52" cy="32" r="2" style="fill:#000" class="net_2 width_1"/><line x1="52" x2="143" y1="117" y2="117" class="net_2 width_1" style="stroke-width: 1"/><line x1="42" x2="77" y1="32" y2="32" class="net_2 width_1" style="stroke-width: 1"/><line x1="173" x2="183" y1="49.5" y2="49.5" class="net_6 width_1" style="stroke-width: 1"/><line x1="183" x2="183" y1="49.5" y2="94.5" class="net_6 width_1" style="stroke-width: 1"/><line x1="183" x2="210" y1="94.5" y2="94.5" class="net_6 width_1" style="stroke-width: 1"/><line x1="173" x2="210" y1="109.5" y2="109.5" class="net_8 width_1" style="stroke-width: 1"/><line x1="238" x2="273" y1="102" y2="102" class="net_4 width_1" style="stroke-width: 1"/></svg>
\ No newline at end of file
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.rst b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.rst
index 5b21ba1..89cd830 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xor2_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xor2_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xor2_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xor2_1 layout**
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.schematic.png b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.schematic.png
deleted file mode 100644
index 47b7a37..0000000
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_2.rst b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_2.rst
index 71ef10f..97be791 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_2.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xor2_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xor2_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xor2_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xor2_2 layout**
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_2.schematic.png b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_2.schematic.png
deleted file mode 100644
index 47b7a37..0000000
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_4.rst b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_4.rst
index 4d4beed..a5f2b19 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_4.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xor2_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xor2_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor2.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xor2_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xor2_4 layout**
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_4.schematic.png b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_4.schematic.png
deleted file mode 100644
index 47b7a37..0000000
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_4.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/xor3/definition.json b/cells/xor3/definition.json
new file mode 100644
index 0000000..b79691b
--- /dev/null
+++ b/cells/xor3/definition.json
@@ -0,0 +1,47 @@
+{
+    "description": "3-input exclusive OR",
+    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__xor3",
+    "library": "gf180mcu_fd_sc_mcu7t5v0",
+    "name": "xor3",
+    "parameters": [],
+    "ports": [
+        [
+            "signal",
+            "A1",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A2",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "A3",
+            "input",
+            ""
+        ],
+        [
+            "signal",
+            "Z",
+            "output",
+            ""
+        ],
+        [
+            "power",
+            "VDD",
+            "input",
+            "supply1"
+        ],
+        [
+            "power",
+            "VSS",
+            "input",
+            "supply0"
+        ]
+    ],
+    "type": "cell",
+    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__xor3"
+}
\ No newline at end of file
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__or3_4.rst b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__or3_4.rst
index cae236d..00ef4a6 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__or3_4.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__or3_4.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xor3_4 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xor3_4.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xor3_4 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xor3_4 layout**
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3.schematic.svg b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3.schematic.svg
new file mode 100644
index 0000000..0014f89
--- /dev/null
+++ b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3.schematic.svg
@@ -0,0 +1,23 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="516" height="330"><style>svg {
+  stroke:#000;
+  fill:none;
+}
+text {
+  fill:#000;
+  stroke:none;
+  font-size:10px;
+  font-weight: bold;
+  font-family: "Courier New", monospace;
+}
+line {
+    stroke-linecap: round;
+}
+.nodelabel {
+  text-anchor: middle;
+}
+.inputPortLabel {
+  text-anchor: end;
+}
+.splitjoinBody {
+  fill:#000;
+}</style><g s:type="and" transform="translate(148.66666666666666,12)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor3.v:24$1"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor3.v:24$1"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(214,19.5)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor3.v:24$2"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor3.v:24$2"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(148.66666666666666,149.5)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor3.v:36$3"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor3.v:36$3"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(214,79.5)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor3.v:36$4"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias val="$reduce_and"/><path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor3.v:36$4"/><g s:x="0" s:y="5" s:pid="A"/><g s:x="0" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="and" transform="translate(214,214.5)" s:width="30" s:height="25" id="cell_$and$gf180mcu_fd_sc_mcu7t5v0__xor3.v:44$5"><s:alias val="$and"/><s:alias val="$logic_and"/><s:alias val="$_AND_"/><s:alias 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val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xor3.v:50$10"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(409,42)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xor3.v:50$11"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias val="$_OR_"/><s:alias val="$reduce_or"/><s:alias val="$reduce_bool"/><path d="M0,0 A30 25 0 0 1 0,25 A30 25 0 0 0 30,12.5 A30 25 0 0 0 0,0" class="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xor3.v:50$11"/><g s:x="2" s:y="5" s:pid="A"/><g s:x="2" s:y="20" s:pid="B"/><g s:x="30" s:y="12.5" s:pid="Y"/></g><g s:type="or" transform="translate(279,27)" s:width="30" s:height="25" id="cell_$or$gf180mcu_fd_sc_mcu7t5v0__xor3.v:50$9"><s:alias val="$or"/><s:alias val="$logic_or"/><s:alias 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diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_1.rst b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_1.rst
index 005191d..f7b2645 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_1.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_1.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xor3_1 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xor3_1.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xor3_1 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xor3_1 layout**
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_1.schematic.png b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_1.schematic.png
deleted file mode 100644
index a560040..0000000
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_1.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_2.rst b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_2.rst
index ca3e10d..8b59dc8 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_2.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_2.rst
@@ -9,7 +9,7 @@
 
 **gf180mcu_fd_sc_mcu7t5v0__xor3_2 schematic**
 
-.. image:: gf180mcu_fd_sc_mcu7t5v0__xor3_2.schematic.png
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor3.schematic.svg
     :alt: gf180mcu_fd_sc_mcu7t5v0__xor3_2 schematic
 
 **gf180mcu_fd_sc_mcu7t5v0__xor3_2 layout**
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_2.schematic.png b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_2.schematic.png
deleted file mode 100644
index a560040..0000000
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_2.schematic.png
+++ /dev/null
Binary files differ
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_4.schematic.png b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_4.schematic.png
deleted file mode 100644
index a560040..0000000
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_4.schematic.png
+++ /dev/null
Binary files differ