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Physical Specifications
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Process Scheme (#Poly/#Metal)     1P1M
Device Type                       5V NMOS & 5V PMOS
Drawn Gate Length PMOS/NMOS(um)   0.50/0.60
Layer of Poly                     1
Well Option                       Outside DNWELL
Layer Grid (um)                   0.005
Tracks per Cell                   7
Cell Height (um)                  3.92
Vertical/Horizontal Pin Grid (um) 0.56
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