Remove image includes.
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
diff --git a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x1.rst b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x1.rst
index 87cd929..16bd888 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x1.rst
+++ b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__addf_x1 layout
-.. include:: images.rst
+
ADDF_X1 is a Full Adder, 1X drive strength
diff --git a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x2.rst b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x2.rst
index 61ebf22..71e43d2 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x2.rst
+++ b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__addf_x2 layout
-.. include:: images.rst
+
ADDF_X2 is a Full Adder, 2X drive strength
diff --git a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x4.rst b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x4.rst
index 6e92c96..2731df1 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x4.rst
+++ b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__addf_x4 layout
-.. include:: images.rst
+
ADDF_X4 is a Full Adder, 4X drive strength
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x1.rst b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x1.rst
index 7b632e3..b363bae 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x1.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__addh_x1 layout
-.. include:: images.rst
+
ADDH_X1 is a Half Adder, 1X drive strength
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x2.rst b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x2.rst
index ab7359e..67eb02f 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x2.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__addh_x2 layout
-.. include:: images.rst
+
ADDH_X2 is a Half Adder, 2X drive strength
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x4.rst b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x4.rst
index a4d74d5..3d9a0e1 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x4.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__addh_x4 layout
-.. include:: images.rst
+
ADDH_X4 is a Half Adder, 4X drive strength
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x1.rst b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x1.rst
index ade8715..f62f0a1 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x1.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__and2_x1 layout
-.. include:: images.rst
+
AND2_X1 is a 2-input AND, AND(A1,A2), 1X drive strength
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x2.rst b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x2.rst
index 0593070..f435e8b 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x2.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__and2_x2 layout
-.. include:: images.rst
+
AND2_X2 is a 2-input AND, AND(A1,A2), 2X drive strength
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x4.rst b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x4.rst
index 9e248cd..ca5ca1e 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x4.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__and2_x4 layout
-.. include:: images.rst
+
AND2_X4 is a 2-input AND, AND(A1,A2), 4X drive strength
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x1.rst b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x1.rst
index de43d34..4542963 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x1.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__and3_x1 layout
-.. include:: images.rst
+
AND3_X1 is a 3-input AND, AND(A1,A2,A3), 1X drive strength
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x2.rst b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x2.rst
index de9eae7..2408917 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x2.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__and3_x2 layout
-.. include:: images.rst
+
AND3_X2 is a 3-input AND, AND(A1,A2,A3), 2X drive strength
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x4.rst b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x4.rst
index a8531ef..7398cd9 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x4.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__and3_x4 layout
-.. include:: images.rst
+
AND3_X4 is a 3-input AND, AND(A1,A2,A3), 4X drive strength
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x1.rst b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x1.rst
index 43078ab..9ef90f5 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x1.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__and4_x1 layout
-.. include:: images.rst
+
AND4_X1 is a 4-input AND, AND(A1,A2,A3,A4), 1X drive strength
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x2.rst b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x2.rst
index ece8f5e..3e8cfc5 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x2.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__and4_x2 layout
-.. include:: images.rst
+
AND4_X2 is a 4-input AND, AND(A1,A2,A3,A4), 2X drive strength
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x4.rst b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x4.rst
index 3905d24..07e2136 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x4.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__and4_x4 layout
-.. include:: images.rst
+
AND4_X4 is a 4-input AND, AND(A1,A2,A3,A4), 4X drive strength
diff --git a/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst b/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst
index 1f29945..cca6c4b 100644
--- a/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst
+++ b/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__antenna layout
-.. include:: images.rst
+
ANTENNA is an antenna cell
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x1.rst b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x1.rst
index fe4f113..4c6363a 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x1.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi21_x1 layout
-.. include:: images.rst
+
AOI21_X1 is a 2-input AND into 2-input NOR, NOR[AND(A1,A2),B], 1X drive strength
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x2.rst b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x2.rst
index ab2b08b..9fc88a4 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x2.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi21_x2 layout
-.. include:: images.rst
+
AOI21_X2 is a 2-input AND into 2-input NOR, NOR[AND(A1,A2),B], 2X drive strength
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x4.rst b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x4.rst
index c81bc51..82eb017 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x4.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi21_x4 layout
-.. include:: images.rst
+
AOI21_X4 is a 2-input AND into 2-input NOR, NOR[AND(A1,A2),B], 4X drive strength
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x1.rst b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x1.rst
index e4db174..7351b71 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x1.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi211_x1 layout
-.. include:: images.rst
+
AOI211_X1 is a 2-input AND into 3-input NOR, NOR[AND(A1,A2),B,C], 1X drive strength
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x2.rst b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x2.rst
index 645e6d4..f3015ce 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x2.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi211_x2 layout
-.. include:: images.rst
+
AOI211_X2 is a 2-input AND into 3-input NOR, NOR[AND(A1,A2),B,C], 2X drive strength
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x4.rst b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x4.rst
index 08e3a74..b765896 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x4.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi211_x4 layout
-.. include:: images.rst
+
AOI211_X4 is a 2-input AND into 3-input NOR, NOR[AND(A1,A2),B,C], 4X drive strength
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x1.rst b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x1.rst
index 51fdc8e..b1237ec 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x1.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi22_x1 layout
-.. include:: images.rst
+
AOI22_X1 is a two 2-input AND into 2-input NOR, NOR[AND(A1,A2),AND(B1,B2)], 1X drive strength
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x2.rst b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x2.rst
index 75f64b3..4d630b9 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x2.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi22_x2 layout
-.. include:: images.rst
+
AOI22_X2 is a two 2-input AND into 2-input NOR, NOR[AND(A1,A2),AND(B1,B2)], 2X drive strength
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x4.rst b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x4.rst
index 5a5b7c6..b2f2967 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x4.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi22_x4 layout
-.. include:: images.rst
+
AOI22_X4 is a two 2-input AND into 2-input NOR, NOR[AND(A1,A2),AND(B1,B2)], 4X drive strength
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x1.rst b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x1.rst
index 871e167..fd24397 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x1.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi221_x1 layout
-.. include:: images.rst
+
AOI221_X1 is a two 2-input AND into 3-input NOR, NOR[AND(A1,A2),AND(B1,B2),C], 1X drive strength
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x2.rst b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x2.rst
index a7ad6fa..560c3b2 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x2.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi221_x2 layout
-.. include:: images.rst
+
AOI221_X2 is a two 2-input AND into 3-input NOR, NOR[AND(A1,A2),AND(B1,B2),C], 2X drive strength
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x4.rst b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x4.rst
index 39a96cf..1255f53 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x4.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi221_x4 layout
-.. include:: images.rst
+
AOI221_X4 is a two 2-input AND into 3-input NOR, NOR[AND(A1,A2),AND(B1,B2),C], 4X drive strength
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x1.rst b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x1.rst
index 768ce3a..30a0f89 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x1.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi222_x1 layout
-.. include:: images.rst
+
AOI222_X1 is a three 2-input AND into 3-input NOR, NOR[AND(A1,A2),AND(B1,B2),AND(C1,C2)], 1X drive strength
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x2.rst b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x2.rst
index a4e45d8..f6c8509 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x2.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi222_x2 layout
-.. include:: images.rst
+
AOI222_X2 is a three 2-input AND into 3-input NOR, NOR[AND(A1,A2),AND(B1,B2),AND(C1,C2)], 2X drive strength
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x4.rst b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x4.rst
index bc616a5..9063b23 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x4.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__aoi222_x4 layout
-.. include:: images.rst
+
AOI222_X4 is a three 2-input AND into 3-input NOR, NOR[AND(A1,A2),AND(B1,B2),AND(C1,C2)], 4X drive strength
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x1.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x1.rst
index d4d3f47..aeacbf6 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x1.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__buf_x1 layout
-.. include:: images.rst
+
BUF_X1 is a buffer, 1X drive strength
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x12.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x12.rst
index 5e80b37..2ff1fe2 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x12.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x12.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__buf_x12 layout
-.. include:: images.rst
+
BUF_X12 is a buffer, 12X drive strength
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x16.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x16.rst
index 1c078f9..88d0420 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x16.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x16.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__buf_x16 layout
-.. include:: images.rst
+
BUF_X16 is a buffer, 16X drive strength
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x2.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x2.rst
index 23908b5..748e724 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x2.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__buf_x2 layout
-.. include:: images.rst
+
BUF_X2 is a buffer, 2X drive strength
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x20.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x20.rst
index 73b1733..f074de9 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x20.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x20.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__buf_x20 layout
-.. include:: images.rst
+
BUF_X20 is a buffer, 20X drive strength
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x3.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x3.rst
index 5cf1ed2..ef0416b 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x3.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x3.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__buf_x3 layout
-.. include:: images.rst
+
BUF_X3 is a buffer, 3X drive strength
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x4.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x4.rst
index ea62ae2..c7e8ff4 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x4.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__buf_x4 layout
-.. include:: images.rst
+
BUF_X4 is a buffer, 4X drive strength
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x8.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x8.rst
index dccd5b2..9d667a3 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x8.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x8.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__buf_x8 layout
-.. include:: images.rst
+
BUF_X8 is a buffer, 8X drive strength
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x1.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x1.rst
index b0e1649..c314318 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x1.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__bufz_x1 layout
-.. include:: images.rst
+
BUFZ_X1 is a tri-state buffer, 1X drive strength
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x12.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x12.rst
index f389e91..682f312 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x12.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x12.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__bufz_x12 layout
-.. include:: images.rst
+
BUFZ_X12 is a tri-state buffer, 12X drive strength
|
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x16.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x16.rst
index 1f7896f..2237bcd 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x16.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x16.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__bufz_x16 layout
-.. include:: images.rst
+
BUFZ_X16 is a tri-state buffer, 16X drive strength
|
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x2.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x2.rst
index c0f183d..e53ac96 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x2.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__bufz_x2 layout
-.. include:: images.rst
+
BUFZ_X2 is a tri-state buffer, 2X drive strength
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x3.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x3.rst
index 3fcdd5b..3fe3c26 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x3.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x3.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__bufz_x3 layout
-.. include:: images.rst
+
BUFZ_X3 is a tri-state buffer, 3X drive strength
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x4.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x4.rst
index 30a41e0..c55c2c8 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x4.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__bufz_x4 layout
-.. include:: images.rst
+
BUFZ_X4 is a tri-state buffer, 4X drive strength
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x8.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x8.rst
index 89e8387..f589dbf 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x8.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x8.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__bufz_x8 layout
-.. include:: images.rst
+
BUFZ_X8 is a tri-state buffer, 8X drive strength
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x1.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x1.rst
index 15c67c2..468981b 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x1.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_x1 layout
-.. include:: images.rst
+
CLKBUF_X1 is a clock buffer, 1X drive strength
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12.rst
index 4d3f89a..d8458ac 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12 layout
-.. include:: images.rst
+
CLKBUF_X12 is a clock buffer, 12X drive strength
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16.rst
index 7e76243..a03380f 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16 layout
-.. include:: images.rst
+
CLKBUF_X16 is a clock buffer, 16X drive strength
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x2.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x2.rst
index 696de25..479c707 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x2.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_x2 layout
-.. include:: images.rst
+
CLKBUF_X2 is a clock buffer, 2X drive strength
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20.rst
index fb092d2..879c566 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20 layout
-.. include:: images.rst
+
CLKBUF_X20 is a clock buffer, 20X drive strength
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x3.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x3.rst
index edff5a6..439566f 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x3.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x3.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_x3 layout
-.. include:: images.rst
+
CLKBUF_X3 is a clock buffer, 3X drive strength
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x4.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x4.rst
index 9641f21..20f5463 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x4.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_x4 layout
-.. include:: images.rst
+
CLKBUF_X4 is a clock buffer, 4X drive strength
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x8.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x8.rst
index 99d13be..3986b1e 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x8.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x8.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkbuf_x8 layout
-.. include:: images.rst
+
CLKBUF_X8 is a clock buffer, 8X drive strength
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x1.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x1.rst
index 179c1ba..6ee6c70 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x1.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_x1 layout
-.. include:: images.rst
+
CLKINV_X1 is a clock inverter, 1X drive strength
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x12.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x12.rst
index 9cf81e4..1a3494a 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x12.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x12.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_x12 layout
-.. include:: images.rst
+
CLKINV_X12 is a clock inverter, 12X drive strength
|
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x16.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x16.rst
index 34e016e..ca415fc 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x16.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x16.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_x16 layout
-.. include:: images.rst
+
CLKINV_X16 is a clock inverter, 16X drive strength
|
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x2.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x2.rst
index 9cd7c36..c6752a0 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x2.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_x2 layout
-.. include:: images.rst
+
CLKINV_X2 is a clock inverter, 2X drive strength
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x20.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x20.rst
index 14b85c6..cd4d60d 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x20.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x20.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_x20 layout
-.. include:: images.rst
+
CLKINV_X20 is a clock inverter, 20X drive strength
|
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x3.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x3.rst
index ffcf3d1..0be872f 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x3.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x3.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_x3 layout
-.. include:: images.rst
+
CLKINV_X3 is a clock inverter, 3X drive strength
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x4.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x4.rst
index 33ee2c1..a5d2fe8 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x4.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_x4 layout
-.. include:: images.rst
+
CLKINV_X4 is a clock inverter, 4X drive strength
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x8.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x8.rst
index ca5b344..1853d67 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x8.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x8.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__clkinv_x8 layout
-.. include:: images.rst
+
CLKINV_X8 is a clock inverter, 8X drive strength
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x1.rst b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x1.rst
index 6a8ded7..dea4dc5 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x1.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnq_x1 layout
-.. include:: images.rst
+
DFFNQ_X1 is a negative edge triggered D-type flip flop, 1X drive strength
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x2.rst b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x2.rst
index fefb9f0..4fe989c 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x2.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnq_x2 layout
-.. include:: images.rst
+
DFFNQ_X2 is a negative edge triggered D-type flip flop, 2X drive strength
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x4.rst b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x4.rst
index 088f71b..0719292 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x4.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnq_x4 layout
-.. include:: images.rst
+
DFFNQ_X4 is a negative edge triggered D-type flip flop, 4X drive strength
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x1.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x1.rst
index f11da78..43c10bc 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x1.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x1 layout
-.. include:: images.rst
+
DFFNRNQ_X1 is a negative edge triggered D-type flip flop, active low reset and 1X drive strength
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x2.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x2.rst
index 80c9c8e..04aeafd 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x2.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x2 layout
-.. include:: images.rst
+
DFFNRNQ_X2 is a negative edge triggered D-type flip flop, active low reset and 2X drive strength
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x4.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x4.rst
index 10b1d2c..ddfc3d0 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x4.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x4 layout
-.. include:: images.rst
+
DFFNRNQ_X4 is a negative edge triggered D-type flip flop, active low reset and 4X drive strength
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x1.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x1.rst
index 67d77c6..162fb2f 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x1.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x1 layout
-.. include:: images.rst
+
DFFNRSNQ_X1 is a negative edge triggered D-type flip flop, active low set/reset and 1X drive strength
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x2.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x2.rst
index 0c5c9b5..47b7cf0 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x2.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x2 layout
-.. include:: images.rst
+
DFFNRSNQ_X2 is a negative edge triggered D-type flip flop, active low set/reset and 2X drive strength
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x4.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x4.rst
index fc020fc..dacd56e 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x4.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x4 layout
-.. include:: images.rst
+
DFFNRSNQ_X4 is a negative edge triggered D-type flip flop, active low set/reset and 4X drive strength
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x1.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x1.rst
index 3c75b8a..2378e52 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x1.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x1 layout
-.. include:: images.rst
+
DFFNSNQ_X1 is a negative edge triggered D-type flip flop, active low set and 1X drive strength
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x2.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x2.rst
index a0854f7..4d8e9f9 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x2.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x2 layout
-.. include:: images.rst
+
DFFNSNQ_X2 is a negative edge triggered D-type flip flop, active low set and 2X drive strength
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x4.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x4.rst
index d1c5140..3bf23c4 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x4.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x4 layout
-.. include:: images.rst
+
DFFNSNQ_X4 is a negative edge triggered D-type flip flop, active low set and 4X drive strength
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x1.rst b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x1.rst
index affee4c..fa703cb 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x1.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffq_x1 layout
-.. include:: images.rst
+
DFFQ_X1 is a poistive edge triggered D-type flip flop, 1X drive strength
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x2.rst b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x2.rst
index a062f48..4fc64ef 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x2.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffq_x2 layout
-.. include:: images.rst
+
DFFQ_X2 is a poistive edge triggered D-type flip flop, 2X drive strength
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x4.rst b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x4.rst
index 2dffa62..accff6a 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x4.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffq_x4 layout
-.. include:: images.rst
+
DFFQ_X4 is a poistive edge triggered D-type flip flop, 4X drive strength
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x1.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x1.rst
index 7297e3e..f8e1f57 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x1.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffrnq_x1 layout
-.. include:: images.rst
+
DFFRNQ_X1 is a positive edge triggered D-type flip flop, active low reset, 1X drive strength
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x2.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x2.rst
index e6716e9..7e70eed 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x2.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffrnq_x2 layout
-.. include:: images.rst
+
DFFRNQ_X2 is a positive edge triggered D-type flip flop, active low reset, 2X drive strength
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x4.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x4.rst
index 5a9ec64..344f59c 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x4.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffrnq_x4 layout
-.. include:: images.rst
+
DFFRNQ_X4 is a positive edge triggered D-type flip flop, active low reset, 4X drive strength
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x1.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x1.rst
index b34ac1a..bd5a216 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x1.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x1 layout
-.. include:: images.rst
+
DFFRSNQ_X1 is a positive edge triggered D-type flip flop, active low set/reset, 1X drive strength
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x2.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x2.rst
index 1c80a6c..60ca1cc 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x2.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x2 layout
-.. include:: images.rst
+
DFFRSNQ_X2 is a positive edge triggered D-type flip flop, active low set/reset, 2X drive strength
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x4.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x4.rst
index 634c0b0..642f26a 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x4.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x4 layout
-.. include:: images.rst
+
DFFRSNQ_X4 is a positive edge triggered D-type flip flop, active low set/reset, 4X drive strength
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x1.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x1.rst
index ffccbca..d34707f 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x1.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffsnq_x1 layout
-.. include:: images.rst
+
DFFSNQ_X1 is a positive edge triggered D-type flip flop, active low set, 1X drive strength
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x2.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x2.rst
index 92e085c..dbd556a 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x2.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffsnq_x2 layout
-.. include:: images.rst
+
DFFSNQ_X2 is a positive edge triggered D-type flip flop, active low set, 2X drive strength
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x4.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x4.rst
index b46e8c3..e65db69 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x4.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dffsnq_x4 layout
-.. include:: images.rst
+
DFFSNQ_X4 is a positive edge triggered D-type flip flop, active low set, 4X drive strength
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x1.rst b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x1.rst
index 665c7de..e5202cc 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x1.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlya_x1 layout
-.. include:: images.rst
+
DLYA_X1 is a 2 buffer delay cell, 1X drive strength
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x2.rst b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x2.rst
index d5f27ad..54ec686 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x2.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlya_x2 layout
-.. include:: images.rst
+
DLYA_X2 is a 2 buffer delay cell, 2X drive strength
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x4.rst b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x4.rst
index 89ed8ff..a5e037d 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x4.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlya_x4 layout
-.. include:: images.rst
+
DLYA_X4 is a 2 buffer delay cell, 4X drive strength
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x1.rst b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x1.rst
index 4f7a262..339eea4 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x1.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlyb_x1 layout
-.. include:: images.rst
+
DLYB_X1 is a 4 buffer delay cell, 1X drive strength
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x2.rst b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x2.rst
index a777402..902cbe1 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x2.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlyb_x2 layout
-.. include:: images.rst
+
DLYB_X2 is a 4 buffer delay cell, 2X drive strength
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x4.rst b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x4.rst
index da9d166..fab2af8 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x4.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlyb_x4 layout
-.. include:: images.rst
+
DLYB_X4 is a 4 buffer delay cell, 4X drive strength
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x1.rst b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x1.rst
index a1eded6..8ba644b 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x1.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlyc_x1 layout
-.. include:: images.rst
+
DLYC_X1 is a 8 buffer delay cell, 1X drive strength
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x2.rst b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x2.rst
index ffbd84c..3027cb1 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x2.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlyc_x2 layout
-.. include:: images.rst
+
DLYC_X2 is a 8 buffer delay cell, 2X drive strength
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x4.rst b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x4.rst
index e4e0b1d..3d28319 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x4.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlyc_x4 layout
-.. include:: images.rst
+
DLYC_X4 is a 8 buffer delay cell, 4X drive strength
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x1.rst b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x1.rst
index f7e478b..89a9342 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x1.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlyd_x1 layout
-.. include:: images.rst
+
DLYD_X1 is a 16 buffer delay cell, 1X drive strength
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x2.rst b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x2.rst
index 5eec3e6..ecb95ce 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x2.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlyd_x2 layout
-.. include:: images.rst
+
DLYD_X2 is a 16 buffer delay cell, 2X drive strength
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x4.rst b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x4.rst
index 769e3bc..2a77685 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x4.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__dlyd_x4 layout
-.. include:: images.rst
+
DLYD_X4 is a 16 buffer delay cell, 4X drive strength
diff --git a/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst b/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst
index 1c09f91..213ea36 100644
--- a/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst
+++ b/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__endcap layout
-.. include:: images.rst
+
ENDCAP is a row end closure cell
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x1.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x1.rst
index af70697..2408a6e 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x1.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fill_x1 layout
-.. include:: images.rst
+
| FILL_X1 is a filler whose cell width is 0.56um
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x16.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x16.rst
index ed1548d..be4da59 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x16.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x16.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fill_x16 layout
-.. include:: images.rst
+
| FILL_X16 is a filler whose cell width is 8.96um
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x2.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x2.rst
index 6f4a8aa..7f2b615 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x2.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fill_x2 layout
-.. include:: images.rst
+
| FILL_X2 is a filler whose cell width is is 1.12um
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x32.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x32.rst
index 4676106..c0d99ea 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x32.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x32.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fill_x32 layout
-.. include:: images.rst
+
| FILL_X32 is a filler whose cell width is 17.92um
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x4.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x4.rst
index c2a75a0..cfd86ae 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x4.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fill_x4 layout
-.. include:: images.rst
+
| FILL_X4 is a filler whose cell width is 2.24um
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x64.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x64.rst
index 08e09a7..1d016ec 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x64.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x64.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fill_x64 layout
-.. include:: images.rst
+
| FILL_X64 is a filler whose cell width is 35.84um
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x8.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x8.rst
index 0c760d6..aae9551 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x8.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x8.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fill_x8 layout
-.. include:: images.rst
+
| FILL_X8 is a filler whose cell width is 4.48um
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x16.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x16.rst
index 0615080..35a81ed 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x16.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x16.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fillcap_x16 layout
-.. include:: images.rst
+
FILLCAP_X16 is a filler whose cell width is 8.96um with decoupling cap between VDD and VSS
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x32.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x32.rst
index 1e1d361..b789783 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x32.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x32.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fillcap_x32 layout
-.. include:: images.rst
+
| FILLCAP_X32 is a filler whose cell width is 17.92um with decoupling cap between VDD and VSS
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x4.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x4.rst
index 2effd85..4e033d3 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x4.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fillcap_x4 layout
-.. include:: images.rst
+
| FILLCAP_X4 is a filler whose cell width is 2.24um with decoupling cap between VDD and VSS
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x64.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x64.rst
index 10fc0f9..9fbdd6b 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x64.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x64.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fillcap_x64 layout
-.. include:: images.rst
+
| FILLCAP_X64 is a filler whose cell width is 35.84um with decoupling cap between VDD and VSS
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x8.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x8.rst
index a28a647..9f60428 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x8.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x8.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__fillcap_x8 layout
-.. include:: images.rst
+
| FILLCAP_X8 is a filler whose width is 4.48um with decoupling cap between VDD and VSS
diff --git a/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst b/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst
index d1a2b17..061cd03 100644
--- a/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst
+++ b/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__filltie layout
-.. include:: images.rst
+
| FILLTIE is a filler with well and substrate tap
diff --git a/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst b/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst
index f20b856..2d343fc 100644
--- a/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst
+++ b/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__hold layout
-.. include:: images.rst
+
HOLD is a state holder cell
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x1.rst b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x1.rst
index a9d5c0d..293194d 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x1.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__icgtn_x1 layout
-.. include:: images.rst
+
ICGTN_X1 is a negative-edge triggered clock-gating latch, 1X drive strength
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x2.rst b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x2.rst
index 7b8ad78..604c5d5 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x2.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__icgtn_x2 layout
-.. include:: images.rst
+
ICGTN_X2 is a negative-edge triggered clock-gating latch, 2X drive strength
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x4.rst b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x4.rst
index 92e2d0f..5eba836 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x4.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__icgtn_x4 layout
-.. include:: images.rst
+
ICGTN_X4 is a negative-edge triggered clock-gating latch, 4X drive strength
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x1.rst b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x1.rst
index 25e6d3c..a55354a 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x1.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__icgtp_x1 layout
-.. include:: images.rst
+
ICGTP_X1 is a positive-edge triggered clock-gating latch, 1X drive strength
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x2.rst b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x2.rst
index cf78974..4b688e0 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x2.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__icgtp_x2 layout
-.. include:: images.rst
+
ICGTP_X2 is a positive-edge triggered clock-gating latch, 2X drive strength
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x4.rst b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x4.rst
index 0582f68..fee812a 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x4.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__icgtp_x4 layout
-.. include:: images.rst
+
ICGTP_X4 is a positive-edge triggered clock-gating latch, 4X drive strength
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x1.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x1.rst
index 3edb7fa..c1d071d 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x1.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__inv_x1 layout
-.. include:: images.rst
+
INV_X1 is an inverter, 1X drive strength
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x12.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x12.rst
index 136d0c2..95698aa 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x12.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x12.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__inv_x12 layout
-.. include:: images.rst
+
INV_X12 is an inverter, 12X drive strength
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x16.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x16.rst
index 3b413b5..bcfc1da 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x16.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x16.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__inv_x16 layout
-.. include:: images.rst
+
INV_X16 is an inverter, 16X drive strength
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x2.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x2.rst
index 4d90de8..770056d 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x2.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__inv_x2 layout
-.. include:: images.rst
+
INV_X2 is an inverter, 2X drive strength
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x20.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x20.rst
index 99e9183..df2cc99 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x20.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x20.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__inv_x20 layout
-.. include:: images.rst
+
INV_X20 is an inverter, 20X drive strength
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x3.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x3.rst
index 320065e..0f9a22d 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x3.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x3.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__inv_x3 layout
-.. include:: images.rst
+
INV_X3 is an inverter, 3X drive strength
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x4.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x4.rst
index b419bfa..b9c70ac 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x4.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__inv_x4 layout
-.. include:: images.rst
+
INV_X4 is an inverter, 4X drive strength
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x8.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x8.rst
index 4896e9a..f1fdc79 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x8.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x8.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__inv_x8 layout
-.. include:: images.rst
+
INV_X8 is an inverter, 8X drive strength
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x1.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x1.rst
index f742ddd..a36f451 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x1.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__invz_x1 layout
-.. include:: images.rst
+
INVZ_X1 is a tri-state inverter, 1X drive strength
|
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x12.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x12.rst
index 965a687..5e95bfe 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x12.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x12.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__invz_x12 layout
-.. include:: images.rst
+
INVZ_X12 is a tri-state inverter, 12X drive strength
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x16.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x16.rst
index e7dfbc2..0249584 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x16.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x16.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__invz_x16 layout
-.. include:: images.rst
+
INVZ_X16 is a tri-state inverter, 16X drive strength
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x2.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x2.rst
index 0ea401e..1929eb8 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x2.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__invz_x2 layout
-.. include:: images.rst
+
INVZ_X2 is a tri-state inverter, 2X drive strength
|
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x3.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x3.rst
index 00bf967..7300010 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x3.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x3.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__invz_x3 layout
-.. include:: images.rst
+
INVZ_X3 is a tri-state inverter, 3X drive strength
|
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x4.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x4.rst
index 5099079..0305642 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x4.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__invz_x4 layout
-.. include:: images.rst
+
INVZ_X4 is a tri-state inverter, 4X drive strength
|
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x8.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x8.rst
index 7cd0700..ec39c3f 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x8.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x8.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__invz_x8 layout
-.. include:: images.rst
+
INVZ_X8 is a tri-state inverter, 8X drive strength
|
diff --git a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x1.rst b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x1.rst
index 2ef8e36..f56c6b5 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x1.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latq_x1 layout
-.. include:: images.rst
+
LATQ_X1 is a positive D-latch, 1X drive strength
diff --git a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x2.rst b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x2.rst
index ff7a533..5e5f2f3 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x2.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latq_x2 layout
-.. include:: images.rst
+
LATQ_X2 is a positive D-latch, 2X drive strength
diff --git a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x4.rst b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x4.rst
index e04a83c..b002121 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x4.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latq_x4 layout
-.. include:: images.rst
+
LATQ_X4 is a positive D-latch, 4X drive strength
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x1.rst b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x1.rst
index 9368559..95b8d7f 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x1.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latrnq_x1 layout
-.. include:: images.rst
+
LATRNQ_X1 is a positive D-latch, active low reset, 1X drive strength
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x2.rst b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x2.rst
index b8c1aaf..9370be6 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x2.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latrnq_x2 layout
-.. include:: images.rst
+
LATRNQ_X2 is a positive D-latch, active low reset, 2X drive strength
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x4.rst b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x4.rst
index bcfe503..e3b9d0c 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x4.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latrnq_x4 layout
-.. include:: images.rst
+
LATRNQ_X4 is a positive D-latch, active low reset, 4X drive strength
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x1.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x1.rst
index ba514fd..1bc22fe 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x1.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latrsnq_x1 layout
-.. include:: images.rst
+
LATRSNQ_X1 is a positive D-latch, active low set/reset, 1X drive strength
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x2.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x2.rst
index 59661ec..19085e2 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x2.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latrsnq_x2 layout
-.. include:: images.rst
+
LATRSNQ_X2 is a positive D-latch, active low set/reset, 2X drive strength
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x4.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x4.rst
index 963e854..91770ca 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x4.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latrsnq_x4 layout
-.. include:: images.rst
+
LATRSNQ_X4 is a positive D-latch, active low set/reset, 4X drive strength
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x1.rst b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x1.rst
index 99865ba..57d2e46 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x1.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latsnq_x1 layout
-.. include:: images.rst
+
LATSNQ_X1 is a positive D-latch, active low set, 1X drive strength
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x2.rst b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x2.rst
index c61c16e..3aca247 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x2.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latsnq_x2 layout
-.. include:: images.rst
+
LATSNQ_X2 is a positive D-latch, active low set, 2X drive strength
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x4.rst b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x4.rst
index fca6662..b6241ec 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x4.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__latsnq_x4 layout
-.. include:: images.rst
+
LATSNQ_X4 is a positive D-latch, active low set, 4X drive strength
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x1.rst b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x1.rst
index d47dcf0..d8c1a14 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x1.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__mux2_x1 layout
-.. include:: images.rst
+
MUX2_X1 is a 2-to-1 multiplexer, 1X drive strength
|
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x2.rst b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x2.rst
index 69ab13f..4184514 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x2.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__mux2_x2 layout
-.. include:: images.rst
+
MUX2_X2 is a 2-to-1 multiplexer, 2X drive strength
|
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x4.rst b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x4.rst
index 84e8958..37fa665 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x4.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__mux2_x4 layout
-.. include:: images.rst
+
MUX2_X4 is a 2-to-1 multiplexer, 4X drive strength
|
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x1.rst b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x1.rst
index 5c9a662..e7bccd2 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x1.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__mux4_x1 layout
-.. include:: images.rst
+
MUX4_X1 is a 4-to-1 multiplexer, 1X drive strength
|
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x2.rst b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x2.rst
index 39530be..8472a96 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x2.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__mux4_x2 layout
-.. include:: images.rst
+
MUX4_X2 is a 4-to-1 multiplexer, 2X drive strength
|
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x4.rst b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x4.rst
index e65e8ed..ff561bd 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x4.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__mux4_x4 layout
-.. include:: images.rst
+
MUX4_X4 is a 4-to-1 multiplexer, 4X drive strength
|
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x1.rst b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x1.rst
index 4276c74..e70454d 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x1.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nand2_x1 layout
-.. include:: images.rst
+
NAND2_X1 is a 2-input NAND, NAND(A1,A2), 1X drive strength
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x2.rst b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x2.rst
index eac1df9..aa184f3 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x2.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nand2_x2 layout
-.. include:: images.rst
+
NAND2_X2 is a 2-input NAND, NAND(A1,A2), 2X drive strength
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x4.rst b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x4.rst
index 53e35d8..30a782d 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x4.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nand2_x4 layout
-.. include:: images.rst
+
NAND2_X4 is a 2-input NAND, NAND(A1,A2), 4X drive strength
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x1.rst b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x1.rst
index a3ceee8..054d186 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x1.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nand3_x1 layout
-.. include:: images.rst
+
NAND3_X1 is a 3-input NAND, NAND(A1,A2,A3), 1X drive strength
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x2.rst b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x2.rst
index f7d66f9..deee3b0 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x2.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nand3_x2 layout
-.. include:: images.rst
+
NAND3_X2 is a 3-input NAND, NAND(A1,A2,A3), 2X drive strength
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x4.rst b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x4.rst
index 4bce107..7554eda 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x4.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nand3_x4 layout
-.. include:: images.rst
+
NAND3_X4 is a 3-input NAND, NAND(A1,A2,A3), 4X drive strength
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x1.rst b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x1.rst
index eb9c03a..2865a4f 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x1.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nand4_x1 layout
-.. include:: images.rst
+
NAND4_X1 is a 4-input NAND, NAND(A1,A2,A3,A4), 1X drive strength
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x2.rst b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x2.rst
index 51912e2..e7e4c94 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x2.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nand4_x2 layout
-.. include:: images.rst
+
NAND4_X2 is a 4-input NAND, NAND(A1,A2,A3,A4), 2X drive strength
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x4.rst b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x4.rst
index 5bc2ec7..af60ef7 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x4.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nand4_x4 layout
-.. include:: images.rst
+
NAND4_X4 is a 4-input NAND, NAND(A1,A2,A3,A4), 4X drive strength
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x1.rst b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x1.rst
index 4b28999..84fbb5d 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x1.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nor2_x1 layout
-.. include:: images.rst
+
NOR2_X1 is a 2-input NOR, NOR(A1,A2), 1X drive strength
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x2.rst b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x2.rst
index 9346603..1342b18 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x2.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nor2_x2 layout
-.. include:: images.rst
+
NOR2_X2 is a 2-input NOR, NOR(A1,A2), 2X drive strength
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x4.rst b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x4.rst
index b9be6f6..e549c2c 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x4.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nor2_x4 layout
-.. include:: images.rst
+
NOR2_X4 is a 2-input NOR, NOR(A1,A2), 4X drive strength
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x1.rst b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x1.rst
index c2c0f9d..9488ca8 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x1.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nor3_x1 layout
-.. include:: images.rst
+
NOR3_X1 is a 3-input NOR, NOR(A1,A2,A3), 1X drive strength
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x2.rst b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x2.rst
index 0d32638..5029d85 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x2.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nor3_x2 layout
-.. include:: images.rst
+
NOR3_X2 is a 3-input NOR, NOR(A1,A2,A3), 2X drive strength
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x4.rst b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x4.rst
index 249d384..2e51acd 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x4.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nor3_x4 layout
-.. include:: images.rst
+
NOR3_X4 is a 3-input NOR, NOR(A1,A2,A3), 4X drive strength
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x1.rst b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x1.rst
index 0275473..3187b02 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x1.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nor4_x1 layout
-.. include:: images.rst
+
NOR4_X1 is a 4-input NOR, NOR(A1,A2,A3,A4), 1X drive strength
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x2.rst b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x2.rst
index b8b819a..672c973 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x2.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nor4_x2 layout
-.. include:: images.rst
+
NOR4_X2 is a 4-input NOR, NOR(A1,A2,A3,A4), 2X drive strength
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x4.rst b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x4.rst
index fdb9eab..1427131 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x4.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__nor4_x4 layout
-.. include:: images.rst
+
NOR4_X4 is a 4-input NOR, NOR(A1,A2,A3,A4), 4X drive strength
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x1.rst b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x1.rst
index 9854acc..5959b70 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x1.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai21_x1 layout
-.. include:: images.rst
+
OAI21_X1 is a 2-input OR into 2-input NAND, NAND[OR(A1,A2),B], 1X drive strength
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x2.rst b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x2.rst
index 0aa285d..9f1666d 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x2.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai21_x2 layout
-.. include:: images.rst
+
OAI21_X2 is a 2-input OR into 2-input NAND, NAND[OR(A1,A2),B], 2X drive strength
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x4.rst b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x4.rst
index 45dd9d3..db84422 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x4.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai21_x4 layout
-.. include:: images.rst
+
OAI21_X4 is a 2-input OR into 2-input NAND, NAND[OR(A1,A2),B], 4X drive strength
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x1.rst b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x1.rst
index d7a598b..e84b42b 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x1.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai211_x1 layout
-.. include:: images.rst
+
OAI211_X1 is a 2-input OR into 3-input NAND, NAND[OR(A1,A2),B,C], 1X drive strength
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x2.rst b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x2.rst
index f9280cc..08c604a 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x2.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai211_x2 layout
-.. include:: images.rst
+
OAI211_X2 is a 2-input OR into 3-input NAND, NAND[OR(A1,A2),B,C], 2X drive strength
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x4.rst b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x4.rst
index b034a4b..2e9f205 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x4.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai211_x4 layout
-.. include:: images.rst
+
OAI211_X4 is a 2-input OR into 3-input NAND, NAND[OR(A1,A2),B,C], 4X drive strength
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x1.rst b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x1.rst
index 0916485..4d86980 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x1.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai22_x1 layout
-.. include:: images.rst
+
OAI22_X1 is a two 2-input OR into 2-input NAND, NAND[OR(A1,A2),OR(B1,B2)], 1X drive strength
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x2.rst b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x2.rst
index 4d885b4..16157be 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x2.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai22_x2 layout
-.. include:: images.rst
+
OAI22_X2 is a two 2-input OR into 2-input NAND, NAND[OR(A1,A2),OR(B1,B2)], 2X drive strength
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x4.rst b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x4.rst
index 7dd1c56..7e67954 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x4.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai22_x4 layout
-.. include:: images.rst
+
OAI22_X4 is a two 2-input OR into 2-input NAND, NAND[OR(A1,A2),OR(B1,B2)], 4X drive strength
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x1.rst b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x1.rst
index 1cd2eb0..a2b545a 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x1.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai221_x1 layout
-.. include:: images.rst
+
OAI221_X1 is a two 2-input OR into 3-input NAND, NAND[OR(A1,A2),OR(B1,B2),C], 1X drive strength
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x2.rst b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x2.rst
index 0cfc03b..6a9feae 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x2.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai221_x2 layout
-.. include:: images.rst
+
OAI221_X2 is a two 2-input OR into 3-input NAND, NAND[OR(A1,A2),OR(B1,B2),C], 2X drive strength
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x4.rst b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x4.rst
index 3b096cb..ede3255 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x4.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai221_x4 layout
-.. include:: images.rst
+
OAI221_X4 is a two 2-input OR into 3-input NAND, NAND[OR(A1,A2),OR(B1,B2),C], 4X drive strength
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x1.rst b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x1.rst
index 6d7b0b7..c0a9b14 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x1.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai222_x1 layout
-.. include:: images.rst
+
OAI222_X1 is a three 2-input OR into 3-input NAND, NAND[OR(A1,A2),OR(B1,B2),OR(C1,C2)], 1X drive strength
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x2.rst b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x2.rst
index 148fc5f..7059614 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x2.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai222_x2 layout
-.. include:: images.rst
+
OAI222_X2 is a three 2-input OR into 3-input NAND, NAND[OR(A1,A2),OR(B1,B2),OR(C1,C2)], 2X drive strength
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x4.rst b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x4.rst
index e2be282..b1ec638 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x4.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai222_x4 layout
-.. include:: images.rst
+
OAI222_X4 is a three 2-input OR into 3-input NAND, NAND[OR(A1,A2),OR(B1,B2),OR(C1,C2)], 4X drive strength
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x1.rst b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x1.rst
index aa952c0..268bf0a 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x1.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai31_x1 layout
-.. include:: images.rst
+
OAI31_X1 is a 3-input OR into 2-input NAND, NAND[OR(A1,A2,A3),B], 1X drive strength
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x2.rst b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x2.rst
index 6d38df1..cd11bc5 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x2.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai31_x2 layout
-.. include:: images.rst
+
OAI31_X2 is a 3-input OR into 2-input NAND, NAND[OR(A1,A2,A3),B], 2X drive strength
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x4.rst b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x4.rst
index 8e65081..9f8914a 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x4.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai31_x4 layout
-.. include:: images.rst
+
OAI31_X4 is a 3-input OR into 2-input NAND, NAND[OR(A1,A2,A3),B], 4X drive strength
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x1.rst b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x1.rst
index 912e742..ff07f8b 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x1.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai32_x1 layout
-.. include:: images.rst
+
OAI32_X1 is a 3-input OR and a 2-input OR into 2-input NAND, NAND[OR(A1,A2,A3),OR(B1,B2)], 1X drive strength
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x2.rst b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x2.rst
index 59dd7cc..cec61d1 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x2.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai32_x2 layout
-.. include:: images.rst
+
OAI32_X2 is a 3-input OR and a 2-input OR into 2-input NAND, NAND[OR(A1,A2,A3),OR(B1,B2)], 2X drive strength
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x4.rst b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x4.rst
index 308a266..f86030b 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x4.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai32_x4 layout
-.. include:: images.rst
+
OAI32_X4 is a 3-input OR and a 2-input OR into 2-input NAND, NAND[OR(A1,A2,A3),OR(B1,B2)], 4X drive strength
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x1.rst b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x1.rst
index 80f94e1..773e429 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x1.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai33_x1 layout
-.. include:: images.rst
+
OAI33_X1 is a two 3-input OR into 2-input NAND, NAND[OR(A1,A2,A3),OR(B1,B2,B3], 1X drive strength
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x2.rst b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x2.rst
index 33c2d8f..bb4609a 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x2.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai33_x2 layout
-.. include:: images.rst
+
OAI33_X2 is a two 3-input OR into 2-input NAND, NAND[OR(A1,A2,A3),OR(B1,B2,B3], 2X drive strength
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x4.rst b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x4.rst
index 1369905..6b6403a 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x4.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__oai33_x4 layout
-.. include:: images.rst
+
OAI33_X4 is a two 3-input OR into 2-input NAND, NAND[OR(A1,A2,A3),OR(B1,B2,B3], 4X drive strength
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x1.rst b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x1.rst
index ec64ca9..a3a8bde 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x1.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__or2_x1 layout
-.. include:: images.rst
+
OR2_X1 is a 2-input OR(A1,A2), 1X drive strength
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x2.rst b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x2.rst
index bf2de2f..8b16164 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x2.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__or2_x2 layout
-.. include:: images.rst
+
OR2_X2 is a 2-input OR(A1,A2), 2X drive strength
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x4.rst b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x4.rst
index a5f5d14..9727c71 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x4.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__or2_x4 layout
-.. include:: images.rst
+
OR2_X4 is a 2-input OR(A1,A2), 4X drive strength
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x1.rst b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x1.rst
index 927f448..c1b1bdf 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x1.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__or3_x1 layout
-.. include:: images.rst
+
OR3_X1 is a 3-input OR(A1,A2,A3), 1X drive strength
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x2.rst b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x2.rst
index 4b1240d..deab681 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x2.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__or3_x2 layout
-.. include:: images.rst
+
OR3_X2 is a 3-input OR(A1,A2,A3), 2X drive strength
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x4.rst b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x4.rst
index 8f5ffd8..484057d 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x4.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__or3_x4 layout
-.. include:: images.rst
+
OR3_X4 is a 3-input OR(A1,A2,A3), 4X drive strength
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x1.rst b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x1.rst
index 8bb3a84..e5dbe63 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x1.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__or4_x1 layout
-.. include:: images.rst
+
OR4_X1 is a 4-input OR(A1,A2,A3,A4), 1X drive strength
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x2.rst b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x2.rst
index 3b9f662..e4a00ec 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x2.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__or4_x2 layout
-.. include:: images.rst
+
OR4_X2 is a 4-input OR(A1,A2,A3,A4), 2X drive strength
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x4.rst b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x4.rst
index 0f08e71..2ca32ac 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x4.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__or4_x4 layout
-.. include:: images.rst
+
OR4_X4 is a 4-input OR(A1,A2,A3,A4), 4X drive strength
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x1.rst b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x1.rst
index 2c5aedf..50cff57 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x1.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffq_x1 layout
-.. include:: images.rst
+
SDFFQ_X1 is a positive edge triggered scan D-type flip flop, 1X drive strength
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x2.rst b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x2.rst
index 2229bcf..493f31a 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x2.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffq_x2 layout
-.. include:: images.rst
+
SDFFQ_X2 is a positive edge triggered scan D-type flip flop, 2X drive strength
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x4.rst b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x4.rst
index 810f7c1..33ae19f 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x4.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffq_x4 layout
-.. include:: images.rst
+
SDFFQ_X4 is a positive edge triggered scan D-type flip flop, 4X drive strength
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x1.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x1.rst
index 049319a..3308510 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x1.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x1 layout
-.. include:: images.rst
+
SDFFRNQ_X1 is a positive edge triggered scan D-type flip flop, active low reset, 1X drive strength
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x2.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x2.rst
index a28913f..0cc1725 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x2.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x2 layout
-.. include:: images.rst
+
SDFFRNQ_X2 is a positive edge triggered scan D-type flip flop, active low reset, 2X drive strength
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x4.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x4.rst
index 135efb8..f7424dd 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x4.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x4 layout
-.. include:: images.rst
+
SDFFRNQ_X4 is a positive edge triggered scan D-type flip flop, active low reset, 4X drive strength
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x1.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x1.rst
index 29c6942..44a50f5 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x1.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x1 layout
-.. include:: images.rst
+
SDFFRSNQ_X1 is a positive edge triggered scan D-type flip flop, active low set/reset, 1X drive strength
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x2.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x2.rst
index ab11fcd..0fd106e 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x2.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x2 layout
-.. include:: images.rst
+
SDFFRSNQ_X2 is a positive edge triggered scan D-type flip flop, active low set/reset, 2X drive strength
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x4.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x4.rst
index c3f75cf..2a456fa 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x4.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x4 layout
-.. include:: images.rst
+
SDFFRSNQ_X4 is a positive edge triggered scan D-type flip flop, active low set/reset, 4X drive strength
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x1.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x1.rst
index 692f41a..ef47042 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x1.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x1 layout
-.. include:: images.rst
+
SDFFSNQ_X1 is a positive edge triggered scan D-type flip flop, active low set, 1X drive strength
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x2.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x2.rst
index f4077ff..5669455 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x2.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x2 layout
-.. include:: images.rst
+
SDFFSNQ_X2 is a positive edge triggered scan D-type flip flop, active low set, 2X drive strength
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x4.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x4.rst
index be76512..45ea893 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x4.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x4 layout
-.. include:: images.rst
+
SDFFSNQ_X4 is a positive edge triggered scan D-type flip flop, active low set, 4X drive strength
diff --git a/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst b/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst
index 6e0935b..caf4e57 100644
--- a/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst
+++ b/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__tieh layout
-.. include:: images.rst
+
TIEH is a high level generator
diff --git a/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst b/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst
index ac43cc4..abd6100 100644
--- a/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst
+++ b/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__tiel layout
-.. include:: images.rst
+
TIEL is a low level generator
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x1.rst b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x1.rst
index e819a05..7bbf970 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x1.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xnor2_x1 layout
-.. include:: images.rst
+
XNOR2_X1 is a 2-input exclusive NOR, 1X drive strength
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x2.rst b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x2.rst
index f812223..eb87da3 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x2.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xnor2_x2 layout
-.. include:: images.rst
+
XNOR2_X2 is a 2-input exclusive NOR, 2X drive strength
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x4.rst b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x4.rst
index 1976694..1777905 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x4.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xnor2_x4 layout
-.. include:: images.rst
+
XNOR2_X4 is a 2-input exclusive NOR, 4X drive strength
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x1.rst b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x1.rst
index dbcd03c..6432c03 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x1.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xnor3_x1 layout
-.. include:: images.rst
+
XNOR3_X1 is a 3-input exclusive NOR, 1X drive strength
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x2.rst b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x2.rst
index 80122aa..a0d8f38 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x2.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xnor3_x2 layout
-.. include:: images.rst
+
XNOR3_X2 is a 3-input exclusive NOR, 2X drive strength
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x4.rst b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x4.rst
index e85791f..1810647 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x4.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xnor3_x4 layout
-.. include:: images.rst
+
XNOR3_X4 is a 3-input exclusive NOR, 4X drive strength
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x1.rst b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x1.rst
index 8f7b266..fdf4df9 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x1.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xor2_x1 layout
-.. include:: images.rst
+
XOR2_X1 is a 2-input exclusive OR, 1X drive strength
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x2.rst b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x2.rst
index 75f28bd..34690dd 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x2.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xor2_x2 layout
-.. include:: images.rst
+
XOR2_X2 is a 2-input exclusive OR, 2X drive strength
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x4.rst b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x4.rst
index 8991116..da8e9d7 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x4.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xor2_x4 layout
-.. include:: images.rst
+
XOR2_X4 is a 2-input exclusive OR, 4X drive strength
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x1.rst b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x1.rst
index 3609df8..0048dd6 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x1.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x1.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xor3_x1 layout
-.. include:: images.rst
+
XOR3_X1 is a 3-input exclusive OR, 1X drive strength
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x2.rst b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x2.rst
index 93ad984..e622af7 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x2.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x2.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xor3_x2 layout
-.. include:: images.rst
+
XOR3_X2 is a 3-input exclusive OR, 2X drive strength
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x4.rst b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x4.rst
index 9edb2aa..086924b 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x4.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x4.rst
@@ -26,7 +26,7 @@
:align: center
:alt: gf180mcu_fd_sc_mcu7t5v0__xor3_x4 layout
-.. include:: images.rst
+
XOR3_X4 is a 3-input exclusive OR, 4X drive strength
