| { |
| "cell gf180mcu_fd_sc_mcu7t5v0__or2_2": { |
| "area": "21.952000", |
| "leakage_power ": [ |
| { |
| "related_pg_pin": "VDD", |
| "when": "!A1&!A2", |
| "value": "0.00384552" |
| }, |
| { |
| "related_pg_pin": "VDD", |
| "when": "!A1&A2", |
| "value": "0.00380412" |
| }, |
| { |
| "related_pg_pin": "VDD", |
| "when": "A1&!A2", |
| "value": "0.00379368" |
| }, |
| { |
| "related_pg_pin": "VDD", |
| "when": "A1&A2", |
| "value": "0.00376524" |
| }, |
| { |
| "related_pg_pin": "VDD", |
| "value": "0.00384552" |
| } |
| ], |
| "pg_pin VDD": { |
| "voltage_name": "VDD", |
| "pg_type": "primary_power" |
| }, |
| "pg_pin VSS": { |
| "voltage_name": "VSS", |
| "pg_type": "primary_ground" |
| }, |
| "pin A1": { |
| "capacitance": "0.004705", |
| "direction": "input", |
| "driver_waveform_rise": "driver_waveform_default_rise", |
| "driver_waveform_fall": "driver_waveform_default_fall", |
| "input_voltage": "default", |
| "max_transition": "7.4", |
| "related_ground_pin": "VSS", |
| "related_power_pin": "VDD", |
| "internal_power ": { |
| "when": "A2", |
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| } |
| } |
| }, |
| "pin A2": { |
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| "driver_waveform_fall": "driver_waveform_default_fall", |
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| "max_transition": "7.4", |
| "related_ground_pin": "VSS", |
| "related_power_pin": "VDD", |
| "internal_power ": { |
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| 0.02066, |
| 0.02065, |
| 0.02066 |
| ] |
| }, |
| "rise_power pwr_tin_10": { |
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| } |
| } |
| }, |
| "pin Z": { |
| "direction": "output", |
| "function": "(A1|A2)", |
| "max_capacitance": "0.7223", |
| "max_transition": "7.4", |
| "min_capacitance": "0.001", |
| "output_voltage": "default", |
| "related_ground_pin": "VSS", |
| "related_power_pin": "VDD", |
| "internal_power ": [ |
| { |
| "related_pin": "A1", |
| "when": "!A2", |
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| }, |
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| 0.5153, |
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| } |
| }, |
| { |
| "related_pin": "A2", |
| "when": "!A1", |
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| }, |
| "rise_power pwr_tin_oload_10x10": { |
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| } |
| } |
| ], |
| "timing ": [ |
| { |
| "related_pin": "A1", |
| "timing_sense": "positive_unate", |
| "timing_type": "combinational", |
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| ] |
| }, |
| "cell_rise tmg_ntin_oload_10x10": { |
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| 0.02, |
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| ] |
| } |
| } |
| } |
