| { | |
| "cell gf180mcu_fd_sc_mcu7t5v0__oai32_4": { | |
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| { | |
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| "pg_pin VDD": { | |
| "voltage_name": "VDD", | |
| "pg_type": "primary_power" | |
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| "pg_pin VSS": { | |
| "voltage_name": "VSS", | |
| "pg_type": "primary_ground" | |
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| "pin A1": { | |
| "capacitance": "0.0176", | |
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| "driver_waveform_rise": "driver_waveform_default_rise", | |
| "driver_waveform_fall": "driver_waveform_default_fall", | |
| "input_voltage": "default", | |
| "max_transition": "5", | |
| "related_ground_pin": "VSS", | |
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| "driver_waveform_fall": "driver_waveform_default_fall", | |
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| "max_transition": "5", | |
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| "related_power_pin": "VDD", | |
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| 0.06072, | |
| 0.0607 | |
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| }, | |
| "pin A3": { | |
| "capacitance": "0.01793", | |
| "direction": "input", | |
| "driver_waveform_rise": "driver_waveform_default_rise", | |
| "driver_waveform_fall": "driver_waveform_default_fall", | |
| "input_voltage": "default", | |
| "max_transition": "5", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
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| { | |
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| { | |
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| "rise_power pwr_tin_10": { | |
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| 5 | |
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| { | |
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| 5 | |
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| "rise_power pwr_tin_10": { | |
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| 5 | |
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| }, | |
| { | |
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| 5 | |
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| }, | |
| "rise_power pwr_tin_10": { | |
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| 5 | |
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| { | |
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| 5 | |
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| "rise_power pwr_tin_10": { | |
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| 5 | |
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| } | |
| } | |
| ] | |
| }, | |
| "pin B1": { | |
| "capacitance": "0.01884", | |
| "direction": "input", | |
| "driver_waveform_rise": "driver_waveform_default_rise", | |
| "driver_waveform_fall": "driver_waveform_default_fall", | |
| "input_voltage": "default", | |
| "max_transition": "5", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
| "internal_power ": [ | |
| { | |
| "when": "!A1&!A2&!A3&!B2", | |
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| 5 | |
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| "rise_power pwr_tin_10": { | |
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| 5 | |
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| } | |
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| "driver_waveform_fall": "driver_waveform_default_fall", | |
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| }, | |
| { | |
| "when": "A1&A2&!A3&B1", | |
| "fall_power pwr_tin_10": { | |
| "index_1": [ | |
| 0.02, | |
| 0.05437, | |
| 0.175, | |
| 0.4054, | |
| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
| "values": [ | |
| 0.1111, | |
| 0.1111, | |
| 0.111, | |
| 0.1107, | |
| 0.1112, | |
| 0.1111, | |
| 0.1111, | |
| 0.1111, | |
| 0.1112, | |
| 0.1112 | |
| ] | |
| }, | |
| "rise_power pwr_tin_10": { | |
| "index_1": [ | |
| 0.02, | |
| 0.05437, | |
| 0.175, | |
| 0.4054, | |
| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
| "values": [ | |
| -0.09482, | |
| -0.1002, | |
| -0.1065, | |
| -0.1075, | |
| -0.1088, | |
| -0.1087, | |
| -0.1093, | |
| -0.1095, | |
| -0.1096, | |
| -0.1097 | |
| ] | |
| } | |
| }, | |
| { | |
| "when": "A1&A2&A3&B1", | |
| "fall_power pwr_tin_10": { | |
| "index_1": [ | |
| 0.02, | |
| 0.05437, | |
| 0.175, | |
| 0.4054, | |
| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
| "values": [ | |
| 0.1111, | |
| 0.111, | |
| 0.111, | |
| 0.1109, | |
| 0.1113, | |
| 0.1111, | |
| 0.1113, | |
| 0.1113, | |
| 0.1112, | |
| 0.1112 | |
| ] | |
| }, | |
| "rise_power pwr_tin_10": { | |
| "index_1": [ | |
| 0.02, | |
| 0.05437, | |
| 0.175, | |
| 0.4054, | |
| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
| "values": [ | |
| -0.09477, | |
| -0.1002, | |
| -0.1065, | |
| -0.1076, | |
| -0.1089, | |
| -0.1087, | |
| -0.1093, | |
| -0.1095, | |
| -0.1096, | |
| -0.1097 | |
| ] | |
| } | |
| } | |
| ] | |
| }, | |
| "pin ZN": { | |
| "direction": "output", | |
| "function": "(((!A1)&(!A2)&(!A3))|((!B1)&(!B2)))", | |
| "max_capacitance": "0.295", | |
| "max_transition": "5", | |
| "min_capacitance": "0.001", | |
| "output_voltage": "default", | |
| "related_ground_pin": "VSS", | |
| "related_power_pin": "VDD", | |
| "internal_power ": [ | |
| { | |
| "related_pin": "A1", | |
| "when": "!A2&!A3&!B1&B2", | |
| "fall_power pwr_tin_oload_10x10": { | |
| "index_1": [ | |
| 0.02, | |
| 0.05437, | |
| 0.175, | |
| 0.4054, | |
| 0.7644, | |
| 1.268, | |
| 1.931, | |
| 2.766, | |
| 3.785, | |
| 5 | |
| ], | |
| "index_2": [ | |
| 0.001, | |