{ | |
"cell gf180mcu_fd_sc_mcu7t5v0__aoi22_4": { | |
"area": "70.246400", | |
"leakage_power ": [ | |
{ | |
"related_pg_pin": "VDD", | |
"when": "!A1&!A2&!B1&!B2", | |
"value": "2.6244e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "!A1&!A2&!B1&B2", | |
"value": "2.6244e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "!A1&!A2&B1&!B2", | |
"value": "3.718062e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "!A1&!A2&B1&B2", | |
"value": "4.429728e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "!A1&A2&!B1&!B2", | |
"value": "2.6244e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "!A1&A2&!B1&B2", | |
"value": "2.6244e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
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"value": "3.718062e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "!A1&A2&B1&B2", | |
"value": "4.443336e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "A1&!A2&!B1&!B2", | |
"value": "3.718062e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "A1&!A2&!B1&B2", | |
"value": "3.718062e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "A1&!A2&B1&!B2", | |
"value": "4.811562e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "A1&!A2&B1&B2", | |
"value": "4.443336e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "A1&A2&!B1&!B2", | |
"value": "2.713986e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "A1&A2&!B1&B2", | |
"value": "2.713986e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "A1&A2&B1&!B2", | |
"value": "2.713986e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"when": "A1&A2&B1&B2", | |
"value": "2.723382e-05" | |
}, | |
{ | |
"related_pg_pin": "VDD", | |
"value": "4.811562e-05" | |
} | |
], | |
"pg_pin VDD": { | |
"voltage_name": "VDD", | |
"pg_type": "primary_power" | |
}, | |
"pg_pin VSS": { | |
"voltage_name": "VSS", | |
"pg_type": "primary_ground" | |
}, | |
"pin A1": { | |
"capacitance": "0.01489", | |
"direction": "input", | |
"driver_waveform_rise": "driver_waveform_default_rise", | |
"driver_waveform_fall": "driver_waveform_default_fall", | |
"input_voltage": "default", | |
"max_transition": "21", | |
"related_ground_pin": "VSS", | |
"related_power_pin": "VDD", | |
"internal_power ": [ | |
{ | |
"when": "!A2&!B1&!B2", | |
"fall_power pwr_tin_10": { | |
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0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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0.01328, | |
0.01327, | |
0.01324, | |
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0.01322, | |
0.01322, | |
0.0132, | |
0.01099 | |
] | |
}, | |
"rise_power pwr_tin_10": { | |
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0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
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] | |
} | |
}, | |
{ | |
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0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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0.01329, | |
0.01326, | |
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0.01323, | |
0.01322, | |
0.01322, | |
0.01317, | |
0.01088 | |
] | |
}, | |
"rise_power pwr_tin_10": { | |
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0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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] | |
} | |
}, | |
{ | |
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0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
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0.01328, | |
0.01329, | |
0.01326, | |
0.01325, | |
0.01324, | |
0.01322, | |
0.01321, | |
0.01317, | |
0.01088 | |
] | |
}, | |
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0.1648, | |
0.6731, | |
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3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
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] | |
} | |
}, | |
{ | |
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1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
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0.004964, | |
0.004981, | |
0.00498, | |
0.005006, | |
0.005012, | |
0.00501, | |
0.005006, | |
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"rise_power pwr_tin_10": { | |
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0.1648, | |
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1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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] | |
} | |
}, | |
{ | |
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0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
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0.01205, | |
0.01203, | |
0.01198, | |
0.01196, | |
0.01188, | |
0.01176, | |
0.01153, | |
0.01094, | |
0.007541 | |
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}, | |
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0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
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] | |
} | |
} | |
] | |
}, | |
"pin A2": { | |
"capacitance": "0.01544", | |
"direction": "input", | |
"driver_waveform_rise": "driver_waveform_default_rise", | |
"driver_waveform_fall": "driver_waveform_default_fall", | |
"input_voltage": "default", | |
"max_transition": "21", | |
"related_ground_pin": "VSS", | |
"related_power_pin": "VDD", | |
"internal_power ": [ | |
{ | |
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0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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0.01116, | |
0.01114, | |
0.01114, | |
0.01113, | |
0.01113, | |
0.01113, | |
0.01111, | |
0.009141 | |
] | |
}, | |
"rise_power pwr_tin_10": { | |
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0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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] | |
} | |
}, | |
{ | |
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0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
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}, | |
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0.1648, | |
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3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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] | |
} | |
}, | |
{ | |
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0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
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0.01116, | |
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] | |
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0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
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] | |
} | |
}, | |
{ | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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0.004975, | |
0.004979, | |
0.004982, | |
0.005012, | |
0.005011, | |
0.005009, | |
0.00501, | |
0.005009, | |
0.004508 | |
] | |
}, | |
"rise_power pwr_tin_10": { | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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-0.005001, | |
-0.005004, | |
-0.005008, | |
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-0.00502, | |
-0.004372 | |
] | |
} | |
}, | |
{ | |
"when": "A1&B1&B2", | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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0.01204, | |
0.01203, | |
0.01199, | |
0.01196, | |
0.01188, | |
0.01175, | |
0.01153, | |
0.01093, | |
0.00754 | |
] | |
}, | |
"rise_power pwr_tin_10": { | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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-0.005032, | |
-0.00503, | |
-0.004378 | |
] | |
} | |
} | |
] | |
}, | |
"pin B1": { | |
"capacitance": "0.01451", | |
"direction": "input", | |
"driver_waveform_rise": "driver_waveform_default_rise", | |
"driver_waveform_fall": "driver_waveform_default_fall", | |
"input_voltage": "default", | |
"max_transition": "21", | |
"related_ground_pin": "VSS", | |
"related_power_pin": "VDD", | |
"internal_power ": [ | |
{ | |
"when": "!A1&!A2&!B2", | |
"fall_power pwr_tin_10": { | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
"values": [ | |
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0.01325, | |
0.01324, | |
0.01322, | |
0.01323, | |
0.01321, | |
0.01321, | |
0.01321, | |
0.01319, | |
0.01108 | |
] | |
}, | |
"rise_power pwr_tin_10": { | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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] | |
} | |
}, | |
{ | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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0.01325, | |
0.01323, | |
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0.01321, | |
0.01321, | |
0.01319, | |
0.01108 | |
] | |
}, | |
"rise_power pwr_tin_10": { | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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] | |
} | |
}, | |
{ | |
"when": "A1&!A2&!B2", | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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0.01325, | |
0.01325, | |
0.01323, | |
0.01322, | |
0.01322, | |
0.01321, | |
0.0132, | |
0.01319, | |
0.01108 | |
] | |
}, | |
"rise_power pwr_tin_10": { | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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] | |
} | |
}, | |
{ | |
"when": "A1&A2&!B2", | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
], | |
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0.0111, | |
0.01109, | |
0.01107, | |
0.01112, | |
0.01112, | |
0.01112, | |
0.01112, | |
0.01112, | |
0.009292 | |
] | |
}, | |
"rise_power pwr_tin_10": { | |
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0.02, | |
0.1648, | |
0.6731, | |
1.644, | |
3.156, | |
5.278, | |
8.07, | |
11.59, | |
15.88, | |
21 | |
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"function": "(((!A1)&(!B1))|((!A1)&(!B2))|((!A2)&(!B1))|((!A2)&(!B2)))", | |
"max_capacitance": "0.3718", | |
"max_transition": "21", | |
"min_capacitance": "0.001", | |
"output_voltage": "default", | |
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"related_power_pin": "VDD", | |
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} | |
}, | |
{ | |
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