| # LVS Documentation |
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| Explains how to use the runset. |
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| ## Folder Structure |
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| ```text |
| 📦runset |
| ┣ 📦testing |
| ┣ 📜README.md |
| ┣ 📜gf_018mcu.lvs |
| ┣ 📜gf_018mcu.lyp |
| ┗ 📜run_lvs.py |
| ``` |
| |
| ## Rule Deck Usage |
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| The `run_lvs.py` script takes a gds file and a netlist to run LVS rule deck of GF180 technology with switches to select subsets of all checks. |
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| ### **Switches** |
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| 1. **GF180MCU**=A : combined options of metal_level=3, mim_option=A, metal_top=30K, poly_res=1K, and mim_cap=2 |
| 2. **GF180MCU**=B : combined options of metal_level=4, mim_option=B, metal_top=11K, poly_res=1K, and mim_cap=2 |
| 3. **GF180MCU**=C : combined options of metal_level=5, mim_option=B, metal_top=9K, poly_res=1K, and mim_cap=2 |
| |
| ### Usage |
| |
| ```bash |
| run_lvs.py (--help| -h) |
| run_lvs.py (--design=<layout_path>) (--net=<netlist_path>) (--gf180mcu=<combined_options>) [--thr=<thr>] [--run_mode=<run_mode>] [--metal_top=<metal_top>] [--mim_option=<mim_option>] [--metal_level=<metal_level>] [--poly_res_val=<res_val>] [--mim_cap_val=<cap_val>] [--no_net_names] [--set_spice_comments] [--set_scale] [--set_verbose] [--set_schematic_simplify] [--set_net_only] [--set_top_lvl_pins] [--set_combine] [--set_purge] [--set_purge_nets] |
| ``` |
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| Example: |
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| ```bash |
| python3 run_lvs.py --path=testing/extraction_checking/sample_nmos_3p3.gds --net=sample_nmos_3p3.spice --thr=16 --gf180mcu=B --set_verbose --set_spice_comments |
| ``` |
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| ### Options |
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| `--help -h` Print this help message. |
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| `--design=<layout_path>` The input GDS file path. |
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| `--net=<netlist_path>` The input netlist file path. |
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| `--thr=<thr>` The number of threads used in run. |
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| `run_mode=<run_mode>` Select klayout mode Allowed modes (flat , deep, tiling). [default: flat] |
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| `--gf180mcu=<combined_options>` Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C). |
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| `--no_net_names` Discard net names in extracted netlist. |
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| `--set_spice_comments` Set netlist comments in extracted netlist. |
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| `--set_scale` Set scale of 1e6 in extracted netlist. |
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| `--set_verbose` Set verbose mode. |
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| `--set_schematic_simplify` Set schematic simplification in input netlist. |
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| `--set_net_only` Set netlist object creation only in extracted netlist. |
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| `--set_top_lvl_pins` Set top level pins only in extracted netlist. |
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| `--set_combine` Set netlist combine only in extracted netlist. |
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| `--set_purge` Set netlist purge all only in extracted netlist. |
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| `--set_purge_nets` Set netlist purge nets only in extracted netlist. |
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| ### **LVS Outputs** |
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| Final results will appear at the end of the run logs. |
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| The output files are : |
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| 1. An extracted netlist (`<your_design_name>.cir`). |
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| 2. Database file (`<your_design_name>..lvdb`) for comparison results. you could view it on your file using klayout. |