# Copyright 2022 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

#=============================================================================================================================================================
#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (COMP) -------------------------------------------------------------
#=============================================================================================================================================================

require 'time'
require "logger"

exec_start_time = Time.now

logger = Logger.new(STDOUT)

logger.formatter = proc do |severity, datetime, progname, msg|
  "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg}
"
end

#================================================
#----------------- FILE SETUP -------------------
#================================================

# optional for a batch launch :   klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb

logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input])

if $input
    if $topcell
        source($input, $topcell)
    else
        source($input)
    end
end

logger.info("Loading database to memory is complete.")

if $report
    logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report])
    report("DRC Run Report at", $report)
else
    logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path])
    report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb"))
end

if $thr
    logger.info("Number of threads to use %s" % [$thr])
    threads($thr)
else
    logger.info("Number of threads to use 16")
    threads(16)
end

# === TILING MODE ===
if $run_mode == "tiling"
  # use a tile size of 1mm - not used in deep mode-
  # tiles(500.um)
  # use a tile border of 10 micron:
  # tile_borders(10.um)
  tiles(1000)
  logger.info("Tiling  mode is enabled.")

elsif $run_mode == "deep"
  #=== HIER MODE ===
  deep
  logger.info("deep  mode is enabled.")

elsif $run_mode == "flat"
  #=== FLAT MODE ===
  flat
  logger.info("flat  mode is enabled.")

else
  #=== FLAT MODE ===
  flat
  logger.info("flat  mode is enabled.")

end # run_mode

#================================================
#------------- LAYERS DEFINITIONS ---------------
#================================================

v5_xtor        = polygons(112, 1 )
dualgate       = polygons(55 , 0 )
poly2          = polygons(30 , 0 )
nplus          = polygons(32 , 0 )
pplus          = polygons(31 , 0 )
comp           = polygons(22 , 0 )
dnwell         = polygons(12 , 0 )
nwell          = polygons(21 , 0 )
lvpwell        = polygons(204, 0 )
mvsd           = polygons(210, 0 )
mvpsd          = polygons(11 , 39)
schottky_diode = polygons(241, 0 )
res_mk         = polygons(110, 5 )
cap_mk         = polygons(117, 5 )
mos_cap_mk     = polygons(166, 5 )
drc_bjt        = polygons(127, 5 )
otp_mk         = polygons(173, 5 )
neo_ee_mk      = polygons(88 , 17)
sramcore       = polygons(108, 5 )
ymtp_mk        = polygons(86 , 17)

logger.info("Starting deriving base layers.")
#================================================
#------------- LAYERS DERIVATIONS ---------------
#================================================

ncomp      =  comp      & nplus
pcomp      =  comp      & pplus
tgate      =  poly2     & comp
ngate      =  nplus     & tgate
pgate      =  pplus     & tgate

#================================================
#------------------ SWITCHES --------------------
#================================================
logger.info("Evaluate switches.")

# FEOL
if $feol == "false"
  FEOL = $feol
  logger.info("FEOL is disabled.")
else
  FEOL = "true"
  logger.info("FEOL is enabled.")
end # FEOL

# BEOL
if $beol == "false"
  BEOL = $beol
  logger.info("BEOL is disabled.")
else
  BEOL = "true"
  logger.info("BEOL is enabled.")
end # BEOL

# connectivity rules
if $conn_drc == "true"
  CONNECTIVITY_RULES = $conn_drc
  logger.info("connectivity rules are enabled.")
else
  CONNECTIVITY_RULES = false
  logger.info("connectivity rules are disabled.")
end # connectivity rules

# METAL_TOP
if $metal_top
  METAL_TOP = $metal_top
else
  METAL_TOP = "9K"
end # METAL_TOP

logger.info("METAL_TOP Selected is %s" % [METAL_TOP])

# METAL_LEVEL
if $metal_level
  METAL_LEVEL = $metal_level
else
  METAL_LEVEL = "6LM"
end # METAL_LEVEL

logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL])

# WEDGE
if $wedge == "false"
  WEDGE = $wedge
else
  WEDGE = "true"
end # WEDGE

logger.info("Wedge enabled  %s" % [WEDGE])

# BALL
if $ball == "false"
  BALL = $ball
else
  BALL = "true"
end # BALL

logger.info("Ball enabled  %s" % [BALL])

# GOLD
if $gold == "false"
  GOLD = $gold
else
  GOLD = "true"
end # GOLD

logger.info("Gold enabled  %s" % [GOLD])

if $mim_option
  MIM_OPTION = $mim_option
else
  MIM_OPTION = "Nan"
end

logger.info("MIM Option selected %s" % [MIM_OPTION])

# OFFGRID
if $offgrid == "false"
  OFFGRID = false
else
  OFFGRID = true
end # OFFGRID

logger.info("Offgrid enabled  %s" % [OFFGRID])

#================================================
#----------------------COMP----------------------
#================================================


if FEOL
logger.info("FEOL section")

# Rule FATAL.FATAL: Nplus can’t overlap with pplus
logger.info("Executing rule FATAL.FATAL")
fatalfatal_l1 = nplus.and(pplus)
fatalfatal_l1.output("FATAL.FATAL", "FATAL.FATAL : Nplus can’t overlap with pplus")
fatalfatal_l1.forget

# Rule DF.1a_3.3V: Min. COMP Width. is 0.22µm
logger.info("Executing rule DF.1a_3.3V")
df1a_l1  = comp.width(0.22.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df1a_l1.output("DF.1a_3.3V", "DF.1a_3.3V : Min. COMP Width. : 0.22µm")
df1a_l1.forget

# Rule DF.1a_5V: Min. COMP Width. is 0.3µm
logger.info("Executing rule DF.1a_5V")
df1a_l1  = comp.not_inside(mvsd).not_inside(mvpsd).width(0.3.um, euclidian).polygons(0.001).overlapping(dualgate)
df1a_l1.output("DF.1a_5V", "DF.1a_5V : Min. COMP Width. : 0.3µm")
df1a_l1.forget

# rule DF.1b_3.3V is not a DRC check

# rule DF.1b_5V is not a DRC check

# Rule DF.1c_3.3V: Min. COMP Width for MOSCAP. is 1µm
logger.info("Executing rule DF.1c_3.3V")
df1c_l1  = comp.and(mos_cap_mk).width(1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df1c_l1.output("DF.1c_3.3V", "DF.1c_3.3V : Min. COMP Width for MOSCAP. : 1µm")
df1c_l1.forget

# Rule DF.1c_5V: Min. COMP Width for MOSCAP. is 1µm
logger.info("Executing rule DF.1c_5V")
df1c_l1  = comp.and(mos_cap_mk).width(1.um, euclidian).polygons(0.001).overlapping(dualgate)
df1c_l1.output("DF.1c_5V", "DF.1c_5V : Min. COMP Width for MOSCAP. : 1µm")
df1c_l1.forget

df_2a = comp.not(poly2).edges.and(tgate.edges)
# Rule DF.2a_3.3V: Min Channel Width. is nil,0.22µm
logger.info("Executing rule DF.2a_3.3V")
df2a_l1 = df_2a.with_length(nil,0.22.um).extended(0, 0, 0.001, 0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df2a_l1.output("DF.2a_3.3V", "DF.2a_3.3V : Min Channel Width. : nil,0.22µm")
df2a_l1.forget

# Rule DF.2a_5V: Min Channel Width. is nil,0.3µm
logger.info("Executing rule DF.2a_5V")
df2a_l1 = df_2a.with_length(nil,0.3.um).extended(0, 0, 0.001, 0.001).overlapping(dualgate)
df2a_l1.output("DF.2a_5V", "DF.2a_5V : Min Channel Width. : nil,0.3µm")
df2a_l1.forget

df_2a.forget
df_2b = comp.drc(width <= 100.um).polygons(0.001).not_inside(mos_cap_mk)
# Rule DF.2b_3.3V: Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.
logger.info("Executing rule DF.2b_3.3V")
df2b_l1 = comp.not_inside(mos_cap_mk).not_interacting(df_2b).not_interacting(v5_xtor).not_interacting(dualgate)
df2b_l1.output("DF.2b_3.3V", "DF.2b_3.3V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.")
df2b_l1.forget

# Rule DF.2b_5V: Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.
logger.info("Executing rule DF.2b_5V")
df2b_l1 = comp.not_inside(mos_cap_mk).not_interacting(df_2b).overlapping(dualgate)
df2b_l1.output("DF.2b_5V", "DF.2b_5V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.")
df2b_l1.forget

df_2b.forget
# Rule DF.3a_3.3V: Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. is 0.28µm
logger.info("Executing rule DF.3a_3.3V")
df3a_l1  = comp.not(otp_mk).space(0.28.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df3a_l1.output("DF.3a_3.3V", "DF.3a_3.3V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.28µm")
df3a_l1.forget

# Rule DF.3a_5V: Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. is 0.36µm
logger.info("Executing rule DF.3a_5V")
df3a_l1  = comp.not(otp_mk).space(0.36.um, euclidian).polygons(0.001).overlapping(dualgate)
df3a_l1.output("DF.3a_5V", "DF.3a_5V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.36µm")
df3a_l1.forget

df_3b_same_well = ncomp.inside(nwell).not_outside(pcomp.inside(nwell)).or(ncomp.inside(lvpwell).not_outside(pcomp.inside(lvpwell)))
df_3b_moscap = ncomp.inside(nwell).interacting(pcomp.inside(nwell)).or(ncomp.inside(lvpwell).interacting(pcomp.inside(lvpwell))).inside(mos_cap_mk)
# Rule DF.3b_3.3V: Min./Max. NCOMP Space to PCOMP in the same well for butted COMP (MOSCAP butting is not allowed).
logger.info("Executing rule DF.3b_3.3V")
df3b_l1 = df_3b_same_well.or(df_3b_moscap).not_interacting(v5_xtor).not_interacting(dualgate)
df3b_l1.output("DF.3b_3.3V", "DF.3b_3.3V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP (MOSCAP butting is not allowed).")
df3b_l1.forget

# Rule DF.3b_5V: Min./Max. NCOMP Space to PCOMP in the same well for butted COMP(MOSCAP butting is not allowed).
logger.info("Executing rule DF.3b_5V")
df3b_l1 = df_3b_same_well.or(df_3b_moscap).overlapping(dualgate)
df3b_l1.output("DF.3b_5V", "DF.3b_5V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP(MOSCAP butting is not allowed).")
df3b_l1.forget

df_3b_same_well.forget
df_3b_moscap.forget
# Rule DF.3c_3.3V: Min. COMP Space in BJT area (area marked by DRC_BJT layer). is 0.32µm
logger.info("Executing rule DF.3c_3.3V")
df3c_l1  = comp.inside(drc_bjt).space(0.32.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df3c_l1.output("DF.3c_3.3V", "DF.3c_3.3V : Min. COMP Space in BJT area (area marked by DRC_BJT layer). : 0.32µm")
df3c_l1.forget

# Rule DF.3c_5V: Min. COMP Space in BJT area (area marked by DRC_BJT layer) hasn’t been assessed.
logger.info("Executing rule DF.3c_5V")
df3c_l1 = comp.interacting(comp.inside(drc_bjt).and(dualgate).space(10.um, euclidian).polygons(0.001))
df3c_l1.output("DF.3c_5V", "DF.3c_5V : Min. COMP Space in BJT area (area marked by DRC_BJT layer) hasn’t been assessed.")
df3c_l1.forget

ntap_dnwell = ncomp.not_interacting(tgate).inside(dnwell)
# Rule DF.4a_3.3V: Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. is 0.12µm
logger.info("Executing rule DF.4a_3.3V")
df4a_l1  = ntap_dnwell.separation(lvpwell.inside(dnwell), 0.12.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df4a_l1.output("DF.4a_3.3V", "DF.4a_3.3V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.12µm")
df4a_l1.forget

# Rule DF.4a_5V: Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. is 0.16µm
logger.info("Executing rule DF.4a_5V")
df4a_l1  = ntap_dnwell.separation(lvpwell.inside(dnwell), 0.16.um, euclidian).polygons(0.001).overlapping(dualgate)
df4a_l1.output("DF.4a_5V", "DF.4a_5V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.16µm")
df4a_l1.forget

# Rule DF.4b_3.3V: Min. DNWELL overlap of NCOMP well tap. is 0.62µm
logger.info("Executing rule DF.4b_3.3V")
df4b_l1 = dnwell.enclosing(ncomp.not_interacting(tgate), 0.62.um, euclidian).polygons(0.001)
df4b_l2 = ncomp.not_interacting(tgate).not_outside(dnwell).not(dnwell)
df4b_l  = df4b_l1.or(df4b_l2).not_interacting(v5_xtor).not_interacting(dualgate)
df4b_l.output("DF.4b_3.3V", "DF.4b_3.3V : Min. DNWELL overlap of NCOMP well tap. : 0.62µm")
df4b_l1.forget
df4b_l2.forget
df4b_l.forget

# Rule DF.4b_5V: Min. DNWELL overlap of NCOMP well tap. is 0.66µm
logger.info("Executing rule DF.4b_5V")
df4b_l1 = dnwell.enclosing(ncomp.not_interacting(tgate), 0.66.um, euclidian).polygons(0.001)
df4b_l2 = ncomp.not_interacting(tgate).not_outside(dnwell).not(dnwell)
df4b_l  = df4b_l1.or(df4b_l2).overlapping(dualgate)
df4b_l.output("DF.4b_5V", "DF.4b_5V : Min. DNWELL overlap of NCOMP well tap. : 0.66µm")
df4b_l1.forget
df4b_l2.forget
df4b_l.forget

ntap_dnwell.forget
nwell_n_dnwell = nwell.outside(dnwell)
# Rule DF.4c_3.3V: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.43µm
logger.info("Executing rule DF.4c_3.3V")
df4c_l1 = nwell_n_dnwell.outside(sramcore).enclosing(pcomp.outside(dnwell), 0.43.um, euclidian).polygons(0.001)
df4c_l2 = pcomp.outside(dnwell).not_outside(nwell_n_dnwell.outside(sramcore)).not(nwell_n_dnwell.outside(sramcore))
df4c_l  = df4c_l1.or(df4c_l2).not_interacting(v5_xtor).not_interacting(dualgate)
df4c_l.output("DF.4c_3.3V", "DF.4c_3.3V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.43µm")
df4c_l1.forget
df4c_l2.forget
df4c_l.forget

# Rule DF.4c_5V: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.6µm
logger.info("Executing rule DF.4c_5V")
df4c_l1 = nwell_n_dnwell.outside(sramcore).enclosing(pcomp.outside(dnwell), 0.6.um, euclidian).polygons(0.001)
df4c_l2 = pcomp.outside(dnwell).not_outside(nwell_n_dnwell.outside(sramcore)).not(nwell_n_dnwell.outside(sramcore))
df4c_l  = df4c_l1.or(df4c_l2).overlapping(dualgate)
df4c_l.output("DF.4c_5V", "DF.4c_5V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.6µm")
df4c_l1.forget
df4c_l2.forget
df4c_l.forget

# Rule DF.4d_3.3V: Min. (Nwell overlap of NCOMP) outside DNWELL. is 0.12µm
logger.info("Executing rule DF.4d_3.3V")
df4d_l1 = nwell_n_dnwell.not_inside(ymtp_mk).not_inside(neo_ee_mk).enclosing(ncomp.outside(dnwell).not_inside(ymtp_mk), 0.12.um, euclidian).polygons(0.001)
df4d_l2 = ncomp.outside(dnwell).not_inside(ymtp_mk).not_outside(nwell_n_dnwell.not_inside(ymtp_mk).not_inside(neo_ee_mk)).not(nwell_n_dnwell.not_inside(ymtp_mk).not_inside(neo_ee_mk))
df4d_l  = df4d_l1.or(df4d_l2).not_interacting(v5_xtor).not_interacting(dualgate)
df4d_l.output("DF.4d_3.3V", "DF.4d_3.3V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.12µm")
df4d_l1.forget
df4d_l2.forget
df4d_l.forget

# Rule DF.4d_5V: Min. (Nwell overlap of NCOMP) outside DNWELL. is 0.16µm
logger.info("Executing rule DF.4d_5V")
df4d_l1 = nwell_n_dnwell.not_inside(ymtp_mk).enclosing(ncomp.outside(dnwell).not_inside(ymtp_mk), 0.16.um, euclidian).polygons(0.001)
df4d_l2 = ncomp.outside(dnwell).not_inside(ymtp_mk).not_outside(nwell_n_dnwell.not_inside(ymtp_mk)).not(nwell_n_dnwell.not_inside(ymtp_mk))
df4d_l  = df4d_l1.or(df4d_l2).overlapping(dualgate)
df4d_l.output("DF.4d_5V", "DF.4d_5V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.16µm")
df4d_l1.forget
df4d_l2.forget
df4d_l.forget

nwell_n_dnwell.forget
# Rule DF.4e_3.3V: Min. DNWELL overlap of PCOMP. is 0.93µm
logger.info("Executing rule DF.4e_3.3V")
df4e_l1 = dnwell.enclosing(pcomp, 0.93.um, euclidian).polygons(0.001)
df4e_l2 = pcomp.not_outside(dnwell).not(dnwell)
df4e_l  = df4e_l1.or(df4e_l2).not_interacting(v5_xtor).not_interacting(dualgate)
df4e_l.output("DF.4e_3.3V", "DF.4e_3.3V : Min. DNWELL overlap of PCOMP. : 0.93µm")
df4e_l1.forget
df4e_l2.forget
df4e_l.forget

# Rule DF.4e_5V: Min. DNWELL overlap of PCOMP. is 1.1µm
logger.info("Executing rule DF.4e_5V")
df4e_l1 = dnwell.enclosing(pcomp, 1.1.um, euclidian).polygons(0.001)
df4e_l2 = pcomp.not_outside(dnwell).not(dnwell)
df4e_l  = df4e_l1.or(df4e_l2).overlapping(dualgate)
df4e_l.output("DF.4e_5V", "DF.4e_5V : Min. DNWELL overlap of PCOMP. : 1.1µm")
df4e_l1.forget
df4e_l2.forget
df4e_l.forget

pwell_dnwell = lvpwell.inside(dnwell)
# Rule DF.5_3.3V: Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. is 0.12µm
logger.info("Executing rule DF.5_3.3V")
df5_l1 = pwell_dnwell.enclosing(pcomp.outside(nwell), 0.12.um, euclidian).polygons(0.001)
df5_l2 = pcomp.outside(nwell).not_outside(pwell_dnwell).not(pwell_dnwell)
df5_l  = df5_l1.or(df5_l2).not_interacting(v5_xtor).not_interacting(dualgate)
df5_l.output("DF.5_3.3V", "DF.5_3.3V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.12µm")
df5_l1.forget
df5_l2.forget
df5_l.forget

# Rule DF.5_5V: Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. is 0.16µm
logger.info("Executing rule DF.5_5V")
df5_l1 = pwell_dnwell.enclosing(pcomp.outside(nwell), 0.16.um, euclidian).polygons(0.001)
df5_l2 = pcomp.outside(nwell).not_outside(pwell_dnwell).not(pwell_dnwell)
df5_l  = df5_l1.or(df5_l2).overlapping(dualgate)
df5_l.output("DF.5_5V", "DF.5_5V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.16µm")
df5_l1.forget
df5_l2.forget
df5_l.forget

# Rule DF.6_3.3V: Min. COMP extend beyond gate (it also means source/drain overhang). is 0.24µm
logger.info("Executing rule DF.6_3.3V")
df6_l1 = comp.not(otp_mk).not_inside(ymtp_mk).enclosing(poly2.not_inside(ymtp_mk), 0.24.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df6_l1.output("DF.6_3.3V", "DF.6_3.3V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.24µm")
df6_l1.forget

# Rule DF.6_5V: Min. COMP extend beyond gate (it also means source/drain overhang). is 0.4µm
logger.info("Executing rule DF.6_5V")
df6_l1 = comp.not(otp_mk).not_inside(mvpsd).not_inside(mvsd).not_inside(ymtp_mk).outside(sramcore).enclosing(poly2.not_inside(ymtp_mk), 0.4.um, euclidian).polygons(0.001).overlapping(dualgate)
df6_l1.output("DF.6_5V", "DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.4µm")
df6_l1.forget

# Rule DF.7_3.3V: Min. (LVPWELL Spacer to PCOMP) inside DNWELL. is 0.43µm
logger.info("Executing rule DF.7_3.3V")
df7_l1  = pcomp.inside(dnwell).separation(pwell_dnwell, 0.43.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df7_l1.output("DF.7_3.3V", "DF.7_3.3V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.43µm")
df7_l1.forget

# Rule DF.7_5V: Min. (LVPWELL Spacer to PCOMP) inside DNWELL. is 0.6µm
logger.info("Executing rule DF.7_5V")
df7_l1  = pcomp.inside(dnwell).outside(sramcore).separation(pwell_dnwell, 0.6.um, euclidian).polygons(0.001).overlapping(dualgate)
df7_l1.output("DF.7_5V", "DF.7_5V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.6µm")
df7_l1.forget

# Rule DF.8_3.3V: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.43µm
logger.info("Executing rule DF.8_3.3V")
df8_l1 = pwell_dnwell.enclosing(ncomp.inside(dnwell), 0.43.um, euclidian).polygons(0.001)
df8_l2 = ncomp.inside(dnwell).not_outside(pwell_dnwell).not(pwell_dnwell)
df8_l  = df8_l1.or(df8_l2).not_interacting(v5_xtor).not_interacting(dualgate)
df8_l.output("DF.8_3.3V", "DF.8_3.3V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.43µm")
df8_l1.forget
df8_l2.forget
df8_l.forget

# Rule DF.8_5V: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.6µm
logger.info("Executing rule DF.8_5V")
df8_l1 = pwell_dnwell.outside(sramcore).enclosing(ncomp.inside(dnwell), 0.6.um, euclidian).polygons(0.001)
df8_l2 = ncomp.inside(dnwell).not_outside(pwell_dnwell.outside(sramcore)).not(pwell_dnwell.outside(sramcore))
df8_l  = df8_l1.or(df8_l2).overlapping(dualgate)
df8_l.output("DF.8_5V", "DF.8_5V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.6µm")
df8_l1.forget
df8_l2.forget
df8_l.forget

pwell_dnwell.forget
# Rule DF.9_3.3V: Min. COMP area (um2). is 0.2025µm²
logger.info("Executing rule DF.9_3.3V")
df9_l1  = comp.not(otp_mk).with_area(nil, 0.2025.um).not_interacting(v5_xtor).not_interacting(dualgate)
df9_l1.output("DF.9_3.3V", "DF.9_3.3V : Min. COMP area (um2). : 0.2025µm²")
df9_l1.forget
# Rule DF.9_5V: Min. COMP area (um2). is 0.2025µm²
logger.info("Executing rule DF.9_5V")
df9_l1  = comp.not(otp_mk).with_area(nil, 0.2025.um).overlapping(dualgate)
df9_l1.output("DF.9_5V", "DF.9_5V : Min. COMP area (um2). : 0.2025µm²")
df9_l1.forget
# Rule DF.10_3.3V: Min. field area (um2). is 0.26µm²
logger.info("Executing rule DF.10_3.3V")
df10_l1  = comp.holes.not(comp).with_area(nil, 0.26.um).not_interacting(v5_xtor).not_interacting(dualgate)
df10_l1.output("DF.10_3.3V", "DF.10_3.3V : Min. field area (um2). : 0.26µm²")
df10_l1.forget
# Rule DF.10_5V: Min. field area (um2). is 0.26µm²
logger.info("Executing rule DF.10_5V")
df10_l1  = comp.holes.not(comp).with_area(nil, 0.26.um).overlapping(dualgate)
df10_l1.output("DF.10_5V", "DF.10_5V : Min. field area (um2). : 0.26µm²")
df10_l1.forget
comp_butt = comp.interacting(ncomp.interacting(pcomp).outside(pcomp))
# Rule DF.11_3.3V: Min. Length of butting COMP edge. is 0.3µm
logger.info("Executing rule DF.11_3.3V")
df11_l1  = comp_butt.width(0.3.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df11_l1.output("DF.11_3.3V", "DF.11_3.3V : Min. Length of butting COMP edge. : 0.3µm")
df11_l1.forget

# Rule DF.11_5V: Min. Length of butting COMP edge. is 0.3µm
logger.info("Executing rule DF.11_5V")
df11_l1  = comp_butt.width(0.3.um, euclidian).polygons(0.001).overlapping(dualgate)
df11_l1.output("DF.11_5V", "DF.11_5V : Min. Length of butting COMP edge. : 0.3µm")
df11_l1.forget

comp_butt.forget
# Rule DF.12_3.3V: COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).
logger.info("Executing rule DF.12_3.3V")
df12_l1 = comp.not_interacting(schottky_diode).not(nplus.or(pplus)).not_interacting(v5_xtor).not_interacting(dualgate)
df12_l1.output("DF.12_3.3V", "DF.12_3.3V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).")
df12_l1.forget

# Rule DF.12_5V: COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).
logger.info("Executing rule DF.12_5V")
df12_l1 = comp.not_interacting(schottky_diode).not(nplus.or(pplus)).overlapping(dualgate)
df12_l1.output("DF.12_5V", "DF.12_5V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).")
df12_l1.forget

df13_ncomp = ncomp.inside(nwell.covering(ncomp).covering(pcomp))
df13_pcomp = pcomp.inside(nwell.covering(ncomp).covering(pcomp))
# Rule DF.13_3.3V: Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).
logger.info("Executing rule DF.13_3.3V")
df13_l1 = df13_ncomp.not_interacting(df13_pcomp.sized(20.um)).not_interacting(v5_xtor).not_interacting(dualgate)
df13_l1.output("DF.13_3.3V", "DF.13_3.3V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).")
df13_l1.forget

# Rule DF.13_5V: Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).
logger.info("Executing rule DF.13_5V")
df13_l1 = df13_ncomp.not_interacting(df13_pcomp.sized(15.um)).overlapping(dualgate)
df13_l1.output("DF.13_5V", "DF.13_5V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).")
df13_l1.forget

df13_ncomp.forget
df13_pcomp.forget
# Rule DF.14_3.3V: Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).
logger.info("Executing rule DF.14_3.3V")
df14_l1 = pcomp.outside(nwell).not_interacting(ncomp.outside(nwell).sized(20.um)).not_interacting(v5_xtor).not_interacting(dualgate)
df14_l1.output("DF.14_3.3V", "DF.14_3.3V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).")
df14_l1.forget

# Rule DF.14_5V: Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).
logger.info("Executing rule DF.14_5V")
df14_l1 = pcomp.outside(nwell).not_interacting(ncomp.outside(nwell).sized(15.um)).overlapping(dualgate)
df14_l1.output("DF.14_5V", "DF.14_5V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).")
df14_l1.forget

# rule DF.15a_3.3V is not a DRC check

# rule DF.15a_5V is not a DRC check

# rule DF.15b_3.3V is not a DRC check

# rule DF.15b_5V is not a DRC check

ncomp_df16 = ncomp.outside(nwell).outside(dnwell)
# Rule DF.16_3.3V: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.43µm
logger.info("Executing rule DF.16_3.3V")
df16_l1  = ncomp_df16.not_inside(ymtp_mk).outside(sramcore).separation(nwell.outside(dnwell).not_inside(ymtp_mk), 0.43.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df16_l1.output("DF.16_3.3V", "DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.43µm")
df16_l1.forget

# Rule DF.16_5V: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.6µm
logger.info("Executing rule DF.16_5V")
df16_l1  = ncomp_df16.not_inside(ymtp_mk).outside(sramcore).separation(nwell.outside(dnwell).not_inside(ymtp_mk), 0.6.um, euclidian).polygons(0.001).overlapping(dualgate)
df16_l1.output("DF.16_5V", "DF.16_5V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.6µm")
df16_l1.forget

pcomp_df17 = pcomp.outside(nwell).outside(dnwell)
# Rule DF.17_3.3V: Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). is 0.12µm
logger.info("Executing rule DF.17_3.3V")
df17_l1  = pcomp_df17.separation(nwell.outside(dnwell), 0.12.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df17_l1.output("DF.17_3.3V", "DF.17_3.3V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.12µm")
df17_l1.forget

# Rule DF.17_5V: Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). is 0.16µm
logger.info("Executing rule DF.17_5V")
df17_l1  = pcomp_df17.separation(nwell.outside(dnwell), 0.16.um, euclidian).polygons(0.001).overlapping(dualgate)
df17_l1.output("DF.17_5V", "DF.17_5V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.16µm")
df17_l1.forget

# Rule DF.18_3.3V: Min. DNWELL space to (PCOMP outside Nwell and DNWELL). is 2.5µm
logger.info("Executing rule DF.18_3.3V")
df18_l1  = pcomp_df17.separation(dnwell, 2.5.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df18_l1.output("DF.18_3.3V", "DF.18_3.3V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm")
df18_l1.forget

# Rule DF.18_5V: Min. DNWELL space to (PCOMP outside Nwell and DNWELL). is 2.5µm
logger.info("Executing rule DF.18_5V")
df18_l1  = pcomp_df17.separation(dnwell, 2.5.um, euclidian).polygons(0.001).overlapping(dualgate)
df18_l1.output("DF.18_5V", "DF.18_5V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm")
df18_l1.forget

pcomp_df17.forget
# Rule DF.19_3.3V: Min. DNWELL space to (NCOMP outside Nwell and DNWELL). is 3.2µm
logger.info("Executing rule DF.19_3.3V")
df19_l1  = ncomp_df16.separation(dnwell, 3.2.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate)
df19_l1.output("DF.19_3.3V", "DF.19_3.3V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.2µm")
df19_l1.forget

# Rule DF.19_5V: Min. DNWELL space to (NCOMP outside Nwell and DNWELL). is 3.28µm
logger.info("Executing rule DF.19_5V")
df19_l1  = ncomp_df16.separation(dnwell, 3.28.um, euclidian).polygons(0.001).overlapping(dualgate)
df19_l1.output("DF.19_5V", "DF.19_5V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.28µm")
df19_l1.forget

ncomp_df16.forget

end #FEOL


exec_end_time = Time.now
run_time = exec_end_time - exec_start_time
logger.info("DRC Run time %f seconds" % [run_time])