# Copyright 2022 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

#=============================================================================================================================================================
#------------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (ESD) -------------------------------------------------------------
#=============================================================================================================================================================

require 'time'
require "logger"

exec_start_time = Time.now

logger = Logger.new(STDOUT)

logger.formatter = proc do |severity, datetime, progname, msg|
  "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg}
"
end

#================================================
#----------------- FILE SETUP -------------------
#================================================

# optional for a batch launch :   klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb

logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input])

if $input
    if $topcell
        source($input, $topcell)
    else
        source($input)
    end
end

logger.info("Loading database to memory is complete.")

if $report
    logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report])
    report("DRC Run Report at", $report)
else
    logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path])
    report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb"))
end

if $thr
    logger.info("Number of threads to use %s" % [$thr])
    threads($thr)
else
    logger.info("Number of threads to use 16")
    threads(16)
end

# === TILING MODE ===
if $run_mode == "tiling"
  # use a tile size of 1mm - not used in deep mode-
  # tiles(500.um)
  # use a tile border of 10 micron:
  # tile_borders(10.um)
  tiles(1000)
  logger.info("Tiling  mode is enabled.")

elsif $run_mode == "deep"
  #=== HIER MODE ===
  deep
  logger.info("deep  mode is enabled.")

elsif $run_mode == "flat"
  #=== FLAT MODE ===
  flat
  logger.info("flat  mode is enabled.")

else
  #=== FLAT MODE ===
  flat
  logger.info("flat  mode is enabled.")

end # run_mode

#================================================
#------------- LAYERS DEFINITIONS ---------------
#================================================

v5_xtor        = polygons(112, 1 )
dualgate       = polygons(55 , 0 )
poly2          = polygons(30 , 0 )
nplus          = polygons(32 , 0 )
pplus          = polygons(31 , 0 )
comp           = polygons(22 , 0 )
esd            = polygons(24 , 0 )
lvs_io         = polygons(119, 5 )

logger.info("Starting deriving base layers.")
#================================================
#------------- LAYERS DERIVATIONS ---------------
#================================================

ncomp      =  comp      & nplus
pcomp      =  comp      & pplus
tgate      =  poly2     & comp
ngate      =  nplus     & tgate
pgate      =  pplus     & tgate

#================================================
#------------------ SWITCHES --------------------
#================================================
logger.info("Evaluate switches.")

# FEOL
if $feol == "false"
  FEOL = $feol
  logger.info("FEOL is disabled.")
else
  FEOL = "true"
  logger.info("FEOL is enabled.")
end # FEOL

# BEOL
if $beol == "false"
  BEOL = $beol
  logger.info("BEOL is disabled.")
else
  BEOL = "true"
  logger.info("BEOL is enabled.")
end # BEOL

# connectivity rules
if $conn_drc == "true"
  CONNECTIVITY_RULES = $conn_drc
  logger.info("connectivity rules are enabled.")
else
  CONNECTIVITY_RULES = false
  logger.info("connectivity rules are disabled.")
end # connectivity rules

# METAL_TOP
if $metal_top
  METAL_TOP = $metal_top
else
  METAL_TOP = "9K"
end # METAL_TOP

logger.info("METAL_TOP Selected is %s" % [METAL_TOP])

# METAL_LEVEL
if $metal_level
  METAL_LEVEL = $metal_level
else
  METAL_LEVEL = "6LM"
end # METAL_LEVEL

logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL])

# WEDGE
if $wedge == "false"
  WEDGE = $wedge
else
  WEDGE = "true"
end # WEDGE

logger.info("Wedge enabled  %s" % [WEDGE])

# BALL
if $ball == "false"
  BALL = $ball
else
  BALL = "true"
end # BALL

logger.info("Ball enabled  %s" % [BALL])

# GOLD
if $gold == "false"
  GOLD = $gold
else
  GOLD = "true"
end # GOLD

logger.info("Gold enabled  %s" % [GOLD])

if $mim_option
  MIM_OPTION = $mim_option
else
  MIM_OPTION = "Nan"
end

logger.info("MIM Option selected %s" % [MIM_OPTION])

# OFFGRID
if $offgrid == "false"
  OFFGRID = false
else
  OFFGRID = true
end # OFFGRID

logger.info("Offgrid enabled  %s" % [OFFGRID])

#================================================
#----------------------ESD-----------------------
#================================================


if FEOL
logger.info("FEOL section")

# Rule ESD.1: Minimum width of an ESD implant area. is 0.6µm
logger.info("Executing rule ESD.1")
esd1_l1  = esd.width(0.6.um, euclidian).polygons(0.001)
esd1_l1.output("ESD.1", "ESD.1 : Minimum width of an ESD implant area. : 0.6µm")
esd1_l1.forget

# Rule ESD.2: Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). is 0.6µm
logger.info("Executing rule ESD.2")
esd2_l1  = esd.space(0.6.um, euclidian).polygons(0.001)
esd2_l1.output("ESD.2", "ESD.2 : Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). : 0.6µm")
esd2_l1.forget

# Rule ESD.3a: Minimum space to NCOMP. is 0.6µm
logger.info("Executing rule ESD.3a")
esd3a_l1  = esd.separation(ncomp, 0.6.um, euclidian).polygons(0.001)
esd3a_l1.output("ESD.3a", "ESD.3a : Minimum space to NCOMP. : 0.6µm")
esd3a_l1.forget

# Rule ESD.3b: Min/max space to a butted PCOMP.
logger.info("Executing rule ESD.3b")
esd3b_l1 = esd.not_outside(pcomp)
esd3b_l1.output("ESD.3b", "ESD.3b : Min/max space to a butted PCOMP.")
esd3b_l1.forget

# Rule ESD.4a: Extension beyond NCOMP. is 0.24µm
logger.info("Executing rule ESD.4a")
esd4a_l1 = esd.edges.not_interacting(pcomp).enclosing(ncomp.edges, 0.24.um, euclidian).polygons(0.001)
esd4a_l1.output("ESD.4a", "ESD.4a : Extension beyond NCOMP. : 0.24µm")
esd4a_l1.forget

# Rule ESD.4b: Minimum overlap of an ESD implant edge to a COMP. is 0.45µm
logger.info("Executing rule ESD.4b")
esd4b_l1  = esd.overlap(comp, 0.45.um, euclidian).polygons(0.001)
esd4b_l1.output("ESD.4b", "ESD.4b : Minimum overlap of an ESD implant edge to a COMP. : 0.45µm")
esd4b_l1.forget

# Rule ESD.5a: Minimum ESD area (um2). is 0.49µm²
logger.info("Executing rule ESD.5a")
esd5a_l1  = esd.with_area(nil, 0.49.um)
esd5a_l1.output("ESD.5a", "ESD.5a : Minimum ESD area (um2). : 0.49µm²")
esd5a_l1.forget
# Rule ESD.5b: Minimum field area enclosed by ESD implant (um2). is 0.49µm²
logger.info("Executing rule ESD.5b")
esd5b_l1  = esd.holes.with_area(nil, 0.49.um)
esd5b_l1.output("ESD.5b", "ESD.5b : Minimum field area enclosed by ESD implant (um2). : 0.49µm²")
esd5b_l1.forget
# Rule ESD.6: Extension perpendicular to Poly2 gate. is 0.45µm
logger.info("Executing rule ESD.6")
esd6_l1 = esd.edges.enclosing(poly2.edges.interacting(tgate.edges), 0.45.um, projection).polygons(0.001)
esd6_l1.output("ESD.6", "ESD.6 : Extension perpendicular to Poly2 gate. : 0.45µm")
esd6_l1.forget

# Rule ESD.7: No ESD implant inside PCOMP.
logger.info("Executing rule ESD.7")
esd7_l1 = esd.not_outside(pcomp)
esd7_l1.output("ESD.7", "ESD.7 : No ESD implant inside PCOMP.")
esd7_l1.forget

# Rule ESD.8: Minimum space to Nplus/Pplus. is 0.3µm
logger.info("Executing rule ESD.8")
esd8_l1 = esd.separation(nplus.or(pplus), 0.3.um).polygons
esd8_l1.output("ESD.8", "ESD.8 : Minimum space to Nplus/Pplus. : 0.3µm")
esd8_l1.forget

# Rule ESD.pl: Minimum gate length of 5V/6V gate NMOS. is 0.8µm
logger.info("Executing rule ESD.pl")
esdpl_l1  = poly2.interacting(esd).edges.and(tgate.edges).width(0.8.um, euclidian).polygons(0.001).overlapping(dualgate)
esdpl_l1.output("ESD.pl", "ESD.pl : Minimum gate length of 5V/6V gate NMOS. : 0.8µm")
esdpl_l1.forget

# Rule ESD.9: ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices).
logger.info("Executing rule ESD.9")
esd9_l1 = esd.not_inside(dualgate)
esd9_l1.output("ESD.9", "ESD.9 : ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices).")
esd9_l1.forget

# Rule ESD.10: LVS_IO shall be drawn covering I/O MOS active area by minimum overlap.
logger.info("Executing rule ESD.10")
esd10_l1 = comp.and(esd).not_outside(lvs_io).not(lvs_io)
esd10_l1.output("ESD.10", "ESD.10 : LVS_IO shall be drawn covering I/O MOS active area by minimum overlap.")
esd10_l1.forget


end #FEOL


exec_end_time = Time.now
run_time = exec_end_time - exec_start_time
logger.info("DRC Run time %f seconds" % [run_time])