Merge pull request #6 from mabrains/pr_naming
Updating primitives names
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/gf180mcu_fd_ip_sram__sram128x8m8wm1.rst b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/gf180mcu_fd_ip_sram__sram128x8m8wm1.rst
new file mode 100644
index 0000000..ad2e0f5
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/gf180mcu_fd_ip_sram__sram128x8m8wm1.rst
@@ -0,0 +1,132 @@
+***********************************
+gf180mcu_fd_ip_sram__sram128x8m8wm1
+***********************************
+
+.. centered::
+ **gf180mcu_fd_ip_sram__sram128x8m8wm1**
+.. centered::
+ **180nm 5V Green synchronous single port SRAM**
+.. centered::
+ **Memory Macro IP**
+.. centered::
+ **Datasheet**
+
+====
+
+**Features**
+
+- Uses 180nm 5V Green CMOS 13.5um2 6 transistors bitcell
+
+- 128 words X 8 bits, mux 8 Instance
+
+- Periphery circuitry uses 5V transistors
+
+- Operating voltage is 1.62V to 5.50V
+
+- Operating temperature is -40 degC to 125 degC
+
+- Minimum 3 layers of metals required: Metal1, Metal2, Metal3
+
+- Bit write mask
+
+- Self timed operation to reduce power
+
+- Separate data in and data out ports
+
+- Macro cell name: gf180mcu_fd_ip_sram__sram128x8m8wm1
+
+
+====================
+1.0 Pins Description
+====================
+
+.. csv-table::
+ :file: specs/1_pins_desc.csv
+
+===============
+2.0 Truth Table
+===============
+
+.. csv-table::
+ :file: specs/2_truth_table.csv
+
+.. note::
+
+ X: don't care
+
+=========================================
+3.0 Capacitance loading ( fF ) @ TT, 25°c
+=========================================
+
+.. csv-table::
+ :file: specs/3_Capacitance_loading.csv
+
+============================
+4.0 Power Consumption ( uW )
+============================
+
+Condition of AC Write power is all data input pins switch and AC Read power is all address input and data output pins switch at 1MHz
+
+==============
+4.1 5.0V Power
+==============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption1.csv
+
+==============
+4.2 3.3V Power
+==============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption2.csv
+
+==============
+4.3 1.8V Power
+==============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption3.csv
+
+======================
+5.0 AC Characteristics
+======================
+
+The timing and power values measured from the input slew of 20ps on clock pin, 20ps on signal and output load .01pF.
+
+===========================
+5.1 5.0V AC Characteristics
+===========================
+
+.. csv-table::
+ :file: specs/5_AC_Characteristics1.csv
+
+===========================
+5.2 3.3V AC Characteristics
+===========================
+
+ .. csv-table::
+ :file: specs/5_AC_Characteristics2.csv
+
+===========================
+5.3 1.8V AC Characteristics
+===========================
+
+.. csv-table::
+ :file: specs/5_AC_Characteristics3.csv
+
+.. centered::
+ **AC Timing Waveform Chart**
+
+.. image:: specs/ac_timing.png
+ :width: 600
+ :align: center
+ :alt: AC Timing Waveform Chart
+
+=======================
+6.0 Physical Dimensions
+=======================
+
+.. csv-table::
+ :file: specs/6_Physical_Dimensions.csv
+
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/0_release.csv b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/0_release.csv
new file mode 100644
index 0000000..f51ecb0
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/0_release.csv
@@ -0,0 +1,2 @@
+,Date,Description
+1,2014/06/20,Release
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/1_pins_desc.csv b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/1_pins_desc.csv
new file mode 100644
index 0000000..4859265
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/1_pins_desc.csv
@@ -0,0 +1,44 @@
+Signal,Direction,Description
+CLK,Input,"Clock for the memory. Rising edge triggers
+
+operation. All inputs are latched at rising edge of the
+
+clock signal"
+CEN,Input,"Memory Enable, Active Low. When CEN is Low, the
+
+memory is enabled. When CEN input is High, the
+
+memory is deactivated but internal states are
+
+retained. CEN must be high before 1st running cycle."
+A[6:0],Input,"Address Input. This Address input port is used to
+
+address the location to be written during the write
+
+cycle and read during the read cycle."
+GWEN,Input,"Write Enable Input. The RAM is in write cycle when
+
+GWEN is low. The RAM is in read cycle when
+
+GWEN is high."
+WEN[7:0],Input,"Bit Write Mask, Active Low. When the memory is in
+
+the write cycle, selectively write into individual
+
+outputs are controlled by WEN[7:0]. For example, if
+
+CEN, GWEN, WEN[0] are low and WEN[7:1] are
+
+high, only D[0] will write into the addressed location and
+
+D[7:1] will be ignored during CLK low to high transition."
+D[7:0],Input,"Data input bus. The data input bus is used to write
+
+data into the memory location specified by address
+
+input port during the write cycle."
+Q[7:0],output,"Data output bus. It outputs the contents of the
+
+memory location addressed by the Address Input signals."
+VDD,Power,Power pin.
+VSS,Ground,Ground pin.
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/2_truth_table.csv b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/2_truth_table.csv
new file mode 100644
index 0000000..94ed477
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/2_truth_table.csv
@@ -0,0 +1,6 @@
+CLK,CEN,GWEN,WEN,A,D,Q,status
+,H,X,X,X,X,Hold previous data,Standby mode
+,L,H,X,A,X,Q,Read mode
+,L,L,H,A,D,Hold previous data,Write mode
+,L,L,L,A,D,Hold previous data,Mask mode
+other,X,X,X,X,X,Hold previous data,Unchanged
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/3_Capacitance_loading.csv b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/3_Capacitance_loading.csv
new file mode 100644
index 0000000..072de75
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/3_Capacitance_loading.csv
@@ -0,0 +1,4 @@
+Voltage,CLK,CEN,GWEN,WEN,A,D
+5.0v,298.116,17.4878,49.6559,7.84667,38.8545,16.7359
+3.3v,293.691,17.5673,48.1696,7.649,38.934,16.7013
+1.8v,282.833,17.5504,44.4816,7.15846,38.9171,16.0438
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/4_Power_Consumption1.csv b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/4_Power_Consumption1.csv
new file mode 100644
index 0000000..8a1ec6f
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/4_Power_Consumption1.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 5.00v, 25°c",0.0002,897.5,805.25
+"SS corner, 4.50v, -40°c",0.00016,702.945,632.295
+"SS corner, 4.50v, 125°c",0.00021,731.97,662.018
+"FF corner, 5.50v, 125°c",0.01252,1146.72,1036.97
+"FF corner, 5.50v, -40°c",0.00024,1091.34,983.758
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/4_Power_Consumption2.csv b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/4_Power_Consumption2.csv
new file mode 100644
index 0000000..faf466c
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/4_Power_Consumption2.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 3.3v, 25°c",0.00009,357.571,324.472
+"SS corner, 3.0v, -40°c",0.00007,284.31,262.08
+"SS corner, 3.6v, 125°c",0.0001,303.885,276.39
+"FF corner, 3.6v, 125°c",0.00491,460.764,413.478
+"FF corner, 3.6v, -40°c",0.0001,427.68,386.604
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/4_Power_Consumption3.csv b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/4_Power_Consumption3.csv
new file mode 100644
index 0000000..a1b4de9
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/4_Power_Consumption3.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 1.8v, 25°c",0.00003,96.498,88.7733
+"SS corner, 1.62v, -40°c",0.00002,76.3255,70.9123
+"SS corner, 1.62v, 125°c",0.00003,81.5346,74.767
+"FF corner, 1.98v, 125°c",0.00159,125.948,114.038
+"FF corner,1.98v, -40°c",0.00003,115.503,105.088
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/5_AC_Characteristics1.csv b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/5_AC_Characteristics1.csv
new file mode 100644
index 0000000..8cd4a65
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/5_AC_Characteristics1.csv
@@ -0,0 +1,92 @@
+Symbol,"Parameter
+
+Description","SNSP
+
+Process
+
+4.5v, -40C","SNSP
+
+Process
+
+4.5v, 125C","Typical
+
+Process
+
+5.0v, 25C","FNFP
+
+Process
+
+5.5v, 125C","FNFP
+
+Process
+
+5.5v, -40C",unit
+Tcyc,Min clock period,7.2968,10.5483,5.8805,5.4403,3.8099,ns
+Tckh,Min clock high time,2.557,4.5174,2.2464,2.1763,1.411,ns
+Tckl,Min clock low time,2.5652,4.5311,2.3734,2.3048,1.3029,ns
+Tcsl,"CEN set up time
+
+( CEN = L )",0.459,0.5874,0.4066,0.3895,0.3233,ns
+Tchl,"CEN hold time
+
+( CEN = L )",1.2324,1.8522,1.1095,1.0791,0.7647,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",0.5119,0.6595,0.4349,0.411,0.3372,ns
+Tchh,"CEN hold time
+
+( CEN = H )",1.2853,1.9179,1.1378,1.1006,0.7786,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",0.7164,1.014,0.6277,0.5876,0.4544,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",0.9936,1.3718,0.8367,0.7948,0.5965,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",0.6741,0.9339,0.5892,0.5612,0.4344,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",0.5303,0.6896,0.4644,0.4611,0.3654,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0.2801,0.3526,0.2642,0.2408,0.2218,ns
+Twihl,"WEN hold time
+
+( WEN = L )",0.9957,1.3718,0.8367,0.7948,0.5965,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",0.5303,0.6924,0.4646,0.4611,0.3654,ns
+Tasl,"A set up time
+
+( A = L )",0.8834,1.1569,0.7313,0.6558,0.5337,ns
+Tahl,"A hold time
+
+( A = L )",0.6364,0.8155,0.5345,0.4939,0.4013,ns
+Tash,"A set up time
+
+( A = H )",0.6186,0.8442,0.5154,0.4813,0.3834,ns
+Tahh,"A hold time
+
+( A = H )",0.6573,0.8495,0.5472,0.5023,0.4071,ns
+Tdsl,"D set up time
+
+( D = L )",0.1168,0.099,0.1188,0.1022,0.1285,ns
+Tdhl,"D hold time
+
+( D = L )",0.5183,0.6714,0.4622,0.472,0.3631,ns
+Tdsh,"D set up time
+
+( D = H )",0.5947,0.7737,0.4831,0.4111,0.359,ns
+Tdhh,"D hold time
+
+( D= H )",0.7521,1.0224,0.6506,0.6352,0.4843,ns
+Tah,"Clock high
+
+to Q high",5.399,7.9528,4.4262,4.1233,2.8427,ns
+Tal,"Clock high
+
+ to Q low",5.5834,8.2156,4.5722,4.2356,2.93,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/5_AC_Characteristics2.csv b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/5_AC_Characteristics2.csv
new file mode 100644
index 0000000..79dde90
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/5_AC_Characteristics2.csv
@@ -0,0 +1,80 @@
+Symbol,"Parameter
+description","SNSP
+Process
+3.0v, -40C","SNSP
+Process
+3.0, 125C","Typical
+Process
+3.3v, 25C","FNFP
+Process
+3.6v, 125C","FNFP
+Process
+3.6v, -40C",unit
+Tcyc,Min clock period,11.287,16.6365,8.4053,7.2375,4.8961,ns
+Tckh,Min clock high time,3.6774,4.7153,2.7639,2.5493,2.4443,ns
+Tckl,Min clock low time,4.4364,5.9546,2.8652,3.328,1.9857,ns
+Tcsl,"CEN set up time
+
+( CEN = L )",0.6575,0.8523,0.5421,0.4968,0.4053,ns
+Tchl,"CEN hold time
+
+( CEN = L )",1.9064,2.8563,1.594,1.4782,1.0188,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",0.8066,1.0749,0.6133,0.5368,0.4259,ns
+Tchh,"CEN hold time
+( CEN = H )",2.0101,2.9791,1.6398,1.5029,1.0368,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",1.1592,1.6428,0.9199,0.8121,0.5999,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",1.4433,2.0627,1.138,1.024,0.7538,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",1.0287,1.4302,0.8238,0.742,0.557,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",0.7157,0.9902,0.592,0.5628,0.4407,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0.441,0.5252,0.3732,0.3322,0.287,ns
+Twihl,"WEN hold time
+
+( WEN = L )",1.4443,2.0643,1.138,1.024,0.7538,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",0.7158,0.9902,0.592,0.5628,0.4407,ns
+Tasl,"A set up time
+
+( A = L )",1.32,1.6823,1.0068,0.8583,0.6762,ns
+Tahl,"A hold time
+
+( A = L )",0.8788,1.1411,0.6955,0.6157,0.4954,ns
+Tash,"A set up time
+
+( A = H )",0.9908,1.2941,0.7507,0.6486,0.5052,ns
+Tahh,"A hold time
+
+( A = H )",0.9417,1.2293,0.7292,0.637,0.5084,ns
+Tdsl,"D set up time
+
+( D = L )",0.1738,0.1041,0.156,0.1357,0.1612,ns
+Tdhl,"D hold time
+
+( D = L )",0.6128,0.8611,0.5512,0.5437,0.4224,ns
+Tdsh,"D set up time
+
+( D = H )",1.0132,1.2631,0.7156,0.5732,0.4724,ns
+Tdhh,"D hold time
+
+( D= H )",1.0883,1.5344,0.8666,0.8014,0.5999,ns
+Tah,"Clock high
+
+to Q high",8.3652,12.1944,6.298,5.501,3.7381,ns
+Tal,"Clock high
+
+ To Q low",8.7238,12.7032,6.5484,5.6867,3.873,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/5_AC_Characteristics3.csv b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/5_AC_Characteristics3.csv
new file mode 100644
index 0000000..44a99b0
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/5_AC_Characteristics3.csv
@@ -0,0 +1,84 @@
+Symbol,"Parameter
+description","SNSP
+Process
+1.62v, -40C","SNSP
+Process
+1.62v,
+125C","Typical
+Process
+1.8v, 25C","FNFP
+Process
+1.98v,
+125C","FNFP
+Process
+1.98v, -40C",unit
+Tcyc,Min clock period,48.0305,51.9626,21.8315,14.0727,10.2767,ns
+Tckh,Min clock high time,21.8197,13.4605,10.6663,3.7733,2.6968,ns
+Tckl,Min clock low time,22.5675,21.362,10.6844,5.1485,3.7226,ns
+Tcsl,"CEN set up time
+
+( CEN = L )",2.3724,2.4562,1.1519,0.8005,0.6534,ns
+Tchl,"CEN hold time
+
+( CEN = L )",7.2717,8.1123,3.8274,2.746,2.0001,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",3.5899,3.621,1.5559,0.9713,0.7968,ns
+Tchh,"CEN hold time
+
+( CEN = H )",8.1139,8.8496,4.0504,2.8068,2.0571,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",5.4203,5.5914,2.4142,1.5341,1.1897,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",6.5279,7.0068,2.5795,1.764,1.3151,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",3.7875,4.1574,1.8835,1.3011,1.0048,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",3.7942,4.0118,1.2881,0.8686,0.6835,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0,0.0413,0.6956,0.5569,0.4878,ns
+Twihl,"WEN hold time
+
+( WEN = L )",6.5574,7.0283,2.5901,1.764,1.3173,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",3.8062,4.024,1.2894,0.8686,0.6835,ns
+Tasl,"A set up time
+
+( A = L )",2.7688,2.9848,2.0331,1.4547,1.1882,ns
+Tahl,"A hold time
+
+( A = L )",2.4697,2.6801,1.3163,0.9482,0.7648,ns
+Tash,"A set up time
+
+( A = H )",3.5404,3.5743,1.6536,1.1654,0.9602,ns
+Tahh,"A hold time
+
+( A = H )",3.0635,3.2382,1.5118,1.0362,0.8406,ns
+Tdsl,"D set up time
+
+( D = L )",0,0,0.0154,0.1334,0.1847,ns
+Tdhl,"D hold time
+
+( D = L )",3.0741,3.1426,0.9688,0.7561,0.5574,ns
+Tdsh,"D set up time
+
+( D = H )",3.4192,3.2969,1.8301,1.0588,0.9275,ns
+Tdhh,"D hold time
+
+( D= H )",5.7672,5.9734,2.1079,1.3541,1.0484,ns
+Tah,"Clock high
+
+ to Q High
+",32.9568,36.3012,15.606,10.2752,7.5431,ns
+Tal,"Clock high
+
+ To Q low",35.4984,38.5848,16.5192,10.751,7.9138,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/6_Physical_Dimensions.csv b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/6_Physical_Dimensions.csv
new file mode 100644
index 0000000..4be6293
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/6_Physical_Dimensions.csv
@@ -0,0 +1,2 @@
+Width(um),Height(um),Area(um^2)
+431.86,268.88,116118.5168
diff --git a/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/ac_timing.png b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/ac_timing.png
new file mode 100644
index 0000000..102954e
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/specs/ac_timing.png
Binary files differ
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/gf180mcu_fd_ip_sram__sram256x8m8wm1.rst b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/gf180mcu_fd_ip_sram__sram256x8m8wm1.rst
new file mode 100644
index 0000000..4cb15f6
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/gf180mcu_fd_ip_sram__sram256x8m8wm1.rst
@@ -0,0 +1,132 @@
+***********************************
+gf180mcu_fd_ip_sram__sram256x8m8wm1
+***********************************
+
+.. centered::
+ **gf180mcu_fd_ip_sram__sram256x8m8wm1**
+.. centered::
+ **180nm 5V Green synchronous single port SRAM**
+.. centered::
+ **Memory Macro IP**
+.. centered::
+ **Datasheet**
+
+====
+
+**Features**
+
+- Uses 180nm 5V Green CMOS 13.5um2 6 transistors bitcell
+
+- 256 words X 8 bits, mux 8 Instance
+
+- Periphery circuitry uses 5V transistors
+
+- Operating voltage is 1.62V to 5.50V
+
+- Operating temperature is -40 degC to 125 degC
+
+- Minimum 3 layers of metals required: Metal1, Metal2, Metal3
+
+- Bit write mask
+
+- Self timed operation to reduce power
+
+- Separate data in and data out ports
+
+- Macro cell name: gf180mcu_fd_ip_sram__sram256x8m8wm1
+
+====================
+1.0 Pins Description
+====================
+
+.. csv-table::
+ :file: specs/1_pins_desc.csv
+
+===============
+2.0 Truth Table
+===============
+
+.. csv-table::
+ :file: specs/2_truth_table.csv
+
+.. note::
+
+ X: don't care
+
+=========================================
+3.0 Capacitance loading ( fF ) @ TT, 25°c
+=========================================
+
+.. csv-table::
+ :file: specs/3_Capacitance_loading.csv
+
+============================
+4.0 Power Consumption ( uW )
+============================
+
+Condition of AC Write power is all data input pins switch and AC Read power is all address input and data output pins switch at 1MHz
+
+==============
+4.1 5.0V Power
+==============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption1.csv
+
+==============
+4.2 3.3V Power
+==============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption2.csv
+
+==============
+4.3 1.8V Power
+==============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption3.csv
+
+======================
+5.0 AC Characteristics
+======================
+
+The timing and power values measured from the input slew of 20ps on clock pin, 20ps on signal and output load .01pF.
+
+===========================
+5.1 5.0V AC Characteristics
+===========================
+
+.. csv-table::
+ :file: specs/5_AC_Characteristics1.csv
+
+===========================
+5.2 3.3V AC Characteristics
+===========================
+
+ .. csv-table::
+ :file: specs/5_AC_Characteristics2.csv
+
+===========================
+5.3 1.8V AC Characteristics
+===========================
+
+.. csv-table::
+ :file: specs/5_AC_Characteristics3.csv
+
+.. centered::
+ **AC Timing Waveform Chart**
+
+.. image:: specs/ac_timing.png
+ :width: 600
+ :align: center
+ :alt: AC Timing Waveform Chart
+
+=======================
+6.0 Physical Dimensions
+=======================
+
+.. csv-table::
+ :file: specs/6_Physical_Dimensions.csv
+
+
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/0_release.csv b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/0_release.csv
new file mode 100644
index 0000000..cc8d44f
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/0_release.csv
@@ -0,0 +1,2 @@
+"",Date,Description
+1.0,2014/06/20,Release
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/1_pins_desc.csv b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/1_pins_desc.csv
new file mode 100644
index 0000000..4859265
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/1_pins_desc.csv
@@ -0,0 +1,44 @@
+Signal,Direction,Description
+CLK,Input,"Clock for the memory. Rising edge triggers
+
+operation. All inputs are latched at rising edge of the
+
+clock signal"
+CEN,Input,"Memory Enable, Active Low. When CEN is Low, the
+
+memory is enabled. When CEN input is High, the
+
+memory is deactivated but internal states are
+
+retained. CEN must be high before 1st running cycle."
+A[6:0],Input,"Address Input. This Address input port is used to
+
+address the location to be written during the write
+
+cycle and read during the read cycle."
+GWEN,Input,"Write Enable Input. The RAM is in write cycle when
+
+GWEN is low. The RAM is in read cycle when
+
+GWEN is high."
+WEN[7:0],Input,"Bit Write Mask, Active Low. When the memory is in
+
+the write cycle, selectively write into individual
+
+outputs are controlled by WEN[7:0]. For example, if
+
+CEN, GWEN, WEN[0] are low and WEN[7:1] are
+
+high, only D[0] will write into the addressed location and
+
+D[7:1] will be ignored during CLK low to high transition."
+D[7:0],Input,"Data input bus. The data input bus is used to write
+
+data into the memory location specified by address
+
+input port during the write cycle."
+Q[7:0],output,"Data output bus. It outputs the contents of the
+
+memory location addressed by the Address Input signals."
+VDD,Power,Power pin.
+VSS,Ground,Ground pin.
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/2_truth_table.csv b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/2_truth_table.csv
new file mode 100644
index 0000000..94ed477
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/2_truth_table.csv
@@ -0,0 +1,6 @@
+CLK,CEN,GWEN,WEN,A,D,Q,status
+,H,X,X,X,X,Hold previous data,Standby mode
+,L,H,X,A,X,Q,Read mode
+,L,L,H,A,D,Hold previous data,Write mode
+,L,L,L,A,D,Hold previous data,Mask mode
+other,X,X,X,X,X,Hold previous data,Unchanged
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/3_Capacitance_loading.csv b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/3_Capacitance_loading.csv
new file mode 100644
index 0000000..84b0125
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/3_Capacitance_loading.csv
@@ -0,0 +1,4 @@
+Voltage,CLK,CEN,GWEN,WEN,A,D
+5.0v,298.056,18.2857,49.4975,7.84667,40.4163,16.4131
+3.3v,293.631,18.3651,48.0112,7.649,40.4958,16.3071
+1.8v,282.773,18.3483,44.3232,7.15846,40.4789,16.0437
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/4_Power_Consumption1.csv b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/4_Power_Consumption1.csv
new file mode 100644
index 0000000..81d0b12
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/4_Power_Consumption1.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 5.00v, 25°c",0.00034,939.625,841.225
+"SS corner, 4.50v, -40°c",0.00028,735.458,662.67
+"SS corner, 4.50v, 125°c",0.00034,761.49,693.63
+"FF corner, 5.50v, 125°c",0.01866,1195.51,1079.29
+"FF corner, 5.50v, -40°c",0.00041,1140.56,1025.26
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/4_Power_Consumption2.csv b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/4_Power_Consumption2.csv
new file mode 100644
index 0000000..ffce61b
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/4_Power_Consumption2.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 3.3v, 25°c",0.00015,375.012,338.663
+"SS corner, 3.0v, -40°c",0.00012,300.42,275.565
+"SS corner, 3.6v, 125°c",0.00016,318.3,288.78
+"FF corner, 3.6v, 125°c",0.00732,478.296,430.812
+"FF corner, 3.6v, -40°c",0.00018,446.67,403.308
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/4_Power_Consumption3.csv b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/4_Power_Consumption3.csv
new file mode 100644
index 0000000..b764f5a
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/4_Power_Consumption3.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 1.8v, 25°c",0.00004,102.006,93.51
+"SS corner, 1.62v, -40°c",0.00004,81.2349,75.087
+"SS corner, 1.62v, 125°c",0.00005,86.0949,79.1103
+"FF corner, 1.98v, 125°c",0.00236,130.858,119.087
+"FF corner,1.98v, -40°c",0.00005,120.602,110.454
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/5_AC_Characteristics1.csv b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/5_AC_Characteristics1.csv
new file mode 100644
index 0000000..e7e744c
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/5_AC_Characteristics1.csv
@@ -0,0 +1,91 @@
+Symbol,"Parameter
+
+Description","SNSP
+
+Process
+
+4.5v, -40C","SNSP
+
+Process
+
+4.5v, 125C","Typical
+
+Process
+
+5.0v, 25C","FNFP
+
+Process
+
+5.5v, 125C","FNFP
+
+Process
+
+5.5v, -40C",unit
+Tcyc,Min clock period,7.5946,11,6.1181,5.6608,3.957,ns
+Tckh,Min clock high time,3.3401,5.4009,2.6907,2.0829,1.4546,ns
+Tckl,Min clock low time,3.5036,4.9693,2.6661,1.9737,1.5862,ns
+,,,,,,,
+Tcsl,"CEN set up time
+
+( CEN = L )",0.4584,0.5869,0.406,0.3883,0.3228,ns
+Tchl,"CEN hold time
+
+( CEN = L )",1.2328,1.8527,1.1081,1.0768,0.7655,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",0.5124,0.6616,0.435,0.411,0.3369,ns
+Tchh,"CEN hold time
+
+( CEN = H )",1.2868,1.9188,1.1371,1.0995,0.7797,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",0.718,1.0143,0.6281,0.5888,0.4541,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",1.0062,1.3936,0.8467,0.8056,0.6051,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",0.6753,0.9358,0.5903,0.5619,0.4329,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",0.5421,0.712,0.4752,0.4717,0.3744,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0.2681,0.3326,0.2552,0.2318,0.2132,ns
+Twihl,"WEN hold time
+
+( WEN = L )",1.0093,1.3936,0.8467,0.8056,0.6051,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",0.5428,0.7142,0.4752,0.4717,0.3744,ns
+Tasl,"A set up time
+
+( A = L )",0.8176,1.0609,0.6825,0.6069,0.4999,ns
+Tahl,"A hold time
+
+( A = L )",0.6347,0.8154,0.5351,0.4936,0.4026,ns
+Tash,"A set up time
+
+( A = H )",0.6116,0.8236,0.5149,0.4745,0.3738,ns
+Tahh,"A hold time
+
+( A = H )",0.6556,0.8491,0.5475,0.5017,0.4073,ns
+Tdsl,"D set up time
+
+( D = L )",0.1068,0.0793,0.1079,0.0931,0.1215,ns
+Tdhl,"D hold time
+
+( D = L )",0.5319,0.6948,0.4699,0.4799,0.3698,ns
+Tdsh,"D set up time
+
+( D = H )",0.5818,0.7537,0.4744,0.4028,0.3544,ns
+Tdhh,"D hold time
+
+( D= H )",0.7624,1.0445,0.659,0.6446,0.491,ns
+Tah,"Clock high to Q
+
+high",5.5913,8.2512,4.5692,4.2569,2.9344,ns
+Tal,Clock high to Q low,5.7745,8.5132,4.7158,4.3699,3.025,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/5_AC_Characteristics2.csv b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/5_AC_Characteristics2.csv
new file mode 100644
index 0000000..6f29a3a
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/5_AC_Characteristics2.csv
@@ -0,0 +1,79 @@
+Symbol,"Parameter
+description","SNSP
+Process
+3.0v, -40C","SNSP
+Process
+3.0, 125C","Typical
+Process
+3.3v, 25C","FNFP
+Process
+3.6v, 125C","FNFP
+Process
+3.6v, -40C",unit
+Tcyc,Min clock period,11.6044,17.0863,8.5597,7.3978,5.1007,ns
+Tckh,Min clock high time,4.1518,5.1878,3.2873,2.8975,1.8998,ns
+Tckl,Min clock low time,4.2752,6.2768,3.891,2.9738,1.8573,ns
+Tcsl,"CEN set up time
+
+( CEN = L )",0.6591,0.8517,0.542,0.4951,0.4047,ns
+Tchl,"CEN hold time
+
+( CEN = L )",1.9054,2.849,1.592,1.4784,1.0184,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",0.8058,1.0775,0.6175,0.5341,0.4262,ns
+Tchh,"CEN hold time
+
+( CEN = H )",2.0065,2.9742,1.64,1.5046,1.0375,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",1.1586,1.6455,0.9198,0.8113,0.6012,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",1.4693,2.0948,1.1528,1.039,0.7639,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",1.0285,1.4295,0.8241,0.741,0.5578,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",0.7347,1.0252,0.6061,0.5779,0.4516,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0.4276,0.4945,0.36,0.3185,0.2767,ns
+Twihl,"WEN hold time
+
+( WEN = L )",1.47,2.0958,1.1533,1.039,0.7639,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",0.7364,1.0252,0.6064,0.5779,0.4516,ns
+Tasl,"A set up time
+
+( A = L )",1.2239,1.5436,0.9321,0.793,0.634,ns
+Tahl,"A hold time
+
+( A = L )",0.883,1.1501,0.6944,0.6117,0.4942,ns
+Tash,"A set up time
+
+( A = H )",0.9765,1.2625,0.7394,0.6387,0.497,ns
+Tahh,"A hold time
+
+( A = H )",0.9455,1.2363,0.7301,0.6353,0.5077,ns
+Tdsl,"D set up time
+
+( D = L )",0.151,0.0675,0.1406,0.1223,0.1528,ns
+Tdhl,"D hold time
+
+( D = L )",0.6331,0.8795,0.5685,0.56,0.4337,ns
+Tdsh,"D set up time
+
+( D = H )",0.9896,1.2399,0.694,0.5587,0.4635,ns
+Tdhh,"D hold time
+
+( D= H )",1.1116,1.5609,0.8826,0.8138,0.6107,ns
+Tah,"Clock high to Q
+
+high",8.6801,12.588,6.501,5.6753,3.8609,ns
+Tal,Clock high to Q low,9.039,13.1052,6.7522,5.8621,3.994,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/5_AC_Characteristics3.csv b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/5_AC_Characteristics3.csv
new file mode 100644
index 0000000..cfd9a8a
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/5_AC_Characteristics3.csv
@@ -0,0 +1,81 @@
+Symbol,"Parameter
+description","SNSP
+Process
+1.62v, -40C","SNSP
+Process
+1.62v,
+125C","Typical
+Process
+1.8v, 25C","FNFP
+Process
+1.98v,
+125C","FNFP
+Process
+1.98v, -40C",unit
+Tcyc,Min clock period,49.6236,53.6235,22.4703,14.439,10.5548,ns
+Tckh,Min clock high time,18.4434,25.7785,10.9148,3.8319,4.6646,ns
+Tckl,Min clock low time,24.2445,20.8014,10.2887,5.3502,4.7431,ns
+Tcsl,"CEN set up time
+
+( CEN = L )",2.3681,2.4651,1.1518,0.7912,0.6521,ns
+Tchl,"CEN hold time
+
+( CEN = L )",7.2637,8.1415,3.8285,2.745,1.9932,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",3.5818,3.6043,1.5568,0.9701,0.7982,ns
+Tchh,"CEN hold time
+
+( CEN = H )",8.1245,8.8521,4.0462,2.8098,2.0519,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",5.3918,5.595,2.4131,1.5312,1.1886,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",6.6902,7.1843,2.641,1.7922,1.3425,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",3.788,4.1484,1.8898,1.3037,1.0054,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",3.9825,4.2086,1.3454,0.9058,0.7109,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0,0,0.635,0.5269,0.4594,ns
+Twihl,"WEN hold time
+
+( WEN = L )",6.7241,7.2059,2.6513,1.7922,1.345,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",3.9825,4.2086,1.3498,0.9058,0.7109,ns
+Tasl,"A set up time
+
+( A = L )",2.5026,2.5937,1.8544,1.345,1.102,ns
+Tahl,"A hold time
+
+( A = L )",2.4783,2.6941,1.3189,0.9519,0.7682,ns
+Tash,"A set up time
+
+( A = H )",3.5235,3.5752,1.5839,1.1347,0.92,ns
+Tahh,"A hold time
+
+( A = H )",3.0774,3.2544,1.517,1.0314,0.8371,ns
+Tdsl,"D set up time
+
+( D = L )",0,0,0,0.1068,0.1609,ns
+Tdhl,"D hold time
+
+( D = L )",3.233,3.3177,1.0226,0.7713,0.5799,ns
+Tdsh,"D set up time
+
+( D = H )",3.2797,3.1593,1.7976,1.0285,0.9057,ns
+Tdhh,"D hold time
+
+( D= H )",5.9233,6.148,2.1673,1.38,1.0712,ns
+Tah,"Clock high to Q
+
+high",34.2708,37.734,16.1892,10.6138,7.8157,ns
+Tal,Clock high to Q low,36.8388,39.9912,17.106,11.0951,8.1864,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/6_Physical_Dimensions.csv b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/6_Physical_Dimensions.csv
new file mode 100644
index 0000000..e21ac1d
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/6_Physical_Dimensions.csv
@@ -0,0 +1,2 @@
+Width(um),Height(um),Area(um^2)
+431.86,340.88,147212.4368
diff --git a/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/ac_timing.png b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/ac_timing.png
new file mode 100644
index 0000000..d0751e8
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/ac_timing.png
Binary files differ
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/gf180mcu_fd_ip_sram__sram512x8m8wm1.rst b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/gf180mcu_fd_ip_sram__sram512x8m8wm1.rst
new file mode 100644
index 0000000..95c1a3b
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/gf180mcu_fd_ip_sram__sram512x8m8wm1.rst
@@ -0,0 +1,128 @@
+***********************************
+gf180mcu_fd_ip_sram__sram512x8m8wm1
+***********************************
+
+.. centered::
+ **gf180mcu_fd_ip_sram__sram512x8m8wm1**
+.. centered::
+ **180nm 5V Green synchronous single port SRAM**
+.. centered::
+ **Memory Macro IP**
+.. centered::
+ **Datasheet**
+
+====
+
+**Features**
+
+- Uses 180nm 5V Green CMOS 13.5um2 6 transistors bitcell
+
+- 512 words X 8 bits, mux 8 Instance
+
+- Periphery circuitry uses 5V transistors
+
+- Operating voltage is 1.62V to 5.50V
+
+- Operating temperature is -40 degC to 125 degC
+
+- Minimum 3 layers of metals required: Metal1, Metal2, Metal3
+
+- Bit write mask
+
+- Self timed operation to reduce power
+
+- Separate data in and data out ports
+
+- Macro cell name: gf180mcu_fd_ip_sram__sram512x8m8wm1
+
+====================
+1.0 Pins Description
+====================
+
+.. csv-table::
+ :file: specs/1_pins_desc.csv
+
+===============
+2.0 Truth Table
+===============
+
+.. csv-table::
+ :file: specs/2_truth_table.csv
+
+.. note::
+
+ X: don't care
+
+=========================================
+3.0 Capacitance loading ( fF ) @ TT, 25°c
+=========================================
+
+.. csv-table::
+ :file: specs/3_Capacitance_loading.csv
+
+============================
+4.0 Power Consumption ( uW )
+============================
+
+Condition of AC Write power is all data input pins switch and AC Read power is all address input and data output pins switch at 1MHz
+
+==============
+4.1 5.0V Power
+==============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption1.csv
+
+==============
+4.2 3.3V Power
+==============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption2.csv
+
+==============
+4.3 1.8V Power
+==============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption3.csv
+
+======================
+5.0 AC Characteristics
+======================
+
+The timing and power values measured from the input slew of 20ps on clock pin, 20ps on signal and output load .01pF.
+
+5.1 5.0V AC Characteristics
+---------------------------
+
+.. csv-table::
+ :file: specs/5_AC_Characteristics1.csv
+
+5.2 3.3V AC Characteristics
+---------------------------
+
+ .. csv-table::
+ :file: specs/5_AC_Characteristics2.csv
+
+5.3 1.8V AC Characteristics
+---------------------------
+
+.. csv-table::
+ :file: specs/5_AC_Characteristics3.csv
+
+.. centered::
+ **AC Timing Waveform Chart**
+
+.. image:: specs/ac_timing.png
+ :width: 600
+ :align: center
+ :alt: AC Timing Waveform Chart
+
+=======================
+6.0 Physical Dimensions
+=======================
+
+.. csv-table::
+ :file: specs/6_Physical_Dimensions.csv
+
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/0_release.csv b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/0_release.csv
new file mode 100644
index 0000000..cc8d44f
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/0_release.csv
@@ -0,0 +1,2 @@
+"",Date,Description
+1.0,2014/06/20,Release
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/1_pins_desc.csv b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/1_pins_desc.csv
new file mode 100644
index 0000000..4859265
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/1_pins_desc.csv
@@ -0,0 +1,44 @@
+Signal,Direction,Description
+CLK,Input,"Clock for the memory. Rising edge triggers
+
+operation. All inputs are latched at rising edge of the
+
+clock signal"
+CEN,Input,"Memory Enable, Active Low. When CEN is Low, the
+
+memory is enabled. When CEN input is High, the
+
+memory is deactivated but internal states are
+
+retained. CEN must be high before 1st running cycle."
+A[6:0],Input,"Address Input. This Address input port is used to
+
+address the location to be written during the write
+
+cycle and read during the read cycle."
+GWEN,Input,"Write Enable Input. The RAM is in write cycle when
+
+GWEN is low. The RAM is in read cycle when
+
+GWEN is high."
+WEN[7:0],Input,"Bit Write Mask, Active Low. When the memory is in
+
+the write cycle, selectively write into individual
+
+outputs are controlled by WEN[7:0]. For example, if
+
+CEN, GWEN, WEN[0] are low and WEN[7:1] are
+
+high, only D[0] will write into the addressed location and
+
+D[7:1] will be ignored during CLK low to high transition."
+D[7:0],Input,"Data input bus. The data input bus is used to write
+
+data into the memory location specified by address
+
+input port during the write cycle."
+Q[7:0],output,"Data output bus. It outputs the contents of the
+
+memory location addressed by the Address Input signals."
+VDD,Power,Power pin.
+VSS,Ground,Ground pin.
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/2_truth_table.csv b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/2_truth_table.csv
new file mode 100644
index 0000000..94ed477
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/2_truth_table.csv
@@ -0,0 +1,6 @@
+CLK,CEN,GWEN,WEN,A,D,Q,status
+,H,X,X,X,X,Hold previous data,Standby mode
+,L,H,X,A,X,Q,Read mode
+,L,L,H,A,D,Hold previous data,Write mode
+,L,L,L,A,D,Hold previous data,Mask mode
+other,X,X,X,X,X,Hold previous data,Unchanged
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/3_Capacitance_loading.csv b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/3_Capacitance_loading.csv
new file mode 100644
index 0000000..1ac9491
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/3_Capacitance_loading.csv
@@ -0,0 +1,4 @@
+Voltage,CLK,CEN,GWEN,WEN,A,D
+5.0v,297.584,18.1905,49.4974,7.84667,40.1181,16.7494
+3.3v,293.159,18.27,48.0111,7.64901,40.1976,16.6433
+1.8v,282.301,18.2531,44.3231,7.15847,40.1807,16.0497
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/4_Power_Consumption1.csv b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/4_Power_Consumption1.csv
new file mode 100644
index 0000000..014d518
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/4_Power_Consumption1.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 5.00v, 25°c",0.00062,1017.1,908.1
+"SS corner, 4.50v, -40°c",0.0005,800.37,721.237
+"SS corner, 4.50v, 125°c",0.00062,830.363,746.438
+"FF corner, 5.50v, 125°c",0.0309,1293.85,1165.42
+"FF corner, 5.50v, -40°c",0.00075,1231.09,1109.16
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/4_Power_Consumption2.csv b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/4_Power_Consumption2.csv
new file mode 100644
index 0000000..1b4f582
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/4_Power_Consumption2.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 3.3v, 25°c",0.00027,408.606,369.6
+"SS corner, 3.0v, -40°c",0.00022,330.795,301.665
+"SS corner, 3.6v, 125°c",0.00028,347.865,314.25
+"FF corner, 3.6v, 125°c",0.01212,520.218,468.576
+"FF corner, 3.6v, -40°c",0.00032,487.188,437.886
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/4_Power_Consumption3.csv b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/4_Power_Consumption3.csv
new file mode 100644
index 0000000..ede4448
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/4_Power_Consumption3.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 1.8v, 25°c",0.00008,112.563,103.176
+"SS corner, 1.62v, -40°c",0.00006,91.53,84.2238
+"SS corner, 1.62v, 125°c",0.00009,95.2317,87.8526
+"FF corner, 1.98v, 125°c",0.00394,144.174,130.433
+"FF corner,1.98v, -40°c",0.0001,133.709,121.344
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/5_AC_Characteristics1.csv b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/5_AC_Characteristics1.csv
new file mode 100644
index 0000000..294e01b
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/5_AC_Characteristics1.csv
@@ -0,0 +1,90 @@
+Symbol,"Parameter
+
+Description","SNSP
+
+Process
+
+4.5v, -40C","SNSP
+
+Process
+
+4.5v, 125C","Typical
+
+Process
+
+5.0v, 25C","FNFP
+
+Process
+
+5.5v, 125C","FNFP
+
+Process
+
+5.5v, -40C",unit
+Tcyc,Min clock period,11.8901,6.5937,6.077,4.2421,11.8901,ns
+Tckh,Min clock high time,4.3873,2.3769,2.1038,1.8983,4.3873,ns
+Tckl,Min clock low time,5.7235,2.2522,1.9814,1.4532,5.7235,ns
+Tcsl,"CEN set up time
+
+( CEN = L )",0.4582,0.5864,0.4059,0.3889,0.3231,ns
+Tchl,"CEN hold time
+
+( CEN = L )",1.2316,1.8518,1.1086,1.0775,0.7646,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",0.5133,0.6606,0.4354,0.411,0.3375,ns
+Tchh,"CEN hold time
+
+( CEN = H )",1.2867,1.9195,1.1381,1.0996,0.779,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",0.7179,1.0125,0.6271,0.5879,0.4532,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",1.0255,1.4235,0.8652,0.819,0.6148,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",0.6755,0.9341,0.5901,0.5622,0.433,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",0.5605,0.7418,0.4925,0.4851,0.3836,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0.2494,0.3009,0.2391,0.218,0.2038,ns
+Twihl,"WEN hold time
+
+( WEN = L )",1.0282,1.4235,0.8652,0.819,0.6148,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",0.5605,0.7418,0.4931,0.4851,0.3837,ns
+Tasl,"A set up time
+
+( A = L )",1.1558,1.5283,0.9474,0.8643,0.679,ns
+Tahl,"A hold time
+
+( A = L )",0.6375,0.8184,0.5362,0.4959,0.4032,ns
+Tash,"A set up time
+
+( A = H )",0.7684,1.0405,0.6332,0.5787,0.4539,ns
+Tahh,"A hold time
+
+( A = H )",0.659,0.8526,0.549,0.5055,0.4089,ns
+Tdsl,"D set up time
+
+( D = L )",0.0889,0.0487,0.094,0.0803,0.1129,ns
+Tdhl,"D hold time
+
+( D = L )",0.5488,0.7168,0.4841,0.4914,0.3799,ns
+Tdsh,"D set up time
+
+( D = H )",0.5634,0.7242,0.4577,0.3912,0.3446,ns
+Tdhh,"D hold time
+
+( D= H )",0.7802,1.0735,0.6741,0.6581,0.5006,ns
+Tah,"Clock high to Q
+
+high",5.953,8.7955,4.8599,4.5151,3.1066,ns
+Tal,Clock high to Q low,6.1438,9.0608,5.008,4.6284,3.2005,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/5_AC_Characteristics2.csv b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/5_AC_Characteristics2.csv
new file mode 100644
index 0000000..45c8971
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/5_AC_Characteristics2.csv
@@ -0,0 +1,79 @@
+Symbol,"Parameter
+description","SNSP
+Process
+3.0v, -40C","SNSP
+Process
+3.0, 125C","Typical
+Process
+3.3v, 25C","FNFP
+Process
+3.6v, 125C","FNFP
+Process
+3.6v, -40C",unit
+Tcyc,Min clock period,12.5529,18.2595,9.2406,7.9594,5.48,ns
+Tckh,Min clock high time,4.5988,5.6648,3.5802,3.2438,2.1235,ns
+Tckl,Min clock low time,5.8235,5.4055,3.3345,3.7782,2.5263,ns
+Tcsl,"CEN set up time
+
+( CEN = L )",0.658,0.8516,0.5415,0.497,0.4053,ns
+Tchl,"CEN hold time
+
+( CEN = L )",1.9061,2.8524,1.5935,1.4765,1.0184,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",0.8032,1.076,0.6128,0.5388,0.4264,ns
+Tchh,"CEN hold time
+
+( CEN = H )",2.0053,2.9771,1.6396,1.5031,1.037,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",1.1636,1.645,0.9175,0.8121,0.5997,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",1.5057,2.1524,1.1825,1.061,0.7786,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",1.0276,1.4295,0.8238,0.742,0.5564,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",0.7708,1.0797,0.6333,0.5996,0.4649,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0.3907,0.444,0.3367,0.2966,0.2662,ns
+Twihl,"WEN hold time
+
+( WEN = L )",1.5067,2.1547,1.1829,1.061,0.7786,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",0.7718,1.0797,0.6336,0.5996,0.4649,ns
+Tasl,"A set up time
+
+( A = L )",1.6927,2.2075,1.2815,1.1145,0.8544,ns
+Tahl,"A hold time
+
+( A = L )",0.884,1.1506,0.6974,0.6173,0.4955,ns
+Tash,"A set up time
+
+( A = H )",1.2458,1.6418,0.9275,0.7869,0.6093,ns
+Tahh,"A hold time
+
+( A = H )",0.9477,1.2387,0.7323,0.6397,0.5087,ns
+Tdsl,"D set up time
+
+( D = L )",0.1197,0.0318,0.1189,0.1044,0.1415,ns
+Tdhl,"D hold time
+
+( D = L )",0.668,0.9388,0.5924,0.576,0.4429,ns
+Tdsh,"D set up time
+
+( D = H )",0.9612,1.1874,0.6739,0.5391,0.4509,ns
+Tdhh,"D hold time
+
+( D= H )",1.1461,1.6115,0.9064,0.8323,0.6202,ns
+Tah,"Clock high to Q
+
+high",13.464,6.9234,6.0334,4.09,13.464,ns
+Tal,Clock high to Q low,13.974,7.1773,6.2146,4.2304,13.974,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/5_AC_Characteristics3.csv b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/5_AC_Characteristics3.csv
new file mode 100644
index 0000000..ec2bd94
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/5_AC_Characteristics3.csv
@@ -0,0 +1,81 @@
+Symbol,"Parameter
+description","SNSP
+Process
+1.62v, -40C","SNSP
+Process
+1.62v,
+125C","Typical
+Process
+1.8v, 25C","FNFP
+Process
+1.98v,
+125C","FNFP
+Process
+1.98v, -40C",unit
+Tcyc,Min clock period,52.6523,56.5713,23.5606,14.9291,10.9449,ns
+Tckh,Min clock high time,17.8208,13.3554,11.779,7.4108,4.2538,ns
+Tckl,Min clock low time,24.5821,27.1047,10.0614,6.1401,4.34,ns
+Tcsl,"CEN set up time
+
+( CEN = L )",2.3698,2.4602,1.1516,0.801,0.6549,ns
+Tchl,"CEN hold time
+
+( CEN = L )",7.2664,8.1591,3.8304,2.7423,2.0008,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",3.5768,3.5842,1.5564,0.9737,0.7969,ns
+Tchh,"CEN hold time
+
+( CEN = H )",8.1164,8.8542,4.0473,2.8046,2.056,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",5.3954,5.5797,2.4116,1.5291,1.1932,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",6.8571,7.3684,2.7234,1.8466,1.3762,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",3.7876,4.1535,1.8907,1.2981,1.0047,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",4.1373,4.3563,1.4279,0.9502,0.7447,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0,0,0.5579,0.4839,0.4286,ns
+Twihl,"WEN hold time
+
+( WEN = L )",6.895,7.3911,2.7323,1.8466,1.3786,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",4.1449,4.3647,1.4331,0.9502,0.7447,ns
+Tasl,"A set up time
+
+( A = L )",3.7675,4.186,2.5915,1.8749,1.4826,ns
+Tahl,"A hold time
+
+( A = L )",2.4888,2.7025,1.3228,0.954,0.7737,ns
+Tash,"A set up time
+
+( A = H )",3.5248,3.6466,2.1665,1.4549,1.1977,ns
+Tahh,"A hold time
+
+( A = H )",3.0827,3.2603,1.5182,1.0367,0.8439,ns
+Tdsl,"D set up time
+
+( D = L )",0,0,0,0.0668,0.1388,ns
+Tdhl,"D hold time
+
+( D = L )",3.3868,3.4901,1.0901,0.8321,0.6123,ns
+Tdsh,"D set up time
+
+( D = H )",3.1979,3.0367,1.745,0.9832,0.8835,ns
+Tdhh,"D hold time
+
+( D= H )",6.0875,6.3089,2.2346,1.4269,1.1036,ns
+Tah,"Clock high to Q
+
+high",36.7512,40.5756,17.2992,11.3022,8.3234,ns
+Tal,Clock high to Q low,39.2964,42.84,18.2016,11.7799,8.7016,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/6_Physical_Dimensions.csv b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/6_Physical_Dimensions.csv
new file mode 100644
index 0000000..b1fec58
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/6_Physical_Dimensions.csv
@@ -0,0 +1,2 @@
+Width(um),Height(um),Area(um^2)
+431.86,484.88,209400.2768
diff --git a/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/ac_timing.png b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/ac_timing.png
new file mode 100644
index 0000000..6058584
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/ac_timing.png
Binary files differ
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/gf180mcu_fd_ip_sram__sram64x8m8wm1.rst b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/gf180mcu_fd_ip_sram__sram64x8m8wm1.rst
new file mode 100644
index 0000000..6ee8623
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/gf180mcu_fd_ip_sram__sram64x8m8wm1.rst
@@ -0,0 +1,128 @@
+**********************************
+gf180mcu_fd_ip_sram__sram64x8m8wm1
+**********************************
+
+.. centered::
+ **gf180mcu_fd_ip_sram__sram64x8m8wm1**
+.. centered::
+ **180nm 5V Green synchronous single port SRAM**
+.. centered::
+ **Memory Macro IP**
+.. centered::
+ **Datasheet**
+
+====
+
+**Features**
+
+- Uses 180nm 5V Green CMOS 13.5um2 6 transistors bitcell
+
+- 64 words X 8 bits, mux 8 Instance
+
+- Periphery circuitry uses 5V transistors
+
+- Operating voltage is 1.62V to 5.50V
+
+- Operating temperature is -40 degC to 125 degC
+
+- Minimum 3 layers of metals required: Metal1, Metal2, Metal3
+
+- Bit write mask
+
+- Self timed operation to reduce power
+
+- Separate data in and data out ports
+
+- Macro cell name: gf180mcu_fd_ip_sram__sram64x8m8wm1
+
+
+1.0 Pins Description
+====================
+
+.. csv-table::
+ :file: specs/1_pins_desc.csv
+
+2.0 Truth Table
+===============
+
+.. csv-table::
+ :file: specs/2_truth_table.csv
+
+.. note::
+
+ X: don't care
+
+3.0 Capacitance loading ( fF ) @ TT, 25°c
+=========================================
+
+.. csv-table::
+ :file: specs/3_Capacitance_loading.csv
+
+============================
+4.0 Power Consumption ( uW )
+============================
+
+Condition of AC Write power is all data input pins switch and AC Read power is all address input and data output pins switch at 1MHz
+
+===============
+ 4.1 5.0V Power
+===============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption1.csv
+
+==============
+4.2 3.3V Power
+==============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption2.csv
+
+==============
+4.3 1.8V Power
+==============
+
+.. csv-table::
+ :file: specs/4_Power_Consumption3.csv
+
+======================
+5.0 AC Characteristics
+======================
+
+The timing and power values measured from the input slew of 20ps on clock pin, 20ps on signal and output load .01pF.
+
+===========================
+5.1 5.0V AC Characteristics
+===========================
+
+.. csv-table::
+ :file: specs/5_AC_Characteristics1.csv
+
+===========================
+5.2 3.3V AC Characteristics
+===========================
+
+ .. csv-table::
+ :file: specs/5_AC_Characteristics2.csv
+
+5.3 1.8V AC Characteristics
+---------------------------
+
+.. csv-table::
+ :file: specs/5_AC_Characteristics3.csv
+
+.. centered::
+ **AC Timing Waveform Chart**
+
+.. image:: specs/ac_timing.png
+ :width: 600
+ :align: center
+ :alt: AC Timing Waveform Chart
+
+6.0 Physical Dimensions
+=======================
+
+.. csv-table::
+ :file: specs/6_Physical_Dimensions.csv
+
+
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/0_release.csv b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/0_release.csv
new file mode 100644
index 0000000..cc8d44f
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/0_release.csv
@@ -0,0 +1,2 @@
+"",Date,Description
+1.0,2014/06/20,Release
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/1_pins_desc.csv b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/1_pins_desc.csv
new file mode 100644
index 0000000..4859265
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/1_pins_desc.csv
@@ -0,0 +1,44 @@
+Signal,Direction,Description
+CLK,Input,"Clock for the memory. Rising edge triggers
+
+operation. All inputs are latched at rising edge of the
+
+clock signal"
+CEN,Input,"Memory Enable, Active Low. When CEN is Low, the
+
+memory is enabled. When CEN input is High, the
+
+memory is deactivated but internal states are
+
+retained. CEN must be high before 1st running cycle."
+A[6:0],Input,"Address Input. This Address input port is used to
+
+address the location to be written during the write
+
+cycle and read during the read cycle."
+GWEN,Input,"Write Enable Input. The RAM is in write cycle when
+
+GWEN is low. The RAM is in read cycle when
+
+GWEN is high."
+WEN[7:0],Input,"Bit Write Mask, Active Low. When the memory is in
+
+the write cycle, selectively write into individual
+
+outputs are controlled by WEN[7:0]. For example, if
+
+CEN, GWEN, WEN[0] are low and WEN[7:1] are
+
+high, only D[0] will write into the addressed location and
+
+D[7:1] will be ignored during CLK low to high transition."
+D[7:0],Input,"Data input bus. The data input bus is used to write
+
+data into the memory location specified by address
+
+input port during the write cycle."
+Q[7:0],output,"Data output bus. It outputs the contents of the
+
+memory location addressed by the Address Input signals."
+VDD,Power,Power pin.
+VSS,Ground,Ground pin.
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/2_truth_table.csv b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/2_truth_table.csv
new file mode 100644
index 0000000..94ed477
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/2_truth_table.csv
@@ -0,0 +1,6 @@
+CLK,CEN,GWEN,WEN,A,D,Q,status
+,H,X,X,X,X,Hold previous data,Standby mode
+,L,H,X,A,X,Q,Read mode
+,L,L,H,A,D,Hold previous data,Write mode
+,L,L,L,A,D,Hold previous data,Mask mode
+other,X,X,X,X,X,Hold previous data,Unchanged
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/3_Capacitance_loading.csv b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/3_Capacitance_loading.csv
new file mode 100644
index 0000000..e20daac
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/3_Capacitance_loading.csv
@@ -0,0 +1,4 @@
+Voltage,CLK,CEN,GWEN,WEN,A,D
+5.0v,296.201,17.6988,49.6735,7.84667,34.5188,16.5528
+3.3v,291.776,17.7783,48.1872,7.64901,34.5983,16.4468
+1.8v,280.919,17.7614,44.4991,7.15847,34.5814,16.1834
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/4_Power_Consumption1.csv b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/4_Power_Consumption1.csv
new file mode 100644
index 0000000..4ff1314
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/4_Power_Consumption1.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 5.00v, 25°c",0.00013,859.2,770.85
+"SS corner, 4.50v, -40°c",0.00011,670.77,603.675
+"SS corner, 4.50v, 125°c",0.00014,701.798,630.697
+"FF corner, 5.50v, 125°c",0.00946,1103.25,991.21
+"FF corner, 5.50v, -40°c",0.00016,1046.15,940.445
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/4_Power_Consumption2.csv b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/4_Power_Consumption2.csv
new file mode 100644
index 0000000..43691c3
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/4_Power_Consumption2.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 3.3v, 25°c",0.00006,342.144,310.2
+"SS corner, 3.0v, -40°c",0.00005,273.045,249.09
+"SS corner, 3.6v, 125°c",0.00006,289.68,263.76
+"FF corner, 3.6v, 125°c",0.0037,441.252,395.91
+"FF corner, 3.6v, -40°c",0.00007,409.23,368.748
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/4_Power_Consumption3.csv b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/4_Power_Consumption3.csv
new file mode 100644
index 0000000..3ee41ca
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/4_Power_Consumption3.csv
@@ -0,0 +1,6 @@
+Condition,DC standby,AC Write,AC Read
+"TT corner, 1.8v, 25°c",0.00002,92.043,84.3399
+"SS corner, 1.62v, -40°c",0.00001,72.2552,67.2535
+"SS corner, 1.62v, 125°c",0.00002,77.4279,71.1626
+"FF corner, 1.98v, 125°c",0.0012,120.582,108.841
+"FF corner,1.98v, -40°c",0.00002,110.484,100.495
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/5_AC_Characteristics1.csv b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/5_AC_Characteristics1.csv
new file mode 100644
index 0000000..b46892f
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/5_AC_Characteristics1.csv
@@ -0,0 +1,90 @@
+Symbol,"Parameter
+
+Description","SNSP
+
+Process
+
+4.5v, -40C","SNSP
+
+Process
+
+4.5v, 125C","Typical
+
+Process
+
+5.0v, 25C","FNFP
+
+Process
+
+5.5v, 125C","FNFP
+
+Process
+
+5.5v, -40C",unit
+Tcyc,Min clock period,7.1094,10.2796,5.7473,5.3301,3.7332,ns
+Tckh,Min clock high time,3.2696,3.9625,2.2315,2.3664,1.4138,ns
+Tckl,Min clock low time,2.723,4.8463,2.5397,2.4258,1.355,ns
+Tcsl,"CEN set up time
+
+( CEN = L )",0.4573,0.5866,0.4058,0.3883,0.3234,ns
+Tchl,"CEN hold time
+
+( CEN = L )",1.2309,1.8505,1.1082,1.0785,0.764,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",0.514,0.6623,0.4352,0.4114,0.3381,ns
+Tchh,"CEN hold time
+
+( CEN = H )",1.2875,1.9179,1.1376,1.1016,0.7788,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",0.719,1.015,0.63,0.5885,0.4551,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",0.9841,1.3576,0.8289,0.7912,0.5933,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",0.6762,0.9362,0.592,0.563,0.4351,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",0.5182,0.6761,0.456,0.4575,0.3629,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0.2931,0.3655,0.2719,0.244,0.2246,ns
+Twihl,"WEN hold time
+
+( WEN = L )",0.9867,1.3576,0.8289,0.7912,0.5933,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",0.5225,0.6786,0.4561,0.4575,0.3629,ns
+Tasl,"A set up time
+
+( A = L )",0.8445,1.095,0.7027,0.6325,0.5165,ns
+Tahl,"A hold time
+
+( A = L )",0.6188,0.7925,0.5272,0.492,0.4005,ns
+Tash,"A set up time
+
+( A = H )",0.6391,0.8833,0.537,0.4936,0.3872,ns
+Tahh,"A hold time
+
+( A = H )",0.6421,0.8303,0.5416,0.5018,0.406,ns
+Tdsl,"D set up time
+
+( D = L )",0.1233,0.1049,0.1234,0.1046,0.1296,ns
+Tdhl,"D hold time
+
+( D = L )",0.5086,0.6605,0.4518,0.4675,0.3608,ns
+Tdsh,"D set up time
+
+( D = H )",0.6006,0.7833,0.4892,0.4136,0.3622,ns
+Tdhh,"D hold time
+
+( D= H )",0.7431,1.0139,0.6432,0.6316,0.4818,ns
+Tah,"Clock high to Q
+
+high",5.2963,7.7968,4.339,4.0561,2.7985,ns
+Tal,Clock high to Q low,5.4809,8.0592,4.4822,4.1672,2.8862,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/5_AC_Characteristics2.csv b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/5_AC_Characteristics2.csv
new file mode 100644
index 0000000..86e8c8a
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/5_AC_Characteristics2.csv
@@ -0,0 +1,90 @@
+Symbol,"Parameter
+
+description","SNSP
+
+Process
+
+3.0v, -40C","SNSP
+
+Process
+
+3.0, 125C","Typical
+
+Process
+
+3.3v, 25C","FNFP
+
+Process
+
+3.6v, 125C","FNFP
+
+Process
+
+3.6v, -40C",unit
+Tcyc,Min clock period,11.0881,16.3302,8.2602,7.1405,4.8003,ns
+Tckh,Min clock high time,5.2766,4.546,2.6935,3.4945,2.3063,ns
+Tckl,Min clock low time,4.0239,7.031,3.0279,3.1873,2.0473,ns
+Tcsl,"CEN set up time
+
+( CEN = L )",0.6574,0.8496,0.5408,0.497,0.4055,ns
+Tchl,"CEN hold time
+
+( CEN = L )",1.8972,2.8488,1.5921,1.4759,1.0202,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",0.8078,1.078,0.6156,0.5383,0.4256,ns
+Tchh,"CEN hold time
+
+( CEN = H )",2.0022,2.9741,1.6413,1.5021,1.0371,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",1.1603,1.6477,0.9192,0.8133,0.601,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",1.426,2.0375,1.1276,1.0157,0.7499,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",1.0297,1.4308,0.8248,0.742,0.5575,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",0.6921,0.962,0.5782,0.5566,0.4374,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0.4664,0.5547,0.3886,0.337,0.2926,ns
+Twihl,"WEN hold time
+
+( WEN = L )",1.4269,2.0375,1.1276,1.016,0.7505,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",0.6944,0.962,0.5789,0.5566,0.4374,ns
+Tasl,"A set up time
+
+( A = L )",1.2506,1.5795,0.9573,0.8183,0.6528,ns
+Tahl,"A hold time
+
+( A = L )",0.8435,1.1028,0.6808,0.6072,0.4906,ns
+Tash,"A set up time
+
+( A = H )",1.0439,1.3746,0.7931,0.6787,0.5232,ns
+Tahh,"A hold time
+
+( A = H )",0.9133,1.1999,0.7195,0.6323,0.5058,ns
+Tdsl,"D set up time
+
+( D = L )",0.182,0.1272,0.1649,0.1445,0.1652,ns
+Tdhl,"D hold time
+
+( D = L )",0.5964,0.8295,0.5427,0.5413,0.421,ns
+Tdsh,"D set up time
+
+( D = H )",1.0245,1.2872,0.7225,0.5774,0.4764,ns
+Tdhh,"D hold time
+
+( D= H )",1.0708,1.5056,0.8569,0.7908,0.5979,ns
+Tah,"Clock high to Q
+
+high",8.1919,11.9542,6.1696,5.4029,3.6754,ns
+Tal,Clock high to Q low,8.5514,12.456,6.417,5.5901,3.8098,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/5_AC_Characteristics3.csv b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/5_AC_Characteristics3.csv
new file mode 100644
index 0000000..4aacb66
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/5_AC_Characteristics3.csv
@@ -0,0 +1,92 @@
+Symbol,"Parameter
+
+description","SNSP
+
+Process
+
+1.62v, -40C","SNSP
+
+Process
+
+1.62v,
+125C","Typical
+
+Process
+
+1.8v, 25C","FNFP
+
+Process
+
+1.98v,
+125C","FNFP
+
+Process
+
+1.98v, -40C",unit
+Tcyc,Min clock period,46.9428,50.9738,21.4387,13.8797,10.1117,ns
+Tckh,Min clock high time,17.8048,12.4148,5.5918,3.916,4.9481,ns
+Tckl,Min clock low time,20.3458,23.4901,9.3467,5.9066,4.7369,ns
+Tcsl,"CEN set up time
+
+( CEN = L )",2.3723,2.4627,1.1531,0.8039,0.6538,ns
+Tchl,"CEN hold time
+
+( CEN = L )",7.2625,8.1371,3.8299,2.7467,2.0012,ns
+Tcsh,"CEN set up time
+
+( CEN = H )",3.5906,3.6093,1.5645,0.973,0.7991,ns
+Tchh,"CEN hold time
+
+( CEN = H )",8.1157,8.8493,4.0493,2.806,2.0585,ns
+Twsl,"GWEN set up time
+
+( GWEN = L )",5.437,5.6091,2.4169,1.5313,1.1881,ns
+Twhl,"GWEN hold time
+
+( GWEN = L )",6.4375,6.9235,2.5611,1.7504,1.3035,ns
+Twsh,"GWEN set up time
+
+( GWEN = H )",3.7804,4.1608,1.8848,1.2969,1.004,ns
+Twhh,"GWEN hold time
+
+( GWEN = H )",3.7001,3.9258,1.2605,0.8555,0.6691,ns
+Twisl,"WEN set up time
+
+( WEN = L )",0.089,0.1242,0.7187,0.566,0.5008,ns
+Twihl,"WEN hold time
+
+( WEN = L )",6.47,6.9448,2.572,1.7504,1.3079,ns
+Twish,"WEN set up time
+
+( WEN = H )",0,0,0,0,0,ns
+Twihh,"WEN hold time
+
+( WEN = H )",3.7346,3.9386,1.2609,0.8555,0.6691,ns
+Tasl,"A set up time
+
+( A = L )",2.7499,2.7972,1.9241,1.362,1.1243,ns
+Tahl,"A hold time
+
+( A = L )",2.3664,2.566,1.276,0.938,0.7583,ns
+Tash,"A set up time
+
+( A = H )",3.4976,3.5401,1.811,1.2267,1.0163,ns
+Tahh,"A hold time
+
+( A = H )",2.9875,3.1533,1.4855,1.0268,0.8386,ns
+Tdsl,"D set up time
+
+( D = L )",0,0,0.0245,0.1435,0.1899,ns
+Tdhl,"D hold time
+
+( D = L )",2.9813,3.0888,0.9452,0.7355,0.5491,ns
+Tdsh,"D set up time
+
+( D = H )",3.4777,3.3172,1.841,1.061,0.9368,ns
+Tdhh,"D hold time
+
+( D= H )",5.6811,5.9063,2.0886,1.3397,1.0391,ns
+Tah,"Clock high to Q
+
+high",32.2344,35.5512,15.2892,10.1268,7.4477,ns
+Tal,Clock high to Q low,34.7448,37.83,16.1808,10.5967,7.8205,ns
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/6_Physical_Dimensions.csv b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/6_Physical_Dimensions.csv
new file mode 100644
index 0000000..40954de
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/6_Physical_Dimensions.csv
@@ -0,0 +1,2 @@
+Width(um),Height(um),Area(um^2)
+431.86,232.88,100571.5568
diff --git a/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/ac_timing.png b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/ac_timing.png
new file mode 100644
index 0000000..30ebd6b
--- /dev/null
+++ b/cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/ac_timing.png
Binary files differ
diff --git a/docs/cells b/docs/cells
new file mode 120000
index 0000000..763bf85
--- /dev/null
+++ b/docs/cells
@@ -0,0 +1 @@
+../cells/
\ No newline at end of file
diff --git a/docs/index.rst b/docs/index.rst
new file mode 100644
index 0000000..1bb1b42
--- /dev/null
+++ b/docs/index.rst
@@ -0,0 +1,14 @@
+
+*******************************************************************************
+`gf180mcu_fd_ip_sram` - GlobalFoundries provided SRAM for GF180MCU process node
+*******************************************************************************
+
+.. toctree::
+ :maxdepth: 2
+ :glob:
+
+ cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/gf180mcu_fd_ip_sram__sram64x8m8wm1
+ cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/gf180mcu_fd_ip_sram__sram128x8m8wm1
+ cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/gf180mcu_fd_ip_sram__sram256x8m8wm1
+ cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/gf180mcu_fd_ip_sram__sram512x8m8wm1
+
