Signal,Direction,Description
CLK,Input,"Clock for the memory. Rising edge triggers

operation. All inputs are latched at rising edge of the

clock signal"
CEN,Input,"Memory Enable, Active Low. When CEN is Low, the

memory is enabled. When CEN input is High, the

memory is deactivated but internal states are

retained. CEN must be high before 1st running cycle."
A[6:0],Input,"Address Input. This Address input port is used to

address the location to be written during the write

cycle and read during the read cycle."
GWEN,Input,"Write Enable Input. The RAM is in write cycle when

GWEN is low. The RAM is in read cycle when

GWEN is high."
WEN[7:0],Input,"Bit Write Mask, Active Low. When the memory is in

the write cycle, selectively write into individual

outputs are controlled by WEN[7:0]. For example, if

CEN, GWEN, WEN[0] are low and WEN[7:1] are

high, only D[0] will write into the addressed location and

D[7:1] will be ignored during CLK low to high transition."
D[7:0],Input,"Data input bus. The data input bus is used to write

data into the memory location specified by address

input port during the write cycle."
Q[7:0],output,"Data output bus. It outputs the contents of the

memory location addressed by the Address Input signals."
VDD,Power,Power pin.
VSS,Ground,Ground pin.