Merge pull request #108 from mabrains/bcdlite_mos
Adding MOS devices derivations for BCDLite
diff --git a/BCDLite/klayout/lvs/gf180BCDLite.lvs b/BCDLite/klayout/lvs/gf180BCDLite.lvs
index f94f962..e489b67 100644
--- a/BCDLite/klayout/lvs/gf180BCDLite.lvs
+++ b/BCDLite/klayout/lvs/gf180BCDLite.lvs
@@ -183,6 +183,21 @@
logger.info("METAL_STACK Selected is #{METAL_LEVEL}")
+# POLY_RES
+POLY_RES = $poly_res || '1k'
+
+logger.info("POLY_RES Selected is #{POLY_RES}")
+
+# MIM
+MIM_OPTION = $mim_option || 'B'
+
+logger.info("MIM Option selected: #{MIM_OPTION}")
+
+# MIM
+MIM_CAP = $mim_cap || '2'
+
+logger.info("MIM CAP selected: #{MIM_CAP}")
+
#================================================
# --------------- CUSTOM CLASSES ----------------
#================================================
@@ -209,7 +224,7 @@
end
#================================================
-#------------- LAYERS DERIVATIONS ---------------
+#------------- LAYERS DEFINITIONS ---------------
#================================================
# %include rule_decks/layers_definition.lvs
@@ -224,7 +239,7 @@
#------------- LAYERS DERIVATIONS ---------------
#================================================
-logger.info('Starting deriving base layers.')
+logger.info('Starting base layers derivations')
#==================================
# ------ GENERAL DERIVATIONS ------
@@ -238,6 +253,30 @@
# %include rule_decks/bjt_derivations.lvs
+#=================================
+# ------ DIODE DERIVATIONS -------
+#=================================
+
+# %include rule_decks/diode_derivations.lvs
+
+#==================================
+# ------ MIMCAP DERIVATIONS -------
+#==================================
+
+# %include rule_decks/mimcap_derivations.lvs
+
+#====================================
+# ------ VARACTOR DERIVATIONS -------
+#====================================
+
+# %include rule_decks/varactor_derivations.lvs
+
+#==================================
+# ------ PISCAP DERIVATIONS -------
+#==================================
+
+# %include rule_decks/piscap_derivations.lvs
+
#================================================
#------------ DEVICES CONNECTIVITY --------------
#================================================
@@ -256,6 +295,30 @@
# %include rule_decks/bjt_extraction.lvs
+#=================================
+# ------- DIODE EXTRACTION -------
+#=================================
+
+# %include rule_decks/diode_extraction.lvs
+
+#==================================
+# ------- MIMCAP EXTRACTION -------
+#==================================
+
+# %include rule_decks/mimcap_extraction.lvs
+
+#====================================
+# ------- VARACTOR EXTRACTION -------
+#====================================
+
+# %include rule_decks/varactor_extraction.lvs
+
+#=================================
+# ------- PICAP EXTRACTION -------
+#=================================
+
+# %include rule_decks/piscap_extraction.lvs
+
#================================================
#------------- COMPARISON OPTIONS ---------------
#================================================
diff --git a/BCDLite/klayout/lvs/rule_decks/bjt_connections.lvs b/BCDLite/klayout/lvs/rule_decks/bjt_connections.lvs
new file mode 100644
index 0000000..5d1e477
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/bjt_connections.lvs
@@ -0,0 +1,73 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ------ BJT CONNECTIONS --------
+#================================
+logger.info('Starting LVS BJT CONNECTIONS')
+
+# ==============
+# ---- vnpn ----
+# ==============
+
+# npn_05p00x05p00 nodes connections
+connect(npn_05p00x05p00_e, contact)
+connect(npn_05p00x05p00_b, contact)
+connect(npn_05p00x05p00_c, contact)
+
+# npn_00p54x16p00 nodes connections
+connect(npn_00p54x16p00_e, contact)
+connect(npn_00p54x16p00_b, contact)
+connect(npn_00p54x16p00_c, contact)
+
+# npn_00p54x08p00 nodes connections
+connect(npn_00p54x08p00_e, contact)
+connect(npn_00p54x08p00_b, contact)
+connect(npn_00p54x08p00_c, contact)
+
+# npn_00p54x02p00 nodes connections
+connect(npn_00p54x02p00_e, contact)
+connect(npn_00p54x02p00_b, contact)
+connect(npn_00p54x02p00_c, contact)
+
+# ==============
+# ---- vpnp ----
+# ==============
+
+# pnp_10p00x10p00_06v0 nodes connections
+connect(pnp_10p00x10p00_06v0_e, contact)
+connect(pnp_10p00x10p00_06v0_b, contact)
+connect(pnp_10p00x10p00_06v0_c, contact)
+
+# pnp_05p00x05p00_06v0 nodes connections
+connect(pnp_05p00x05p00_06v0_e, contact)
+connect(pnp_05p00x05p00_06v0_b, contact)
+connect(pnp_05p00x05p00_06v0_c, contact)
+
+# pnp_00p42x20p00_06v0 nodes connections
+connect(pnp_00p42x20p00_06v0_e, contact)
+connect(pnp_00p42x20p00_06v0_b, contact)
+connect(pnp_00p42x20p00_06v0_c, contact)
+
+# pnp_00p42x10p00_06v0 nodes connections
+connect(pnp_00p42x10p00_06v0_e, contact)
+connect(pnp_00p42x10p00_06v0_b, contact)
+connect(pnp_00p42x10p00_06v0_c, contact)
+
+# pnp_00p42x05p00_06v0 nodes connections
+connect(pnp_00p42x05p00_06v0_e, contact)
+connect(pnp_00p42x05p00_06v0_b, contact)
+connect(pnp_00p42x05p00_06v0_c, contact)
diff --git a/BCDLite/klayout/lvs/rule_decks/bjt_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/bjt_derivations.lvs
index c6581c7..21e4a69 100644
--- a/BCDLite/klayout/lvs/rule_decks/bjt_derivations.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/bjt_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/BCDLite/klayout/lvs/rule_decks/bjt_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/bjt_extraction.lvs
index 80bd18e..775eed1 100644
--- a/BCDLite/klayout/lvs/rule_decks/bjt_extraction.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/bjt_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs b/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs
index 23f3250..333f1e2 100644
--- a/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -158,3 +158,23 @@
enable_parameter('P', true)
end
end
+
+# VARACTOR device extractor
+class VarCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
+end
+
+# PISCAP device extractor
+class PisCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
+end
diff --git a/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs b/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs
index 670e2cf..ac9fab0 100644
--- a/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -24,124 +24,28 @@
# ----- GENERAL CONNECTIONS -----
#================================
-logger.info('Starting GF180 LVS connectivity setup (Inter-layer)')
-
-# Inter-layer
-connect(sub, ptap)
-connect(lvpwell_con, ptap)
-connect(lvpwell_con, ptap_dw)
-connect(dnwell, ntap_dw)
-connect(nwell_con, ntap)
-connect(ptap, contact)
-connect(ptap_dw, contact)
-connect(ntap, contact)
-connect(ntap_dw, contact)
-connect(psd, contact)
-connect(psd_dw, contact)
-connect(nsd, contact)
-connect(poly2_con, contact)
-connect(contact, metal1)
-connect(metal1, via1)
-connect(via1, metal2_ncap)
-if METAL_LEVEL != '2LM'
- connect(metal2_ncap, via2)
- connect(via2, metal3_ncap)
- if METAL_LEVEL != '3LM'
- connect(metal3_ncap, via3)
- connect(via3, metal4_ncap)
- if METAL_LEVEL != '4LM'
- connect(metal4_ncap, via4)
- connect(via4, metal5_ncap)
- if METAL_LEVEL != '5LM'
- connect(metal5_ncap, via5)
- connect(via5, metaltop_con)
- end
- end
- end
-end
-
-logger.info('Starting GF180 LVS connectivity setup (Attaching labels)')
-
-# Attaching labels
-connect(comp, comp_label)
-connect(poly2_con, poly2_label)
-connect(metal1, metal1_label)
-connect(metal2_ncap, metal2_label)
-if METAL_LEVEL != '2LM'
- connect(metal3_ncap, metal3_label)
- if METAL_LEVEL != '3LM'
- connect(metal4_ncap, metal4_label)
- if METAL_LEVEL != '4LM'
- connect(metal5_ncap, metal5_label)
- connect(metaltop_con, metaltop_label) if METAL_LEVEL != '5LM'
- end
- end
-end
-
-logger.info('Starting GF180 LVS connectivity setup (Global)')
-
-# Global
-connect_global(sub, substrate_name)
-
-logger.info('Starting GF180 LVS connectivity setup (Multifinger Devices)')
-
-# Multifinger Devices
-connect_implicit('*')
+# %include general_connections.lvs
#================================
# ------ BJT CONNECTIONS --------
#================================
-logger.info('Starting LVS BJT CONNECTIONS')
-# ==============
-# ---- vnpn ----
-# ==============
+# %include bjt_connections.lvs
-# npn_05p00x05p00 nodes connections
-connect(npn_05p00x05p00_e, contact)
-connect(npn_05p00x05p00_b, contact)
-connect(npn_05p00x05p00_c, contact)
+#=================================
+# ------ DIODE CONNECTIONS -------
+#=================================
-# npn_00p54x16p00 nodes connections
-connect(npn_00p54x16p00_e, contact)
-connect(npn_00p54x16p00_b, contact)
-connect(npn_00p54x16p00_c, contact)
+# %include diode_connections.lvs
-# npn_00p54x08p00 nodes connections
-connect(npn_00p54x08p00_e, contact)
-connect(npn_00p54x08p00_b, contact)
-connect(npn_00p54x08p00_c, contact)
+#==================================
+# ------ MIMCAP CONNECTIONS -------
+#==================================
-# npn_00p54x02p00 nodes connections
-connect(npn_00p54x02p00_e, contact)
-connect(npn_00p54x02p00_b, contact)
-connect(npn_00p54x02p00_c, contact)
+# %include mimcap_connections.lvs
-# ==============
-# ---- vpnp ----
-# ==============
+#====================================
+# ------ VARACTOR CONNECTIONS -------
+#====================================
-# pnp_10p00x10p00_06v0 nodes connections
-connect(pnp_10p00x10p00_06v0_e, contact)
-connect(pnp_10p00x10p00_06v0_b, contact)
-connect(pnp_10p00x10p00_06v0_c, contact)
-
-# pnp_05p00x05p00_06v0 nodes connections
-connect(pnp_05p00x05p00_06v0_e, contact)
-connect(pnp_05p00x05p00_06v0_b, contact)
-connect(pnp_05p00x05p00_06v0_c, contact)
-
-# pnp_00p42x20p00_06v0 nodes connections
-connect(pnp_00p42x20p00_06v0_e, contact)
-connect(pnp_00p42x20p00_06v0_b, contact)
-connect(pnp_00p42x20p00_06v0_c, contact)
-
-# pnp_00p42x10p00_06v0 nodes connections
-connect(pnp_00p42x10p00_06v0_e, contact)
-connect(pnp_00p42x10p00_06v0_b, contact)
-connect(pnp_00p42x10p00_06v0_c, contact)
-
-# pnp_00p42x05p00_06v0 nodes connections
-connect(pnp_00p42x05p00_06v0_e, contact)
-connect(pnp_00p42x05p00_06v0_b, contact)
-connect(pnp_00p42x05p00_06v0_c, contact)
+# %include varactor_connections.lvs
diff --git a/BCDLite/klayout/lvs/rule_decks/diode_connections.lvs b/BCDLite/klayout/lvs/rule_decks/diode_connections.lvs
new file mode 100644
index 0000000..c0be24e
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/diode_connections.lvs
@@ -0,0 +1,142 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- DIODE CONNECTIONS -------
+#================================
+
+logger.info('Starting LVS DIODE CONNECTIONS')
+
+#=====================
+# --- NP 1P8 DIODE ---
+#=====================
+
+# diode_nd2ps_01v8: Model for 1.8V P+/Nwell diode (outside DNWELL) [np_1p8]
+connect(diode_nd2ps_01v8_terminal_n, contact)
+
+# diode_nd2ps_01v8_dn: Model for 1.8V N+/Psub diode (inside DNWELL) [np_1p8_dw]
+connect(diode_nd2ps_01v8_dn_terminal_n, contact)
+
+#=====================
+# --- PN 1P8 DIODE ---
+#=====================
+
+# diode_pd2nw_01v8: Model for 1.8V P+/Nwell diode (outside DNWELL) [pn_1p8]
+connect(diode_pd2nw_01v8_terminal_p, contact)
+
+# diode_pd2nw_01v8_dn: Model for 1.8V P+/Nwell diode (inside DNWELL) [pn_1p8_dw]
+connect(diode_pd2nw_01v8_dn_terminal_p, contact)
+
+#=====================
+# --- NP 6P0 DIODE ---
+#=====================
+
+# diode_nd2ps_06v0: Model for 6V N+/Pwell diode (outside DNWELL) [np_6p0]
+connect(diode_nd2ps_06v0_terminal_n, contact)
+
+# diode_nd2ps_06v0_dn: Model for 6V N+/Psub diode (inside DNWELL) [np_6p0_dw]
+connect(diode_nd2ps_06v0_dn_terminal_n, contact)
+
+#=====================
+# --- PN 6P0 DIODE ---
+#=====================
+
+# diode_pd2nw_06v0: Model for 6V P+/Nwell diode (outside DNWELL) [pn_6p0]
+connect(diode_pd2nw_06v0_terminal_p, contact)
+
+# diode_pd2nw_06v0_dn: Model for 6V P+/Nwell diode (inside DNWELL) [pn_6p0_dw]
+connect(diode_pd2nw_06v0_dn_terminal_p, contact)
+
+#======================
+# --- NWP 6P0 DIODE ---
+#======================
+
+# diode_nw2ps_06v0: Model for Nwell/Psub diode (applicable for both 1.8V/6V) [nwp_6p0]
+connect(diode_nw2ps_06v0_terminal_p, contact)
+connect(diode_nw2ps_06v0_terminal_n, nwell)
+
+#====================
+# --- DNWPW DIODE ---
+#====================
+
+# diode_pw2dw: Model for LVPWELL/DNWELL diode (applicable for both 1.8V/6V) [dnwpw]
+connect(diode_pw2dw_terminal_p, contact)
+
+#======================
+# --- DNWPWHV DIODE ---
+#======================
+
+# diode_pw2dw_hv: Model for NW/PWHV diode (10V diode) [dnwpwhv]
+connect(diode_pw2dw_hv_terminal_n, contact)
+connect(diode_pw2dw_hv_terminal_p, contact)
+
+#=======================
+# --- DPWHVDNW DIODE ---
+#=======================
+
+# diode_pw2dnw_hv: Model for PWHV/DNW diode [dpwhvdnw]
+connect(diode_pw2dnw_hv_terminal_n, contact)
+connect(diode_pw2dnw_hv_terminal_p, contact)
+
+#======================
+# --- NP 30P0 DIODE ---
+#======================
+
+# diode_nd2ps_30v0: Model for HVNDDD/Psub diode [np_30p0]
+connect(diode_nd2ps_30v0_terminal_n, contact)
+connect(diode_nd2ps_30v0_terminal_p, contact)
+
+#======================
+# --- PN 30P0 DIODE ---
+#======================
+
+# diode_pd2nw_30v0: Model for HVPDDD/DNWELL diode [np_30p0]
+connect(diode_pd2nw_30v0_terminal_n, contact)
+
+#====================
+# --- DNWPS DIODE ---
+#====================
+
+# diode_dw2ps: Model for DNWELL/Psub diode(1.8V/6V) [dnwps]
+connect(diode_dw2ps_terminal_p, contact)
+
+#=================
+# --- SC DIODE ---
+#=================
+
+# diode_sc: Model for schottky diode [sc_diode]
+connect(diode_sc_terminal_n, contact)
+connect(diode_sc_terminal_p, schottky_diode)
+
+#====================
+# --- ZENER DIODE ---
+#====================
+
+# diode_zener: Model for zener diode outside DNWELL [zener_diode]
+connect(diode_zener_terminal_n, contact)
+connect(diode_zener_terminal_p, zener)
+
+# diode_zener_dn: Model for zener diode inside DNWELL [zener_diode_dw]
+connect(diode_zener_dn_terminal_n, contact)
+connect(diode_zener_dn_terminal_p, zener)
+
+#===================
+# --- POLY DIODE ---
+#===================
+
+# diode_poly: Model for poly diode [poly_diode]
+connect(diode_poly_terminal_n, contact)
+connect(diode_poly_terminal_p, contact)
diff --git a/BCDLite/klayout/lvs/rule_decks/diode_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/diode_derivations.lvs
new file mode 100644
index 0000000..be7cc47
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/diode_derivations.lvs
@@ -0,0 +1,225 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- DIODE DERIVATIONS -------
+#================================
+
+logger.info('Starting DIODE DERIVATIONS')
+
+#================================
+# ------ DIODE DERIVATIONS ------
+#================================
+
+#======================
+# --- DIODE EXCLUDE ---
+#======================
+
+diode_exclude = resistor.join(esd).join(sab).join(fusewindow_d)
+ .join(polyfuse).join(piscap).join(v5_xtor)
+ .join(drc_bjt).join(nat).join(fhres).join(dni)
+ .join(mos_cap_mk).join(mvpsd).join(elmd_mk)
+ .join(elmd2_mk).join(lvs_rf).join(lvs_source)
+ .join(mk_35v).join(lvs_35v).join(esd_hbm_mk)
+ .join(mos_mk_type1).join(swfet_mk).join(hvpolyrs)
+
+diode_nd2ps_pd2nw_exclude = diode_exclude.join(poly2).join(pwhv)
+ .join(schottky_diode).join(zener).join(res_mk)
+ .join(mvsd).join(hvnddd).join(hvpddd)
+ .join(ldmos_xtor)
+#=====================
+# --- NP 1P8 DIODE ---
+#=====================
+
+diode_nd2ps_01v8_exclude = diode_nd2ps_pd2nw_exclude.join(nwell).join(pplus).join(dualgate2_d)
+diode_nd2ps_01v8 = ncomp.and(diode_mk).not(diode_nd2ps_01v8_exclude)
+
+# diode_nd2ps_01v8: Model for 1.8V N+/Psub diode (outside DNWELL) [np_1p8]
+diode_nd2ps_01v8_terminal_n = diode_nd2ps_01v8.not(dnwell)
+
+# diode_nd2ps_01v8_dn: Model for 1.8V N+/Psub diode (inside DNWELL) [np_1p8_dw]
+diode_nd2ps_01v8_dn_terminal_n = diode_nd2ps_01v8.and(dnwell)
+
+#=====================
+# --- PN 1P8 DIODE ---
+#=====================
+
+diode_pd2nw_01v8_exclude = diode_nd2ps_pd2nw_exclude.join(lvpwell).join(nplus).join(dualgate2_d)
+diode_pd2nw_01v8 = pcomp.and(diode_mk).not(diode_pd2nw_01v8_exclude)
+
+# diode_pd2nw_01v8: Model for 1.8V P+/Nwell diode (outside DNWELL) [pn_1p8]
+diode_pd2nw_01v8_terminal_p = diode_pd2nw_01v8.not(dnwell)
+
+# diode_pd2nw_01v8_dn: Model for 1.8V P+/Nwell diode (inside DNWELL) [pn_1p8_dw]
+diode_pd2nw_01v8_dn_terminal_p = diode_pd2nw_01v8.and(dnwell)
+
+#=====================
+# --- NP 6P0 DIODE ---
+#=====================
+
+diode_nd2ps_06v0_exclude = diode_nd2ps_pd2nw_exclude.join(nwell).join(pplus)
+diode_nd2ps_06v0 = ncomp.and(diode_mk).and(dualgate2_d).not(diode_nd2ps_06v0_exclude)
+
+# diode_nd2ps_06v0: Model for 6V N+/Pwell diode (outside DNWELL) [np_6p0]
+diode_nd2ps_06v0_terminal_n = diode_nd2ps_06v0.not(dnwell)
+
+# diode_nd2ps_06v0_dn: Model for 6V N+/Psub diode (inside DNWELL) [np_6p0_dw]
+diode_nd2ps_06v0_dn_terminal_n = diode_nd2ps_06v0.and(dnwell)
+
+#=====================
+# --- PN 6P0 DIODE ---
+#=====================
+
+diode_pd2nw_06v0_exclude = diode_nd2ps_pd2nw_exclude.join(lvpwell).join(nplus)
+diode_pd2nw_06v0 = pcomp.and(diode_mk).and(dualgate2_d).not(diode_pd2nw_06v0_exclude)
+
+# diode_pd2nw_06v0: Model for 6V P+/Nwell diode (outside DNWELL) [pn_6p0]
+diode_pd2nw_06v0_terminal_p = diode_pd2nw_06v0.not(dnwell)
+
+# diode_pd2nw_06v0_dn: Model for 6V P+/Nwell diode (inside DNWELL) [pn_6p0_dw]
+diode_pd2nw_06v0_dn_terminal_p = diode_pd2nw_06v0.and(dnwell)
+
+#======================
+# --- NWP 6P0 DIODE ---
+#======================
+
+diode_nw2ps_06v0_exclude = diode_nd2ps_pd2nw_exclude.join(dnwell).join(lvpwell)
+
+# diode_nw2ps_06v0: Model for Nwell/Psub diode (applicable for both 1.8V/6V) [nwp_6p0]
+diode_nw2ps_06v0_terminal_p = pcomp.and(diode_mk).not(diode_nw2ps_06v0_exclude)
+diode_nw2ps_06v0_terminal_n = diode_mk.covering(nwell.covering(ncomp)).not(diode_nw2ps_06v0_exclude)
+
+#====================
+# --- DNWPW DIODE ---
+#====================
+
+diode_pw2dw_exclude = diode_nd2ps_pd2nw_exclude.join(nwell).join(nplus)
+
+# diode_pw2dw: Model for LVPWELL/DNWELL diode (applicable for both 1.8V/6V) [dnwpw]
+diode_pw2dw_terminal_p = lvpwell.interacting(pcomp).and(well_diode_mk).not(diode_pw2dw_exclude)
+
+#======================
+# --- DNWPWHV DIODE ---
+#======================
+
+diode_pw2dw_hv_exclude = diode_exclude.join(lvpwell).join(poly2)
+ .join(pplus).join(schottky_diode).join(zener)
+ .join(res_mk).join(hvnddd).join(hvpddd)
+ .join(nwell)
+
+# diode_pw2dw_hv: Model for NW/PWHV diode (10V diode) [dnwpwhv]
+dnwell_hv = dnwell.and(dualgate2_d)
+diode_pw2dw_hv_terminal_p = pwhv.and(well_diode_mk).and(ldmos_xtor).not(diode_pw2dw_hv_exclude)
+diode_pw2dw_hv_terminal_n = well_diode_mk.covering(dnwell_hv.covering(ncomp)).and(ldmos_xtor)
+ .interacting(mvsd).not(diode_pw2dw_hv_exclude)
+
+#=======================
+# --- DPWHVDNW DIODE ---
+#=======================
+
+diode_pw2dnw_hv_exclude = diode_exclude.join(lvpwell).join(poly2)
+ .join(nplus).join(schottky_diode).join(zener)
+ .join(res_mk).join(hvnddd).join(hvpddd)
+ .join(nwell)
+
+# diode_pw2dnw_hv: Model for PWHV/DNW diode [dpwhvdnw]
+diode_pw2dnw_hv_terminal_p = pwhv.and(well_diode_mk).and(ldmos_xtor).not(diode_pw2dnw_hv_exclude)
+diode_pw2dnw_hv_terminal_n = well_diode_mk.covering(dnwell_hv.covering(pcomp)).and(ldmos_xtor)
+ .interacting(mvsd).not(diode_pw2dnw_hv_exclude)
+
+#======================
+# --- NP 30P0 DIODE ---
+#======================
+
+diode_nd2ps_30v0_exclude = diode_exclude.join(dnwell).join(nwell)
+ .join(lvpwell).join(poly2)
+
+# diode_nd2ps_30v0: Model for HVNDDD/Psub diode [np_30p0]
+diode_nd2ps_30v0_terminal_n = dualgate2_d.covering(hvnddd.and(diode_mk)).not(diode_nd2ps_30v0_exclude)
+diode_nd2ps_30v0_terminal_p = pcomp.and(diode_mk).not(diode_nd2ps_30v0_exclude)
+
+#======================
+# --- PN 30P0 DIODE ---
+#======================
+
+diode_pd2nw_30v0_exclude = diode_exclude.join(nwell).join(lvpwell).join(poly2)
+
+# diode_pd2nw_30v0: Model for HVPDDD/DNWELL diode [np_30p0]
+diode_pd2nw_30v0_terminal_n = hvpddd.and(diode_mk).and(dualgate2_d).not(diode_pd2nw_30v0_exclude)
+
+#====================
+# --- DNWPS DIODE ---
+#====================
+
+# diode_dw2ps: Model for DNWELL/Psub diode(1.8V/6V) [dnwps]
+diode_dw2ps_exclude = diode_exclude.join(nwell).join(lvpwell)
+ .join(poly2).join(pwhv).join(schottky_diode)
+ .join(zener).join(mvsd).join(hvnddd)
+ .join(hvpddd).join(ldmos_xtor)
+
+diode_dw2ps_terminal_p = pcomp.and(dualgate2_d).and(dnwell).and(well_diode_mk)
+ .not(diode_dw2ps_exclude)
+
+#=================
+# --- SC DIODE ---
+#=================
+
+diode_sc_exclude = diode_exclude.join(lvpwell).join(poly2)
+ .join(pplus).join(zener).join(res_mk)
+ .join(hvnddd).join(hvpddd).join(ldmos_xtor)
+
+# diode_sc: Model for schottky diode [sc_diode]
+diode_sc_terminal_n = ncomp.and(dnwell).and(schottky_diode).not(diode_sc_exclude)
+diode_sc_terminal_p = metal1.and(dnwell).not_interacting(diode_sc_terminal_n).not(diode_sc_exclude)
+
+#====================
+# --- ZENER DIODE ---
+#====================
+
+diode_zener_exclude = diode_exclude.join(lvpwell).join(poly2)
+ .join(pplus).join(zener).join(res_mk)
+ .join(hvnddd).join(hvpddd).join(ldmos_xtor)
+
+# diode_zener: Model for zener diode outside DNWELL [zener_diode]
+zener_mv = zener.and(dualgate2_d)
+diode_zener_terminal_n = ncomp.and(zener_mv).not(dnwell).not(diode_zener_exclude)
+diode_zener_terminal_p = nwell.and(zener_mv).not(dnwell).covering(pcomp).and(diode_mk).not(diode_zener_exclude)
+
+# diode_zener_dn: Model for zener diode inside DNWELL [zener_diode_dw]
+diode_zener_dn_terminal_n = ncomp.and(zener_mv).and(dnwell).and(diode_mk).not(diode_zener_exclude)
+diode_zener_dn_terminal_p = nwell.and(zener_mv).and(dnwell).covering(pcomp).and(diode_mk).not(diode_zener_exclude)
+
+
+#===================
+# --- POLY DIODE ---
+#===================
+
+# diode_poly: Model for poly diode [poly_diode]
+diode_poly_exclude = comp.join(resistor).join(esd)
+ .join(pwhv).join(polyfuse).join(fusewindow_d)
+ .join(schottky_diode).join(piscap).join(zener)
+ .join(res_mk).join(v5_xtor).join(nat)
+ .join(fhres).join(mvsd).join(mvpsd)
+ .join(elmd_mk).join(elmd2_mk).join(lvs_rf)
+ .join(lvs_source).join(lvs_35v).join(mk_35v)
+ .join(well_diode_mk).join(esd_hbm_mk).join(mos_mk_type1)
+ .join(hvnddd).join(hvpddd).join(hvpolyrs)
+ .join(ldmos_xtor)
+
+diode_poly_terminal_p = poly2.and(sab).interacting(nplus).interacting(pplus)
+ .and(diode_mk).not(diode_poly_exclude)
+diode_poly_terminal_n = diode_mk.covering(diode_poly_terminal_p)
+
diff --git a/BCDLite/klayout/lvs/rule_decks/diode_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/diode_extraction.lvs
new file mode 100644
index 0000000..c598159
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/diode_extraction.lvs
@@ -0,0 +1,154 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ------ DIODE EXTRACTION -------
+#================================
+
+logger.info('Starting DIODE EXTRACTION')
+
+#=====================
+# --- NP 1P8 DIODE ---
+#=====================
+
+# diode_nd2ps_01v8: Model for 1.8V N+/Psub diode (outside DNWELL) [np_1p8]
+logger.info('Extracting diode_nd2ps_01v8')
+extract_devices(diode('diode_nd2ps_01v8'), { 'N' => diode_nd2ps_01v8_terminal_n, 'P' => lvpwell_con })
+
+# diode_nd2ps_01v8_dn: Model for 1.8V N+/Psub diode (inside DNWELL) [np_1p8_dw]
+logger.info('Extracting diode_nd2ps_01v8_dn')
+extract_devices(diode('diode_nd2ps_01v8_dn'), { 'N' => diode_nd2ps_01v8_dn_terminal_n, 'P' => lvpwell_con })
+
+#=====================
+# --- PN 1P8 DIODE ---
+#=====================
+
+# diode_pd2nw_01v8: Model for 1.8V P+/Nwell diode (outside DNWELL) [pn_1p8]
+logger.info('Extracting diode_pd2nw_01v8')
+extract_devices(diode('diode_pd2nw_01v8'), { 'N' => nwell_con, 'P' => diode_pd2nw_01v8_terminal_p })
+
+# diode_pd2nw_01v8_dn: Model for 1.8V P+/Nwell diode (inside DNWELL) [pn_1p8_dw]
+logger.info('Extracting diode_pd2nw_01v8_dn')
+extract_devices(diode('diode_pd2nw_01v8_dn'), { 'N' => nwell_con, 'P' => diode_pd2nw_01v8_dn_terminal_p })
+
+#=====================
+# --- NP 6P0 DIODE ---
+#=====================
+
+# diode_nd2ps_06v0: Model for 6V N+/Pwell diode (outside DNWELL) [np_6p0]
+logger.info('Extracting diode_nd2ps_06v0')
+extract_devices(diode('diode_nd2ps_06v0'), { 'N' => diode_nd2ps_06v0_terminal_n, 'P' => lvpwell_con })
+
+# diode_nd2ps_06v0_dn: Model for 6V N+/Psub diode (inside DNWELL) [np_6p0_dw]
+logger.info('Extracting diode_nd2ps_06v0_dn')
+extract_devices(diode('diode_nd2ps_06v0_dn'), { 'N' => diode_nd2ps_06v0_dn_terminal_n, 'P' => lvpwell_con })
+
+#=====================
+# --- PN 6P0 DIODE ---
+#=====================
+
+# diode_pd2nw_06v0: Model for 6V P+/Nwell diode (outside DNWELL) [pn_6p0]
+logger.info('Extracting diode_pd2nw_06v0')
+extract_devices(diode('diode_pd2nw_06v0'), { 'N' => nwell_con, 'P' => diode_pd2nw_06v0_terminal_p })
+
+# diode_pd2nw_06v0_dn: Model for 6V P+/Nwell diode (inside DNWELL) [pn_6p0_dw]
+logger.info('Extracting diode_pd2nw_06v0_dn')
+extract_devices(diode('diode_pd2nw_06v0_dn'), { 'N' => nwell_con, 'P' => diode_pd2nw_06v0_dn_terminal_p })
+
+#======================
+# --- NWP 6P0 DIODE ---
+#======================
+
+# diode_nw2ps_06v0: Model for Nwell/Psub diode (applicable for both 1.8V/6V) [nwp_6p0]
+logger.info('Extracting diode_nw2ps_06v0 diode')
+extract_devices(diode('diode_nw2ps_06v0'), { 'N' => diode_nw2ps_06v0_terminal_n, 'P' => diode_nw2ps_06v0_terminal_p })
+
+#====================
+# --- DNWPW DIODE ---
+#====================
+
+# diode_pw2dw: Model for LVPWELL/DNWELL diode (applicable for both 1.8V/6V) [dnwpw]
+logger.info('Extracting diode_pw2dw diode')
+extract_devices(diode('diode_pw2dw'), { 'N' => dnwell, 'P' => diode_pw2dw_terminal_p })
+
+#======================
+# --- DNWPWHV DIODE ---
+#======================
+
+# diode_pw2dw_hv: Model for NW/PWHV diode (10V diode) [dnwpwhv]
+logger.info('Extracting diode_pw2dw_hv diode')
+extract_devices(diode('diode_pw2dw_hv'), { 'N' => diode_pw2dw_hv_terminal_n, 'P' => diode_pw2dw_hv_terminal_p })
+
+#=======================
+# --- DPWHVDNW DIODE ---
+#=======================
+
+# diode_pw2dnw_hv: Model for PWHV/DNW diode [dpwhvdnw]
+logger.info('Extracting diode_pw2dnw_hv diode')
+extract_devices(diode('diode_pw2dnw_hv'), { 'N' => diode_pw2dnw_hv_terminal_n, 'P' => diode_pw2dnw_hv_terminal_p })
+
+#======================
+# --- NP 30P0 DIODE ---
+#======================
+
+# diode_nd2ps_30v0: Model for HVNDDD/Psub diode [np_30p0]
+logger.info('Extracting diode_nd2ps_30v0 diode')
+extract_devices(diode('diode_nd2ps_30v0'), { 'N' => diode_nd2ps_30v0_terminal_n, 'P' => diode_nd2ps_30v0_terminal_p })
+
+#======================
+# --- PN 30P0 DIODE ---
+#======================
+
+# diode_pd2nw_30v0: Model for HVPDDD/DNWELL diode [np_30p0]
+logger.info('Extracting diode_pd2nw_30v0 diode')
+extract_devices(diode('diode_pd2nw_30v0'), { 'N' => diode_pd2nw_30v0_terminal_n, 'P' => dnwell })
+
+#====================
+# --- DNWPS DIODE ---
+#====================
+
+# diode_dw2ps: Model for DNWELL/Psub diode(1.8V/6V) [dnwps]
+logger.info('Extracting diode_dw2ps diode')
+extract_devices(diode('diode_dw2ps'), { 'N' => dnwell, 'P' => diode_dw2ps_terminal_p })
+
+#=================
+# --- SC DIODE ---
+#=================
+
+# diode_sc: Model for schottky diode [sc_diode]
+logger.info('Extracting diode_sc diode')
+extract_devices(diode('diode_sc'), { 'N' => diode_sc_terminal_n, 'P' => schottky_diode })
+
+#====================
+# --- ZENER DIODE ---
+#====================
+
+# diode_zener: Model for zener diode outside DNWELL [zener_diode]
+logger.info('Extracting diode_zener diode')
+extract_devices(diode('diode_zener'), { 'N' => diode_zener_terminal_n, 'P' => zener })
+
+# diode_zener_dn: Model for zener diode inside DNWELL [zener_diode_dw]
+logger.info('Extracting diode_zener_dn diode')
+extract_devices(diode('diode_zener_dn'), { 'N' => diode_zener_dn_terminal_n, 'P' => zener })
+
+#===================
+# --- POLY DIODE ---
+#===================
+
+# diode_poly: Model for poly diode [poly_diode]
+logger.info('Extracting diode_poly diode')
+extract_devices(diode('diode_poly'), { 'N' => diode_poly_terminal_n, 'P' => diode_poly_terminal_p })
+
diff --git a/BCDLite/klayout/lvs/rule_decks/general_connections.lvs b/BCDLite/klayout/lvs/rule_decks/general_connections.lvs
new file mode 100644
index 0000000..ce0d606
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/general_connections.lvs
@@ -0,0 +1,88 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================================
+#------------ DEVICES CONNECTIVITY --------------
+#================================================
+
+logger.info('Starting GF180BCDLite LVS connectivity setup')
+
+#================================
+# ----- GENERAL CONNECTIONS -----
+#================================
+
+logger.info('Starting GF180BCDLite LVS connectivity setup (Inter-layer)')
+
+# Inter-layer
+connect(sub, ptap)
+connect(lvpwell_con, ptap)
+connect(lvpwell_con, ptap_dw)
+connect(dnwell, ntap_dw)
+connect(nwell_con, ntap)
+connect(ptap, contact)
+connect(ptap_dw, contact)
+connect(ntap, contact)
+connect(ntap_dw, contact)
+connect(psd, contact)
+connect(psd_dw, contact)
+connect(nsd, contact)
+connect(poly2_con, contact)
+connect(contact, metal1_con)
+connect(metal1_con, via1)
+connect(via1, metal2_con)
+
+case METAL_LEVEL
+when '3LM', '4LM', '5LM', '6LM'
+ connect(metal2_con, via2_n_cap)
+ connect(via2_n_cap, metal3_con)
+ connect(metal3_con, metal3_label)
+end
+case METAL_LEVEL
+when '4LM', '5LM', '6LM'
+ connect(metal3_con, via3_n_cap)
+ connect(via3_n_cap, metal4_con)
+ connect(metal4_con, metal4_label)
+end
+case METAL_LEVEL
+when '5LM', '6LM'
+ connect(metal4_con, via4_n_cap)
+ connect(via4_n_cap, metal5_con)
+ connect(metal5_con, metal5_label)
+end
+case METAL_LEVEL
+when '6LM'
+ connect(metal5_con, via5_n_cap)
+ connect(via5_n_cap, metaltop_con)
+ connect(metaltop_con, metaltop_label)
+end
+connect(top_via, top_metal_con)
+connect(top_metal, top_metal_label)
+
+# Attaching labels
+connect(comp, comp_label)
+connect(poly2_con, poly2_label)
+connect(metal1_con, metal1_label)
+connect(metal2_ncap, metal2_label)
+
+logger.info('Starting GF180BCDLite LVS connectivity setup (Global)')
+
+# Global
+connect_global(sub, substrate_name)
+
+logger.info('Starting GF180BCDLite LVS connectivity setup (Multifinger Devices)')
+
+# Multifinger Devices
+connect_implicit('*')
diff --git a/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs
index 0274429..bea0ccd 100644
--- a/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs
@@ -1,7 +1,5 @@
-# frozen_string_literal: true
-
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -51,3 +49,57 @@
nwell_con = nwell.not(res_mk)
lvpwell_con = lvpwell.not(res_mk)
poly2_con = poly2.not(res_mk).not(plfuse)
+
+metal1_con = metal1.not(mom_mk).not(mom_m1_mk)
+metal2_con = metal2.not(mom_mk).not(mom_m2_mk)
+
+case METAL_LEVEL
+when '3LM', '4LM', '5LM', '6LM'
+ metal3_con = metal3.not(mom_mk).not(mom_m3_mk)
+ via2_n_cap = via2.not(fusetop)
+ via2_cap = via2.and(fusetop)
+end
+case METAL_LEVEL
+when '4LM', '5LM', '6LM'
+ metal4_con = metal4.not(mom_mk).not(mom_m4_mk)
+ via3_n_cap = via3.not(fusetop)
+ via3_cap = via3.and(fusetop)
+end
+case METAL_LEVEL
+when '5LM', '6LM'
+ metal5_con = metal5.not(mom_mk).not(mom_m5_mk)
+ via4_n_cap = via4.not(fusetop)
+ via4_cap = via4.and(fusetop)
+end
+case METAL_LEVEL
+when '6LM'
+ metaltop_con = metaltop.not(mom_mk)
+ via5_n_cap = via5.not(fusetop)
+ via5_cap = via5.and(fusetop)
+end
+
+case METAL_LEVEL
+when '2LM'
+ top_metal_con = metal2_con
+ top_via_n_cap = via1.not(fusetop)
+ top_via_cap = via1.and(fusetop)
+when '3LM'
+ top_metal_con = metal3_con
+ top_via_n_cap = via2.not(fusetop)
+ top_via_cap = via2.and(fusetop)
+when '4LM'
+ top_metal_con = metal4.not(mom_mk).not(mom_m4_mk)
+ top_via_n_cap = via3.not(fusetop)
+ top_via_cap = via3.and(fusetop)
+when '5LM'
+ top_metal_con = metal5.not(mom_mk).not(mom_m5_mk)
+ top_via_n_cap = via4.not(fusetop)
+ top_via_cap = via4.and(fusetop)
+when '6LM'
+ top_metal_con = metaltop.not(mom_mk)
+ top_via_n_cap = via5.not(fusetop)
+ top_via_cap = via5.and(fusetop)
+else
+ logger.error("Unknown metal stack #{METAL_LEVEL}")
+ raise
+end
diff --git a/BCDLite/klayout/lvs/rule_decks/layers_definition.lvs b/BCDLite/klayout/lvs/rule_decks/layers_definition.lvs
index d18f000..0bf1d1b 100644
--- a/BCDLite/klayout/lvs/rule_decks/layers_definition.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/layers_definition.lvs
@@ -1,7 +1,5 @@
-# frozen_string_literal: true
-
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -320,7 +318,7 @@
metal1 = metal1_drawn + metal1_dummy
-metal1_label = get_polygons(34, 10)
+metal1_label = labels(34, 10)
count = metal1_label.count
logger.info("metal1_label has #{count} polygons")
polygons_count += count
@@ -352,7 +350,7 @@
metal2 = metal2_drawn + metal2_dummy
-metal2_label = get_polygons(36, 10)
+metal2_label = labels(36, 10)
count = metal2_label.count
logger.info("metal2_label has #{count} polygons")
polygons_count += count
@@ -367,17 +365,8 @@
logger.info("metal2_blk has #{count} polygons")
polygons_count += count
-if METAL_LEVEL == '2LM'
-
- top_via = via1
- topmin1_via = contact
- top_metal = metal2
- topmin1_metal = metal1
- top_metal_slot = metal2_slot
- topmin1_metal_slot = metal1_slot
-
-else
-
+case METAL_LEVEL
+when '3LM', '4LM', '5LM', '6LM'
via2 = get_polygons(38, 0)
count = via2.count
logger.info("via2 has #{count} polygons")
@@ -395,7 +384,7 @@
metal3 = metal3_drawn + metal3_dummy
- metal3_label = get_polygons(42, 10)
+ metal3_label = labels(42, 10)
count = metal3_label.count
logger.info("metal3_label has #{count} polygons")
polygons_count += count
@@ -409,171 +398,147 @@
count = metal3_blk.count
logger.info("metal3_blk has #{count} polygons")
polygons_count += count
+end
- if METAL_LEVEL == '3LM'
+case METAL_LEVEL
+when '4LM', '5LM', '6LM'
+ via3 = get_polygons(40, 0)
+ count = via3.count
+ logger.info("via3 has #{count} polygons")
+ polygons_count += count
- top_via = via2
- topmin1_via = via1
- top_metal = metal3
- topmin1_metal = metal2
- top_metal_slot = metal3_slot
- topmin1_metal_slot = metal2_slot
- else
+ metal4_drawn = get_polygons(46, 0)
+ count = metal4_drawn.count
+ logger.info("metal4_drawn has #{count} polygons")
+ polygons_count += count
- via3 = get_polygons(40, 0)
- count = via3.count
- logger.info("via3 has #{count} polygons")
- polygons_count += count
+ metal4_dummy = get_polygons(46, 4)
+ count = metal4_dummy.count
+ logger.info("metal4_dummy has #{count} polygons")
+ polygons_count += count
- metal4_drawn = get_polygons(46, 0)
- count = metal4_drawn.count
- logger.info("metal4_drawn has #{count} polygons")
- polygons_count += count
+ metal4 = metal4_drawn + metal4_dummy
- metal4_dummy = get_polygons(46, 4)
- count = metal4_dummy.count
- logger.info("metal4_dummy has #{count} polygons")
- polygons_count += count
+ metal4_label = labels(46, 10)
+ count = metal4_label.count
+ logger.info("metal4_label has #{count} polygons")
+ polygons_count += count
- metal4 = metal4_drawn + metal4_dummy
+ metal4_slot = get_polygons(46, 3)
+ count = metal4_slot.count
+ logger.info("metal4_slot has #{count} polygons")
+ polygons_count += count
- metal4_label = get_polygons(46, 10)
- count = metal4_label.count
- logger.info("metal4_label has #{count} polygons")
- polygons_count += count
+ metal4_blk = get_polygons(46, 5)
+ count = metal4_blk.count
+ logger.info("metal4_blk has #{count} polygons")
+ polygons_count += count
+end
- metal4_slot = get_polygons(46, 3)
- count = metal4_slot.count
- logger.info("metal4_slot has #{count} polygons")
- polygons_count += count
+case METAL_LEVEL
+when '5LM', '6LM'
+ via4 = get_polygons(41, 0)
+ count = via4.count
+ logger.info("via4 has #{count} polygons")
+ polygons_count += count
- metal4_blk = get_polygons(46, 5)
- count = metal4_blk.count
- logger.info("metal4_blk has #{count} polygons")
- polygons_count += count
+ metal5_drawn = get_polygons(81, 0)
+ count = metal5_drawn.count
+ logger.info("metal5_drawn has #{count} polygons")
+ polygons_count += count
- if METAL_LEVEL == '4LM'
+ metal5_dummy = get_polygons(81, 4)
+ count = metal5_dummy.count
+ logger.info("metal5_dummy has #{count} polygons")
+ polygons_count += count
- top_via = via3
- topmin1_via = via2
- top_metal = metal4
- topmin1_metal = metal3
- top_metal_slot = metal4_slot
- topmin1_metal_slot = metal3_slot
- else
+ metal5 = metal5_drawn + metal5_dummy
- via4 = get_polygons(41, 0)
- count = via4.count
- logger.info("via4 has #{count} polygons")
- polygons_count += count
+ metal5_label = labels(81, 10)
+ count = metal5_label.count
+ logger.info("metal5_label has #{count} polygons")
+ polygons_count += count
- case METAL_LEVEL
- when '5LM'
- metal5_drawn = get_polygons(81, 0)
- count = metal5_drawn.count
- logger.info("metal5_drawn has #{count} polygons")
- polygons_count += count
+ metal5_slot = get_polygons(81, 3)
+ count = metal5_slot.count
+ logger.info("metal5_slot has #{count} polygons")
+ polygons_count += count
- metal5_dummy = get_polygons(81, 4)
- count = metal5_dummy.count
- logger.info("metal5_dummy has #{count} polygons")
- polygons_count += count
+ metal5_blk = get_polygons(81, 5)
+ count = metal5_blk.count
+ logger.info("metal5_blk has #{count} polygons")
+ polygons_count += count
+end
- metal5 = metal5_drawn + metal5_dummy
+case METAL_LEVEL
+when '6LM'
+ via5 = get_polygons(82, 0)
+ count = via5.count
+ logger.info("via5 has #{count} polygons")
+ polygons_count += count
- metal5_label = get_polygons(81, 10)
- count = metal5_label.count
- logger.info("metal5_label has #{count} polygons")
- polygons_count += count
+ metaltop_drawn = get_polygons(53, 0)
+ count = metaltop_drawn.count
+ logger.info("metaltop_drawn has #{count} polygons")
+ polygons_count += count
- metal5_slot = get_polygons(81, 3)
- count = metal5_slot.count
- logger.info("metal5_slot has #{count} polygons")
- polygons_count += count
+ metaltop_dummy = get_polygons(53, 4)
+ count = metaltop_dummy.count
+ logger.info("metaltop_dummy has #{count} polygons")
+ polygons_count += count
- metal5_blk = get_polygons(81, 5)
- count = metal5_blk.count
- logger.info("metal5_blk has #{count} polygons")
- polygons_count += count
+ metaltop = metaltop_drawn + metaltop_dummy
- top_via = via4
- topmin1_via = via3
- top_metal = metal5
- topmin1_metal = metal4
- top_metal_slot = metal5_slot
- topmin1_metal_slot = metal4_slot
- when '6LM'
- metal5_drawn = get_polygons(81, 0)
- count = metal5_drawn.count
- logger.info("metal5_drawn has #{count} polygons")
- polygons_count += count
+ metaltop_label = labels(53, 10)
+ count = metaltop_label.count
+ logger.info("metaltop_label has #{count} polygons")
+ polygons_count += count
- metal5_dummy = get_polygons(81, 4)
- count = metal5_dummy.count
- logger.info("metal5_dummy has #{count} polygons")
- polygons_count += count
+ metaltop_slot = get_polygons(53, 3)
+ count = metaltop_slot.count
+ logger.info("metaltop_slot has #{count} polygons")
+ polygons_count += count
- metal5 = metal5_drawn + metal5_dummy
+ metaltop_blk = get_polygons(53, 5)
+ count = metaltop_blk.count
+ logger.info("metaltop_blk has #{count} polygons")
+ polygons_count += count
+end
- metal5_label = get_polygons(81, 10)
- count = metal5_label.count
- logger.info("metal5_label has #{count} polygons")
- polygons_count += count
-
- metal5_slot = get_polygons(81, 3)
- count = metal5_slot.count
- logger.info("metal5_slot has #{count} polygons")
- polygons_count += count
-
- metal5_blk = get_polygons(81, 5)
- count = metal5_blk.count
- logger.info("metal5_blk has #{count} polygons")
- polygons_count += count
-
- via5 = get_polygons(82, 0)
- count = via5.count
- logger.info("via5 has #{count} polygons")
- polygons_count += count
-
- metaltop_drawn = get_polygons(53, 0)
- count = metaltop_drawn.count
- logger.info("metaltop_drawn has #{count} polygons")
- polygons_count += count
-
- metaltop_dummy = get_polygons(53, 4)
- count = metaltop_dummy.count
- logger.info("metaltop_dummy has #{count} polygons")
- polygons_count += count
-
- metaltop = metaltop_drawn + metaltop_dummy
-
- metaltop_label = get_polygons(53, 10)
- count = metaltop_label.count
- logger.info("metaltop_label has #{count} polygons")
- polygons_count += count
-
- metaltop_slot = get_polygons(53, 3)
- count = metaltop_slot.count
- logger.info("metaltop_slot has #{count} polygons")
- polygons_count += count
-
- metaltop_blk = get_polygons(53, 5)
- count = metaltop_blk.count
- logger.info("metaltop_blk has #{count} polygons")
- polygons_count += count
-
- top_via = via5
- topmin1_via = via4
- top_metal = metaltop
- topmin1_metal = metal5
- top_metal_slot = metaltop_slot
- topmin1_metal_slot = metal5_slot
- else
- logger.error("Unknown metal stack #{METAL_LEVEL}")
- raise
- end
- end
- end
+case METAL_LEVEL
+when '2LM'
+ top_via = via1
+ topmin1_via = contact
+ top_metal = metal2
+ topmin1_metal = metal1
+ top_metal_label = metal2_label
+when '3LM'
+ top_via = via2
+ topmin1_via = via1
+ top_metal = metal3
+ topmin1_metal = metal2
+ top_metal_label = metal3_label
+when '4LM'
+ top_via = via3
+ topmin1_via = via2
+ top_metal = metal4
+ topmin1_metal = metal3
+ top_metal_label = metal4_label
+when '5LM'
+ top_via = via4
+ topmin1_via = via3
+ top_metal = metal5
+ topmin1_metal = metal4
+ top_metal_label = metal5_label
+when '6LM'
+ top_via = via5
+ topmin1_via = via4
+ top_metal = metaltop
+ topmin1_metal = metal5
+ top_metal_label = metaltop_label
+else
+ logger.error("Unknown metal stack #{METAL_LEVEL}")
+ raise
end
piscap = get_polygons(120, 0)
diff --git a/BCDLite/klayout/lvs/rule_decks/mimcap_connections.lvs b/BCDLite/klayout/lvs/rule_decks/mimcap_connections.lvs
new file mode 100644
index 0000000..ae533fa
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/mimcap_connections.lvs
@@ -0,0 +1,38 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MIMCAP CONNECTIONS -------
+#==================================
+
+logger.info('Starting LVS MIMCAP CONNECTIONS')
+
+case MIM_OPTION
+
+#==================
+# --- MIM-A CAP ---
+#==================
+when 'A'
+ connect(metal2, mim_virtual)
+ connect(fuse_cap, via2_cap)
+
+#==================
+# --- MIM-B CAP ---
+#==================
+when 'B'
+ connect(topmin1_metal, mimtm_virtual)
+ connect(fuse_cap, top_via_cap)
+end
diff --git a/BCDLite/klayout/lvs/rule_decks/mimcap_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/mimcap_derivations.lvs
new file mode 100644
index 0000000..3da4c70
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/mimcap_derivations.lvs
@@ -0,0 +1,41 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MIMCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting MIMCAP DERIVATIONS')
+
+#==================
+# --- MIM-A CAP ---
+#==================
+
+mim_a_exclude = tanres.join(tanres_mk).join(tanres_l_mk)
+ .join(drc_bjt).join(lvs_rf).join(esd_hbm_mk)
+ .join(mom_mk).join(mom_m1_mk).join(mom_m2_mk)
+ .join(mom_m3_mk).join(mom_m4_mk).join(mom_m5_mk)
+
+mim_virtual = fusetop.sized(1.06.um).and(metal2.interacting(fusetop)).not(mim_a_exclude)
+metal2_ncap = metal2_con.not(mim_virtual)
+fuse_cap = fusetop.interacting(cap_mk).interacting(mim_l_mk).not(mim_a_exclude)
+
+#==================
+# --- MIM-B CAP ---
+#==================
+
+mim_b_exclude = mim_a_exclude.join(fusewindow_d).join(polyfuse)
+mimtm_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop)).not(mim_b_exclude)
diff --git a/BCDLite/klayout/lvs/rule_decks/mimcap_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/mimcap_extraction.lvs
new file mode 100644
index 0000000..ca5a1f6
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/mimcap_extraction.lvs
@@ -0,0 +1,131 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- MIMCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting MIMCAP EXTRACTION')
+
+case MIM_OPTION
+
+#==================
+# --- MIM-A CAP ---
+#==================
+when 'A'
+
+ case MIM_CAP
+ when '0.85'
+ # cap_mim_0f85 capacitor: 0.85fF/um2 MIM capacitor (usable for Volts <= 32V across capacitor) [mim_0p85fF]
+ logger.info('Extracting cap_mim_0f85 capacitor')
+ extract_devices(capacitor('cap_mim_0f85_m2m3_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_0f85_m2m3_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # cap_mim_1f0 capacitor: 1fF/um2 MIM capacitor (usable for Volts <= 20V across capacitor) [mim_1p0fF]
+ logger.info('Extracting cap_mim_1f0 capacitor')
+ extract_devices(capacitor('cap_mim_1f0_m2m3_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m2m3_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # cap_mim_1f5 capacitor: 1.5fF/um2 MIM capacitor (usable for Volts <= 6V across capacitor) [mim_1p5fF]
+ logger.info('Extracting cap_mim_1f5 capacitor')
+ extract_devices(capacitor('cap_mim_1f5_m2m3_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m2m3_noshield', 'C', relative: 0.25)
+ end
+
+#==================
+# --- MIM-B CAP ---
+#==================
+when 'B'
+ case METAL_LEVEL
+ when '6LM'
+
+ case MIM_CAP
+ when '0.85'
+ # cap_mim_0f85_tm capacitor: 0.85fF/um2 MIM capacitor (usable for Volts <= 32V across capacitor) (For MIM option-B case) [mim_0p85fF_tm]
+ logger.info('Extracting cap_mim_0f85 capacitor')
+ extract_devices(capacitor('cap_mim_0f85_m5m6_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_0f85_m5m6_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # cap_mim_1f0 capacitor: 1fF/um2 MIM capacitor (usable for Volts <= 20V across capacitor) (For MIM option-B case) [mim_1p0fF_tm]
+ logger.info('Extracting cap_mim_1f0 capacitor')
+ extract_devices(capacitor('cap_mim_1f0_m5m6_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m5m6_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # cap_mim_1f5 capacitor: 1.5fF/um2 MIM capacitor (usable for Volts <= 6V across capacitor) (For MIM option-B case) [mim_1p5fF_tm]
+ logger.info('Extracting cap_mim_1f5 capacitor')
+ extract_devices(capacitor('cap_mim_1f5_m5m6_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m5m6_noshield', 'C', relative: 0.25)
+ end
+
+ when '5LM'
+ case MIM_CAP
+ when '0.85'
+ # cap_mim_0f85 capacitor: 0.85fF/um2 MIM capacitor (usable for Volts <= 32V across capacitor) (For MIM option-B case) [mim_0p85fF_tm]
+ logger.info('Extracting cap_mim_0f85 capacitor')
+ extract_devices(capacitor('cap_mim_0f85_m4m5_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_0f85_m4m5_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # cap_mim_1f0 capacitor: 1fF/um2 MIM capacitor (usable for Volts <= 20V across capacitor) (For MIM option-B case) [mim_1p0fF_tm]
+ logger.info('Extracting cap_mim_1f0 capacitor')
+ extract_devices(capacitor('cap_mim_1f0_m4m5_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m4m5_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # cap_mim_1f5 capacitor: 1.5fF/um2 MIM capacitor (usable for Volts <= 6V across capacitor) (For MIM option-B case) [mim_1p5fF_tm]
+ logger.info('Extracting cap_mim_1f5 capacitor')
+ extract_devices(capacitor('cap_mim_1f5_m4m5_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m4m5_noshield', 'C', relative: 0.25)
+ end
+
+ when '4LM'
+ case MIM_CAP
+ when '0.85'
+ # cap_mim_0f85 capacitor: 0.85fF/um2 MIM capacitor (usable for Volts <= 32V across capacitor) (For MIM option-B case) [mim_0p85fF_tm]
+ logger.info('Extracting cap_mim_0f85 capacitor')
+ extract_devices(capacitor('cap_mim_0f85_m3m4_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_0f85_m3m4_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # cap_mim_1f0 capacitor: 1fF/um2 MIM capacitor (usable for Volts <= 20V across capacitor) (For MIM option-B case) [mim_1p0fF_tm]
+ logger.info('Extracting cap_mim_1f0 capacitor')
+ extract_devices(capacitor('cap_mim_1f0_m3m4_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m3m4_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # cap_mim_1f5 capacitor: 1.5fF/um2 MIM capacitor (usable for Volts <= 6V across capacitor) (For MIM option-B case) [mim_1p5fF_tm]
+ logger.info('Extracting cap_mim_1f5 capacitor')
+ extract_devices(capacitor('cap_mim_1f5_m3m4_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m3m4_noshield', 'C', relative: 0.25)
+ end
+ end
+end
diff --git a/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs
new file mode 100644
index 0000000..72dea73
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs
@@ -0,0 +1,58 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ PISCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting PISCAP DERIVATIONS')
+
+piscap_exclude = lvpwell.join(pplus).join(resistor)
+ .join(esd).join(sab).join(dni)
+ .join(pwhv).join(fusewindow_d).join(polyfuse)
+ .join(schottky_diode).join(zener).join(res_mk)
+ .join(diode_mk).join(v5_xtor).join(drc_bjt)
+ .join(nat).join(fhres).join(mos_cap_mk)
+ .join(mvsd).join(mvpsd).join(elmd_mk)
+ .join(elmd2_mk).join(lvs_rf).join(lvs_source)
+ .join(mk_35v).join(well_diode_mk).join(esd_hbm_mk)
+ .join(mos_mk_type1).join(swfet_mk).join(lvs_35v)
+ .join(hvpddd).join(hvpolyrs).join(ldmos_xtor)
+
+ngate_nw = ngate.and(piscap).and(nwell).not(piscap_exclude)
+
+ngate_nw_lv = ngate_nw.not(dualgate2_d)
+ngate_nw_mv = ngate_nw.and(dualgate2_d)
+
+#====================
+# --- PIS 1P8 CAP ---
+#====================
+
+# cap_pis_01v8: Model for 1.8V PIS capacitor (outside DNWELL) [pis_1p8]
+cap_pis_01v8_gate = ngate_nw_lv.not(dnwell)
+
+# cap_pis_01v8_dn: Model for (1.8V PIS capacitor (inside DNWEL) [pis_1p8_dw]
+cap_pis_01v8_dn_gate = ngate_nw_lv.and(dnwell)
+
+#====================
+# --- PIS 6P0 CAP ---
+#====================
+
+# cap_pis_06v0: Model for 6V PIS capacitor (outside DNWELL) [pis_6p0]
+cap_pis_06v0_gate = ngate_nw_mv.not(dnwell)
+
+# cap_pis_06v0_dn: Model for 6V PIS capacitor (inside DNWEL) [pis_6p0_dw]
+cap_pis_06v0_dn_gate = ngate_nw_mv.and(dnwell)
diff --git a/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs
new file mode 100644
index 0000000..16a21aa
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs
@@ -0,0 +1,53 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- PISCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting PISCAP EXTRACTION')
+
+#====================
+# --- PIS 1P8 CAP ---
+#====================
+
+# cap_pis_01v8: Model for 1.8V PIS capacitor (outside DNWELL) [pis_1p8]
+logger.info('Extracting cap_pis_01v8 device')
+extract_devices(capacitor('cap_pis_01v8', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_01v8_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_pis_01v8_dn: Model for (1.8V PIS capacitor (inside DNWEL) [pis_1p8_dw]
+logger.info('Extracting cap_pis_01v8_dn device')
+extract_devices(capacitor('cap_pis_01v8_dn', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_01v8_dn_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+#====================
+# --- PIS 6P0 CAP ---
+#====================
+
+# cap_pis_06v0: Model for 6V PIS capacitor (outside DNWELL) [pis_6p0]
+logger.info('Extracting cap_pis_06v0 device')
+extract_devices(capacitor('cap_pis_06v0', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_06v0_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_pis_06v0_dn: Model for 6V PIS capacitor (inside DNWEL) [pis_6p0_dw]
+logger.info('Extracting cap_pis_06v0_dn device')
+extract_devices(capacitor('cap_pis_06v0_dn', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_06v0_dn_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs
new file mode 100644
index 0000000..abfc448
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs
@@ -0,0 +1,47 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor CONNECTIONS -----
+#================================
+
+#========================
+# --- PN 1P8 VARACTOR ---
+#========================
+
+connect(cap_var_pd2nw_01v8_terminal_p ,contact)
+connect(cap_var_pd2nw_01v8_dn_terminal_p ,contact)
+
+#========================
+# --- PN 6P0 VARACTOR ---
+#========================
+
+connect(cap_var_pd2nw_06v0_terminal_p ,contact)
+connect(cap_var_pd2nw_06v0_dn_terminal_p ,contact)
+
+#=========================
+# --- MOS 1P8 VARACTOR ---
+#=========================
+
+connect(cap_var_fet_01v8_gate ,contact)
+connect(cap_var_fet_01v8_dn_gate ,contact)
+
+#=========================
+# --- MOS 6P0 VARACTOR ---
+#=========================
+
+connect(cap_var_fet_06v0_gate ,contact)
+connect(cap_var_fet_06v0_dn_gate ,contact)
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
new file mode 100644
index 0000000..aff1b79
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
@@ -0,0 +1,90 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor DERIVATIONS ----
+#================================
+
+logger.info('Starting VARACTOR DERIVATIONS')
+
+#=========================
+# --- VARACTOR EXCLUDE ---
+#=========================
+
+var_exclude = lvpwell.join(resistor).join(esd)
+ .join(sab).join(fusetop).join(tanres)
+ .join(dni).join(pwhv).join(fusewindow_d)
+ .join(polyfuse).join(schottky_diode).join(piscap)
+ .join(zener).join(res_mk).join(diode_mk)
+ .join(v5_xtor).join(drc_bjt).join(nat)
+ .join(fhres).join(mos_cap_mk).join(tanres_mk)
+ .join(tanres_l_mk).join(mvsd).join(mvpsd)
+ .join(elmd_mk).join(elmd2_mk).join(lvs_source)
+ .join(mk_35v).join(well_diode_mk).join(esd_hbm_mk)
+ .join(mos_mk_type1).join(swfet_mk).join(mom_mk)
+ .join(mom_m1_mk).join(mom_m2_mk).join(mom_m3_mk)
+ .join(mom_m4_mk).join(mom_m5_mk).join(hvnddd)
+ .join(hvpddd).join(hvpolyrs).join(ldmos_xtor)
+
+pcomp_nw_var = pcomp.and(nwell).and(lvs_rf).not(poly2).not(var_exclude)
+ngate_nw_var = ngate.and(nwell).and(lvs_rf).not(var_exclude)
+
+pcomp_nw_var_lv = pcomp_nw_var.not(dualgate2_d)
+pcomp_nw_var_mv = pcomp_nw_var.and(dualgate2_d)
+
+ngate_nw_var_lv = ngate_nw_var.not(dualgate2_d)
+ngate_nw_var_mv = ngate_nw_var.and(dualgate2_d)
+
+#========================
+# --- PN 1P8 VARACTOR ---
+#========================
+
+# cap_var_pd2nw_01v8: Model for 1.8V Scalable PN-varactor (outside DNWELL) [pn_varactor_1p8]
+cap_var_pd2nw_01v8_terminal_p = pcomp_nw_var_lv.not(dnwell)
+
+# cap_var_pd2nw_01v8_dn: Model for 1.8V Scalable PN-varactor (inside DNWELL) [pn_varactor_1p8_dw]
+cap_var_pd2nw_01v8_dn_terminal_p = pcomp_nw_var_lv.and(dnwell)
+
+#========================
+# --- PN 6P0 VARACTOR ---
+#========================
+
+# cap_var_pd2nw_06v0: Model for 6V Scalable PN-varactor (outside DNWELL) [pn_varactor_6p0]
+cap_var_pd2nw_06v0_terminal_p = pcomp_nw_var_mv.not(dnwell)
+
+# cap_var_pd2nw_06v0_dn: Model for 6V Scalable PN-varactor (inside DNWELL) [pn_varactor_6p0_dw]
+cap_var_pd2nw_06v0_dn_terminal_p = pcomp_nw_var_mv.and(dnwell)
+
+#=========================
+# --- MOS 1P8 VARACTOR ---
+#=========================
+
+# cap_var_fet_01v8: Model for 1.8V Scalable MOS-varactor (outside DNWELL) [mos_varactor_1p8]
+cap_var_fet_01v8_gate = ngate_nw_var_lv.not(dnwell)
+
+# cap_var_fet_01v8_dn: Model for 1.8V Scalable MOS-varactor (inside DNWELL) [mos_varactor_1p8_dw]
+cap_var_fet_01v8_dn_gate = ngate_nw_var_lv.and(dnwell)
+
+#=========================
+# --- MOS 6P0 VARACTOR ---
+#=========================
+
+# cap_var_fet_06v0: Model for 6V Scalable MOS-varactor (outside DNWELL) [mos_varactor_6p0]
+cap_var_fet_06v0_gate = ngate_nw_var_mv.not(dnwell)
+
+# cap_var_fet_06v0_dn: Model for 6V Scalable MOS-varactor (inside DNWELL) [mos_varactor_6p0_dw]
+cap_var_fet_06v0_dn_gate = ngate_nw_var_mv.and(dnwell)
+
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs
new file mode 100644
index 0000000..098d0d9
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs
@@ -0,0 +1,85 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor EXTRACTION ----
+#================================
+
+logger.info('Starting VARACTOR EXTRACTION')
+
+#========================
+# --- PN 1P8 VARACTOR ---
+#========================
+
+# cap_var_pd2nw_01v8: Model for 1.8V Scalable PN-varactor (outside DNWELL) [pn_varactor_1p8]
+logger.info('Extracting cap_var_pd2nw_01v8 varactor')
+extract_devices(capacitor('cap_var_pd2nw_01v8', 4.4e-15, VarCap),
+ { "P1" => cap_var_pd2nw_01v8_terminal_p, "P2" => nwell_con,
+ "tA" => cap_var_pd2nw_01v8_terminal_p, "tB" => nwell_con })
+
+# cap_var_pd2nw_01v8_dn: Model for 1.8V Scalable PN-varactor (inside DNWELL) [pn_varactor_1p8_dw]
+logger.info('Extracting cap_var_pd2nw_01v8_dn')
+extract_devices(capacitor('cap_var_pd2nw_01v8_dn', 4.4e-15, VarCap),
+ { "P1" => cap_var_pd2nw_01v8_dn_terminal_p, "P2" => dnwell,
+ "tA" => cap_var_pd2nw_01v8_dn_terminal_p, "tB" => dnwell })
+
+#========================
+# --- PN 6P0 VARACTOR ---
+#========================
+
+# cap_var_pd2nw_06v0: Model for 6V Scalable PN-varactor (outside DNWELL) [pn_varactor_6p0]
+logger.info('Extracting cap_var_pd2nw_06v0')
+extract_devices(capacitor('cap_var_pd2nw_06v0', 4.4e-15, VarCap),
+ { "P1" => cap_var_pd2nw_06v0_terminal_p, "P2" => nwell_con,
+ "tA" => cap_var_pd2nw_06v0_terminal_p, "tB" => nwell_con })
+
+# cap_var_pd2nw_06v0_dn: Model for 6V Scalable PN-varactor (inside DNWELL) [pn_varactor_6p0_dw]
+logger.info('Extracting cap_var_pd2nw_06v0_dn')
+extract_devices(capacitor('cap_var_pd2nw_06v0_dn', 4.4e-15, VarCap),
+ { "P1" => cap_var_pd2nw_06v0_dn_terminal_p, "P2" => dnwell,
+ "tA" => cap_var_pd2nw_06v0_dn_terminal_p, "tB" => dnwell })
+
+#=========================
+# --- MOS 1P8 VARACTOR ---
+#=========================
+
+# cap_var_fet_01v8: Model for 1.8V Scalable MOS-varactor (outside DNWELL) [mos_varactor_1p8]
+logger.info('Extracting cap_var_fet_01v8')
+extract_devices(capacitor('cap_var_fet_01v8', 4.4e-15, VarCap),
+ { 'P1' => cap_var_fet_01v8_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_var_fet_01v8_dn: Model for 1.8V Scalable MOS-varactor (inside DNWELL) [mos_varactor_1p8_dw]
+logger.info('Extracting cap_var_fet_01v8_dn')
+extract_devices(capacitor('cap_var_fet_01v8_dn', 4.4e-15, VarCap),
+ { 'P1' => cap_var_fet_01v8_dn_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+#=========================
+# --- MOS 6P0 VARACTOR ---
+#=========================
+
+# cap_var_fet_06v0: Model for 6V Scalable MOS-varactor (outside DNWELL) [mos_varactor_6p0]
+logger.info('Extracting cap_var_fet_06v0')
+extract_devices(capacitor('cap_var_fet_06v0', 4.4e-15, VarCap),
+ { 'P1' => cap_var_fet_06v0_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_var_fet_06v0_dn: Model for 6V Scalable MOS-varactor (inside DNWELL) [mos_varactor_6p0_dw]
+logger.info('Extracting cap_var_fet_06v0_dn')
+extract_devices(capacitor('cap_var_fet_06v0_dn', 4.4e-15, VarCap),
+ { 'P1' => cap_var_fet_06v0_dn_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
diff --git a/BCDLite/klayout/lvs/testing/run_regression.py b/BCDLite/klayout/lvs/testing/run_regression.py
index 6320d34..814058b 100644
--- a/BCDLite/klayout/lvs/testing/run_regression.py
+++ b/BCDLite/klayout/lvs/testing/run_regression.py
@@ -20,7 +20,7 @@
Options:
--help -h Print this help message.
- --device_name=<device_name> Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, ESD, EFUSE).
+ --device_name=<device_name> Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, PISCAP, ESD, EFUSE).
--mp=<num> The number of threads used in run.
--run_name=<run_name> Select your run name.
"""
@@ -71,7 +71,7 @@
exit(1)
elif len(klayout_v_list) >= 2 or len(klayout_v_list) <= 3:
if klayout_v_list[1] < 28 or (klayout_v_list[1] == 28 and klayout_v_list[2] <= 3):
- logging.error("Prerequisites at a minimum: KLayout 0.28.6")
+ logging.error("Prerequisites at a minimum: KLayout 0.28.4")
logging.error(
"Using this klayout version is not supported in this development."
)
@@ -248,8 +248,8 @@
# Creating run folder structure and copy testcases in it
pattern_clean = ".".join(os.path.basename(layout_path).split(".")[:-1])
- output_loc = f"{run_dir}/{device_name}"
- pattern_log = f"{output_loc}/{pattern_clean}_lvs.log"
+ output_loc = os.path.join(run_dir, device_name)
+ pattern_log = os.path.join(output_loc, f"{pattern_clean}_lvs.log")
os.makedirs(output_loc, exist_ok=True)
layout_path_run = os.path.join(run_dir, device_name, f"{device_name}.gds")
netlist_path_run = os.path.join(run_dir, device_name, f"{device_name}.cdl")
@@ -519,11 +519,11 @@
)
## selected device
- allowed_devices = ["MOS", "BJT", "DIODE", "RES", "MIMCAP", "MOSCAP", "APMOMCAP", "VARACTOR" , "EFUSE", "ESD"]
+ allowed_devices = ["MOS", "BJT", "DIODE", "RES", "MIMCAP", "MOSCAP", "PISCAP", "APMOMCAP", "VARACTOR" , "EFUSE", "ESD"]
target_device_group = args["--device_name"]
if target_device_group and target_device_group not in allowed_devices:
- logging.error("Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, ESD, EFUSE) only")
+ logging.error("Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, PISCAP, ESD, EFUSE) only")
exit(1)
# Calling main function
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8.gds
new file mode 100644
index 0000000..284da06
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8_dn.gds
new file mode 100644
index 0000000..f0d50cd
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0.gds
new file mode 100644
index 0000000..a84a81b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0_dn.gds
new file mode 100644
index 0000000..11fde57
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nw2ps_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nw2ps_06v0.gds
new file mode 100644
index 0000000..e2da907
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nw2ps_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8.gds
new file mode 100644
index 0000000..8b2356f
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8_dn.gds
new file mode 100644
index 0000000..c2eba47
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0.gds
new file mode 100644
index 0000000..b47a9d8
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0_dn.gds
new file mode 100644
index 0000000..c6ba90b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8.cdl
new file mode 100644
index 0000000..0f81e63
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:16:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_01v8 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=1.32n PJ=226.4u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=110p PJ=202.2u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=36p PJ=200.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=1.32n PJ=226.4u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=4.752p PJ=27.12u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=110p PJ=202.2u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=1.21p PJ=4.4u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=396f PJ=2.92u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=36p PJ=200.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=4.752p PJ=27.12u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=396f PJ=2.92u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=203.4f PJ=1.85u
+DI1_default vdd! I1_default_MINUS diode_nd2ps_01v8 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8_dn.cdl
new file mode 100644
index 0000000..9fa6328
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8_dn.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:17:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_01v8_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_nd2ps_01v8_dn m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0.cdl
new file mode 100644
index 0000000..283a244
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:18:14 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_06v0 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=1.32n PJ=226.4u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=110p PJ=202.2u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=36p PJ=200.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=1.32n PJ=226.4u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=4.752p PJ=27.12u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=110p PJ=202.2u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=1.21p PJ=4.4u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=396f PJ=2.92u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=36p PJ=200.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=4.752p PJ=27.12u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=396f PJ=2.92u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=203.4f PJ=1.85u
+DI1_default vdd! I1_default_MINUS diode_nd2ps_06v0 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0_dn.cdl
new file mode 100644
index 0000000..d34964b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0_dn.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:18:59 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_06v0_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_nd2ps_06v0_dn m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nw2ps_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nw2ps_06v0.cdl
new file mode 100644
index 0000000..4da7be2
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nw2ps_06v0.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nw2ps_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:43:35 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nw2ps_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nw2ps_06v0 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=1.21n PJ=224.2u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=123p PJ=202.46u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=86p PJ=201.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=1.21n PJ=224.2u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=146.41p PJ=48.4u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=14.883p PJ=26.66u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=10.406p PJ=25.92u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=123p PJ=202.46u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=14.883p PJ=26.66u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=1.5129p PJ=4.92u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=1.0578p PJ=4.18u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=86p PJ=201.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=10.406p PJ=25.92u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=1.0578p PJ=4.18u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=739.6f PJ=3.44u
+DI1_default vdd! I1_default_MINUS diode_nw2ps_06v0 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8.cdl
new file mode 100644
index 0000000..8f87022
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pd2nw_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:49:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pd2nw_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pd2nw_01v8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=36p
++ PJ=200.72u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=174.24p
++ PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=36p
++ PJ=200.72u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=203.4f
++ PJ=1.85u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pd2nw_01v8 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8_dn.cdl
new file mode 100644
index 0000000..472e9a9
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8_dn.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pd2nw_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:00 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pd2nw_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pd2nw_01v8_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pd2nw_01v8_dn m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0.cdl
new file mode 100644
index 0000000..60c1eb1
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pd2nw_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pd2nw_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pd2nw_06v0 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=36p
++ PJ=200.72u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=174.24p
++ PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=36p
++ PJ=200.72u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=203.4f
++ PJ=1.85u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pd2nw_06v0 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0_dn.cdl
new file mode 100644
index 0000000..8b38902
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0_dn.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pd2nw_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:51:10 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pd2nw_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pd2nw_06v0_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pd2nw_06v0_dn m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.gds
new file mode 100644
index 0000000..683b329
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.yaml
new file mode 100644
index 0000000..46c3411
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_0f85_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "0.85"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.gds
new file mode 100644
index 0000000..04d7f53
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.yaml
new file mode 100644
index 0000000..c273392
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_0f85_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "0.85"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.gds
new file mode 100644
index 0000000..889daa5
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.yaml
new file mode 100644
index 0000000..f58e8ed
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_0f85_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "0.85"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.gds
new file mode 100644
index 0000000..8c8e2c6
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.yaml
new file mode 100644
index 0000000..e8458e4
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_0f85_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "0.85"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds
new file mode 100644
index 0000000..5ca7b27
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml
new file mode 100644
index 0000000..5cdd347
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "1"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds
new file mode 100644
index 0000000..f7aa6d5
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml
new file mode 100644
index 0000000..652e54d
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "1"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds
new file mode 100644
index 0000000..98d4a1d
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml
new file mode 100644
index 0000000..4718dcb
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "1"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds
new file mode 100644
index 0000000..3e256ac
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml
new file mode 100644
index 0000000..e77a318
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "1"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds
new file mode 100644
index 0000000..54a51f1
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml
new file mode 100644
index 0000000..a4ade5d
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml
@@ -0,0 +1,5 @@
+cap_mim_1f5_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "1.5"
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds
new file mode 100644
index 0000000..926dd7c
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml
new file mode 100644
index 0000000..847938a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "1.5"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds
new file mode 100644
index 0000000..2d5f3f0
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml
new file mode 100644
index 0000000..353ebb4
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "1.5"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds
new file mode 100644
index 0000000..4023827
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml
new file mode 100644
index 0000000..781fbe8
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "1.5"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m2m3_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m2m3_noshield.cdl
new file mode 100644
index 0000000..85b2338
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_0f85_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:39:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_0f85_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_0f85_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_0f85_m2m3_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m3m4_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m3m4_noshield.cdl
new file mode 100644
index 0000000..19ee6d1
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_0f85_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_0f85_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_0f85_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_0f85_m3m4_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m4m5_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m4m5_noshield.cdl
new file mode 100644
index 0000000..5682262
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_0f85_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_0f85_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_0f85_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_0f85_m4m5_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m5m6_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m5m6_noshield.cdl
new file mode 100644
index 0000000..f28729e
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_0f85_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_0f85_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_0f85_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_0f85_m5m6_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl
new file mode 100644
index 0000000..ba2c560
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:39:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m2m3_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl
new file mode 100644
index 0000000..674d7e6
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m3m4_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl
new file mode 100644
index 0000000..4918d52
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m4m5_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl
new file mode 100644
index 0000000..4bfabb6
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m5m6_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl
new file mode 100644
index 0000000..262610a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:42:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m2m3_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl
new file mode 100644
index 0000000..22327d8
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m3m4_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl
new file mode 100644
index 0000000..aa81915
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m4m5_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl
new file mode 100644
index 0000000..d657f55
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m5m6_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds
new file mode 100644
index 0000000..9979044
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds
new file mode 100644
index 0000000..81e3719
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds
new file mode 100644
index 0000000..0349a37
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds
new file mode 100644
index 0000000..6d24d7a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl
new file mode 100644
index 0000000..e70e083
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_01v8 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_01v8 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_01v8 m=1 l=5.88u w=5u
+.ENDS
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl
new file mode 100644
index 0000000..834803f
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl
@@ -0,0 +1,34 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_01v8_dn I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_01v8_dn m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_01v8_dn m=1 l=5.88u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl
new file mode 100644
index 0000000..66e879a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_06v0 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_06v0 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_06v0 m=1 l=5.88u w=5u
+.ENDS
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl
new file mode 100644
index 0000000..ab6e6da
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_06v0_dn I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_06v0_dn m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_06v0_dn m=1 l=5.88u w=5u
+.ENDS
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8.gds
new file mode 100644
index 0000000..1b8269c
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8_dn.gds
new file mode 100644
index 0000000..2bb01f9
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0.gds
new file mode 100644
index 0000000..8057fcf
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0_dn.gds
new file mode 100644
index 0000000..dcbc03b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8.gds
new file mode 100644
index 0000000..a9bd13e
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8_dn.gds
new file mode 100644
index 0000000..d7d181d
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0.gds
new file mode 100644
index 0000000..22d79d3
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0_dn.gds
new file mode 100644
index 0000000..3535905
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8.cdl
new file mode 100644
index 0000000..aac3115
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_fet_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_fet_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_fet_01v8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_01v8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_01v8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_01v8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_01v8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_01v8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_01v8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_01v8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_01v8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_01v8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_01v8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8_dn.cdl
new file mode 100644
index 0000000..16d2038
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_fet_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:12:27 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_fet_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_fet_01v8_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_01v8_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_01v8_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_01v8_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_01v8_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_01v8_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_01v8_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_01v8_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_01v8_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_01v8_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_01v8_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0.cdl
new file mode 100644
index 0000000..99613b1
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_fet_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:13:17 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_fet_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_fet_06v0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_06v0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_06v0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_06v0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_06v0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_06v0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_06v0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_06v0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_06v0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_06v0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_06v0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0_dn.cdl
new file mode 100644
index 0000000..b2b34ba
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_fet_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:15:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_fet_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_fet_06v0_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_06v0_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_06v0_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_06v0_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_06v0_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_06v0_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_06v0_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_06v0_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_06v0_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_06v0_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_06v0_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8.cdl
new file mode 100644
index 0000000..09d3dea
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_pd2nw_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:49:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_pd2nw_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_01v8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_default_MINUS I1_default_PLUS
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_01v8 m=1 L=1u W=1u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8_dn.cdl
new file mode 100644
index 0000000..b7c1439
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8_dn.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_pd2nw_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:00 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_pd2nw_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_01v8_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS
++ I1_default_PLUS I1_default_MINUS
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_01v8_dn m=1 L=1u W=1u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0.cdl
new file mode 100644
index 0000000..723bda2
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_pd2nw_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_pd2nw_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_06v0 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_default_MINUS I1_default_PLUS
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_06v0 m=1 L=1u W=1u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0_dn.cdl
new file mode 100644
index 0000000..2783ab4
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0_dn.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_pd2nw_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:51:10 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_pd2nw_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_06v0_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS
++ I1_default_PLUS I1_default_MINUS
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_06v0_dn m=1 L=1u W=1u
+.ENDS
+
diff --git a/IC/klayout/lvs/rule_decks/bjt_connection.lvs b/IC/klayout/lvs/rule_decks/bjt_connection.lvs
new file mode 100644
index 0000000..5e21220
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/bjt_connection.lvs
@@ -0,0 +1,68 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ------ BJT CONNECTIONS --------
+#================================
+logger.info('Starting LVS BJT CONNECTIONS')
+
+# ==============
+# ---- vnpn ----
+# ==============
+
+# npn_02p00x02p00 nodes connections
+connect(npn_02p00x02p00_e, contact)
+connect(npn_02p00x02p00_b, contact)
+connect(npn_02p00x02p00_c, contact)
+
+# npn_05p00x05p00 nodes connections
+connect(npn_05p00x05p00_e, contact)
+connect(npn_05p00x05p00_b, contact)
+connect(npn_05p00x05p00_c, contact)
+
+# ==============
+# ---- vpnp ----
+# ==============
+
+# pnp_10p00x10p00 nodes connections
+connect(pnp_10p00x10p00_e, contact)
+connect(pnp_10p00x10p00_b, contact)
+connect(pnp_10p00x10p00_c, contact)
+
+# pnp_05p00x05p00 nodes connections
+connect(pnp_05p00x05p00_e, contact)
+connect(pnp_05p00x05p00_b, contact)
+connect(pnp_05p00x05p00_c, contact)
+
+# pnp_05p00x00p42 nodes connections
+connect(pnp_05p00x00p42_e, contact)
+connect(pnp_05p00x00p42_b, contact)
+connect(pnp_05p00x00p42_c, contact)
+
+# pnp_1p2x2p5 nodes connections
+connect(pnp_1p2x2p5_e, contact)
+connect(pnp_1p2x2p5_b, contact)
+connect(pnp_1p2x2p5_c, contact)
+
+# pnp_00p46x1p2 nodes connections
+connect(pnp_00p46x1p2_e, contact)
+connect(pnp_00p46x1p2_b, contact)
+connect(pnp_00p46x1p2_c, contact)
+
+# pnp_00p46x00p46 nodes connections
+connect(pnp_00p46x00p46_e, contact)
+connect(pnp_00p46x00p46_b, contact)
+connect(pnp_00p46x00p46_c, contact)
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/devices_connections.lvs b/IC/klayout/lvs/rule_decks/devices_connections.lvs
index 7848e93..d4f6b9d 100644
--- a/IC/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/IC/klayout/lvs/rule_decks/devices_connections.lvs
@@ -40,19 +40,27 @@
connect(poly2_con, contact)
connect(contact, metal1)
connect(metal1, via1)
-connect(via1, metal2_ncap)
+connect(via1, metal2)
if METAL_LEVEL != '2LM'
- connect(metal2_ncap, via2)
- connect(via2, metal3_ncap)
+ connect(metal2, via2_ncap)
+ connect(via2_ncap, metal3)
+ connect(via2_cap, fusetop)
+ connect(via2_cap, fusetop2)
if METAL_LEVEL != '3LM'
- connect(metal3_ncap, via3)
- connect(via3, metal4_ncap)
+ connect(metal3, via3_ncap)
+ connect(via3_ncap, metal4)
+ connect(via3_cap, fusetop)
+ connect(via3_cap, fusetop2)
if METAL_LEVEL != '4LM'
- connect(metal4_ncap, via4)
- connect(via4, metal5_ncap)
+ connect(metal4, via4_ncap)
+ connect(via4_ncap, metal5)
+ connect(via4_cap, fusetop)
+ connect(via4_cap, fusetop2)
if METAL_LEVEL != '5LM'
- connect(metal5_ncap, via5)
- connect(via5, metaltop)
+ connect(metal5, via5_ncap)
+ connect(via5_ncap, metaltop)
+ connect(via5_cap, fusetop)
+ connect(via5_cap, fusetop2)
end
end
end
@@ -64,13 +72,13 @@
connect(comp, comp_label)
connect(poly2_con, poly2_label)
connect(metal1, metal1_label)
-connect(metal2_ncap, metal2_label)
+connect(metal2, metal2_label)
if METAL_LEVEL != '2LM'
- connect(metal3_ncap, metal3_label)
+ connect(metal3, metal3_label)
if METAL_LEVEL != '3LM'
- connect(metal4_ncap, metal4_label)
+ connect(metal4, metal4_label)
if METAL_LEVEL != '4LM'
- connect(metal5_ncap, metal5_label)
+ connect(metal5, metal5_label)
connect(metaltop, metaltop_label) if METAL_LEVEL != '5LM'
end
end
@@ -90,131 +98,29 @@
#================================
# ------ BJT CONNECTIONS --------
#================================
-logger.info('Starting LVS BJT CONNECTIONS')
-# ==============
-# ---- vnpn ----
-# ==============
-
-# npn_02p00x02p00 nodes connections
-connect(npn_02p00x02p00_e, contact)
-connect(npn_02p00x02p00_b, contact)
-connect(npn_02p00x02p00_c, contact)
-
-# npn_05p00x05p00 nodes connections
-connect(npn_05p00x05p00_e, contact)
-connect(npn_05p00x05p00_b, contact)
-connect(npn_05p00x05p00_c, contact)
-
-# ==============
-# ---- vpnp ----
-# ==============
-
-# pnp_10p00x10p00 nodes connections
-connect(pnp_10p00x10p00_e, contact)
-connect(pnp_10p00x10p00_b, contact)
-connect(pnp_10p00x10p00_c, contact)
-
-# pnp_05p00x05p00 nodes connections
-connect(pnp_05p00x05p00_e, contact)
-connect(pnp_05p00x05p00_b, contact)
-connect(pnp_05p00x05p00_c, contact)
-
-# pnp_05p00x00p42 nodes connections
-connect(pnp_05p00x00p42_e, contact)
-connect(pnp_05p00x00p42_b, contact)
-connect(pnp_05p00x00p42_c, contact)
-
-# pnp_1p2x2p5 nodes connections
-connect(pnp_1p2x2p5_e, contact)
-connect(pnp_1p2x2p5_b, contact)
-connect(pnp_1p2x2p5_c, contact)
-
-# pnp_00p46x1p2 nodes connections
-connect(pnp_00p46x1p2_e, contact)
-connect(pnp_00p46x1p2_b, contact)
-connect(pnp_00p46x1p2_c, contact)
-
-# pnp_00p46x00p46 nodes connections
-connect(pnp_00p46x00p46_e, contact)
-connect(pnp_00p46x00p46_b, contact)
-connect(pnp_00p46x00p46_c, contact)
-
+# %include bjt_connection.lvs
#================================
# ----- DIODE CONNECTIONS -------
#================================
-logger.info('Starting LVS DIODE CONNECTIONS')
-
-# diode_np_1p8
-connect(diode_np_1p8_terminal_n, contact)
-connect(diode_np_1p8_terminal_p, contact)
-
-# diode_pn_1p8
-connect(diode_pn_1p8_terminal_n, contact)
-connect(diode_pn_1p8_terminal_p, contact)
-
-# diode_np_3p3
-connect(diode_np_3p3_terminal_n, contact)
-connect(diode_np_3p3_terminal_p, contact)
-
-# diode_pn_3p3
-connect(diode_pn_3p3_terminal_n, contact)
-connect(diode_pn_3p3_terminal_p, contact)
-
-# diode_nwp
-connect(diode_nwp_terminal_n, contact)
-connect(diode_nwp_terminal_p, contact)
-
-# diode_np_1p8_nat
-connect(diode_np_1p8_nat_terminal_n, contact)
-connect(diode_np_1p8_nat_terminal_p, contact)
-
-# diode_np_3p3_nat
-connect(diode_np_3p3_nat_terminal_n, contact)
-connect(diode_np_3p3_nat_terminal_p, contact)
-
-# diode_dnwpw
-connect(diode_dnwps_terminal_p, contact)
-
-# diode_dnwps
-connect(diode_dnwps_terminal_p, contact)
-
+# %include diode_connection.lvs
#==================================
# ------ MIMCAP CONNECTIONS -------
#==================================
-logger.info('Starting LVS MIMCAP CONNECTIONS')
-
-case MIM_OPTION
-when 'A'
- connect(metal2, mim_virtual)
- connect(fuse_cap, via2)
-
-when 'B'
- connect(topmin1_metal, mimtm_virtual)
- connect(fuse_cap, top_via)
- connect(topmin1_metal, mimtm_stack1_virtual)
- connect(topmin2_metal, mimtm_stack2_virtual)
- connect(fuse2_cap, topmin1_via)
-end
+# %include mimcap_connection.lvs
#========================================
# ------ PN Varactors CONNECTIONS -------
#========================================
-# pnvar_1p8 varactor nodes connections
-connect(pnvar_1p8_terminal_n, contact)
-connect(pnvar_1p8_terminal_p, contact)
-
+# %include pn_varactor_connection.lvs
#================================
# ---- RESISTOR DERIVATIONS -----
#================================
-logger.info('Starting LVS RESISTOR CONNECTIONS')
-
-connect(nplus_cont, contact)
-connect(pplus_cont, contact)
\ No newline at end of file
+# %include res_connection.lvs
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/diode_connection.lvs b/IC/klayout/lvs/rule_decks/diode_connection.lvs
new file mode 100644
index 0000000..2bd1560
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/diode_connection.lvs
@@ -0,0 +1,55 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- DIODE CONNECTIONS -------
+#================================
+
+logger.info('Starting LVS DIODE CONNECTIONS')
+
+# diode_np_1p8
+connect(diode_np_1p8_terminal_n, contact)
+connect(diode_np_1p8_terminal_p, contact)
+
+# diode_pn_1p8
+connect(diode_pn_1p8_terminal_n, contact)
+connect(diode_pn_1p8_terminal_p, contact)
+
+# diode_np_3p3
+connect(diode_np_3p3_terminal_n, contact)
+connect(diode_np_3p3_terminal_p, contact)
+
+# diode_pn_3p3
+connect(diode_pn_3p3_terminal_n, contact)
+connect(diode_pn_3p3_terminal_p, contact)
+
+# diode_nwp
+connect(diode_nwp_terminal_n, contact)
+connect(diode_nwp_terminal_p, contact)
+
+# diode_np_1p8_nat
+connect(diode_np_1p8_nat_terminal_n, contact)
+connect(diode_np_1p8_nat_terminal_p, contact)
+
+# diode_np_3p3_nat
+connect(diode_np_3p3_nat_terminal_n, contact)
+connect(diode_np_3p3_nat_terminal_p, contact)
+
+# diode_dnwpw
+connect(diode_dnwps_terminal_p, contact)
+
+# diode_dnwps
+connect(diode_dnwps_terminal_p, contact)
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/general_derivations.lvs b/IC/klayout/lvs/rule_decks/general_derivations.lvs
index 3ab99e9..efd371d 100644
--- a/IC/klayout/lvs/rule_decks/general_derivations.lvs
+++ b/IC/klayout/lvs/rule_decks/general_derivations.lvs
@@ -39,3 +39,24 @@
psd_dw = pcomp.and(dnwell).interacting(pgate).not(pgate).not(res_mk)
nwell_con = nwell.not(res_mk)
poly2_con = poly2.not(res_mk).not(plfuse)
+
+
+# Splitting vias into cap-vias, ncap-vias
+
+if METAL_LEVEL != '2LM'
+ via2_ncap = via2.not(fusetop.or(fusetop2))
+ via2_cap = via2.and(fusetop.or(fusetop2))
+ if METAL_LEVEL != '3LM'
+ via3_ncap = via3.not(fusetop.or(fusetop2))
+ via3_cap = via3.and(fusetop.or(fusetop2))
+ if METAL_LEVEL != '4LM'
+ via4_ncap = via4.not(fusetop.or(fusetop2))
+ via4_cap = via4.and(fusetop.or(fusetop2))
+ if METAL_LEVEL != '5LM'
+ via5_ncap = via5.not(fusetop.or(fusetop2))
+ via5_cap = via5.and(fusetop.or(fusetop2))
+ end
+ end
+ end
+end
+
diff --git a/IC/klayout/lvs/rule_decks/mimcap_connection.lvs b/IC/klayout/lvs/rule_decks/mimcap_connection.lvs
new file mode 100644
index 0000000..c2e6646
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/mimcap_connection.lvs
@@ -0,0 +1,34 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MIMCAP CONNECTIONS -------
+#==================================
+
+logger.info('Starting LVS MIMCAP CONNECTIONS')
+
+case MIM_OPTION
+when 'A'
+ connect(metal2, mim_virtual)
+ connect(fuse_cap, via2)
+
+when 'B'
+ connect(topmin1_metal, mimtm_virtual)
+ connect(fuse_cap, top_via)
+ connect(topmin1_metal, mimtm_stack1_virtual)
+ connect(topmin2_metal, mimtm_stack2_virtual)
+ connect(fuse2_cap, topmin1_via)
+end
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs b/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
index 2fa2226..de22dc7 100644
--- a/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
+++ b/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
@@ -23,7 +23,6 @@
# mim option A
# stacked mim cannot exist in 2LM
mim_virtual = fusetop.sized(1.06.um).and(metal2.interacting(fusetop)).not(fusetop2)
-metal2_ncap = metal2.not(mim_virtual)
fuse_cap = fusetop.interacting(lvs_cap)
fuse2_cap = fusetop2.interacting(lvs_cap)
@@ -32,12 +31,3 @@
mimtm_stack1_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop))
mimtm_stack2_virtual = fusetop2.sized(1.06.um).and(topmin2_metal.interacting(fusetop2))
-if METAL_LEVEL != '2LM'
- metal3_ncap = metal3.not(mimtm_virtual).not(mimtm_stack2_virtual).not(mimtm_stack1_virtual)
-
- if METAL_LEVEL != '3LM'
- metal4_ncap = metal4.not(mimtm_virtual).not(mimtm_stack2_virtual).not(mimtm_stack1_virtual)
- metal5_ncap = metal5.not(mimtm_virtual).not(mimtm_stack2_virtual).not(mimtm_stack1_virtual) if METAL_LEVEL != '4LM'
- end
-
-end
diff --git a/IC/klayout/lvs/rule_decks/pn_varactor_connection.lvs b/IC/klayout/lvs/rule_decks/pn_varactor_connection.lvs
new file mode 100644
index 0000000..8f4c111
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/pn_varactor_connection.lvs
@@ -0,0 +1,23 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#========================================
+# ------ PN Varactors CONNECTIONS -------
+#========================================
+
+# pnvar_1p8 varactor nodes connections
+connect(pnvar_1p8_terminal_n, contact)
+connect(pnvar_1p8_terminal_p, contact)
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/res_connection.lvs b/IC/klayout/lvs/rule_decks/res_connection.lvs
new file mode 100644
index 0000000..813bd1b
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/res_connection.lvs
@@ -0,0 +1,24 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- RESISTOR DERIVATIONS -----
+#================================
+
+logger.info('Starting LVS RESISTOR CONNECTIONS')
+
+connect(nplus_cont, contact)
+connect(pplus_cont, contact)
\ No newline at end of file
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.gds
new file mode 100644
index 0000000..3e95cd6
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.yaml
new file mode 100644
index 0000000..a347fd3
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_3f0_m2m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap_stack: "3"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.gds
new file mode 100644
index 0000000..913993f
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.yaml
new file mode 100644
index 0000000..9cd5c50
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_3f0_m3m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap_stack: "3"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.gds
new file mode 100644
index 0000000..6b8701a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.yaml
new file mode 100644
index 0000000..1798498
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_3f0_m4m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap_stack: "3"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m2m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m2m4_noshield.cdl
new file mode 100644
index 0000000..0ab1cdb
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m2m4_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_3f0_m2m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_3f0_m2m4_noshield
+* View Name: schematic
+************************************************************************
+.SUBCKT cap_mim_3f0_m2m4_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_3f0_m2m4_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_3f0_m2m4_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+.ENDS cap_mim_3f0_m2m4_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m3m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m3m5_noshield.cdl
new file mode 100644
index 0000000..1a9f274
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m3m5_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_3f0_m3m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_3f0_m3m5_noshield
+* View Name: schematic
+************************************************************************
+.SUBCKT cap_mim_3f0_m3m5_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_3f0_m3m5_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_3f0_m3m5_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+.ENDS cap_mim_3f0_m3m5_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m4m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m4m6_noshield.cdl
new file mode 100644
index 0000000..aea33a7
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m4m6_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_3f0_m4m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_3f0_m4m6_noshield
+* View Name: schematic
+************************************************************************
+.SUBCKT cap_mim_3f0_m4m6_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_3f0_m4m6_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_3f0_m4m6_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+.ENDS cap_mim_3f0_m4m6_noshield
diff --git a/ULL/klayout/lvs/gf180ull.lvs b/ULL/klayout/lvs/gf180ull.lvs
index 341633b..f15323e 100644
--- a/ULL/klayout/lvs/gf180ull.lvs
+++ b/ULL/klayout/lvs/gf180ull.lvs
@@ -260,12 +260,6 @@
# %include 'rule_decks/mos_derivations.lvs'
#================================
-# ------ RES DERIVATIONS --------
-#================================
-
-# %include 'rule_decks/res_derivations.lvs'
-
-#================================
# ------ DIODE DERIVATIONS --------
#================================
@@ -289,6 +283,12 @@
# %include 'rule_decks/piscap_derivations.lvs'
+#===================================
+# ------ MIMCAP DERIVATIONS ------
+#===================================
+
+# %include 'rule_decks/mimcap_derivations.lvs'
+
#================================================
#------------ DEVICES CONNECTIVITY --------------
#================================================
@@ -314,12 +314,6 @@
# %include 'rule_decks/mos_extraction.lvs'
#================================
-# ------- RES EXTRACTION --------
-#================================
-
-# %include 'rule_decks/res_extraction.lvs'
-
-#================================
# ------- Diode EXTRACTION ------
#================================
@@ -343,6 +337,12 @@
# %include 'rule_decks/piscap_extraction.lvs'
+#================================
+# ------ MIMCAP EXTRACTION -----
+#================================
+
+# %include 'rule_decks/mimcap_extraction.lvs'
+
#================================================
#------------- COMPARISON OPTIONS ---------------
#================================================
diff --git a/ULL/klayout/lvs/rule_decks/bjt_connection.lvs b/ULL/klayout/lvs/rule_decks/bjt_connection.lvs
new file mode 100644
index 0000000..d0a894f
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/bjt_connection.lvs
@@ -0,0 +1,98 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ------ BJT CONNECTIONS --------
+#================================
+logger.info('Starting LVS BJT CONNECTIONS')
+
+# ========================================
+# ---- VNPN (isolated collector) (5V) ----
+# ========================================
+
+# vnpn_5x5 nodes connections
+connect(npn_05p00x05p00_e, contact)
+connect(npn_05p00x05p00_b, contact)
+connect(npn_05p00x05p00_c, contact)
+
+# vnpn_0p54x16 nodes connections
+connect(npn_00p54x16p00_e, contact)
+connect(npn_00p54x16p00_b, contact)
+connect(npn_00p54x16p00_c, contact)
+
+# vnpn_0p54x8 nodes connections
+connect(npn_00p54x08p00_e, contact)
+connect(npn_00p54x08p00_b, contact)
+connect(npn_00p54x08p00_c, contact)
+
+# vnpn_0p54x2 nodes connections
+connect(npn_00p54x02p00_e, contact)
+connect(npn_00p54x02p00_b, contact)
+connect(npn_00p54x02p00_c, contact)
+
+# ===========================================
+# ---- VNPN (isolated collector) (3.3V) ----
+# ===========================================
+
+# vnpn_5x5_3p3 nodes connections
+connect(npn_05p00x05p00_e_3p3, contact)
+connect(npn_05p00x05p00_b_3p3, contact)
+connect(npn_05p00x05p00_c_3p3, contact)
+
+# vnpn_0p54x16_3p3 nodes connections
+connect(npn_00p54x16p00_e_3p3, contact)
+connect(npn_00p54x16p00_b_3p3, contact)
+connect(npn_00p54x16p00_c_3p3, contact)
+
+# vnpn_0p54x8_3p3 nodes connections
+connect(npn_00p54x08p00_e_3p3, contact)
+connect(npn_00p54x08p00_b_3p3, contact)
+connect(npn_00p54x08p00_c_3p3, contact)
+
+# vnpn_0p54x2_3p3 nodes connections
+connect(npn_00p54x02p00_e_3p3, contact)
+connect(npn_00p54x02p00_b_3p3, contact)
+connect(npn_00p54x02p00_c_3p3, contact)
+
+
+# ========================================
+# ---- VPNP (Psub as collector) (6V) ----
+# ========================================
+
+# vpnp_6p0_10x10 nodes connections
+connect(pnp_10p00x10p00_e, contact)
+connect(pnp_10p00x10p00_b, contact)
+connect(pnp_10p00x10p00_c, contact)
+
+# vpnp_6p0_5x5 nodes connections
+connect(pnp_05p00x05p00_e, contact)
+connect(pnp_05p00x05p00_b, contact)
+connect(pnp_05p00x05p00_c, contact)
+
+# vpnp_6p0_0p42x20 nodes connections
+connect(pnp_00p42x20p00_e, contact)
+connect(pnp_00p42x20p00_b, contact)
+connect(pnp_00p42x20p00_c, contact)
+
+# vpnp_6p0_0p42x10 nodes connections
+connect(pnp_00p42x10p00_e, contact)
+connect(pnp_00p42x10p00_b, contact)
+connect(pnp_00p42x10p00_c, contact)
+
+# vpnp_6p0_0p42x5 nodes connections
+connect(pnp_00p42x05p00_e, contact)
+connect(pnp_00p42x05p00_b, contact)
+connect(pnp_00p42x05p00_c, contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/devices_connections.lvs b/ULL/klayout/lvs/rule_decks/devices_connections.lvs
index a0d119c..1cd89c1 100644
--- a/ULL/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/ULL/klayout/lvs/rule_decks/devices_connections.lvs
@@ -42,19 +42,23 @@
connect(poly2_con, contact)
connect(contact, metal1)
connect(metal1, via1)
-connect(via1, metal2_ncap)
+connect(via1, metal2)
if METAL_LEVEL != '2LM'
- connect(metal2_ncap, via2)
- connect(via2, metal3_ncap)
+ connect(metal2, via2_ncap)
+ connect(via2_ncap, metal3)
+ connect(via2_cap, fusetop)
if METAL_LEVEL != '3LM'
- connect(metal3_ncap, via3)
- connect(via3, metal4_ncap)
+ connect(metal3, via3_ncap)
+ connect(via3_ncap, metal4)
+ connect(via3_cap, fusetop)
if METAL_LEVEL != '4LM'
- connect(metal4_ncap, via4)
- connect(via4, metal5_ncap)
+ connect(metal4, via4_ncap)
+ connect(via4_ncap, metal5)
+ connect(via4_cap, fusetop)
if METAL_LEVEL != '5LM'
- connect(metal5_ncap, via5)
- connect(via5, metaltop)
+ connect(metal5, via5_ncap)
+ connect(via5_ncap, metaltop)
+ connect(via5_cap, fusetop)
end
end
end
@@ -65,13 +69,13 @@
# Attaching labels
connect(metal1, metal1_label)
-connect(metal2_ncap, metal2_label)
+connect(metal2, metal2_label)
if METAL_LEVEL != '2LM'
- connect(metal3_ncap, metal3_label)
+ connect(metal3, metal3_label)
if METAL_LEVEL != '3LM'
- connect(metal4_ncap, metal4_label)
+ connect(metal4, metal4_label)
if METAL_LEVEL != '4LM'
- connect(metal5_ncap, metal5_label)
+ connect(metal5, metal5_label)
connect(metaltop, metaltop_label) if METAL_LEVEL != '5LM'
end
end
@@ -90,172 +94,30 @@
#================================
# ----- MOSFET CONNECTIONS ------
#================================
-logger.info('Starting LVS MOSFET CONNECTIONS')
-connect(psd_dw, contact)
-
+# %include mos_connection.lvs
#================================
# ------ BJT CONNECTIONS --------
#================================
-logger.info('Starting LVS BJT CONNECTIONS')
-# ========================================
-# ---- VNPN (isolated collector) (5V) ----
-# ========================================
-
-# vnpn_5x5 nodes connections
-connect(npn_05p00x05p00_e, contact)
-connect(npn_05p00x05p00_b, contact)
-connect(npn_05p00x05p00_c, contact)
-
-# vnpn_0p54x16 nodes connections
-connect(npn_00p54x16p00_e, contact)
-connect(npn_00p54x16p00_b, contact)
-connect(npn_00p54x16p00_c, contact)
-
-# vnpn_0p54x8 nodes connections
-connect(npn_00p54x08p00_e, contact)
-connect(npn_00p54x08p00_b, contact)
-connect(npn_00p54x08p00_c, contact)
-
-# vnpn_0p54x2 nodes connections
-connect(npn_00p54x02p00_e, contact)
-connect(npn_00p54x02p00_b, contact)
-connect(npn_00p54x02p00_c, contact)
-
-# ===========================================
-# ---- VNPN (isolated collector) (3.3V) ----
-# ===========================================
-
-# vnpn_5x5_3p3 nodes connections
-connect(npn_05p00x05p00_e_3p3, contact)
-connect(npn_05p00x05p00_b_3p3, contact)
-connect(npn_05p00x05p00_c_3p3, contact)
-
-# vnpn_0p54x16_3p3 nodes connections
-connect(npn_00p54x16p00_e_3p3, contact)
-connect(npn_00p54x16p00_b_3p3, contact)
-connect(npn_00p54x16p00_c_3p3, contact)
-
-# vnpn_0p54x8_3p3 nodes connections
-connect(npn_00p54x08p00_e_3p3, contact)
-connect(npn_00p54x08p00_b_3p3, contact)
-connect(npn_00p54x08p00_c_3p3, contact)
-
-# vnpn_0p54x2_3p3 nodes connections
-connect(npn_00p54x02p00_e_3p3, contact)
-connect(npn_00p54x02p00_b_3p3, contact)
-connect(npn_00p54x02p00_c_3p3, contact)
-
-
-# ========================================
-# ---- VPNP (Psub as collector) (6V) ----
-# ========================================
-
-# vpnp_6p0_10x10 nodes connections
-connect(pnp_10p00x10p00_e, contact)
-connect(pnp_10p00x10p00_b, contact)
-connect(pnp_10p00x10p00_c, contact)
-
-# vpnp_6p0_5x5 nodes connections
-connect(pnp_05p00x05p00_e, contact)
-connect(pnp_05p00x05p00_b, contact)
-connect(pnp_05p00x05p00_c, contact)
-
-# vpnp_6p0_0p42x20 nodes connections
-connect(pnp_00p42x20p00_e, contact)
-connect(pnp_00p42x20p00_b, contact)
-connect(pnp_00p42x20p00_c, contact)
-
-# vpnp_6p0_0p42x10 nodes connections
-connect(pnp_00p42x10p00_e, contact)
-connect(pnp_00p42x10p00_b, contact)
-connect(pnp_00p42x10p00_c, contact)
-
-# vpnp_6p0_0p42x5 nodes connections
-connect(pnp_00p42x05p00_e, contact)
-connect(pnp_00p42x05p00_b, contact)
-connect(pnp_00p42x05p00_c, contact)
-
+# %include bjt_connection.lvs
#================================
# ----- DIODE CONNECTIONS -------
#================================
-logger.info('Starting LVS DIODE CONNECTIONS')
-
-#================================
-# ---- LV DIODE DERIVATIONS ----
-#================================
-
-# diode_np_1p8
-connect(diode_np_1p8_terminal_n, contact)
-
-# diode_np_1p8_dw
-connect(diode_np_1p8_dw_terminal_n, contact)
-
-# diode_pn_1p8
-connect(diode_pn_1p8_terminal_p, contact)
-
-# diode_pn_1p8_dw
-connect(diode_pn_1p8_dw_terminal_p, contact)
-
-#================================
-# ---- MV DIODE DERIVATIONS ----
-#================================
-
-# diode_np_3p3
-connect(diode_np_3p3_terminal_n, contact)
-
-# diode_pn_3p3
-connect(diode_pn_3p3_terminal_p, contact)
-
-# diode_np_3p3_dw
-connect(diode_np_3p3_dw_terminal_n, contact)
-
-# diode_pn_3p3_dw
-connect(diode_pn_3p3_dw_terminal_p, contact)
-
-# diode_np_6p0
-connect(diode_np_6p0_terminal_n, contact)
-
-# diode_pn_6p0
-connect(diode_pn_6p0_terminal_p, contact)
-
-# diode_np_6p0_dw
-connect(diode_np_6p0_dw_terminal_n, contact)
-
-# diode_pn_6p0_dw
-connect(diode_pn_6p0_dw_terminal_p, contact)
-
-# diode_nwp_6p0
-connect(diode_nwp_6p0_terminal_n, nwell)
-connect(diode_nwp_6p0_terminal_p, contact)
-
-# diode_dnwpw
-connect(diode_dnwpw_terminal_p, contact)
-
-# diode_dnwps
-connect(diode_dnwps_terminal_p, contact)
-
-
-
-#================================
-# ---- RESISTOR CONNECTIONS -----
-#================================
-
-logger.info('Starting LVS RESISTOR CONNECTIONS')
-
-connect(nplus_cont, contact)
-connect(pplus_cont, contact)
-connect(pplus_dw_cont, contact)
+# %include diode_connection.lvs
#================================
# ---- Varactor CONNECTIONS -----
#================================
-connect(pn_varactor_1p8_tp ,contact)
-connect(pn_varactor_1p8_dw_tp ,contact)
-connect(pn_varactor_6p0_tp ,contact)
-connect(pn_varactor_6p0_dw_tp ,contact)
\ No newline at end of file
+# %include varactor_connection.lvs
+
+
+#==================================
+# ------ MIMCAP CONNECTIONS -------
+#==================================
+
+# %include mimcap_connection.lvs
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/diode_connection.lvs b/ULL/klayout/lvs/rule_decks/diode_connection.lvs
new file mode 100644
index 0000000..a8c8769
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/diode_connection.lvs
@@ -0,0 +1,75 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- DIODE CONNECTIONS -------
+#================================
+
+logger.info('Starting LVS DIODE CONNECTIONS')
+
+#================================
+# ---- LV DIODE DERIVATIONS ----
+#================================
+
+# diode_np_1p8
+connect(diode_np_1p8_terminal_n, contact)
+
+# diode_np_1p8_dw
+connect(diode_np_1p8_dw_terminal_n, contact)
+
+# diode_pn_1p8
+connect(diode_pn_1p8_terminal_p, contact)
+
+# diode_pn_1p8_dw
+connect(diode_pn_1p8_dw_terminal_p, contact)
+
+#================================
+# ---- MV DIODE DERIVATIONS ----
+#================================
+
+# diode_np_3p3
+connect(diode_np_3p3_terminal_n, contact)
+
+# diode_pn_3p3
+connect(diode_pn_3p3_terminal_p, contact)
+
+# diode_np_3p3_dw
+connect(diode_np_3p3_dw_terminal_n, contact)
+
+# diode_pn_3p3_dw
+connect(diode_pn_3p3_dw_terminal_p, contact)
+
+# diode_np_6p0
+connect(diode_np_6p0_terminal_n, contact)
+
+# diode_pn_6p0
+connect(diode_pn_6p0_terminal_p, contact)
+
+# diode_np_6p0_dw
+connect(diode_np_6p0_dw_terminal_n, contact)
+
+# diode_pn_6p0_dw
+connect(diode_pn_6p0_dw_terminal_p, contact)
+
+# diode_nwp_6p0
+connect(diode_nwp_6p0_terminal_n, nwell)
+connect(diode_nwp_6p0_terminal_p, contact)
+
+# diode_dnwpw
+connect(diode_dnwpw_terminal_p, contact)
+
+# diode_dnwps
+connect(diode_dnwps_terminal_p, contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/general_derivations.lvs b/ULL/klayout/lvs/rule_decks/general_derivations.lvs
index 8e1dabe..d365520 100644
--- a/ULL/klayout/lvs/rule_decks/general_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/general_derivations.lvs
@@ -41,3 +41,22 @@
nwell_con = nwell.not(res_mk)
lvpwell_con = lvpwell.not(res_mk)
poly2_con = poly2.not(res_mk)
+
+
+# Splitting vias into cap-vias(connected to fusetop), ncap-vias(connected to metals)
+if METAL_LEVEL != '2LM'
+ via2_ncap = via2.not(fusetop)
+ via2_cap = via2.and(fusetop)
+ if METAL_LEVEL != '3LM'
+ via3_ncap = via3.not(fusetop)
+ via3_cap = via3.and(fusetop)
+ if METAL_LEVEL != '4LM'
+ via4_ncap = via4.not(fusetop)
+ via4_cap = via4.and(fusetop)
+ if METAL_LEVEL != '5LM'
+ via5_ncap = via5.not(fusetop)
+ via5_cap = via5.and(fusetop)
+ end
+ end
+ end
+ end
diff --git a/ULL/klayout/lvs/rule_decks/mimcap_connection.lvs b/ULL/klayout/lvs/rule_decks/mimcap_connection.lvs
new file mode 100644
index 0000000..886bdc9
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/mimcap_connection.lvs
@@ -0,0 +1,31 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MIMCAP CONNECTIONS -------
+#==================================
+
+logger.info('Starting LVS MIMCAP CONNECTIONS')
+
+case MIM_OPTION
+when 'A'
+ connect(metal2, mim_virtual)
+ connect(fuse_cap, via2)
+
+when 'B'
+ connect(topmin1_metal, mimtm_virtual)
+ connect(fuse_cap, top_via)
+end
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/mimcap_derivations.lvs b/ULL/klayout/lvs/rule_decks/mimcap_derivations.lvs
new file mode 100644
index 0000000..a5e7570
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/mimcap_derivations.lvs
@@ -0,0 +1,37 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MIMCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting MIMCAP DERIVATIONS')
+
+# mim option A
+mim_virtual = fusetop.sized(1.06.um).and(metal2.interacting(fusetop)).not(lvs_rf)
+metal2_ncap = metal2.not(mim_virtual)
+fuse_cap = fusetop.interacting(cap_mk).interacting(mim_l_mk).not(lvs_rf)
+
+# mim_option B
+mimtm_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop)).not(lvs_rf)
+
+if METAL_LEVEL != '2LM'
+ metal3_ncap = metal3.not(mimtm_virtual)
+ if METAL_LEVEL != '3LM'
+ metal4_ncap = metal4.not(mimtm_virtual)
+ metal5_ncap = metal5.not(mimtm_virtual) if METAL_LEVEL != '4LM'
+ end
+end
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/mimcap_extraction.lvs b/ULL/klayout/lvs/rule_decks/mimcap_extraction.lvs
new file mode 100644
index 0000000..54906ab
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/mimcap_extraction.lvs
@@ -0,0 +1,153 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- MIMCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting MIMCAP EXTRACTION')
+
+case MIM_OPTION
+when 'A'
+
+ case MIM_CAP
+ when '0.85'
+ # mim_0p85fF capacitor
+ logger.info('Extracting mim_0p85fF device')
+ extract_devices(capacitor('mim_0p85fF_m2m3_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('mim_0p85fF_m2m3_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # mim_1p0fF capacitor
+ logger.info('Extracting mim_1p0fF device')
+ extract_devices(capacitor('mim_1p0fF_m2m3_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p0fF_m2m3_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # mim_1p5fF capacitor
+ logger.info('Extracting mim_1p5fF device')
+ extract_devices(capacitor('mim_1p5fF_m2m3_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p5fF_m2m3_noshield', 'C', relative: 0.25)
+
+ when '2'
+ # mim_2p0fF capacitor
+ logger.info('Extracting mim_2p0fF device')
+ extract_devices(capacitor('mim_2p0fF_m2m3_noshield', 2.0e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('mim_2p0fF_m2m3_noshield', 'C', relative: 0.25)
+
+ end
+
+when 'B'
+ case METAL_LEVEL
+ when '6LM'
+
+ case MIM_CAP
+ when '0.85'
+ # mim_0p85fF_tm capacitor
+ logger.info('Extracting mim_0p85fF_tm device')
+ extract_devices(capacitor('mim_0p85fF_tm_m5m6_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_0p85fF_tm_m5m6_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # mim_1p0fF_tm capacitor
+ logger.info('Extracting mim_1p0fF_tm device')
+ extract_devices(capacitor('mim_1p0fF_tm_m5m6_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p0fF_tm_m5m6_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # mim_1p5fF_tm capacitor
+ logger.info('Extracting mim_1p5fF_tm device')
+ extract_devices(capacitor('mim_1p5fF_tm_m5m6_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p5fF_tm_m5m6_noshield', 'C', relative: 0.25)
+
+ when '2'
+ # mim_2p0fF_tm capacitor
+ logger.info('Extracting mim_2p0fF_tm device')
+ extract_devices(capacitor('mim_2p0fF_tm_m5m6_noshield', 2.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_2p0fF_tm_m5m6_noshield', 'C', relative: 0.25)
+ end
+
+ when '5LM'
+ case MIM_CAP
+ when '0.85'
+ # mim_0p85fF_tm capacitor
+ logger.info('Extracting mim_0p85fF_tm device')
+ extract_devices(capacitor('mim_0p85fF_tm_m4m5_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_0p85fF_tm_m4m5_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # mim_1p0fF_tm capacitor
+ logger.info('Extracting mim_1p0fF_tm device')
+ extract_devices(capacitor('mim_1p0fF_tm_m4m5_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p0fF_tm_m4m5_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # mim_1p5fF_tm capacitor
+ logger.info('Extracting mim_1p5fF_tm device')
+ extract_devices(capacitor('mim_1p5fF_tm_m4m5_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p5fF_tm_m4m5_noshield', 'C', relative: 0.25)
+
+ when '2'
+ # mim_2p0fF_tm capacitor
+ logger.info('Extracting mim_2p0fF_tm device')
+ extract_devices(capacitor('mim_2p0fF_tm_m4m5_noshield', 2.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_2p0fF_tm_m4m5_noshield', 'C', relative: 0.25)
+ end
+
+ when '4LM'
+ case MIM_CAP
+ when '0.85'
+ # mim_0p85fF_tm capacitor
+ logger.info('Extracting mim_0p85fF_tm device')
+ extract_devices(capacitor('mim_0p85fF_tm_m3m4_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_0p85fF_tm_m3m4_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # mim_1p0fF_tm capacitor
+ logger.info('Extracting mim_1p0fF_tm device')
+ extract_devices(capacitor('mim_1p0fF_tm_m3m4_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p0fF_tm_m3m4_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # mim_1p5fF_tm capacitor
+ logger.info('Extracting mim_1p5fF_tm device')
+ extract_devices(capacitor('mim_1p5fF_tm_m3m4_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p5fF_tm_m3m4_noshield', 'C', relative: 0.25)
+
+ when '2'
+ # mim_2p0fF_tm capacitor
+ logger.info('Extracting mim_2p0fF_tm device')
+ extract_devices(capacitor('mim_2p0fF_tm_m3m4_noshield', 2.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_2p0fF_tm_m3m4_noshield', 'C', relative: 0.25)
+ end
+ end
+end
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/mos_connection.lvs b/ULL/klayout/lvs/rule_decks/mos_connection.lvs
new file mode 100644
index 0000000..862cda2
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/mos_connection.lvs
@@ -0,0 +1,22 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- MOSFET CONNECTIONS ------
+#================================
+logger.info('Starting LVS MOSFET CONNECTIONS')
+
+connect(psd_dw, contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/res_connection.lvs b/ULL/klayout/lvs/rule_decks/res_connection.lvs
new file mode 100644
index 0000000..8f716d5
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/res_connection.lvs
@@ -0,0 +1,25 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- RESISTOR CONNECTIONS -----
+#================================
+
+logger.info('Starting LVS RESISTOR CONNECTIONS')
+
+connect(nplus_cont, contact)
+connect(pplus_cont, contact)
+connect(pplus_dw_cont, contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/varactor_connection.lvs b/ULL/klayout/lvs/rule_decks/varactor_connection.lvs
new file mode 100644
index 0000000..68f3f08
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/varactor_connection.lvs
@@ -0,0 +1,24 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor CONNECTIONS -----
+#================================
+
+connect(pn_varactor_1p8_tp ,contact)
+connect(pn_varactor_1p8_dw_tp ,contact)
+connect(pn_varactor_6p0_tp ,contact)
+connect(pn_varactor_6p0_dw_tp ,contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.gds
new file mode 100644
index 0000000..fac56eb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.yaml
new file mode 100644
index 0000000..060a3c2
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+mim_0p85fF_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "0.85"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.gds
new file mode 100644
index 0000000..fd7f31e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.yaml
new file mode 100644
index 0000000..64335cc
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+mim_0p85fF_tm_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "0.85"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.gds
new file mode 100644
index 0000000..c1fb759
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.yaml
new file mode 100644
index 0000000..35532ba
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+mim_0p85fF_tm_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "0.85"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.gds
new file mode 100644
index 0000000..7cfaae6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.yaml
new file mode 100644
index 0000000..0c52e94
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+mim_0p85fF_tm_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "0.85"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.gds
new file mode 100644
index 0000000..cdcface
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.yaml
new file mode 100644
index 0000000..a3a5244
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p0fF_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "1"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.gds
new file mode 100644
index 0000000..72c62bd
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.yaml
new file mode 100644
index 0000000..00b0fe1
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p0fF_tm_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "1"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.gds
new file mode 100644
index 0000000..7049ddb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.yaml
new file mode 100644
index 0000000..d835d95
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p0fF_tm_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "1"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.gds
new file mode 100644
index 0000000..453c75e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.yaml
new file mode 100644
index 0000000..5825807
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p0fF_tm_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "1"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.gds
new file mode 100644
index 0000000..6d25b72
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.yaml
new file mode 100644
index 0000000..5d0b626
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.yaml
@@ -0,0 +1,5 @@
+mim_1p5fF_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "1.5"
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.gds
new file mode 100644
index 0000000..f85ae78
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.yaml
new file mode 100644
index 0000000..7028012
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p5fF_tm_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "1.5"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.gds
new file mode 100644
index 0000000..6d72e9c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.yaml
new file mode 100644
index 0000000..3426e30
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p5fF_tm_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "1.5"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.gds
new file mode 100644
index 0000000..6c53293
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.yaml
new file mode 100644
index 0000000..e08c7dc
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p5fF_tm_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "1.5"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.gds
new file mode 100644
index 0000000..020b0e6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.yaml
new file mode 100644
index 0000000..f9f80c1
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+mim_2p0fF_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "2"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.gds
new file mode 100644
index 0000000..2e671ef
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.yaml
new file mode 100644
index 0000000..2b0309b
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+mim_2p0fF_tm_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "2"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.gds
new file mode 100644
index 0000000..b0291da
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.yaml
new file mode 100644
index 0000000..ab478fe
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+mim_2p0fF_tm_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "2"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.gds
new file mode 100644
index 0000000..7d359f1
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.yaml
new file mode 100644
index 0000000..a7d59a4
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+mim_2p0fF_tm_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "2"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_m2m3_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_m2m3_noshield.cdl
new file mode 100644
index 0000000..808d77a
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_0p85fF_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:39:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_0p85fF_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_0p85fF_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT mim_0p85fF_m2m3_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m3m4_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m3m4_noshield.cdl
new file mode 100644
index 0000000..84dcbd3
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_0p85fF_tm_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_0p85fF_tm_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_0p85fF_tm_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m4m5_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m4m5_noshield.cdl
new file mode 100644
index 0000000..2dbf6ae
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_0p85fF_tm_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_0p85fF_tm_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_0p85fF_tm_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m5m6_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m5m6_noshield.cdl
new file mode 100644
index 0000000..eeb3db6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_0p85fF_tm_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_0p85fF_tm_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_0p85fF_tm_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_m2m3_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_m2m3_noshield.cdl
new file mode 100644
index 0000000..e83fa1f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p0fF_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:39:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p0fF_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p0fF_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT mim_1p0fF_m2m3_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m3m4_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m3m4_noshield.cdl
new file mode 100644
index 0000000..a4a4ba7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p0fF_tm_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p0fF_tm_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p0fF_tm_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m4m5_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m4m5_noshield.cdl
new file mode 100644
index 0000000..6e0ae99
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p0fF_tm_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p0fF_tm_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p0fF_tm_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m5m6_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m5m6_noshield.cdl
new file mode 100644
index 0000000..eda163d
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p0fF_tm_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p0fF_tm_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p0fF_tm_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_m2m3_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_m2m3_noshield.cdl
new file mode 100644
index 0000000..2fceba7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_m2m3_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p5fF_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:42:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p5fF_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p5fF_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT mim_1p5fF_m2m3_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m3m4_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m3m4_noshield.cdl
new file mode 100644
index 0000000..34731c2
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m3m4_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p5fF_tm_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p5fF_tm_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p5fF_tm_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m4m5_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m4m5_noshield.cdl
new file mode 100644
index 0000000..1ceddc8
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m4m5_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p5fF_tm_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p5fF_tm_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p5fF_tm_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m5m6_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m5m6_noshield.cdl
new file mode 100644
index 0000000..9a6bad7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m5m6_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p5fF_tm_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p5fF_tm_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p5fF_tm_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_m2m3_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_m2m3_noshield.cdl
new file mode 100644
index 0000000..0223463
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_2p0fF_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:53:54 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_2p0fF_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_2p0fF_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT mim_2p0fF_m2m3_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m3m4_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m3m4_noshield.cdl
new file mode 100644
index 0000000..0cb1eb6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_2p0fF_tm_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_2p0fF_tm_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_2p0fF_tm_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m4m5_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m4m5_noshield.cdl
new file mode 100644
index 0000000..0dc8b9b
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_2p0fF_tm_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_2p0fF_tm_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_2p0fF_tm_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m5m6_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m5m6_noshield.cdl
new file mode 100644
index 0000000..898b421
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_2p0fF_tm_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_2p0fF_tm_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_2p0fF_tm_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
