Layer Name,Purpose,GDS #,Data type,MCU,BCDLite,ULL,IC
COMP,Diffusion for device and interconnect,22,0,yes,yes,yes,yes
DNWELL,Deep Nwell,12,0,yes,yes,yes,yes
Nwell,Nwell implant,21,0,yes,yes,yes,yes
LVPWELL,Pwell implant,204,0,yes,yes,yes,
HVNDDD,LDNMOS drain extension,202,0,,yes,,
HVPDDD,LDPMOS drain extension,197,0,,yes,,
Dualgate,6V Gate Oxide,55,0,yes,,yes,yes
DV2,5/6V Gate Oxide,144,0,,,yes,
DV2_D,Medium Gate Oxide,144,1,,yes,,
OTPGate,OTP Memory Thick GOX area in a dual voltage process,225,0,,,,yes
Poly2,POLY2 gate & interconnect,30,0,yes,yes,yes,yes
Nplus,Nplus Implant,32,0,yes,yes,yes,yes
Pplus,Pplus Implant,31,0,yes,yes,yes,yes
SAB,Unsalicided poly & active regions,49,0,yes,yes,yes,yes
ESD,ESD Implant (Optional),24,0,yes,yes,yes,yes
Contact,Metal1 to Active or Poly2 contact,33,0,yes,yes,yes,yes
Metal1,Metal1 interconnect,34,0,yes,yes,yes,yes
Via1,Metal2 to Metal1 contact,35,0,yes,yes,yes,yes
Metal2,Metal2 interconnect,36,0,yes,yes,yes,yes
Via2,Metal3 to Metal2 contact,38,0,yes,yes,yes,yes
Metal3,Metal3 interconnect,42,0,yes,yes,yes,yes
Via3,Metal4 to Metal3 contact,40,0,yes,yes,yes,yes
Metal4,Metal4 interconnect,46,0,yes,yes,yes,yes
Via4,Metal5 to Metal4 contact,41,0,yes,yes,yes,yes
Metal5,Metal5 interconnect,81,0,yes,yes,yes,yes
Via5,Metal 6 to Metal5 contact,82,0,yes,yes,yes,yes
MetalTop,MetalTop interconnect,53,0,yes,yes,yes,yes
Pad,Bond pad opening,37,0,yes,yes,yes,yes
Resistor,High sheet rho P-poly resistor (Optional),62,0,yes,yes,yes,yes
PISCAP,Poly2 to substrate capacitors (Optional),120,0,,yes,yes,yes
FHRES,Free high sheet rho P-POLY2 resistor,227,0,yes,yes,yes,
FuseTop,Top plate of MIM capacitors (Optional),75,0,yes,yes,yes,yes
FuseTop2,Top plate of 2 MiM which beneath normal MIM,215,0,,,,yes
FuseWindow_D,Metal Fuse window (Optional),96,1,yes,yes,yes,
POLYFUSE,POLY FUSE window (Optional),220,0,yes,yes,yes,
MVSD,Define LDNMOS Drain,210,0,yes,yes,,
MVPSD,Define LDPMOS Drain,11,39,yes,yes,,
NAT,N-channel native VT mark layer,5,0,yes,yes,yes,yes
LVT,N- and P- channel low-vt transistors,87,0,,,,yes
COMP_Dummy,COMP Dummy fill,22,4,yes,yes,yes,yes
Poly2_Dummy,Poly2 Dummy Fill,30,4,yes,yes,yes,yes
Metal1_Dummy,Metal1 Dummy Fill,34,4,yes,yes,yes,yes
Metal2_Dummy,Metal2 Dummy Fill,36,4,yes,yes,yes,yes
Metal3_Dummy,Metal3 Dummy Fill,42,4,yes,yes,yes,yes
Metal4_Dummy,Metal4 Dummy Fill,46,4,yes,yes,yes,yes
Metal5_Dummy,Metal5 Dummy Fill,81,4,yes,yes,yes,yes
MetalTop_Dummy,MetalTop Dummy Fill,53,4,yes,yes,yes,yes
COMP_Label,LABEL drawn at active layer,22,10,yes,yes,,yes
Poly2_Label,LABEL drawn at poly2 layer,30,10,yes,yes,,yes
Metal1_Label,LABEL drawn at Metal1 layer,34,10,yes,yes,yes,yes
Metal2_Label,LABEL drawn at Metal2 layer,36,10,yes,yes,yes,yes
Metal3_Label,LABEL drawn at Metal3 layer,42,10,yes,yes,yes,yes
Metal4_Label,LABEL drawn at Metal4 layer,46,10,yes,yes,yes,yes
Metal5_Label,LABEL drawn at Metal5 layer,81,10,yes,yes,yes,yes
MetalTop_Label,LABEL drawn at MetalTop layer,53,10,yes,yes,yes,yes
MetalRDL_Label,LABEL drawn at MetalRDL layer,171,10,,,,yes
Pad_Label,LABEL drawn at Pad layer,37,10,,,,yes
Metal1_Slot,Metal1 Slot (used to create slots in metal1),34,3,yes,yes,,
Metal2_Slot,Metal2 Slot (used to create slots in metal2),36,3,yes,yes,,
Metal3_Slot,Metal3 Slot (used to create slots in metal3),42,3,yes,yes,,
Metal4_Slot,Metal4 Slot (used to create slots in metal4),46,3,yes,yes,,
Metal5_Slot,Metal5 Slot (used to create slots in metal5),81,3,yes,yes,,
MetalTop_Slot,MetalTop Slot (used to create slots in metal top),53,3,yes,yes,,
UBMPPeri,Direct Bumping option using peripheral printing,183,0,yes,yes,yes,yes
UBMPPeri_Label,LABEL drawn at UBMPPeri,29,39,,yes,,
UBMPArray,Direct Bumping option using Array printing,184,0,yes,yes,yes,yes
UBMPArray_Label,LABEL drawn at UBMPArray,33,39,,yes,yes,
UBMEPlate,Direct Bumping option using Electroplating,185,0,yes,yes,yes,yes
UBMEPlate_Label,LABEL drawn at UBMEPlate,28,39,,yes,,
Cu_PPI,"Cu Post Passivation Interconnect Metal
Routing in between 2 polymer layers",25,39,,yes,,
Cu_PPI_BLK,Place & Route CU_PPI Blockage,30,39,,yes,,
Cu_PPI_Dummy,Cu_PPI Dummy fill,31,39,,yes,,
Cu_PPI_Label,LABEL drawn at Cu_PPI layer,32,39,,yes,,
PM1_PPI,Polyimide1 Opening for PPI,26,39,,yes,,
PM2_PPI,Polyimide2 Opening for PPI,27,39,,yes,,
PM1_BOP,Polyimide1 Opening for Bump on Pad (BOP),35,39,,yes,,
Schottky_diode,Define Schottky diode area,241,0,yes,,,
ZENER,ZENER diode implant,178,0,yes,yes,,
DNI,DDD implant for DDD MV NMOS (nmos_ddd),78,0,,yes,,
PWHV,High voltage Pwell for Isolated MV LDNMOS,44,0,,yes,,
METAL_SHIELD,For customer shielding purpose,35,28,,yes,,
METAL_SHIELD_Slot,METAL_SHIELD Slot (used to create slots in METAL_SHIELD),78,39,,yes,,
METAL_SHIELD_Dummy,METAL_SHIELD Dummy Fill,79,39,,yes,,
METAL_SHIELD_Label,LABEL drawn at METAL_SHIELD layer,68,39,,yes,,
METAL_SHIELD_VIA,Via for METAL_SHIELD,36,28,,yes,,
METAL_SHIELD_VIA_Label,Label drawn at METAL_SHIELD_VIA_Label,69,39,,yes,,
METAL_SHIELD_BLK,Place & Route METAL_SHIELD Blockage,110,19,,yes,,
TANRES,TaN Resistor,222,0,,yes,,
TANRES_MK,TaN Resistor Mark,56,17,,yes,,
TANRES_Label,Label drawn at TaN Resistor,222,10,,yes,,
TANRES_L_MK,Identification of length for TaN Resistor,72,17,,yes,,
PRES,Marking layer for narrow width HR poly resistor,12,201,,yes,,
CAP_MK_TYPE2,Marking layer for sub size MIM(<5x5um2),75,17,,yes,,
MOS_MK_TYPE4,4.2V hybrid device marking layer,73,17,,yes,,
MOS_SOURCE_TYPE1,4.2V hybrid device source side marking layer,154,51,,yes,,
RES_MK,Resistor Mark,110,5,yes,yes,yes,yes
OPC_drc,Marking layer for OPC design rule check,124,5,yes,yes,yes,
NDMY,Dummy Active Exclude Mark layer,111,5,yes,yes,yes,yes
PMNDMY,Dummy Poly & Metal Exclude Mark,152,5,yes,yes,yes,
V5_XTOR,Define 5V Transistor Marking Layer,112,1,yes,yes,yes,
CAP_MK,MIM Capacitor Marking layer,117,5,yes,yes,yes,
MOS_CAP_MK,MOS capacitor LVS marking,166,5,yes,yes,yes,
IND_MK,Inductor Mark,151,5,yes,yes,,yes
LVS_CAP,Capacitor marking layer (for LVS & DRC),117,5,,,,yes
ViaRDL,Via Connecting MetalTop & MetalRDL,170,0,,,,yes
MetalRDL,Metal connected to the Al Cap,171,0,,,,yes
DIODE_MK,Diode Mark,115,5,yes,yes,yes,yes
DRC_BJT,BJT marking for DRC,127,5,yes,yes,yes,
LVS_BJT,BJT Mark,118,5,yes,yes,yes,yes
MIM_L_MK,"Min length marking layer for MIM Capacitor
(Identification of length for MIM cap)",117,10,yes,yes,yes,
35V_MK,Marking layer for 35V LDMOS device,25,17,,yes,,
LVS_35V,LVS marking layer for 35V LDMOS unit device (2 fingers),27,17,,yes,,
ELMD_MK,Marking layer for Extended LDD MV NMOS (nmos_eldd) Drain,18,17,,yes,,
ELMD2_MK,Marking layer for Extended LDD MOS(ELxMOS) Drain (Type2),19,17,,yes,,
Schottky_Diode,Marking layer for Schottky diode,241,0,,yes,,
MOS_MK_TYPE1,Marking layer for sub-nominal 5V PMOS,151,51,,yes,,
ESD_HBM_MK,Marking layer for ESD device,37,17,,yes,,
LVS_PSUB2,Drawing to separate substrate,23,5,,yes,,
MV_WELL_MK,Well voltage marking layer for 5/6V well bias,57,17,,yes,,
MHV_WELL_MK,Well voltage marking layer for 10V well bias,58,17,,yes,,
HV_WELL_MK,Well voltage marking layer for 30V well bias,59,17,,yes,,
MHV_WELL_MK_TYPE1,Marker for DNW biasing of > 14V and < 30V,96,17,,yes,,
LVS_DONUT,Donut shape SAB marker,55,17,,yes,,
RES_MK_TYPE1,Marking layer for 2K Poly Resistor,26,17,,yes,,yes
CAP_MK_TYPE1,Marking layer for 1.5fF/um2 MIM capacitor,62,17,,yes,,
SWFET_MK,Marking layer for MV switch devices,69,17,,yes,,
Latchup_MK,Marking layer for I/O latch-up rule check,137,5,yes,yes,yes,
GUARD_RING_MK,Marking Layer for Scribe Line Guard Ring,167,5,yes,yes,yes,yes
OTP_MK,To define OTP area with Marking layer,173,5,yes,yes,yes,
MTPMARK,Multi Time Program Memory cell marking,122,5,yes,yes,yes,
NEO_EE_MK,NeoEE OTP area with Marking layer,88,17,yes,,,
SramCore,SRAM Mark,108,5,yes,yes,yes,
SramCore,SRAM Mark,"101
102
103
105
108",5,,,,yes
LVS_RF,RF LVS Mark,100,5,yes,yes,yes,yes
LVS_Drain,RF Drain LVS Mark,100,7,yes,yes,yes,yes
VCID,IP tagging layer using Texttype 63,63,,,,,
HVPOLYRS,High Voltage Poly2 Resistor in HV area Marking layer,123,5,yes,yes,yes,
LVS_IO,IO LVS Mark,119,5,yes,yes,yes,yes
PROBE_MK,Marking layer for probe pad,13,17,yes,yes,,yes
ESD_MK,Marking layer on ESD protection device,24,5,yes,yes,,
LVS_Source,"Source LVS/DRC marking Layer
(Marking layer for symmetrical LDMOS source
and ESD transistor source
Marking layer for eFuse anode)",100,8,yes,yes,,yes
WELL_DIODE_MK,"Marking layer for Nwell/Psub, LVPwell/Dnwell,
 DNwell/Psub diode
Marking layer for Nwell/PWHV diode",153,51,yes,yes,,yes
LDMOS_XTOR,LDMOS device mark layer,226,0,yes,yes,,
PLFUSE,Marking layer for eFUSE Link,125,5,yes,yes,,yes
EFUSE_MK,Marking layer for whole eFUSE Element,80,5,yes,yes,,yes
MOM_MK,Marking layer for Alternating Polarity MOM,51,17,,yes,,
MOM_M1_Mk,Marking layer for APMOM M1 fingers,40,17,,yes,,
MOM_M2_Mk,Marking layer for APMOM M2 fingers,41,17,,yes,,
MOM_M3_Mk,Marking layer for APMOM M3 fingers,42,17,,yes,,
MOM_M4_Mk,Marking layer for APMOM M4 fingers,43,17,,yes,,
MOM_M5_Mk,Marking layer for APMOM M5 fingers,44,17,,yes,,
MCELL_FEOL_MK,Marking layer to define YMTP Mcell Implant region,11,17,yes,,,yes
YMTP_MK,Marking layer to define YMTP Cell and exclude NLDD region,86,17,yes,,,
DEV_WF_MK,LVS marking layer for Fab special purposes layout,128,17,yes,,,
Metal1_BLK,Place & Route Metal1 Blockage,34,5,yes,yes,yes,yes
Metal2_BLK,Place & Route Metal2 Blockage,36,5,yes,yes,yes,yes
Metal3_BLK,Place & Route Metal3 Blockage,42,5,yes,yes,yes,yes
Metal4_BLK,Place & Route Metal4 Blockage,46,5,yes,yes,yes,yes
Metal5_BLK,Place & Route Metal5 Blockage,81,5,yes,yes,yes,yes
MetalT_BLK,Place & Route MetalTop Blockage,53,5,yes,yes,yes,yes
PR_bndry,"PR Boundary for cell, block or chip",0,0,yes,yes,yes,yes
MDIODE,MDiode Mark,116,5,yes,yes,yes,yes
Metal1_Res,Metal 1 Resistor,110,11,yes,,,
Metal2_Res,Metal 2 Resistor,110,12,yes,,,
Metal3_Res,Metal 3 Resistor,110,13,yes,,,
Metal4_Res,Metal 4 Resistor,110,14,yes,,,
Metal5_Res,Metal 5 Resistor,110,15,yes,,,
Metal6_Res,Metal6 Resistor,110,16,yes,,,
Border,Border,63,0,yes,yes,yes,