################################################################################################
# Copyright 2022 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the 'License');
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an 'AS IS' BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################################

if FEOL

    #================================================
    #--------------------dualgate2_d-----------------
    #================================================


    # Rule DV2.2: Min. dualgate2_d Space. Merge if Space is less than this design rule. is 0.44µm
    logger.info('Executing rule DV2.2')
    dv2_l1  = dualgate2_d.space(0.44.um, euclidian).polygons(0.001)
    dv2_l1.output('DV2.2', 'DV2.2 : Min. dualgate2_d Space. Merge if Space is less than this design rule. : 0.44µm')
    dv2_l1.forget

    # Rule DV2.3: Min. dualgate2_d to COMP space [unrelated]. is 0.24µm
    logger.info('Executing rule DV2.3')
    dv3_l1  = dualgate2_d.separation(comp.outside(dualgate2_d), 0.24.um, euclidian).polygons(0.001)
    dv3_l1.output('DV2.3', 'DV2.3 : Min. dualgate2_d to COMP space [unrelated]. : 0.24µm')
    dv3_l1.forget


    # Rule DV2.5: Min. dualgate2_d width. is 0.7µm
    logger.info('Executing rule DV2.5')
    dv5_l1  = dualgate2_d.width(0.7.um, euclidian).polygons(0.001)
    dv5_l1.output('DV2.5', 'DV2.5 : Min. dualgate2_d width. : 0.7µm')
    dv5_l1.forget

    comp_dv = comp.not(pcomp.outside(nwell))
    # Rule DV2.6: Min. dualgate2_d enclose COMP (except substrate tap). is 0.24µm
    logger.info('Executing rule DV2.6')
    dv6_l1 = dualgate2_d.enclosing(comp_dv, 0.24.um, euclidian).polygons(0.001)
    dv6_l2 = comp_dv.not_outside(dualgate2_d).not(dualgate2_d)
    dv6_l  = dv6_l1.or(dv6_l2)
    dv6_l.output('DV2.6', 'DV2.6 : Min. dualgate2_d enclose COMP (except substrate tap). : 0.24µm')
    dv6_l1.forget
    dv6_l2.forget
    dv6_l.forget

    # Rule DV2.7: COMP (except substrate tap) can not be partially overlapped by dualgate2_d.
    logger.info('Executing rule DV2.7')
    dv7_l1 = dualgate2_d.not_outside(comp_dv).not(dualgate2_d.covering(comp_dv))
    dv7_l1.output('DV2.7', 'DV2.7 : COMP (except substrate tap) can not be partially overlapped by dualgate2_d.')
    dv7_l1.forget

    comp_dv.forget

    # Rule DV2.8: Min dualgate2_d enclose gate (Poly2 AND COMP). is 0.4µm
    logger.info('Executing rule DV2.8')
    dv8_l1 = dualgate2_d.enclosing(tgate, 0.4.um, euclidian).polygons(0.001)
    dv8_l2 = tgate.not_outside(dualgate2_d).not(dualgate2_d)
    dv8_l  = dv8_l1.or(dv8_l2)
    dv8_l.output('DV2.8', 'DV2.8 : Min dualgate2_d enclose gate (Poly2 AND COMP). : 0.4µm')
    dv8_l1.forget
    dv8_l2.forget
    dv8_l.forget
        
end #FEOL