Adding PISCAP derivations & extraction & testcases
diff --git a/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs b/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
new file mode 100644
index 0000000..1ace25a
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
@@ -0,0 +1,41 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ PISCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting PISCAP DERIVATIONS')
+
+piscap_exclude_layers = mos_cap_mk.or(sab).or(esd).or(polyfuse).or(cap_mk).or(diode_mk).or(nat)
+ .or(v5_xtor).or(drc_bjt).or(lvs_bjt).or(fhres)
+ .or(fusewindow_d).or(lvs_rf).or(fusetop).or(resistor)
+
+# pis_1p8 (1.8V PIS capacitor (outside DNWELL))
+pis_1p8_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).not(dnwell)
+ .not(dualgate).not(dv2).not(piscap_exclude_layers)
+
+# pis_1p8_dw (1.8V PIS capacitor (inside DNWEL)
+pis_1p8_dw_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).inside(dnwell)
+ .not(dualgate).not(dv2).not(piscap_exclude_layers)
+
+# pis_6p0 (6V PIS capacitor (outside DNWELL))
+pis_6p0_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).not(dnwell)
+ .and(dv2).not(piscap_exclude_layers)
+
+# pis_6p0_dw (6V PIS capacitor (inside DNWEL)
+pis_6p0_dw_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).inside(dnwell)
+ .and(dv2).not(piscap_exclude_layers)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs b/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
new file mode 100644
index 0000000..d24e852
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
@@ -0,0 +1,41 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- PISCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting PISCAP EXTRACTION')
+
+# pis_1p8 (1.8V PIS capacitor (outside DNWELL))
+logger.info('Extracting pis_1p8 device')
+extract_devices(capacitor('piscap_1p8', 4.4e-15, PisCap),
+ { 'P1' => pis_1p8_gate, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+# pis_1p8_dw (1.8V PIS capacitor (inside DNWEL)
+logger.info('Extracting pis_1p8_dw device')
+extract_devices(capacitor('piscap_1p8_dw', 4.4e-15, PisCap),
+ { 'P1' => pis_1p8_dw_gate, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
+
+# pis_6p0 (6V PIS capacitor (outside DNWELL))
+logger.info('Extracting pis_6p0 device')
+extract_devices(capacitor('piscap_6p0', 4.4e-15, PisCap),
+ { 'P1' => pis_6p0_gate, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+# pis_6p0_dw (6V PIS capacitor (inside DNWEL)
+logger.info('Extracting pis_6p0_dw device')
+extract_devices(capacitor('piscap_6p0_dw', 4.4e-15, PisCap),
+ { 'P1' => pis_6p0_dw_gate, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
\ No newline at end of file
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds
new file mode 100644
index 0000000..d6a4e5f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds
new file mode 100644
index 0000000..26bb5ed
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds
new file mode 100644
index 0000000..c91e63c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds
new file mode 100644
index 0000000..1638d1c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl
new file mode 100644
index 0000000..811a4ce
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: piscap_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: piscap_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT piscap_1p8 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_1p8 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_1p8 m=1 l=5.88u w=5u
+.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
new file mode 100644
index 0000000..88262cb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
@@ -0,0 +1,34 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: piscap_1p8_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: piscap_1p8_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT piscap_1p8_dw I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_1p8_dw m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_1p8_dw m=1 l=5.88u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl
new file mode 100644
index 0000000..a8bc9a5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: piscap_6p0
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: piscap_6p0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT piscap_6p0 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_6p0 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_6p0 m=1 l=5.88u w=5u
+.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl
new file mode 100644
index 0000000..ad8c71e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: piscap_6p0_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: piscap_6p0_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT piscap_6p0_dw I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_6p0_dw m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_6p0_dw m=1 l=5.88u w=5u
+.ENDS
