1.0 Purpose
===========

This document provides topological layout rules to generate masks for 0.18μm 1.8V/3.3V/6V Triple Gate
Oxide High Voltage CMOS process. [The corresponding process ID for 1.8V/3.3V/6V is x-Vxxxx-xxx-
183360-xxx-xxx where 183360 stand for CMOS device with 1.8/3.3/6V operating voltage.]