Merge pull request #119 from mabrains/piscap_bcdlite
Adding PISCAP devices for GF180BCDLite [Tested]
diff --git a/BCDLite/klayout/lvs/gf180BCDLite.lvs b/BCDLite/klayout/lvs/gf180BCDLite.lvs
index 7aa8367..e489b67 100644
--- a/BCDLite/klayout/lvs/gf180BCDLite.lvs
+++ b/BCDLite/klayout/lvs/gf180BCDLite.lvs
@@ -271,6 +271,12 @@
# %include rule_decks/varactor_derivations.lvs
+#==================================
+# ------ PISCAP DERIVATIONS -------
+#==================================
+
+# %include rule_decks/piscap_derivations.lvs
+
#================================================
#------------ DEVICES CONNECTIVITY --------------
#================================================
@@ -307,6 +313,12 @@
# %include rule_decks/varactor_extraction.lvs
+#=================================
+# ------- PICAP EXTRACTION -------
+#=================================
+
+# %include rule_decks/piscap_extraction.lvs
+
#================================================
#------------- COMPARISON OPTIONS ---------------
#================================================
diff --git a/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs b/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs
index 84b1316..333f1e2 100644
--- a/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs
@@ -167,4 +167,14 @@
enable_parameter("A", true)
enable_parameter("P", true)
end
-end
\ No newline at end of file
+end
+
+# PISCAP device extractor
+class PisCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
+end
diff --git a/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs
new file mode 100644
index 0000000..72dea73
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs
@@ -0,0 +1,58 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ PISCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting PISCAP DERIVATIONS')
+
+piscap_exclude = lvpwell.join(pplus).join(resistor)
+ .join(esd).join(sab).join(dni)
+ .join(pwhv).join(fusewindow_d).join(polyfuse)
+ .join(schottky_diode).join(zener).join(res_mk)
+ .join(diode_mk).join(v5_xtor).join(drc_bjt)
+ .join(nat).join(fhres).join(mos_cap_mk)
+ .join(mvsd).join(mvpsd).join(elmd_mk)
+ .join(elmd2_mk).join(lvs_rf).join(lvs_source)
+ .join(mk_35v).join(well_diode_mk).join(esd_hbm_mk)
+ .join(mos_mk_type1).join(swfet_mk).join(lvs_35v)
+ .join(hvpddd).join(hvpolyrs).join(ldmos_xtor)
+
+ngate_nw = ngate.and(piscap).and(nwell).not(piscap_exclude)
+
+ngate_nw_lv = ngate_nw.not(dualgate2_d)
+ngate_nw_mv = ngate_nw.and(dualgate2_d)
+
+#====================
+# --- PIS 1P8 CAP ---
+#====================
+
+# cap_pis_01v8: Model for 1.8V PIS capacitor (outside DNWELL) [pis_1p8]
+cap_pis_01v8_gate = ngate_nw_lv.not(dnwell)
+
+# cap_pis_01v8_dn: Model for (1.8V PIS capacitor (inside DNWEL) [pis_1p8_dw]
+cap_pis_01v8_dn_gate = ngate_nw_lv.and(dnwell)
+
+#====================
+# --- PIS 6P0 CAP ---
+#====================
+
+# cap_pis_06v0: Model for 6V PIS capacitor (outside DNWELL) [pis_6p0]
+cap_pis_06v0_gate = ngate_nw_mv.not(dnwell)
+
+# cap_pis_06v0_dn: Model for 6V PIS capacitor (inside DNWEL) [pis_6p0_dw]
+cap_pis_06v0_dn_gate = ngate_nw_mv.and(dnwell)
diff --git a/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs
new file mode 100644
index 0000000..16a21aa
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs
@@ -0,0 +1,53 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- PISCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting PISCAP EXTRACTION')
+
+#====================
+# --- PIS 1P8 CAP ---
+#====================
+
+# cap_pis_01v8: Model for 1.8V PIS capacitor (outside DNWELL) [pis_1p8]
+logger.info('Extracting cap_pis_01v8 device')
+extract_devices(capacitor('cap_pis_01v8', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_01v8_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_pis_01v8_dn: Model for (1.8V PIS capacitor (inside DNWEL) [pis_1p8_dw]
+logger.info('Extracting cap_pis_01v8_dn device')
+extract_devices(capacitor('cap_pis_01v8_dn', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_01v8_dn_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+#====================
+# --- PIS 6P0 CAP ---
+#====================
+
+# cap_pis_06v0: Model for 6V PIS capacitor (outside DNWELL) [pis_6p0]
+logger.info('Extracting cap_pis_06v0 device')
+extract_devices(capacitor('cap_pis_06v0', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_06v0_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_pis_06v0_dn: Model for 6V PIS capacitor (inside DNWEL) [pis_6p0_dw]
+logger.info('Extracting cap_pis_06v0_dn device')
+extract_devices(capacitor('cap_pis_06v0_dn', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_06v0_dn_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs
index facb153..abfc448 100644
--- a/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs
@@ -36,12 +36,12 @@
# --- MOS 1P8 VARACTOR ---
#=========================
-connect(cap_var_fet_01v8_terminal_p ,contact)
-connect(cap_var_fet_01v8_dn_terminal_p ,contact)
+connect(cap_var_fet_01v8_gate ,contact)
+connect(cap_var_fet_01v8_dn_gate ,contact)
#=========================
# --- MOS 6P0 VARACTOR ---
#=========================
-connect(cap_var_fet_06v0_terminal_p ,contact)
-connect(cap_var_fet_06v0_dn_terminal_p ,contact)
+connect(cap_var_fet_06v0_gate ,contact)
+connect(cap_var_fet_06v0_dn_gate ,contact)
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
index 280fd40..aff1b79 100644
--- a/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
@@ -73,18 +73,18 @@
#=========================
# cap_var_fet_01v8: Model for 1.8V Scalable MOS-varactor (outside DNWELL) [mos_varactor_1p8]
-cap_var_fet_01v8_terminal_p = ngate_nw_var_lv.not(dnwell)
+cap_var_fet_01v8_gate = ngate_nw_var_lv.not(dnwell)
# cap_var_fet_01v8_dn: Model for 1.8V Scalable MOS-varactor (inside DNWELL) [mos_varactor_1p8_dw]
-cap_var_fet_01v8_dn_terminal_p = ngate_nw_var_lv.and(dnwell)
+cap_var_fet_01v8_dn_gate = ngate_nw_var_lv.and(dnwell)
#=========================
# --- MOS 6P0 VARACTOR ---
#=========================
# cap_var_fet_06v0: Model for 6V Scalable MOS-varactor (outside DNWELL) [mos_varactor_6p0]
-cap_var_fet_06v0_terminal_p = ngate_nw_var_mv.not(dnwell)
+cap_var_fet_06v0_gate = ngate_nw_var_mv.not(dnwell)
# cap_var_fet_06v0_dn: Model for 6V Scalable MOS-varactor (inside DNWELL) [mos_varactor_6p0_dw]
-cap_var_fet_06v0_dn_terminal_p = ngate_nw_var_mv.and(dnwell)
+cap_var_fet_06v0_dn_gate = ngate_nw_var_mv.and(dnwell)
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs
index a52b50e..098d0d9 100644
--- a/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs
@@ -59,13 +59,13 @@
# cap_var_fet_01v8: Model for 1.8V Scalable MOS-varactor (outside DNWELL) [mos_varactor_1p8]
logger.info('Extracting cap_var_fet_01v8')
extract_devices(capacitor('cap_var_fet_01v8', 4.4e-15, VarCap),
- { 'P1' => cap_var_fet_01v8_terminal_p, 'P2' => nwell_con,
+ { 'P1' => cap_var_fet_01v8_gate, 'P2' => nwell_con,
'tA' => poly2_con, 'tB' => ntap })
# cap_var_fet_01v8_dn: Model for 1.8V Scalable MOS-varactor (inside DNWELL) [mos_varactor_1p8_dw]
logger.info('Extracting cap_var_fet_01v8_dn')
extract_devices(capacitor('cap_var_fet_01v8_dn', 4.4e-15, VarCap),
- { 'P1' => cap_var_fet_01v8_dn_terminal_p, 'P2' => dnwell,
+ { 'P1' => cap_var_fet_01v8_dn_gate, 'P2' => dnwell,
'tA' => poly2_con, 'tB' => ntap })
#=========================
@@ -75,11 +75,11 @@
# cap_var_fet_06v0: Model for 6V Scalable MOS-varactor (outside DNWELL) [mos_varactor_6p0]
logger.info('Extracting cap_var_fet_06v0')
extract_devices(capacitor('cap_var_fet_06v0', 4.4e-15, VarCap),
- { 'P1' => cap_var_fet_06v0_terminal_p, 'P2' => nwell_con,
+ { 'P1' => cap_var_fet_06v0_gate, 'P2' => nwell_con,
'tA' => poly2_con, 'tB' => ntap })
# cap_var_fet_06v0_dn: Model for 6V Scalable MOS-varactor (inside DNWELL) [mos_varactor_6p0_dw]
logger.info('Extracting cap_var_fet_06v0_dn')
extract_devices(capacitor('cap_var_fet_06v0_dn', 4.4e-15, VarCap),
- { 'P1' => cap_var_fet_06v0_dn_terminal_p, 'P2' => dnwell,
+ { 'P1' => cap_var_fet_06v0_dn_gate, 'P2' => dnwell,
'tA' => poly2_con, 'tB' => ntap })
diff --git a/BCDLite/klayout/lvs/testing/run_regression.py b/BCDLite/klayout/lvs/testing/run_regression.py
index 40417f2..814058b 100644
--- a/BCDLite/klayout/lvs/testing/run_regression.py
+++ b/BCDLite/klayout/lvs/testing/run_regression.py
@@ -20,7 +20,7 @@
Options:
--help -h Print this help message.
- --device_name=<device_name> Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, ESD, EFUSE).
+ --device_name=<device_name> Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, PISCAP, ESD, EFUSE).
--mp=<num> The number of threads used in run.
--run_name=<run_name> Select your run name.
"""
@@ -519,11 +519,11 @@
)
## selected device
- allowed_devices = ["MOS", "BJT", "DIODE", "RES", "MIMCAP", "MOSCAP", "APMOMCAP", "VARACTOR" , "EFUSE", "ESD"]
+ allowed_devices = ["MOS", "BJT", "DIODE", "RES", "MIMCAP", "MOSCAP", "PISCAP", "APMOMCAP", "VARACTOR" , "EFUSE", "ESD"]
target_device_group = args["--device_name"]
if target_device_group and target_device_group not in allowed_devices:
- logging.error("Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, ESD, EFUSE) only")
+ logging.error("Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, PISCAP, ESD, EFUSE) only")
exit(1)
# Calling main function
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds
new file mode 100644
index 0000000..9979044
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds
new file mode 100644
index 0000000..81e3719
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds
new file mode 100644
index 0000000..0349a37
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds
new file mode 100644
index 0000000..6d24d7a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl
new file mode 100644
index 0000000..e70e083
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_01v8 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_01v8 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_01v8 m=1 l=5.88u w=5u
+.ENDS
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl
new file mode 100644
index 0000000..834803f
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl
@@ -0,0 +1,34 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_01v8_dn I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_01v8_dn m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_01v8_dn m=1 l=5.88u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl
new file mode 100644
index 0000000..66e879a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_06v0 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_06v0 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_06v0 m=1 l=5.88u w=5u
+.ENDS
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl
new file mode 100644
index 0000000..ab6e6da
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_06v0_dn I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_06v0_dn m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_06v0_dn m=1 l=5.88u w=5u
+.ENDS