Adding PISCAP devices for GF180BCDLite
diff --git a/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs b/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs
index 84b1316..333f1e2 100644
--- a/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs
@@ -167,4 +167,14 @@
enable_parameter("A", true)
enable_parameter("P", true)
end
-end
\ No newline at end of file
+end
+
+# PISCAP device extractor
+class PisCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
+end
diff --git a/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs
new file mode 100644
index 0000000..0a99cb6
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs
@@ -0,0 +1,58 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ PISCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting PISCAP DERIVATIONS')
+
+piscap_exclude = lvpwell.join(pplus).join(resistor)
+ .join(esd).join(sab).join(dni)
+ .join(pwhv).join(fusewindow_d).join(polyfuse)
+ .join(schottky_diode).join(zener).join(res_mk)
+ .join(diode_mk).join(v5_xtor).join(drc_bjt)
+ .join(nat).join(fhres).join(mos_cap_mk)
+ .join(mvsd).join(mvpsd).join(elmd_mk)
+ .join(elmd2_mk).join(lvs_rf).join(lvs_source)
+ .join(mk_35v).join(well_diode_mk).join(esd_hbm_mk)
+ .join(mos_mk_type1).join(swfet_mk).join(lvs_35v)
+ .join(hvpddd).join(hvpolyrs).join(ldmos_xtor)
+
+ngate_nw = ngate.and(piscap).and(nwell).not(piscap_exclude)
+
+ngate_nw_lv = ngate_nw.not(dualgate2_d)
+ngate_nw_mv = ngate_nw.and(dualgate2_d)
+
+#====================
+# --- PIS 1P8 CAP ---
+#====================
+
+# cap_pis_01v8: Model for 1.8V PIS capacitor (outside DNWELL) [pis_1p8]
+pis_1p8_gate = ngate_nw_lv.not(dnwell)
+
+# cap_pis_01v8_dn: Model for (1.8V PIS capacitor (inside DNWEL) [pis_1p8_dw]
+pis_1p8_dw_gate = ngate_nw_lv.and(dnwell)
+
+#====================
+# --- PIS 6P0 CAP ---
+#====================
+
+# cap_pis_06v0: Model for 6V PIS capacitor (outside DNWELL) [pis_6p0]
+pis_6p0_gate = ngate_nw_mv.not(dnwell)
+
+# cap_pis_06v0_dn: Model for 6V PIS capacitor (inside DNWEL) [pis_6p0_dw]
+pis_6p0_dw_gate = ngate_nw_mv.and(dnwell)
diff --git a/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs
new file mode 100644
index 0000000..d43e846
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs
@@ -0,0 +1,53 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- PISCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting PISCAP EXTRACTION')
+
+#====================
+# --- PIS 1P8 CAP ---
+#====================
+
+# cap_pis_01v8: Model for 1.8V PIS capacitor (outside DNWELL) [pis_1p8]
+logger.info('Extracting pis_1p8 device')
+extract_devices(capacitor('piscap_1p8', 4.4e-15, PisCap),
+ { 'P1' => pis_1p8_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_pis_01v8_dn: Model for (1.8V PIS capacitor (inside DNWEL) [pis_1p8_dw]
+logger.info('Extracting pis_1p8_dw device')
+extract_devices(capacitor('piscap_1p8_dw', 4.4e-15, PisCap),
+ { 'P1' => pis_1p8_dw_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+#====================
+# --- PIS 6P0 CAP ---
+#====================
+
+# cap_pis_06v0: Model for 6V PIS capacitor (outside DNWELL) [pis_6p0]
+logger.info('Extracting pis_6p0 device')
+extract_devices(capacitor('piscap_6p0', 4.4e-15, PisCap),
+ { 'P1' => pis_6p0_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_pis_06v0_dn: Model for 6V PIS capacitor (inside DNWEL) [pis_6p0_dw]
+logger.info('Extracting pis_6p0_dw device')
+extract_devices(capacitor('piscap_6p0_dw', 4.4e-15, PisCap),
+ { 'P1' => pis_6p0_dw_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs
index facb153..abfc448 100644
--- a/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs
@@ -36,12 +36,12 @@
# --- MOS 1P8 VARACTOR ---
#=========================
-connect(cap_var_fet_01v8_terminal_p ,contact)
-connect(cap_var_fet_01v8_dn_terminal_p ,contact)
+connect(cap_var_fet_01v8_gate ,contact)
+connect(cap_var_fet_01v8_dn_gate ,contact)
#=========================
# --- MOS 6P0 VARACTOR ---
#=========================
-connect(cap_var_fet_06v0_terminal_p ,contact)
-connect(cap_var_fet_06v0_dn_terminal_p ,contact)
+connect(cap_var_fet_06v0_gate ,contact)
+connect(cap_var_fet_06v0_dn_gate ,contact)
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
index 280fd40..aff1b79 100644
--- a/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
@@ -73,18 +73,18 @@
#=========================
# cap_var_fet_01v8: Model for 1.8V Scalable MOS-varactor (outside DNWELL) [mos_varactor_1p8]
-cap_var_fet_01v8_terminal_p = ngate_nw_var_lv.not(dnwell)
+cap_var_fet_01v8_gate = ngate_nw_var_lv.not(dnwell)
# cap_var_fet_01v8_dn: Model for 1.8V Scalable MOS-varactor (inside DNWELL) [mos_varactor_1p8_dw]
-cap_var_fet_01v8_dn_terminal_p = ngate_nw_var_lv.and(dnwell)
+cap_var_fet_01v8_dn_gate = ngate_nw_var_lv.and(dnwell)
#=========================
# --- MOS 6P0 VARACTOR ---
#=========================
# cap_var_fet_06v0: Model for 6V Scalable MOS-varactor (outside DNWELL) [mos_varactor_6p0]
-cap_var_fet_06v0_terminal_p = ngate_nw_var_mv.not(dnwell)
+cap_var_fet_06v0_gate = ngate_nw_var_mv.not(dnwell)
# cap_var_fet_06v0_dn: Model for 6V Scalable MOS-varactor (inside DNWELL) [mos_varactor_6p0_dw]
-cap_var_fet_06v0_dn_terminal_p = ngate_nw_var_mv.and(dnwell)
+cap_var_fet_06v0_dn_gate = ngate_nw_var_mv.and(dnwell)
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs
index a52b50e..098d0d9 100644
--- a/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs
@@ -59,13 +59,13 @@
# cap_var_fet_01v8: Model for 1.8V Scalable MOS-varactor (outside DNWELL) [mos_varactor_1p8]
logger.info('Extracting cap_var_fet_01v8')
extract_devices(capacitor('cap_var_fet_01v8', 4.4e-15, VarCap),
- { 'P1' => cap_var_fet_01v8_terminal_p, 'P2' => nwell_con,
+ { 'P1' => cap_var_fet_01v8_gate, 'P2' => nwell_con,
'tA' => poly2_con, 'tB' => ntap })
# cap_var_fet_01v8_dn: Model for 1.8V Scalable MOS-varactor (inside DNWELL) [mos_varactor_1p8_dw]
logger.info('Extracting cap_var_fet_01v8_dn')
extract_devices(capacitor('cap_var_fet_01v8_dn', 4.4e-15, VarCap),
- { 'P1' => cap_var_fet_01v8_dn_terminal_p, 'P2' => dnwell,
+ { 'P1' => cap_var_fet_01v8_dn_gate, 'P2' => dnwell,
'tA' => poly2_con, 'tB' => ntap })
#=========================
@@ -75,11 +75,11 @@
# cap_var_fet_06v0: Model for 6V Scalable MOS-varactor (outside DNWELL) [mos_varactor_6p0]
logger.info('Extracting cap_var_fet_06v0')
extract_devices(capacitor('cap_var_fet_06v0', 4.4e-15, VarCap),
- { 'P1' => cap_var_fet_06v0_terminal_p, 'P2' => nwell_con,
+ { 'P1' => cap_var_fet_06v0_gate, 'P2' => nwell_con,
'tA' => poly2_con, 'tB' => ntap })
# cap_var_fet_06v0_dn: Model for 6V Scalable MOS-varactor (inside DNWELL) [mos_varactor_6p0_dw]
logger.info('Extracting cap_var_fet_06v0_dn')
extract_devices(capacitor('cap_var_fet_06v0_dn', 4.4e-15, VarCap),
- { 'P1' => cap_var_fet_06v0_dn_terminal_p, 'P2' => dnwell,
+ { 'P1' => cap_var_fet_06v0_dn_gate, 'P2' => dnwell,
'tA' => poly2_con, 'tB' => ntap })
