################################################################################################
# Copyright 2022 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the 'License');
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an 'AS IS' BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################################


if FEOL

    nwell_lv = nwell.not(dualgate_2)
    nwell_mv = nwell.and(dualgate_2).not(dualgate)

    #================================================
    #---------------------NWELL----------------------
    #================================================ 

    # Rule NW.1a_LV: Min. Nwell Width (This is only for litho purpose on the generated area). is 0.86µm
    logger.info('Executing rule NW.1a_LV')
    nw1a_l1  = nwell_lv.width(0.86.um, euclidian).polygons(0.001)
    nw1a_l1.output('NW.1a_LV', 'NW.1a_LV : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm')
    nw1a_l1.forget 

    # Rule NW.1a_MV: Min. Nwell Width (This is only for litho purpose on the generated area). is 0.86µm
    logger.info('Executing rule NW.1a_MV')
    nw1a_l1  = nwell_mv.width(0.86.um, euclidian).polygons(0.001)
    nw1a_l1.output('NW.1a_MV', 'NW.1a_MV : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm')
    nw1a_l1.forget 

    nw_1b_lv = nwell_lv.outside(dnwell).and(res_mk)
    # Rule NW.1b_LV: Min. Nwell Width as a resistor (Outside DNWELL only). is 2µm
    logger.info('Executing rule NW.1b_LV')
    nw1b_l1  = nw_1b_lv.width(2.um, euclidian).polygons(0.001)
    nw1b_l1.output('NW.1b_LV', 'NW.1b_LV : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm')
    nw1b_l1.forget 
    nw_1b_lv.forget 

    nw_1b_mv = nwell_mv.outside(dnwell).and(res_mk)
    # Rule NW.1b_MV: Min. Nwell Width as a resistor (Outside DNWELL only). is 2µm
    logger.info('Executing rule NW.1b_MV')
    nw1b_l1  = nw_1b_mv.width(2.um, euclidian).polygons(0.001)
    nw1b_l1.output('NW.1b_MV', 'NW.1b_MV : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm')
    nw1b_l1.forget 
    nw_1b_mv.forget 

    if CONNECTIVITY_RULES
        logger.info('CONNECTIVITY_RULES section') 

        connected_nwell_3p3v, unconnected_nwell_3p3v = conn_space(nwell, 0.6, 1.4, euclidian) 

        connected_nwell_5p0v, unconnected_nwell_5p0v = conn_space(nwell, 0.74, 1.7, euclidian) 

        # Rule NW.2a_LV: Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. is 0.6µm
        logger.info('Executing rule NW.2a_LV')
        nw2a_l1  = connected_nwell_3p3v.not(dualgate_2).outside(dnwell)
        nw2a_l1.output('NW.2a_LV', 'NW.2a_LV : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.6µm')
        nw2a_l1.forget 

        # Rule NW.2a_MV: Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. is 0.74µm
        logger.info('Executing rule NW.2a_MV')
        nw2a_l1  = connected_nwell_5p0v.and(dualgate_2).not(dualgate).outside(dnwell)
        nw2a_l1.output('NW.2a_MV', 'NW.2a_MV : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.74µm')
        nw2a_l1.forget 

        # Rule NW.2b_LV: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.4µm
        logger.info('Executing rule NW.2b_LV')
        nw2b_l1  = unconnected_nwell_3p3v.not(dualgate_2).outside(dnwell)
        nw2b_l1.output('NW.2b_LV', 'NW.2b_LV : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.4µm')
        nw2b_l1.forget 

        # Rule NW.2b_MV: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.7µm
        logger.info('Executing rule NW.2b_MV')
        nw2b_l1  = unconnected_nwell_5p0v.and(dualgate_2).not(dualgate).outside(dnwell)
        nw2b_l1.output('NW.2b_MV', 'NW.2b_MV : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.7µm')
        nw2b_l1.forget 
    else
        logger.info('CONNECTIVITY_RULES disabled section') 

        # Rule NW.2b_LV : Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.4µm
        logger.info('Executing rule NW.2b_LV ')
        nw2b_l1  = nwell_lv.isolated(1.4.um, euclidian).polygons(0.001)
        nw2b_l1.output('NW.2b_LV', 'NW.2b_LV  : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.4µm')
        nw2b_l1.forget 

        # Rule NW.2b_MV : Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.7µm
        logger.info('Executing rule NW.2b_MV ')
        nw2b_l1  = nwell_mv.isolated(1.7.um, euclidian).polygons(0.001)
        nw2b_l1.output('NW.2b_MV', 'NW.2b_MV  : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.7µm')
        nw2b_l1.forget 

    end #CONNECTIVITY_RULES 

    # Rule NW.3_LV: Min. Nwell to DNWELL space. is 3.1µm
    logger.info('Executing rule NW.3_LV')
    nw3_l1  = nwell_lv.separation(dnwell, 3.1.um, euclidian).polygons(0.001)
    nw3_l1.output('NW.3_LV', 'NW.3_LV : Min. Nwell to DNWELL space. : 3.1µm')
    nw3_l1.forget 

    # Rule NW.3_MV: Min. Nwell to DNWELL space. is 3.1µm
    logger.info('Executing rule NW.3_MV')
    nw3_l1  = nwell_mv.separation(dnwell, 3.1.um, euclidian).polygons(0.001)
    nw3_l1.output('NW.3_MV', 'NW.3_MV : Min. Nwell to DNWELL space. : 3.1µm')
    nw3_l1.forget 

    # Rule NW.4_LV: Min. Nwell to LVPWELL space.
    logger.info('Executing rule NW.4_LV')
    nw4_l1 = nwell_lv.not_outside(lvpwell)
    nw4_l1.output('NW.4_LV', 'NW.4_LV : Min. Nwell to LVPWELL space.')
    nw4_l1.forget

    # Rule NW.4_MV: Min. Nwell to LVPWELL space.
    logger.info('Executing rule NW.4_MV')
    nw4_l1 = nwell_mv.not_outside(lvpwell)
    nw4_l1.output('NW.4_MV', 'NW.4_MV : Min. Nwell to LVPWELL space.')
    nw4_l1.forget

    # Rule NW.5_LV: Min. DNWELL enclose Nwell. is 0.5µm
    logger.info('Executing rule NW.5_LV')
    nw5_l1 = dnwell.enclosing(nwell_lv, 0.5.um, euclidian).polygons(0.001)
    nw5_l2 = nwell_lv.not_outside(dnwell).not(dnwell)
    nw5_l  = nw5_l1.or(nw5_l2)
    nw5_l.output('NW.5_LV', 'NW.5_LV : Min. DNWELL enclose Nwell. : 0.5µm')
    nw5_l1.forget
    nw5_l2.forget
    nw5_l.forget

    # Rule NW.5_MV: Min. DNWELL enclose Nwell. is 0.5µm
    logger.info('Executing rule NW.5_MV')
    nw5_l1 = dnwell.enclosing(nwell_mv, 0.5.um, euclidian).polygons(0.001)
    nw5_l2 = nwell_mv.not_outside(dnwell).not(dnwell)
    nw5_l  = nw5_l1.or(nw5_l2)
    nw5_l.output('NW.5_MV', 'NW.5_MV : Min. DNWELL enclose Nwell. : 0.5µm')
    nw5_l1.forget
    nw5_l2.forget
    nw5_l.forget

    # Rule NW.6: Nwell resistors can only exist outside DNWELL.
    logger.info('Executing rule NW.6')
    nw6_l1 = nwell.inside(res_mk).interacting(dnwell)
    nw6_l1.output('NW.6', 'NW.6 : Nwell resistors can only exist outside DNWELL.')
    nw6_l1.forget

    # rule NW.6_MV is not a DRC check

    # rule NW.7_LV is not a DRC check

    # rule NW.7_MV is not a DRC check
    nwell_lv.forget 
    nwell_mv.forget 

end #FEOL