diff --git a/.github/workflows/regression.yml b/.github/workflows/drc_regression.yml
similarity index 80%
rename from .github/workflows/regression.yml
rename to .github/workflows/drc_regression.yml
index 8026e5f..0db8498 100644
--- a/.github/workflows/regression.yml
+++ b/.github/workflows/drc_regression.yml
@@ -12,7 +12,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-name: regression testing
+name: DRC regression testing
 
 # Prevent keeping resources busy when a branch/PR is updated
 # https://docs.github.com/en/actions/using-jobs/using-concurrency
@@ -76,21 +76,4 @@
         run: |
           make test-"$(python3 -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
 
-  lvs_regression:
-    runs-on: ${{ fromJSON('["ubuntu-latest", "self-hosted"]')[github.repository == 'github/docs-internal'] }}
-    strategy:
-      fail-fast: false
-      matrix:
-        include:
-          - { tool: klayout, part: lvs, test: main }
-          - { tool: klayout, part: lvs, test: switch }
 
-    name: ${{ matrix.part }} | ${{ matrix.test }}
-
-    steps:
-      - uses: actions/checkout@v3
-        with:
-          submodules: 'recursive'
-      - name: Testing ${{ matrix.part }} for ${{ matrix.test }}
-        run: |
-          make test-"$(python3 -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
diff --git a/.github/workflows/lvs_regression.yml b/.github/workflows/lvs_regression.yml
new file mode 100644
index 0000000..3b26c9f
--- /dev/null
+++ b/.github/workflows/lvs_regression.yml
@@ -0,0 +1,77 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: LVS regression testing
+
+# Prevent keeping resources busy when a branch/PR is updated
+# https://docs.github.com/en/actions/using-jobs/using-concurrency
+concurrency:
+  group: ${{ github.repository }}-${{ github.workflow }}-${{ github.ref }}
+  cancel-in-progress: true
+
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+
+jobs:
+  lvs_switch:
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          - { tool: klayout, part: lvs, test: switch }
+
+    name: ${{ matrix.part }} | ${{ matrix.test }}
+
+    steps:
+      - uses: actions/checkout@v3
+        with:
+          submodules: 'recursive'
+      - name: Testing ${{ matrix.part }} for ${{ matrix.test }}
+        run: |
+          make test-"$(python -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
+
+  build_lvs-matrix:
+    runs-on: ubuntu-latest
+    outputs:
+      lvs_table: ${{ steps.set-matrix.outputs.lvs_table }}
+    steps:
+      - uses: actions/checkout@v3
+      - id: set-matrix
+        run: |
+          lvs_table=`find -iname '*_extraction.lvs' | grep -i rule_decks | grep -v main | grep -v tail | awk -F'/' '{printf "\"%s-%s\",", $2, $NF}' | sed -e "s/^/[/g" -e "s/,$/]/g" -e "s/_extraction.lvs//g"`
+          lvs_table=`echo $lvs_table | jq -c .`
+          echo $lvs_table
+          echo "lvs_table=$lvs_table" >>$GITHUB_OUTPUT
+
+  lvs_regression:
+    needs: build_lvs-matrix
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        part: [lvs]
+        test: ${{ fromJson(needs.build_lvs-matrix.outputs.lvs_table) }}
+
+    name: ${{ matrix.part }} | ${{ matrix.test }}
+
+    steps:
+      - uses: actions/checkout@v3
+        with:
+          submodules: 'recursive'
+      - name: Testing ${{ matrix.part }} for ${{ matrix.test }}
+        run: |
+          make test-"$(python -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
diff --git a/BCDLite/klayout/lvs/testing/Makefile b/BCDLite/klayout/lvs/testing/Makefile
new file mode 100644
index 0000000..270b923
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/Makefile
@@ -0,0 +1,38 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+#=========================================================================
+# ---------------------------------- LVS ---------------------------------
+#=========================================================================
+
+SHELL        := /bin/bash
+Testing_DIR  ?= $(shell pwd)
+
+.DEFAULT_GOAL := all
+
+all: test-LVS
+
+test-LVS: test-LVS-main
+
+#=================================
+# ----- test-LVS_regression ------
+#=================================
+
+.ONESHELL:
+test-LVS-main: test-LVS-MOS test-LVS-BJT test-LVS-DIODE test-LVS-RES test-LVS-MIMCAP test-LVS-APMOMCAP test-LVS-VARACTOR test-LVS-MOSCAP test-LVS-ESD test-LVS-EFUSE
+
+.ONESHELL:
+test-LVS-%:
+	@ python3 run_regression.py --device_name=$*
+
diff --git a/BCDLite/klayout/lvs/testing/README.md b/BCDLite/klayout/lvs/testing/README.md
new file mode 100644
index 0000000..59f45c8
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/README.md
@@ -0,0 +1,33 @@
+# Globalfoundries 180nm BCDLite LVS Testing
+
+Explains how to test GF180nm LVS rule decks.
+
+## Folder Structure
+
+```text
+📁 testing
+ ┣ 📜Makefile
+ ┣ 📜README.md
+ ┣ 📜run_regression.py
+ ┗ 📜testcases
+ ```
+
+## Prerequisites
+
+At a minimum:
+
+- Git 2.34.1+
+- Python 3.9.12+
+- KLayout 0.28.6+
+
+## Usage
+
+To make a full test for GF180nm LVS rule deck, you could use the following command in testing directory:
+
+```bash
+make all
+```
+
+## **Regression Outputs**
+
+- Final results will appear at the end of the run logs.
diff --git a/BCDLite/klayout/lvs/testing/run_regression.py b/BCDLite/klayout/lvs/testing/run_regression.py
new file mode 100644
index 0000000..6320d34
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/run_regression.py
@@ -0,0 +1,530 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""Run GlobalFoundries 180nm BCDLite LVS Regression.
+
+Usage:
+    run_regression.py (--help| -h)
+    run_regression.py [--device_name=<device_name>] [--mp=<num>] [--run_name=<run_name>]
+
+Options:
+    --help -h                      Print this help message.
+    --device_name=<device_name>    Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, ESD, EFUSE).
+    --mp=<num>                     The number of threads used in run.
+    --run_name=<run_name>          Select your run name.
+"""
+
+from subprocess import check_call
+from subprocess import Popen, PIPE
+import concurrent.futures
+import traceback
+import yaml
+from docopt import docopt
+import os
+from datetime import datetime
+import xml.etree.ElementTree as ET
+import time
+import pandas as pd
+import logging
+import glob
+from pathlib import Path
+from tqdm import tqdm
+import re
+import errno
+import numpy as np
+from collections import defaultdict
+import shutil
+
+SUPPORTED_TC_EXT = "gds"
+SUPPORTED_SPICE_EXT = "cdl"
+SUPPORTED_SW_EXT = "yaml"
+
+
+def check_klayout_version():
+    """
+    check_klayout_version checks klayout version and makes sure it would work with the DRC.
+    """
+    # ======= Checking Klayout version =======
+    klayout_v_ = os.popen("klayout -b -v").read()
+    klayout_v_ = klayout_v_.split("\n")[0]
+    klayout_v_list = []
+
+    if klayout_v_ == "":
+        logging.error("Klayout is not found. Please make sure klayout is installed.")
+        exit(1)
+    else:
+        klayout_v_list = [int(v) for v in klayout_v_.split(" ")[-1].split(".")]
+
+    if len(klayout_v_list) < 1 or len(klayout_v_list) > 3:
+        logging.error("Was not able to get klayout version properly.")
+        exit(1)
+    elif len(klayout_v_list) >= 2 or len(klayout_v_list) <= 3:
+        if klayout_v_list[1] < 28 or (klayout_v_list[1] == 28 and klayout_v_list[2] <= 3):
+            logging.error("Prerequisites at a minimum: KLayout 0.28.6")
+            logging.error(
+                "Using this klayout version is not supported in this development."
+            )
+            exit(1)
+
+    logging.info(f"Your Klayout version is: {klayout_v_}")
+
+
+def parse_existing_devices(rule_deck_path, output_path, target_device_group=None):
+    """
+    This function collects the rule names from the existing drc rule decks.
+
+    Parameters
+    ----------
+    rule_deck_path : string or Path object
+        Path string to the LVS directory where all the LVS files are located.
+    output_path : string or Path
+        Path of the run location to store the output analysis file.
+    target_device_group : string Optional
+        Name of the device group to be in testing
+
+    Returns
+    -------
+    pd.DataFrame
+        A pandas DataFrame with the rule and rule deck used.
+    """
+
+    if target_device_group is None:
+        lvs_files = glob.glob(os.path.join(rule_deck_path, "rule_decks", "*_extraction.lvs"))
+    else:
+        table_device_file = os.path.join(
+            rule_deck_path, "rule_decks", f"{str(target_device_group).lower()}_extraction.lvs"
+        )
+        if not os.path.isfile(table_device_file):
+            raise FileNotFoundError(
+                errno.ENOENT, os.strerror(errno.ENOENT), table_device_file
+            )
+
+        lvs_files = [table_device_file]
+
+    rules_data = list()
+
+    for runset in lvs_files:
+        with open(runset, "r") as f:
+            for line in f:
+                if "extract_devices" in line:
+                    line_list = line.split("'")
+                    rule_info = dict()
+                    rule_info["device_group"] = os.path.basename(runset).replace(
+                        "_extraction.lvs", ""
+                    ).upper()
+                    rule_info["device_name"] = line_list[1]
+                    rule_info["in_rule_deck"] = 1
+                    rules_data.append(rule_info)
+
+    df = pd.DataFrame(rules_data)
+    df.drop_duplicates(inplace=True)
+    df.to_csv(os.path.join(output_path, "rule_deck_rules.csv"), index=False)
+    return df
+
+
+def build_tests_dataframe(unit_test_cases_dir, target_device_group):
+    """
+    This function is used for getting all test cases available in a formated dataframe before running.
+
+    Parameters
+    ----------
+    unit_test_cases_dir : str
+        Path string to the location of unit test cases path.
+    target_device_group : str or None
+        Name of device group that we want to run regression for. If None, run all found.
+
+    Returns
+    -------
+    pd.DataFrame
+        A DataFrame that has all the targetted test cases that we need to run.
+    """
+    all_unit_test_cases_layout = sorted(
+        Path(unit_test_cases_dir).rglob("*.{}".format(SUPPORTED_TC_EXT))
+    )
+    logging.info(
+        "## Total number of gds files test cases found: {}".format(len(all_unit_test_cases_layout))
+    )
+
+    all_unit_test_cases_netlist = sorted(
+        Path(unit_test_cases_dir).rglob("*.{}".format(SUPPORTED_SPICE_EXT))
+    )
+    logging.info(
+        "## Total number of spice files test cases found: {}".format(len(all_unit_test_cases_netlist))
+    )
+
+    if len(all_unit_test_cases_netlist) != len(all_unit_test_cases_layout):
+        logging.error(
+            "## Each testcase should have Layout and Netlist file"
+        )
+        exit(1)
+
+    # Get test cases df from test cases
+    tc_df = pd.DataFrame({"test_layout_path": all_unit_test_cases_layout , "test_netlist_path": all_unit_test_cases_netlist})
+    tc_df["device_name"] = tc_df["test_layout_path"].apply(lambda x: x.name.replace(".gds", ""))
+    tc_df["device_group"] = tc_df["test_layout_path"].apply(lambda x: x.parent.parent.name.replace("_devices", "").upper())
+
+    if target_device_group is not None:
+        tc_df = tc_df[tc_df["device_group"] == target_device_group]
+    if len(tc_df) < 1:
+        logging.error("No test cases remaining after filtering.")
+        exit(1)
+
+    tc_df["run_id"] = range(len(tc_df))
+    return tc_df
+
+
+def get_switches(yaml_file, rule_name):
+    """Parse yaml file and extract switches data
+    Parameters
+    ----------
+    yaml_file : str
+            yaml config file path given py the user.
+    Returns
+    -------
+    yaml_dic : dictionary
+            dictionary containing switches data.
+    """
+
+    # load yaml config data
+    with open(yaml_file, "r") as stream:
+        try:
+            yaml_dic = yaml.safe_load(stream)
+        except yaml.YAMLError as exc:
+            print(exc)
+
+    return [f"{param}={value}" for param, value in yaml_dic[rule_name].items()]
+
+
+def run_test_case(
+    lvs_dir,
+    layout_path,
+    netlist_path,
+    run_dir,
+    device_name,
+):
+    """
+    This function run a single test case using the correct DRC file.
+
+    Parameters
+    ----------
+    lvs_dir : string or Path
+        Path to the location where all runsets exist.
+    layout_path : stirng or Path object
+        Path string to the layout of the test pattern we want to test.
+    netlist_path : stirng or Path object
+        Path string to the netlist of the test pattern we want to test.
+    run_dir : stirng or Path object
+        Path to the location where is the regression run is done.
+    device_name : string
+        Device name that we are running on.
+
+    Returns
+    -------
+    dict
+        A dict with all rule counts
+    """
+
+    # Get switches used for each run
+    sw_file = os.path.join(
+        Path(layout_path.parent).absolute(), f"{device_name}.{SUPPORTED_SW_EXT}"
+    )
+
+    if os.path.exists(sw_file):
+        switches = " ".join(get_switches(sw_file, device_name))
+    else:
+        # Get switches
+        switches = " -rd lvs_sub=sub!" if device_name == "sample_ggnfet_06v0_dss" else " -rd lvs_sub=vdd!"  # default switch
+
+    # Creating run folder structure and copy testcases in it
+    pattern_clean = ".".join(os.path.basename(layout_path).split(".")[:-1])
+    output_loc = f"{run_dir}/{device_name}"
+    pattern_log = f"{output_loc}/{pattern_clean}_lvs.log"
+    os.makedirs(output_loc, exist_ok=True)
+    layout_path_run = os.path.join(run_dir, device_name, f"{device_name}.gds")
+    netlist_path_run = os.path.join(run_dir, device_name, f"{device_name}.cdl")
+    shutil.copyfile(layout_path, layout_path_run)
+    shutil.copyfile(netlist_path, netlist_path_run)
+
+    # command to run drc
+    call_str = f"klayout -b -r {lvs_dir}/gf180BCDLite.lvs -rd input={layout_path_run} -rd schematic={device_name}.cdl -rd report={device_name}.lvsdb  -rd target_netlist={device_name}_extracted.cir {switches} > {pattern_log} 2>&1"
+
+    # Starting klayout run
+    try:
+        check_call(call_str, shell=True)
+    except Exception as e:
+        pattern_results = glob.glob(os.path.join(output_loc, f"{pattern_clean}*.lvsdb"))
+        if len(pattern_results) < 1:
+            logging.error("%s generated an exception: %s" % (pattern_clean, e))
+            traceback.print_exc()
+            raise Exception("Failed DRC run.")
+
+    # dumping log into output to make CI have the log
+    if os.path.isfile(pattern_log):
+        with open(pattern_log, "r") as f:
+            result = f.read()
+            for line in f:
+                line = line.strip()
+                logging.info(f"{line}")
+
+    # checking device status
+        device_status = 'Failed'
+        if "Congratulations! Netlists match" in result:
+            logging.info(f"{device_name} testcase passed")
+            device_status = 'Passed'
+        else:
+            logging.error(f"{device_name} testcase failed.")
+            logging.error(f"Please recheck {layout_path} file.")
+    else:
+        logging.error("Klayout LVS run failed, there is no log file is generated")
+        exit(1)
+
+    return device_status
+
+
+def run_all_test_cases(tc_df, lvs_dir, run_dir, num_workers):
+    """
+    This function run all test cases from the input dataframe.
+
+    Parameters
+    ----------
+    tc_df : pd.DataFrame
+        DataFrame that holds all the test cases information for running.
+    lvs_dir : string or Path
+        Path string to the location of the lvs runsets.
+    run_dir : string or Path
+        Path string to the location of the testing code and output.
+    num_workers : int
+        Number of workers to use for running the regression.
+
+    Returns
+    -------
+    pd.DataFrame
+        A pandas DataFrame with all test cases information post running.
+    """
+
+    tc_df["device_status"] = "no status"
+
+    with concurrent.futures.ThreadPoolExecutor(max_workers=num_workers) as executor:
+        future_to_run_id = dict()
+        for i, row in tc_df.iterrows():
+            future_to_run_id[
+                executor.submit(
+                    run_test_case,
+                    lvs_dir,
+                    row["test_layout_path"],
+                    row["test_netlist_path"],
+                    run_dir,
+                    row["device_name"],
+                )
+            ] = row["run_id"]
+
+        for future in concurrent.futures.as_completed(future_to_run_id):
+            run_id = future_to_run_id[future]
+            try:
+                tc_df.loc[tc_df["run_id"] == run_id, "device_status"] = future.result()
+            except Exception as exc:
+                logging.error("%d generated an exception: %s" % (run_id, exc))
+                traceback.print_exc()
+                tc_df.loc[tc_df["run_id"] == run_id, "device_status"] = "exception"
+
+    return tc_df
+
+
+def aggregate_results(
+    results_df: pd.DataFrame, devices_df: pd.DataFrame
+):
+    """
+    aggregate_results Aggregate the results for all runs.
+
+    Parameters
+    ----------
+    results_df : pd.DataFrame
+        Dataframe that holds the information about the unit test rules.
+    devices_df : pd.DataFrame
+        Dataframe that holds the information about all the devices implemented in the rule deck.
+
+    Returns
+    -------
+    pd.DataFrame
+        A DataFrame that has all data analysis aggregated into one.
+    """
+    if len(devices_df) < 1 and len(results_df) < 1:
+        logging.error("## There are no rules for analysis or run.")
+        exit(1)
+    elif len(devices_df) < 1 and len(results_df) > 0:
+        df = results_df
+    elif len(devices_df) > 0 and len(results_df) < 1:
+        df = devices_df
+    else:
+        df = results_df.merge(devices_df, how="outer", on=["device_group", "device_name"])
+
+    df.loc[(df["device_status"] != 'Passed'), "device_status"] = "Failed"
+
+    return df
+
+
+def run_regression(lvs_dir, output_path, target_device_group, cpu_count):
+    """
+    Running Regression Procedure.
+
+    This function runs the full regression on all test cases.
+
+    Parameters
+    ----------
+    lvs_dir : string
+        Path string to the LVS directory where all the LVS files are located.
+    output_path : str
+        Path string to the location of the output results of the run.
+    target_device_group : str or None
+        Name of device group that we want to run regression for. If None, run all found.
+    cpu_count : int
+        Number of cpus to use in running testcases.
+    Returns
+    -------
+    bool
+        If all regression passed, it returns true. If any of the rules failed it returns false.
+    """
+
+    ## Parse Existing Rules
+    devices_df = parse_existing_devices(lvs_dir, output_path, target_device_group)
+    logging.info(
+        "## Total number of devices found in rule decks: {}".format(len(devices_df))
+    )
+    logging.info("## Parsed devices: \n" + str(devices_df))
+
+    ## Get all test cases available in the repo.
+    test_cases_path = os.path.join(lvs_dir, "testing/testcases")
+    unit_test_cases_path = os.path.join(test_cases_path, "unit")
+    tc_df = build_tests_dataframe(unit_test_cases_path, target_device_group)
+    logging.info("## Total table gds files found: {}".format(len(tc_df)))
+    logging.info("## Found testcases: \n" + str(tc_df))
+
+    ## Run all test cases.
+    results_df = run_all_test_cases(tc_df, lvs_dir, output_path, cpu_count)
+    logging.info("## Testcases found results: \n" + str(results_df))
+
+    ## Aggregate all dataframes into one
+    df = aggregate_results(results_df, devices_df)
+    df.drop_duplicates(inplace=True)
+    df.drop('run_id', inplace=True, axis=1)
+    logging.info("## Final analysis table: \n" + str(df))
+
+    ## Generate error if there are any missing info or fails.
+    df.to_csv(os.path.join(output_path, "all_test_cases_results.csv"), index=False)
+
+    ## Check if there any rules that generated false positive or false negative
+    failing_results = df[~df["device_status"].isin(["Passed"])]
+    logging.info("## Failing test cases: \n" + str(failing_results))
+
+    if len(failing_results) > 0:
+        logging.error("## Some test cases failed .....")
+        return False
+    else:
+        logging.info("## All testcases passed.")
+        return True
+
+
+def main(lvs_dir, output_path, target_device_group):
+    """
+    Main Procedure.
+
+    This function is the main execution procedure
+
+    Parameters
+    ----------
+    lvs_dir : str
+        Path string to the LVS directory where all the LVS files are located.
+    output_path : str
+        Path string to the location of the output results of the run.
+    target_device_group : str or None
+        Name of device group that we want to run regression for. If None, run all found.
+    Returns
+    -------
+    bool
+        If all regression passed, it returns true. If any of the rules failed it returns false.
+    """
+
+    # No. of threads
+    cpu_count = os.cpu_count() if args["--mp"] is None else int(args["--mp"])
+
+    # Pandas printing setup
+    pd.set_option("display.max_columns", None)
+    pd.set_option("display.max_rows", None)
+    pd.set_option("max_colwidth", None)
+    pd.set_option("display.width", 1000)
+
+    # info logs for args
+    logging.info("## Run folder is: {}".format(run_name))
+    logging.info("## Target device is: {}".format(target_device_group))
+
+    # Start of execution time
+    t0 = time.time()
+
+    ## Check Klayout version
+    check_klayout_version()
+
+    # Calling regression function
+    run_status = run_regression(lvs_dir, output_path, target_device_group, cpu_count)
+
+    #  End of execution time
+    logging.info("Total execution time {}s".format(time.time() - t0))
+
+    if run_status:
+        logging.info("Test completed successfully.")
+    else:
+        logging.error("Test failed.")
+        exit(1)
+
+
+if __name__ == "__main__":
+
+    # docopt reader
+    args = docopt(__doc__, version="LVS Regression: 0.2")
+
+    # arguments
+    run_name = args["--run_name"]
+
+    # run name
+    if run_name is None:
+        run_name = datetime.utcnow().strftime("unit_tests_%Y_%m_%d_%H_%M_%S")
+
+    # Paths of regression dirs
+    testing_dir = os.path.dirname(os.path.abspath(__file__))
+    lvs_dir = os.path.dirname(testing_dir)
+    output_path = os.path.join(testing_dir, run_name)
+
+    # Creating output dir
+    os.makedirs(output_path, exist_ok=True)
+
+    # logs format
+    logging.basicConfig(
+        level=logging.DEBUG,
+        handlers=[
+            logging.FileHandler(os.path.join(output_path, "{}.log".format(run_name))),
+            logging.StreamHandler(),
+        ],
+        format="%(asctime)s | %(levelname)-7s | %(message)s",
+        datefmt="%d-%b-%Y %H:%M:%S",
+    )
+
+    ## selected device
+    allowed_devices = ["MOS", "BJT", "DIODE", "RES", "MIMCAP", "MOSCAP", "APMOMCAP", "VARACTOR" , "EFUSE", "ESD"]
+    target_device_group = args["--device_name"]
+
+    if target_device_group and target_device_group not in allowed_devices:
+        logging.error("Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, ESD, EFUSE) only")
+        exit(1)
+
+    # Calling main function
+    run_status = main(lvs_dir, output_path, target_device_group)
diff --git a/IC/klayout/lvs/gf180ic.lvs b/IC/klayout/lvs/gf180ic.lvs
index ac05839..c15c0b8 100644
--- a/IC/klayout/lvs/gf180ic.lvs
+++ b/IC/klayout/lvs/gf180ic.lvs
@@ -188,11 +188,11 @@
 logger.info("MIM Option selected: #{MIM_OPTION}")
 
 # MIM
-MIM_CAP = $mim_cap || '2'
+MIM_CAP = $mim_cap || '0'
 
 logger.info("MIM CAP selected: #{MIM_CAP}")
 
-MIM_CAP_STACK = $mim_cap_stack || '2'
+MIM_CAP_STACK = $mim_cap_stack || '0'
 
 logger.info("STACKED MIM CAP selected: #{MIM_CAP_STACK}")
 
@@ -211,24 +211,21 @@
   when '6LM'
     cap_mim1f0 = 'cap_mim_1f0_m5m6_noshield'
     cap_mim1f5 = 'cap_mim_1f5_m5m6_noshield'
-    cap_mim2f0 = 'cap_mim_2f0_m5m6_noshield'
     cap_mim_single_2f0 = 'cap_mim_single_2f0_m5m6_noshield'
-    cap_mim2f0 = 'cap_mim_2f0_m5m6_noshield'
-    cap_mim3f0 = 'cap_mim_3f0_m5m6_noshield'
+    cap_mim2f0 = 'cap_mim_2f0_m4m6_noshield'
+    cap_mim3f0 = 'cap_mim_3f0_m4m6_noshield'
   when '5LM'
     cap_mim1f0 = 'cap_mim_1f0_m4m5_noshield'
     cap_mim1f5 = 'cap_mim_1f5_m4m5_noshield'
-    cap_mim2f0 = 'cap_mim_2f0_m4m5_noshield'
     cap_mim_single_2f0 = 'cap_mim_single_2f0_m4m5_noshield'
-    cap_mim2f0 = 'cap_mim_2f0_m4m5_noshield'
-    cap_mim3f0 = 'cap_mim_3f0_m4m5_noshield'
+    cap_mim2f0 = 'cap_mim_2f0_m3m5_noshield'
+    cap_mim3f0 = 'cap_mim_3f0_m3m5_noshield'
   when '4LM'
     cap_mim1f0 = 'cap_mim_1f0_m3m4_noshield'
     cap_mim1f5 = 'cap_mim_1f5_m3m4_noshield'
-    cap_mim2f0 = 'cap_mim_2f0_m3m4_noshield'
     cap_mim_single_2f0 = 'cap_mim_single_2f0_m3m4_noshield'
-    cap_mim2f0 = 'cap_mim_2f0_m3m4_noshield'
-    cap_mim3f0 = 'cap_mim_3f0_m3m4_noshield'
+    cap_mim2f0 = 'cap_mim_2f0_m2m4_noshield'
+    cap_mim3f0 = 'cap_mim_3f0_m2m4_noshield'
   end
 end
 
diff --git a/IC/klayout/lvs/rule_decks/devices_connections.lvs b/IC/klayout/lvs/rule_decks/devices_connections.lvs
index 8eb2702..7848e93 100644
--- a/IC/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/IC/klayout/lvs/rule_decks/devices_connections.lvs
@@ -190,23 +190,16 @@
 
 case MIM_OPTION
 when 'A'
-  if MIM_CAP
-    connect(metal2, mim_virtual)
-    connect(fuse_cap, via2)
-  end
-when 'B'
-  if MIM_CAP
-    connect(topmin1_metal, mimtm_virtual)
-    connect(fuse_cap, top_via)
-  end
-  if MIM_CAP_STACK
-    connect(topmin1_metal, mimtm_stack1_virtual)
-    connect(fuse_cap, top_via)
-    connect(topmin2_metal, mimtm_stack2_virtual)
-    connect(fuse2_cap, topmin1_via)
-  end
-end
+  connect(metal2, mim_virtual)
+  connect(fuse_cap, via2)
 
+when 'B'
+  connect(topmin1_metal, mimtm_virtual)
+  connect(fuse_cap, top_via)
+  connect(topmin1_metal, mimtm_stack1_virtual)
+  connect(topmin2_metal, mimtm_stack2_virtual)
+  connect(fuse2_cap, topmin1_via)
+end
 
 #========================================
 # ------ PN Varactors CONNECTIONS -------
diff --git a/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs b/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
index 6ced825..2fa2226 100644
--- a/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
+++ b/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
@@ -32,16 +32,12 @@
 mimtm_stack1_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop))
 mimtm_stack2_virtual = fusetop2.sized(1.06.um).and(topmin2_metal.interacting(fusetop2))
 
-
 if METAL_LEVEL != '2LM'
   metal3_ncap = metal3.not(mimtm_virtual).not(mimtm_stack2_virtual).not(mimtm_stack1_virtual)
 
   if METAL_LEVEL != '3LM'
-    metal4_ncap = metal4.not(mimtm_virtual).not(mimtm_virtual).not(mimtm_stack2_virtual).not(mimtm_stack1_virtual)
-  end
-
-  if METAL_LEVEL != '4LM'
-    metal5_ncap = metal5.not(mimtm_virtual).not(mimtm_virtual).not(mimtm_stack2_virtual).not(mimtm_stack1_virtual)
+    metal4_ncap = metal4.not(mimtm_virtual).not(mimtm_stack2_virtual).not(mimtm_stack1_virtual)
+    metal5_ncap = metal5.not(mimtm_virtual).not(mimtm_stack2_virtual).not(mimtm_stack1_virtual) if METAL_LEVEL != '4LM'
   end
 
 end
diff --git a/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs b/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs
index 11cb015..0f0a15b 100644
--- a/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs
+++ b/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs
@@ -74,6 +74,7 @@
   end
   
   case MIM_CAP_STACK
+
   when '2'
   
       # cap_mim2f0 capacitor
@@ -81,8 +82,6 @@
 
       extract_devices(capacitor(cap_mim2f0, 2.0e-15, MIMCap), { 'P1' => mimtm_stack1_virtual,
                                                                 'P2' => fuse_cap, })
-      tolerance(cap_mim2f0, 'C', relative: 0.25)
-      
       extract_devices(capacitor(cap_mim2f0, 2.0e-15, MIMCap), { 'P1' => mimtm_stack2_virtual,  
                                                                 'P2' => fuse2_cap, })
       tolerance(cap_mim2f0, 'C', relative: 0.25)
@@ -94,8 +93,6 @@
       
       extract_devices(capacitor(cap_mim3f0, 3.0e-15, MIMCap), { 'P1' => mimtm_stack1_virtual,
                                                                 'P2' => fuse_cap, })
-      tolerance(cap_mim3f0, 'C', relative: 0.25)
-
       extract_devices(capacitor(cap_mim3f0, 3.0e-15, MIMCap), { 'P1' => mimtm_stack2_virtual,  
                                                                 'P2' => fuse2_cap, })
       tolerance(cap_mim3f0, 'C', relative: 0.25)
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds
new file mode 100644
index 0000000..fd1709c
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml
new file mode 100644
index 0000000..5cdd347
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m2m3_noshield:
+  -rd mim_option: "A"
+  -rd metal_level: "3LM"
+  -rd mim_cap: "1"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds
new file mode 100644
index 0000000..415d044
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml
new file mode 100644
index 0000000..652e54d
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m3m4_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "4LM"
+  -rd mim_cap: "1"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds
new file mode 100644
index 0000000..9777d8c
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml
new file mode 100644
index 0000000..4718dcb
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m4m5_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "5LM"
+  -rd mim_cap: "1"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds
new file mode 100644
index 0000000..97f0ad7
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml
new file mode 100644
index 0000000..e77a318
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m5m6_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "6LM"
+  -rd mim_cap: "1"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds
new file mode 100644
index 0000000..c36c36e
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml
new file mode 100644
index 0000000..a4ade5d
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml
@@ -0,0 +1,5 @@
+cap_mim_1f5_m2m3_noshield:
+  -rd mim_option: "A"
+  -rd metal_level: "3LM"
+  -rd mim_cap: "1.5"
+  
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds
new file mode 100644
index 0000000..0d275d1
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml
new file mode 100644
index 0000000..847938a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m3m4_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "4LM"
+  -rd mim_cap: "1.5"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds
new file mode 100644
index 0000000..83be00c
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml
new file mode 100644
index 0000000..353ebb4
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m4m5_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "5LM"
+  -rd mim_cap: "1.5"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds
new file mode 100644
index 0000000..54039ae
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml
new file mode 100644
index 0000000..781fbe8
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m5m6_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "6LM"
+  -rd mim_cap: "1.5"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.gds
new file mode 100644
index 0000000..0b9ce22
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.yaml
new file mode 100644
index 0000000..d6d92ba
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_2f0_m2m4_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "4LM"
+  -rd mim_cap_stack: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.gds
new file mode 100644
index 0000000..183a4f5
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.yaml
new file mode 100644
index 0000000..b16f754
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_2f0_m3m5_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "5LM"
+  -rd mim_cap_stack: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.gds
new file mode 100644
index 0000000..94fb19d
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.yaml
new file mode 100644
index 0000000..7e1db3f
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_2f0_m4m6_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "6LM"
+  -rd mim_cap_stack: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.gds
new file mode 100644
index 0000000..2499b86
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.yaml
new file mode 100644
index 0000000..8447ef4
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_single_2f0_m2m3_noshield:
+  -rd mim_option: "A"
+  -rd metal_level: "3LM"
+  -rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.gds
new file mode 100644
index 0000000..0efcff6
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.yaml
new file mode 100644
index 0000000..f98ba7a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_single_2f0_m3m4_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "4LM"
+  -rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.gds
new file mode 100644
index 0000000..1cde1f1
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.yaml
new file mode 100644
index 0000000..8f4830f
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_single_2f0_m4m5_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "5LM"
+  -rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.gds
new file mode 100644
index 0000000..1c81603
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.yaml
new file mode 100644
index 0000000..a816f4a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_single_2f0_m5m6_noshield:
+  -rd mim_option: "B"
+  -rd metal_level: "6LM"
+  -rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl
new file mode 100644
index 0000000..ba2c560
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_1f0_m2m3_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 10:39:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_1f0_m2m3_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=50.000u 
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=11.560u 
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=5.000u 
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=50.000u 
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=11.560u 
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=5.000u 
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=50.000u 
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=11.560u 
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=5.000u 
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m2m3_noshield M=1 l=5u w=5u 
++ c=0.031275p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl
new file mode 100644
index 0000000..674d7e6
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_1f0_m3m4_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_1f0_m3m4_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=50.000u 
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=11.560u 
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=5.000u 
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=50.000u 
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=11.560u 
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=5.000u 
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=50.000u 
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=11.560u 
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=5.000u 
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m3m4_noshield M=1 l=5u w=5u 
++ c=0.031275p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl
new file mode 100644
index 0000000..4918d52
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_1f0_m4m5_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_1f0_m4m5_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=50.000u 
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=11.560u 
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=5.000u 
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=50.000u 
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=11.560u 
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=5.000u 
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=50.000u 
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=11.560u 
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=5.000u 
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m4m5_noshield M=1 l=5u w=5u 
++ c=0.031275p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl
new file mode 100644
index 0000000..4bfabb6
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_1f0_m5m6_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_1f0_m5m6_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=50.000u 
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=11.560u 
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=5.000u 
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=50.000u 
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=11.560u 
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=5.000u 
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=50.000u 
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=11.560u 
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=5.000u 
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m5m6_noshield M=1 l=5u w=5u 
++ c=0.031275p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl
new file mode 100644
index 0000000..262610a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_1f5_m2m3_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 11:42:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_1f5_m2m3_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=100.000u 
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=12.340u 
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=5.000u 
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=100.000u 
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=12.340u 
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=5.000u 
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=100.000u 
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=12.340u 
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=5.000u 
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m2m3_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl
new file mode 100644
index 0000000..22327d8
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_1f5_m3m4_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_1f5_m3m4_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=100.000u 
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=12.340u 
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=5.000u 
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=100.000u 
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=12.340u 
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=5.000u 
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=100.000u 
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=12.340u 
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=5.000u 
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m3m4_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl
new file mode 100644
index 0000000..aa81915
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_1f5_m4m5_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_1f5_m4m5_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=100.000u 
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=12.340u 
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=5.000u 
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=100.000u 
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=12.340u 
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=5.000u 
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=100.000u 
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=12.340u 
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=5.000u 
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m4m5_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl
new file mode 100644
index 0000000..d657f55
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_1f5_m5m6_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_1f5_m5m6_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=100.000u 
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=12.340u 
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=5.000u 
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=100.000u 
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=12.340u 
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=5.000u 
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=100.000u 
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=12.340u 
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=5.000u 
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m5m6_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m4_noshield.cdl
new file mode 100644
index 0000000..888a326
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m4_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_2f0_m2m4_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_2f0_m2m4_noshield
+* View Name:    schematic
+************************************************************************
+.SUBCKT cap_mim_2f0_m2m4_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m2m4_noshield M=1 l=100.000u 
++ w=100.000u c=2e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m2m4_noshield M=1 l=100.000u 
++ w=100.000u c=2e-11
+
+.ENDS cap_mim_2f0_m2m4_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m5_noshield.cdl
new file mode 100644
index 0000000..1350b61
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m5_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_2f0_m3m5_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_2f0_m3m5_noshield
+* View Name:    schematic
+************************************************************************ 
+.SUBCKT cap_mim_2f0_m3m5_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m3m5_noshield M=1 l=100.000u 
++ w=100.000u c=2e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m3m5_noshield M=1 l=100.000u 
++ w=100.000u c=2e-11
+
+.ENDS cap_mim_2f0_m3m5_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m6_noshield.cdl
new file mode 100644
index 0000000..a19b204
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m6_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_2f0_m4m6_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_2f0_m4m6_noshield
+* View Name:    schematic
+************************************************************************  
+.SUBCKT cap_mim_2f0_m4m6_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m4m6_noshield M=1 l=100.000u 
++ w=100.000u c=2e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m4m6_noshield M=1 l=100.000u 
++ w=100.000u c=2e-11
+
+.ENDS cap_mim_2f0_m4m6_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m2m3_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m2m3_noshield.cdl
new file mode 100644
index 0000000..523b1ac
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_single_2f0_m2m3_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 10:53:54 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_single_2f0_m2m3_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_single_2f0_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=100.000u 
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=100.000u 
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=100.000u 
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=12.340u 
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=12.340u 
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=12.340u 
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5.000u 
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5.000u 
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5.000u 
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5u w=5u 
++ c=0.054516p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m3m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m3m4_noshield.cdl
new file mode 100644
index 0000000..4689f50
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_single_2f0_m3m4_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_single_2f0_m3m4_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_single_2f0_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=100.000u 
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=100.000u 
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=100.000u 
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=12.340u 
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=12.340u 
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=12.340u 
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5.000u 
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5.000u 
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5.000u 
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5u w=5u 
++ c=0.054516p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m4m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m4m5_noshield.cdl
new file mode 100644
index 0000000..30e708a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_single_2f0_m4m5_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_single_2f0_m4m5_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_single_2f0_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=100.000u 
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=100.000u 
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=100.000u 
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=12.340u 
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=12.340u 
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=12.340u 
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5.000u 
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5.000u 
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5.000u 
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5u w=5u 
++ c=0.054516p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m5m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m5m6_noshield.cdl
new file mode 100644
index 0000000..a5d4e30
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_mim_single_2f0_m5m6_noshield
+* View Name:     schematic
+* Netlisted on:  Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_mim_single_2f0_m5m6_noshield
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_mim_single_2f0_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP 
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT 
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP 
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT 
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I 
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I 
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I 
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I 
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=100.000u 
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=100.000u 
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=100.000u 
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=12.340u 
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=12.340u 
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=12.340u 
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5.000u 
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5.000u 
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5.000u 
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5u w=5u 
++ c=0.054516p
+.ENDS
+
diff --git a/Makefile b/Makefile
index 7b38c0d..6273977 100644
--- a/Makefile
+++ b/Makefile
@@ -22,6 +22,8 @@
 # https://docs.conda.io/projects/conda/en/latest/user-guide/tasks/manage-environments.html
 ENVIRONMENT_FILE := pdk_regression.yml
 
+KLAYOUT_LVS_TESTS := klayout/lvs/testing/
+
 include third_party/make-env/conda.mk
 
 # Lint python code
@@ -63,10 +65,28 @@
 ################################################################################
 ## LVS Regression section
 ################################################################################
-# LVS main testing
-test-LVS-main: | $(CONDA_ENV_PYTHON)
-	@$(IN_CONDA_ENV) klayout -v
+#=================================
+# ----- test-LVS_regression ------
+#=================================
 
-# LVS main testing
-test-LVS-switch: | $(CONDA_ENV_PYTHON)
-	@$(IN_CONDA_ENV) klayout -v
+# run regression on all variants` devices 
+.ONESHELL:
+test-LVS-main: | $(CONDA_ENV_PYTHON)
+	@$(IN_CONDA_ENV) cd IC/$(KLAYOUT_LVS_TESTS) && make test-LVS-main
+	@$(IN_CONDA_ENV) cd ULL/$(KLAYOUT_LVS_TESTS) && make test-LVS-main
+	@$(IN_CONDA_ENV) cd BCDLite/$(KLAYOUT_LVS_TESTS) && make test-LVS-main
+
+.ONESHELL:
+test-LVS-% : | $(CONDA_ENV_PYTHON)
+	@which python3
+ifeq ($(findstring ULL, $($*)), ULL)
+	cd ULL/$(KLAYOUT_LVS_TESTS) && make test-LVS-$(subst ULL-,,$($*))
+endif  
+
+ifeq ($(findstring IC, $($*)), IC)
+	cd IC/$(KLAYOUT_LVS_TESTS) && make test-LVS-$(subst IC-,,$($*))
+endif
+
+ifeq ($(findstring BCDLite, $($*)), BCDLite)
+	cd BCDLite/$(KLAYOUT_LVS_TESTS) && make test-LVS-$(subst BCDLite-,,$($*))
+endif
\ No newline at end of file
diff --git a/ULL/klayout/lvs/gf180ull.lvs b/ULL/klayout/lvs/gf180ull.lvs
index 554b08c..341633b 100644
--- a/ULL/klayout/lvs/gf180ull.lvs
+++ b/ULL/klayout/lvs/gf180ull.lvs
@@ -271,6 +271,24 @@
 
 # %include 'rule_decks/diode_derivations.lvs'
 
+#================================
+# ------ MOSCAP DERIVATIONS -----
+#================================
+
+# %include 'rule_decks/moscap_derivations.lvs'
+
+#===================================
+# ------ Varactor DERIVATIONS ------
+#===================================
+
+# %include 'rule_decks/varactor_derivations.lvs'
+
+#===================================
+# ------ PISCAP DERIVATIONS ------
+#===================================
+
+# %include 'rule_decks/piscap_derivations.lvs'
+
 #================================================
 #------------ DEVICES CONNECTIVITY --------------
 #================================================
@@ -302,11 +320,29 @@
 # %include 'rule_decks/res_extraction.lvs'
 
 #================================
-# ------- Diode EXTRACTION --------
+# ------- Diode EXTRACTION ------
 #================================
 
 # %include 'rule_decks/diode_extraction.lvs'
 
+#================================
+# ------- MOSCAP EXTRACTION -----
+#================================
+
+# %include 'rule_decks/moscap_extraction.lvs'
+
+#================================
+# ----- Varactor EXTRACTION ----
+#================================
+
+# %include 'rule_decks/varactor_extraction.lvs'
+
+#================================
+# ------ PISCAP EXTRACTION -----
+#================================
+
+# %include 'rule_decks/piscap_extraction.lvs'
+
 #================================================
 #------------- COMPARISON OPTIONS ---------------
 #================================================
diff --git a/ULL/klayout/lvs/rule_decks/custom_classes.lvs b/ULL/klayout/lvs/rule_decks/custom_classes.lvs
index 23f3250..11fcf5d 100644
--- a/ULL/klayout/lvs/rule_decks/custom_classes.lvs
+++ b/ULL/klayout/lvs/rule_decks/custom_classes.lvs
@@ -158,3 +158,23 @@
     enable_parameter('P', true)
   end
 end
+
+# Varactor class
+class VarCap < RBA::DeviceClassCapacitor
+  def initialize
+    super
+    enable_parameter("C", false)
+    enable_parameter("A", true)
+    enable_parameter("P", true)
+  end
+end
+
+# PISCAP class
+class PisCap < RBA::DeviceClassCapacitor
+  def initialize
+    super
+    enable_parameter("C", false)
+    enable_parameter("A", true)
+    enable_parameter("P", true)
+  end
+end
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/devices_connections.lvs b/ULL/klayout/lvs/rule_decks/devices_connections.lvs
index 9f86dd1..a0d119c 100644
--- a/ULL/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/ULL/klayout/lvs/rule_decks/devices_connections.lvs
@@ -65,7 +65,7 @@
 
 # Attaching labels
 connect(metal1, metal1_label)
-connect(metal2, metal2_label)
+connect(metal2_ncap, metal2_label)
 if METAL_LEVEL != '2LM'
   connect(metal3_ncap, metal3_label)
   if METAL_LEVEL != '3LM'
@@ -249,4 +249,13 @@
 
 connect(nplus_cont, contact)
 connect(pplus_cont, contact)
-connect(pplus_dw_cont, contact)
\ No newline at end of file
+connect(pplus_dw_cont, contact)
+
+#================================
+# ---- Varactor CONNECTIONS -----
+#================================
+
+connect(pn_varactor_1p8_tp ,contact)
+connect(pn_varactor_1p8_dw_tp ,contact)
+connect(pn_varactor_6p0_tp ,contact)
+connect(pn_varactor_6p0_dw_tp ,contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs b/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs
new file mode 100644
index 0000000..8f59869
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs
@@ -0,0 +1,93 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MOSCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting MOSCAP DERIVATIONS')
+
+# nmoscap_1p8 capacitor
+nmos_gate_1p8 = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).not(nwell).not(sab).not(esd)
+                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# nmoscap_1p8_dw capacitor
+nmos_gate_1p8_dw = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).not(nwell).not(sab).not(esd)
+                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# pmoscap_1p8 capacitor
+pmos_gate_1p8 = pgate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).not(sab).not(esd)
+                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# pmoscap_1p8_dw capacitor
+pmos_gate_1p8_dw = pgate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).not(sab).not(esd)
+                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# nmoscap_6p0 capacitor
+nmoscap_6p0_g = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).not(nwell).and(dv2).not(esd)
+                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+
+# nmoscap_6p0_dw capacitor
+nmoscap_6p0_dw_g = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).not(nwell).and(dv2).not(esd)
+                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+
+# pmoscap_6p0 capacitor
+pmoscap_6p0_g = pgate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).and(dv2).not(esd)
+                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+
+# pmoscap_6p0_dw capacitor
+pmoscap_6p0_dw_g = pgate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).and(dv2).not(esd)
+                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+
+# nmoscap_1p8_nwell capacitor
+nmoscap_1p8_nwell_g = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).not(sab)
+                        .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                        .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
+                        .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# nmoscap_1p8_dnwell capacitor
+nmoscap_1p8_dnwell_g = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).and(nwell).not(sab)
+                        .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                        .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
+                        .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# nmoscap_6p0_nwell capacitor
+nmoscap_6p0_nwell_g = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).and(dv2)
+                        .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                        .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
+                        .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+
+# nmoscap_6p0_dnwell capacitor
+nmoscap_6p0_dnwell_g = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).and(nwell).and(dv2)
+                        .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+                        .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
+                        .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
diff --git a/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs b/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs
new file mode 100644
index 0000000..99c0318
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs
@@ -0,0 +1,84 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- MOSCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting MOSCAP EXTRACTION')
+
+# nmoscap_1p8
+logger.info('Extracting nmoscap_1p8 device')
+extract_devices(capacitor('nmoscap_1p8', 4.4e-15, MosCap),
+                { 'P1' => nmos_gate_1p8, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+# nmoscap_1p8_dw
+logger.info('Extracting nmoscap_1p8_dw device')
+extract_devices(capacitor('nmoscap_1p8_dw', 4.4e-15, MosCap),
+                { 'P1' => nmos_gate_1p8_dw, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+# pmoscap_1p8
+logger.info('Extracting pmoscap_1p8 device')
+extract_devices(capacitor('pmoscap_1p8', 4.4e-15, MosCap),
+                { 'P1' => pmos_gate_1p8, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => psd })
+
+# pmoscap_1p8_dw
+logger.info('Extracting pmoscap_1p8_dw device')
+extract_devices(capacitor('pmoscap_1p8_dw', 4.4e-15, MosCap),
+                { 'P1' => pmos_gate_1p8_dw, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => psd_dw })
+
+# nmoscap_6p0
+logger.info('Extracting nmoscap_6p0 device')
+extract_devices(capacitor('nmoscap_6p0', 2.3e-15, MosCap),
+                { 'P1' => nmoscap_6p0_g, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+# nmoscap_6p0_dw
+logger.info('Extracting nmoscap_6p0_dw device')
+extract_devices(capacitor('nmoscap_6p0_dw', 2.3e-15, MosCap),
+                { 'P1' => nmoscap_6p0_dw_g, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+# pmoscap_6p0
+logger.info('Extracting pmoscap_6p0 device')
+extract_devices(capacitor('pmoscap_6p0', 2.3e-15, MosCap),
+                { 'P1' => pmoscap_6p0_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => psd })
+
+# pmoscap_6p0_dw
+logger.info('Extracting pmoscap_6p0_dw device')
+extract_devices(capacitor('pmoscap_6p0_dw', 2.3e-15, MosCap),
+                { 'P1' => pmoscap_6p0_dw_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => psd_dw })
+
+
+# nmoscap_1p8_nwell capacitor
+logger.info('Extracting nmoscap_1p8_nwell device')
+extract_devices(capacitor('nmoscap_1p8_nwell', 4.4e-15, MosCap),
+                { 'P1' => nmoscap_1p8_nwell_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+# nmoscap_1p8_dnwell capacitor
+logger.info('Extracting nmoscap_1p8_dnwell device')
+extract_devices(capacitor('nmoscap_1p8_dnwell', 4.4e-15, MosCap),
+                { 'P1' => nmoscap_1p8_dnwell_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
+
+# nmoscap_6p0_nwell capacitor
+logger.info('Extracting nmoscap_6p0_nwell device')
+extract_devices(capacitor('nmoscap_6p0_nwell', 2.3e-15, MosCap),
+                { 'P1' => nmoscap_6p0_nwell_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+# nmoscap_6p0_dnwell capacitor
+logger.info('Extracting nmoscap_6p0_dnwell device')
+extract_devices(capacitor('nmoscap_6p0_dnwell', 2.3e-15, MosCap),
+                { 'P1' => nmoscap_6p0_dnwell_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
+
+
diff --git a/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs b/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
new file mode 100644
index 0000000..1ace25a
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
@@ -0,0 +1,41 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ PISCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting PISCAP DERIVATIONS')
+
+piscap_exclude_layers = mos_cap_mk.or(sab).or(esd).or(polyfuse).or(cap_mk).or(diode_mk).or(nat)
+                            .or(v5_xtor).or(drc_bjt).or(lvs_bjt).or(fhres)
+                            .or(fusewindow_d).or(lvs_rf).or(fusetop).or(resistor)
+
+# pis_1p8 (1.8V PIS capacitor (outside DNWELL))
+pis_1p8_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).not(dnwell)
+                        .not(dualgate).not(dv2).not(piscap_exclude_layers)
+
+# pis_1p8_dw (1.8V PIS capacitor (inside DNWEL)
+pis_1p8_dw_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).inside(dnwell)
+                        .not(dualgate).not(dv2).not(piscap_exclude_layers)
+
+# pis_6p0 (6V PIS capacitor (outside DNWELL))
+pis_6p0_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).not(dnwell)
+                        .and(dv2).not(piscap_exclude_layers)
+
+# pis_6p0_dw (6V PIS capacitor (inside DNWEL)
+pis_6p0_dw_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).inside(dnwell)
+                            .and(dv2).not(piscap_exclude_layers)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs b/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
new file mode 100644
index 0000000..d24e852
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
@@ -0,0 +1,41 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- PISCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting PISCAP EXTRACTION')
+
+# pis_1p8 (1.8V PIS capacitor (outside DNWELL))
+logger.info('Extracting pis_1p8 device')
+extract_devices(capacitor('piscap_1p8', 4.4e-15, PisCap),
+                { 'P1' => pis_1p8_gate, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+# pis_1p8_dw (1.8V PIS capacitor (inside DNWEL)
+logger.info('Extracting pis_1p8_dw device')
+extract_devices(capacitor('piscap_1p8_dw', 4.4e-15, PisCap),
+                { 'P1' => pis_1p8_dw_gate, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
+
+# pis_6p0 (6V PIS capacitor (outside DNWELL))
+logger.info('Extracting pis_6p0 device')
+extract_devices(capacitor('piscap_6p0', 4.4e-15, PisCap),
+                { 'P1' => pis_6p0_gate, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+# pis_6p0_dw (6V PIS capacitor (inside DNWEL)
+logger.info('Extracting pis_6p0_dw device')
+extract_devices(capacitor('piscap_6p0_dw', 4.4e-15, PisCap),
+                { 'P1' => pis_6p0_dw_gate, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs b/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
new file mode 100644
index 0000000..b2ff75a
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
@@ -0,0 +1,51 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor DERIVATIONS ----
+#================================
+
+logger.info('Starting VARACTOR DERIVATIONS')
+
+exclude_layers = v5_xtor.or(fusetop).or(polyfuse).or(dualgate)
+                    .or(lvs_bjt).or(drc_bjt).or(sab).or(esd).or(resistor).or(res_mk)
+                    .or(cap_mk).or(nat).or(fhres).or(fusewindow_d).or(diode_mk)
+                    .or(piscap).or(mos_cap_mk).or(mim_l_mk)
+
+# pn_varactor_1p8
+pn_varactor_1p8_tp = pcomp.outside(dnwell).inside(nwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# pn_varactor_1p8_dw
+pn_varactor_1p8_dw_tp = pcomp.inside(dnwell).inside(nwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# pn_varactor_6p0
+pn_varactor_6p0_tp = pcomp.outside(dnwell).inside(nwell).and(lvs_rf).and(dv2).not(exclude_layers)
+
+# pn_varactor_6p0_dw
+pn_varactor_6p0_dw_tp = pcomp.inside(dnwell).inside(nwell).and(lvs_rf).and(dv2).not(exclude_layers)
+        
+
+# mos_varactor_1p8
+mos_varactor_1p8_g = ngate.inside(nwell).outside(dnwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# mos_varactor_1p8_dw
+mos_varactor_1p8_dw_g = ngate.inside(nwell).inside(dnwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# mos_varactor_6p0
+mos_varactor_6p0_g = ngate.inside(nwell).outside(dnwell).and(lvs_rf).and(dv2).not(exclude_layers)
+
+# mos_varactor_6p0_dw
+mos_varactor_6p0_dw_g = ngate.inside(nwell).inside(dnwell).and(lvs_rf).and(dv2).not(exclude_layers)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs b/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
new file mode 100644
index 0000000..1ef4ffe
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
@@ -0,0 +1,69 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor EXTRACTION ----
+#================================
+
+logger.info('Starting VARACTOR EXTRACTION')
+
+# pn_varactor_1p8
+logger.info('Extracting pn_varactor_1p8')
+extract_devices(capacitor('pn_varactor_1p8', 4.4e-15, VarCap),
+                 { "P1" => pn_varactor_1p8_tp, "P2" => nwell_con,
+                  "tA" => pn_varactor_1p8_tp, "tB" => nwell_con })
+
+# pn_varactor_1p8_dw
+logger.info('Extracting pn_varactor_1p8_dw')
+extract_devices(capacitor('pn_varactor_1p8_dw', 4.4e-15, VarCap),
+                 { "P1" => pn_varactor_1p8_dw_tp, "P2" => dnwell,
+                  "tA" => pn_varactor_1p8_dw_tp, "tB" => dnwell })
+
+# pn_varactor_6p0
+logger.info('Extracting pn_varactor_6p0')
+extract_devices(capacitor('pn_varactor_6p0', 4.4e-15, VarCap),
+                 { "P1" => pn_varactor_6p0_tp, "P2" => nwell_con,
+                  "tA" => pn_varactor_6p0_tp, "tB" => nwell_con })
+
+# pn_varactor_6p0_dw
+logger.info('Extracting pn_varactor_6p0_dw')
+extract_devices(capacitor('pn_varactor_6p0_dw', 4.4e-15, VarCap),
+                 { "P1" => pn_varactor_6p0_dw_tp, "P2" => dnwell,
+                  "tA" => pn_varactor_6p0_dw_tp, "tB" => dnwell })
+
+# mos_varactor_1p8
+logger.info('Extracting mos_varactor_1p8')
+extract_devices(capacitor('mos_varactor_1p8', 4.4e-15, VarCap),
+                { 'P1' => mos_varactor_1p8_g, 'P2' => nwell_con,
+                 'tA' => poly2_con, 'tB' => ntap })
+
+# mos_varactor_1p8_dw
+logger.info('Extracting mos_varactor_1p8_dw')
+extract_devices(capacitor('mos_varactor_1p8_dw', 4.4e-15, VarCap),
+                { 'P1' => mos_varactor_1p8_dw_g, 'P2' => dnwell,
+                 'tA' => poly2_con, 'tB' => ntap })
+
+# mos_varactor_6p0
+logger.info('Extracting mos_varactor_6p0')
+extract_devices(capacitor('mos_varactor_6p0', 4.4e-15, VarCap),
+                { 'P1' => mos_varactor_6p0_g, 'P2' => nwell_con,
+                 'tA' => poly2_con, 'tB' => ntap })
+
+# mos_varactor_6p0_dw
+logger.info('Extracting mos_varactor_6p0_dw')
+extract_devices(capacitor('mos_varactor_6p0_dw', 4.4e-15, VarCap),
+                { 'P1' => mos_varactor_6p0_dw_g, 'P2' => dnwell,
+                 'tA' => poly2_con, 'tB' => ntap })
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8.gds
new file mode 100644
index 0000000..16ab300
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dnwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dnwell.gds
new file mode 100644
index 0000000..07997de
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dnwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dw.gds
new file mode 100644
index 0000000..3559daf
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_nwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_nwell.gds
new file mode 100644
index 0000000..d409b7f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_nwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0.gds
new file mode 100644
index 0000000..b7b05bb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dnwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dnwell.gds
new file mode 100644
index 0000000..b4c9a71
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dnwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dw.gds
new file mode 100644
index 0000000..14b3eab
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_nwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_nwell.gds
new file mode 100644
index 0000000..86d96d4
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_nwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8.gds
new file mode 100644
index 0000000..08d8d04
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8_dw.gds
new file mode 100644
index 0000000..c7f73a6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0.gds
new file mode 100644
index 0000000..0e678ed
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0_dw.gds
new file mode 100644
index 0000000..e0bd3fd
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8.cdl
new file mode 100644
index 0000000..d0f6935
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: nmoscap_1p8
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    nmoscap_1p8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT nmoscap_1p8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_1p8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dnwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dnwell.cdl
new file mode 100644
index 0000000..0e7e9ad
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dnwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: nmoscap_1p8_dnwell
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:11:11 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    nmoscap_1p8_dnwell
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT nmoscap_1p8_dnwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8_dnwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8_dnwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8_dnwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8_dnwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8_dnwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8_dnwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8_dnwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8_dnwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8_dnwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_1p8_dnwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dw.cdl
new file mode 100644
index 0000000..e5823d4
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: nmoscap_1p8_dw
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:12:27 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    nmoscap_1p8_dw
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT nmoscap_1p8_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_1p8_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_nwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_nwell.cdl
new file mode 100644
index 0000000..648f007
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_nwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: nmoscap_1p8_nwell
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:11:11 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    nmoscap_1p8_nwell
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT nmoscap_1p8_nwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8_nwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8_nwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8_nwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8_nwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8_nwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8_nwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8_nwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8_nwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8_nwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_1p8_nwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0.cdl
new file mode 100644
index 0000000..508a56c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: nmoscap_6p0
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:13:17 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    nmoscap_6p0
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT nmoscap_6p0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_6p0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dnwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dnwell.cdl
new file mode 100644
index 0000000..9e8092b
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dnwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: nmoscap_6p0_dnwell
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:14:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    nmoscap_6p0_dnwell
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT nmoscap_6p0_dnwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0_dnwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0_dnwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0_dnwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0_dnwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0_dnwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0_dnwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0_dnwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0_dnwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0_dnwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_6p0_dnwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dw.cdl
new file mode 100644
index 0000000..2515b81
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: nmoscap_6p0_dw
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:15:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    nmoscap_6p0_dw
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT nmoscap_6p0_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_6p0_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_nwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_nwell.cdl
new file mode 100644
index 0000000..e618d63
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_nwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: nmoscap_6p0_nwell
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:14:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    nmoscap_6p0_nwell
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT nmoscap_6p0_nwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0_nwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0_nwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0_nwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0_nwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0_nwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0_nwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0_nwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0_nwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0_nwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_6p0_nwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8.cdl
new file mode 100644
index 0000000..3f04861
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: pmoscap_1p8
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:44:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    pmoscap_1p8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT pmoscap_1p8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_1p8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_1p8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_1p8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_1p8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_1p8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_1p8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_1p8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_1p8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_1p8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D pmoscap_1p8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8_dw.cdl
new file mode 100644
index 0000000..bcd13a6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: pmoscap_1p8_dw
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:45:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    pmoscap_1p8_dw
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT pmoscap_1p8_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_1p8_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_1p8_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_1p8_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_1p8_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_1p8_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_1p8_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_1p8_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_1p8_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_1p8_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D pmoscap_1p8_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0.cdl
new file mode 100644
index 0000000..f9c0f84
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: pmoscap_6p0
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:47:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    pmoscap_6p0
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT pmoscap_6p0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_6p0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_6p0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_6p0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_6p0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_6p0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_6p0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_6p0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_6p0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_6p0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D pmoscap_6p0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0_dw.cdl
new file mode 100644
index 0000000..01d0eb8
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: pmoscap_6p0_dw
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:48:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    pmoscap_6p0_dw
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT pmoscap_6p0_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_6p0_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_6p0_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_6p0_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_6p0_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_6p0_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_6p0_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_6p0_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_6p0_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_6p0_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D pmoscap_6p0_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds
new file mode 100644
index 0000000..d6a4e5f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds
new file mode 100644
index 0000000..26bb5ed
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds
new file mode 100644
index 0000000..c91e63c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds
new file mode 100644
index 0000000..1638d1c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl
new file mode 100644
index 0000000..811a4ce
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: piscap_1p8
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    piscap_1p8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT piscap_1p8 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_1p8 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_1p8 m=1 l=5.88u w=5u
+.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
new file mode 100644
index 0000000..88262cb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
@@ -0,0 +1,34 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: piscap_1p8_dw
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    piscap_1p8_dw
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT piscap_1p8_dw I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_1p8_dw m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_1p8_dw m=1 l=5.88u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl
new file mode 100644
index 0000000..a8bc9a5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: piscap_6p0
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    piscap_6p0
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT piscap_6p0 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_6p0 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_6p0 m=1 l=5.88u w=5u
+.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl
new file mode 100644
index 0000000..ad8c71e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: piscap_6p0_dw
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    piscap_6p0_dw
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT piscap_6p0_dw I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_6p0_dw m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_6p0_dw m=1 l=5.88u w=5u
+.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds
new file mode 100644
index 0000000..7efb14d
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds
new file mode 100644
index 0000000..6893fe8
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds
new file mode 100644
index 0000000..7a85d9f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds
new file mode 100644
index 0000000..280f16e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds
new file mode 100644
index 0000000..0bcb398
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds
new file mode 100644
index 0000000..576a490
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds
new file mode 100644
index 0000000..a91f22d
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds
new file mode 100644
index 0000000..ddbf511
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl
new file mode 100644
index 0000000..80daea9
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: mos_varactor_1p8
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    mos_varactor_1p8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT mos_varactor_1p8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G 
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_1p8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_1p8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_1p8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_1p8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_1p8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_1p8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_1p8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_1p8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_1p8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_1p8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl
new file mode 100644
index 0000000..918db43
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: mos_varactor_1p8_dw
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:12:27 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    mos_varactor_1p8_dw
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT mos_varactor_1p8_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G 
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_1p8_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl
new file mode 100644
index 0000000..47c6313
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: mos_varactor_6p0
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:13:17 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    mos_varactor_6p0
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT mos_varactor_6p0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_6p0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_6p0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_6p0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_6p0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_6p0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_6p0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_6p0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_6p0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_6p0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_6p0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl
new file mode 100644
index 0000000..05f01ad
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: mos_varactor_6p0_dw
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:15:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    mos_varactor_6p0_dw
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT mos_varactor_6p0_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_6p0_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl
new file mode 100644
index 0000000..5395cc5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: pn_varactor_1p8
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:49:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    pn_varactor_1p8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT pn_varactor_1p8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS 
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS 
++ I1_default_MINUS I1_default_PLUS 
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS pn_varactor_1p8 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_1p8 m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl
new file mode 100644
index 0000000..adc3e1b
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: pn_varactor_1p8_dw
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:50:00 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    pn_varactor_1p8_dw
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT pn_varactor_1p8_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS 
++ I1_default_PLUS I1_default_MINUS 
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_1p8_dw m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl
new file mode 100644
index 0000000..7a8a560
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: pn_varactor_6p0
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:50:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    pn_varactor_6p0
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT pn_varactor_6p0 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS 
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS 
++ I1_default_MINUS I1_default_PLUS 
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS pn_varactor_6p0 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_6p0 m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl
new file mode 100644
index 0000000..e7361a4
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: pn_varactor_6p0_dw
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:51:10 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    pn_varactor_6p0_dw
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT pn_varactor_6p0_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS 
++ I1_default_PLUS I1_default_MINUS 
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_6p0_dw m=1 L=1u W=1u
+.ENDS
+