diff --git a/BCDLite/klayout/lvs/rule_decks/moscap_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/moscap_derivations.lvs
index 163c04c..979a783 100644
--- a/BCDLite/klayout/lvs/rule_decks/moscap_derivations.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/moscap_derivations.lvs
@@ -36,8 +36,8 @@
                          .join(swfet_mk).join(hvnddd).join(hvpddd)
                          .join(hvpolyrs).join(ldmos_xtor)
 
-ngate_lv = ngate.not(dualgate2_d).and(mos_cap_mk)
-ngate_mv = ngate.and(dualgate2_d).and(mos_cap_mk)
+ngate_lv = nplus.and(tgate).not(dualgate2_d).and(mos_cap_mk)
+ngate_mv = nplus.and(tgate).and(dualgate2_d).and(mos_cap_mk)
 
 ngate_lv_nw = ngate_lv.and(nwell)
 ngate_lv_n_nw = ngate_lv.not(nwell)
@@ -45,8 +45,8 @@
 ngate_mv_nw = ngate_mv.and(nwell)
 ngate_mv_n_nw = ngate_mv.not(nwell)
 
-pgate_lv = pgate.not(dualgate2_d).and(mos_cap_mk)
-pgate_mv = pgate.and(dualgate2_d).and(mos_cap_mk)
+pgate_lv = pplus.and(tgate).not(dualgate2_d).and(mos_cap_mk)
+pgate_mv = pplus.and(tgate).and(dualgate2_d).and(mos_cap_mk)
 
 #=====================
 # --- NMOS 1P8 CAP ---
diff --git a/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs
index 72dea73..a36397e 100644
--- a/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs
@@ -32,7 +32,7 @@
                         .join(mos_mk_type1).join(swfet_mk).join(lvs_35v)
                         .join(hvpddd).join(hvpolyrs).join(ldmos_xtor)
 
-ngate_nw = ngate.and(piscap).and(nwell).not(piscap_exclude)
+ngate_nw = nplus.and(tgate).and(piscap).and(nwell).not(piscap_exclude)
 
 ngate_nw_lv = ngate_nw.not(dualgate2_d)
 ngate_nw_mv = ngate_nw.and(dualgate2_d)
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
index aff1b79..7e7fa00 100644
--- a/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
@@ -40,7 +40,7 @@
                      .join(hvpddd).join(hvpolyrs).join(ldmos_xtor)
 
 pcomp_nw_var = pcomp.and(nwell).and(lvs_rf).not(poly2).not(var_exclude)
-ngate_nw_var = ngate.and(nwell).and(lvs_rf).not(var_exclude)
+ngate_nw_var = nplus.and(tgate).and(nwell).and(lvs_rf).not(var_exclude)
 
 pcomp_nw_var_lv = pcomp_nw_var.not(dualgate2_d)
 pcomp_nw_var_mv = pcomp_nw_var.and(dualgate2_d)
diff --git a/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs b/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs
index 00433fb..78e569d 100644
--- a/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs
@@ -20,74 +20,47 @@
 
 logger.info('Starting MOSCAP DERIVATIONS')
 
+moscap_exclude = sab.join(esd).join(polyfuse)
+                    .join(cap_mk).join(diode_mk).join(nat)
+                    .join(v5_xtor).join(drc_bjt).join(lvs_bjt)
+                    .join(fhres).join(fusewindow_d).join(piscap)
+                    .join(mim_l_mk).join(fusetop).join(resistor)
+
+moscap_ngate = nplus.and(tgate).interacting(mos_cap_mk)
+moscap_pgate = pplus.and(tgate).interacting(mos_cap_mk)
+
 # nmoscap_1p8 capacitor
-nmos_gate_1p8 = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).not(nwell).not(sab).not(esd)
-                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
-                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+nmos_gate_1p8 = moscap_ngate.not(nwell).not(dnwell).not(dv2).not(dualgate)
 
 # nmoscap_1p8_dw capacitor
-nmos_gate_1p8_dw = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).not(nwell).not(sab).not(esd)
-                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
-                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+nmos_gate_1p8_dw = moscap_ngate.and(dnwell).not(nwell).not(dv2).not(dualgate)
 
 # pmoscap_1p8 capacitor
-pmos_gate_1p8 = pgate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).not(sab).not(esd)
-                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
-                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+pmos_gate_1p8 = pgate.not(dnwell).and(nwell).not(dv2).not(dualgate)
 
 # pmoscap_1p8_dw capacitor
-pmos_gate_1p8_dw = pgate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).not(sab).not(esd)
-                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
-                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+pmos_gate_1p8_dw = pgate.and(dnwell).not(dv2).not(dualgate)
 
 # nmoscap_6p0 capacitor
-nmoscap_6p0_g = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).not(nwell).and(dv2).not(esd)
-                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
-                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+nmoscap_6p0_g = moscap_ngate.not(nwell).not(dnwell).and(dv2).not(dualgate)
 
 # nmoscap_6p0_dw capacitor
-nmoscap_6p0_dw_g = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).not(nwell).and(dv2).not(esd)
-                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
-                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+nmoscap_6p0_dw_g = moscap_ngate.and(dnwell).not(nwell).and(dv2).not(dualgate)
 
 # pmoscap_6p0 capacitor
-pmoscap_6p0_g = pgate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).and(dv2).not(esd)
-                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
-                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+pmoscap_6p0_g = pgate.not(dnwell).and(nwell).and(dv2).not(dualgate)
 
 # pmoscap_6p0_dw capacitor
-pmoscap_6p0_dw_g = pgate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).and(dv2).not(esd)
-                    .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                    .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
-                    .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+pmoscap_6p0_dw_g = pgate.and(dnwell).and(dv2).not(dualgate)
 
 # nmoscap_1p8_nwell capacitor
-nmoscap_1p8_nwell_g = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).not(sab)
-                        .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                        .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
-                        .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+nmoscap_1p8_nwell_g = moscap_ngate.not(dnwell).and(nwell).not(dv2).not(dualgate)
 
 # nmoscap_1p8_dnwell capacitor
-nmoscap_1p8_dnwell_g = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).and(nwell).not(sab)
-                        .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                        .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
-                        .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+nmoscap_1p8_dnwell_g = moscap_ngate.and(nwell).and(dnwell).not(dv2).not(dualgate)
 
 # nmoscap_6p0_nwell capacitor
-nmoscap_6p0_nwell_g = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).and(dv2)
-                        .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                        .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
-                        .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+nmoscap_6p0_nwell_g = moscap_ngate.not(dnwell).and(nwell).and(dv2).not(dualgate)
 
 # nmoscap_6p0_dnwell capacitor
-nmoscap_6p0_dnwell_g = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).and(nwell).and(dv2)
-                        .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
-                        .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
-                        .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+nmoscap_6p0_dnwell_g = moscap_ngate.and(nwell).and(dnwell).and(dv2).not(dualgate)
diff --git a/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs b/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs
index b3db44b..f95dc82 100644
--- a/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs
+++ b/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs
@@ -20,65 +20,63 @@
 
 logger.info('Starting MOSCAP EXTRACTION')
 
-# nmoscap_1p8
-logger.info('Extracting nmoscap_1p8 device')
-extract_devices(capacitor('nmoscap_1p8', 4.4e-15, MosCap),
+# cap_nmos_01v8
+logger.info('Extracting cap_nmos_01v8 device')
+extract_devices(capacitor('cap_nmos_01v8', 4.4e-15, MosCap),
                 { 'P1' => nmos_gate_1p8, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
 
-# nmoscap_1p8_dw
-logger.info('Extracting nmoscap_1p8_dw device')
-extract_devices(capacitor('nmoscap_1p8_dw', 4.4e-15, MosCap),
+# cap_nmos_01v8_dn
+logger.info('Extracting cap_nmos_01v8_dn device')
+extract_devices(capacitor('cap_nmos_01v8_dn', 4.4e-15, MosCap),
                 { 'P1' => nmos_gate_1p8_dw, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
 
-# pmoscap_1p8
-logger.info('Extracting pmoscap_1p8 device')
-extract_devices(capacitor('pmoscap_1p8', 4.4e-15, MosCap),
+# cap_pmos_01v8
+logger.info('Extracting cap_pmos_01v8 device')
+extract_devices(capacitor('cap_pmos_01v8', 4.4e-15, MosCap),
                 { 'P1' => pmos_gate_1p8, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => psd })
 
-# pmoscap_1p8_dw
-logger.info('Extracting pmoscap_1p8_dw device')
-extract_devices(capacitor('pmoscap_1p8_dw', 4.4e-15, MosCap),
+# cap_pmos_01v8_dn
+logger.info('Extracting cap_pmos_01v8_dn device')
+extract_devices(capacitor('cap_pmos_01v8_dn', 4.4e-15, MosCap),
                 { 'P1' => pmos_gate_1p8_dw, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => psd_dn })
 
-# nmoscap_6p0
-logger.info('Extracting nmoscap_6p0 device')
-extract_devices(capacitor('nmoscap_6p0', 2.3e-15, MosCap),
+# cap_nmos_06v0
+logger.info('Extracting cap_nmos_06v0 device')
+extract_devices(capacitor('cap_nmos_06v0', 2.3e-15, MosCap),
                 { 'P1' => nmoscap_6p0_g, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
 
-# nmoscap_6p0_dw
-logger.info('Extracting nmoscap_6p0_dw device')
-extract_devices(capacitor('nmoscap_6p0_dw', 2.3e-15, MosCap),
+# cap_nmos_06v0_dn
+logger.info('Extracting cap_nmos_06v0_dn device')
+extract_devices(capacitor('cap_nmos_06v0_dn', 2.3e-15, MosCap),
                 { 'P1' => nmoscap_6p0_dw_g, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
 
-# pmoscap_6p0
-logger.info('Extracting pmoscap_6p0 device')
-extract_devices(capacitor('pmoscap_6p0', 2.3e-15, MosCap),
+# cap_pmos_06v0
+logger.info('Extracting cap_pmos_06v0 device')
+extract_devices(capacitor('cap_pmos_06v0', 2.3e-15, MosCap),
                 { 'P1' => pmoscap_6p0_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => psd })
 
-# pmoscap_6p0_dw
-logger.info('Extracting pmoscap_6p0_dw device')
-extract_devices(capacitor('pmoscap_6p0_dw', 2.3e-15, MosCap),
+# cap_pmos_06v0_dn
+logger.info('Extracting cap_pmos_06v0_dn device')
+extract_devices(capacitor('cap_pmos_06v0_dn', 2.3e-15, MosCap),
                 { 'P1' => pmoscap_6p0_dw_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => psd_dn })
 
-
-# nmoscap_1p8_nwell capacitor
-logger.info('Extracting nmoscap_1p8_nwell device')
-extract_devices(capacitor('nmoscap_1p8_nwell', 4.4e-15, MosCap),
+# cap_nmos_01v8_nwell capacitor
+logger.info('Extracting cap_nmos_01v8_nwell device')
+extract_devices(capacitor('cap_nmos_01v8_nwell', 4.4e-15, MosCap),
                 { 'P1' => nmoscap_1p8_nwell_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
 
-# nmoscap_1p8_dnwell capacitor
-logger.info('Extracting nmoscap_1p8_dnwell device')
-extract_devices(capacitor('nmoscap_1p8_dnwell', 4.4e-15, MosCap),
+# cap_nmos_01v8_dnwell capacitor
+logger.info('Extracting cap_nmos_01v8_dnwell device')
+extract_devices(capacitor('cap_nmos_01v8_dnwell', 4.4e-15, MosCap),
                 { 'P1' => nmoscap_1p8_dnwell_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
 
-# nmoscap_6p0_nwell capacitor
-logger.info('Extracting nmoscap_6p0_nwell device')
-extract_devices(capacitor('nmoscap_6p0_nwell', 2.3e-15, MosCap),
+# cap_nmos_06v0_nwell capacitor
+logger.info('Extracting cap_nmos_06v0_nwell device')
+extract_devices(capacitor('cap_nmos_06v0_nwell', 2.3e-15, MosCap),
                 { 'P1' => nmoscap_6p0_nwell_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
 
-# nmoscap_6p0_dnwell capacitor
-logger.info('Extracting nmoscap_6p0_dnwell device')
-extract_devices(capacitor('nmoscap_6p0_dnwell', 2.3e-15, MosCap),
+# cap_nmos_06v0_dnwell capacitor
+logger.info('Extracting cap_nmos_06v0_dnwell device')
+extract_devices(capacitor('cap_nmos_06v0_dnwell', 2.3e-15, MosCap),
                 { 'P1' => nmoscap_6p0_dnwell_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
 
-
diff --git a/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs b/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
index 5ca4166..72851df 100644
--- a/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
@@ -20,22 +20,22 @@
 
 logger.info('Starting PISCAP DERIVATIONS')
 
-piscap_exclude_layers = mos_cap_mk.or(sab).or(esd).or(polyfuse).or(cap_mk).or(diode_mk).or(nat)
-                            .or(v5_xtor).or(drc_bjt).or(lvs_bjt).or(fhres)
-                            .or(fusewindow_d).or(lvs_rf).or(fusetop).or(resistor)
+piscap_exclude = mos_cap_mk.join(sab).join(esd)
+                            .join(polyfuse).join(cap_mk).join(diode_mk)
+                            .join(nat).join(v5_xtor).join(drc_bjt)
+                            .join(lvs_bjt).join(fhres).join(fusewindow_d)
+                            .join(lvs_rf).join(fusetop).join(resistor)
+
+pis_ngate = nplus.and(tgate).and(nwell).and(piscap).interacting(mim_l_mk).not(piscap_exclude)
 
 # pis_1p8 (1.8V PIS capacitor (outside DNWELL))
-pis_1p8_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).not(dnwell)
-                        .not(dualgate).not(dv2).not(piscap_exclude_layers)
+pis_1p8_gate = pis_ngate.not(dnwell).not(dualgate).not(dv2)
 
 # pis_1p8_dw (1.8V PIS capacitor (inside DNWEL)
-pis_1p8_dw_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).inside(dnwell)
-                        .not(dualgate).not(dv2).not(piscap_exclude_layers)
+pis_1p8_dw_gate = pis_ngate.and(dnwell).not(dualgate).not(dv2)
 
 # pis_6p0 (6V PIS capacitor (outside DNWELL))
-pis_6p0_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).not(dnwell)
-                        .and(dv2).not(piscap_exclude_layers)
+pis_6p0_gate = pis_ngate.not(dnwell).and(dv2).not(dualgate)
 
 # pis_6p0_dw (6V PIS capacitor (inside DNWEL)
-pis_6p0_dw_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).inside(dnwell)
-                            .and(dv2).not(piscap_exclude_layers)
\ No newline at end of file
+pis_6p0_dw_gate = pis_ngate.and(dnwell).and(dv2).not(dualgate)
diff --git a/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs b/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
index 3fab5fa..55bd279 100644
--- a/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
+++ b/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
@@ -20,22 +20,22 @@
 
 logger.info('Starting PISCAP EXTRACTION')
 
-# pis_1p8 (1.8V PIS capacitor (outside DNWELL))
-logger.info('Extracting pis_1p8 device')
-extract_devices(capacitor('piscap_1p8', 4.4e-15, PisCap),
+# cap_pis_01v8 (1.8V PIS capacitor (outside DNWELL))
+logger.info('Extracting cap_pis_01v8 device')
+extract_devices(capacitor('cap_pis_01v8', 4.4e-15, PisCap),
                 { 'P1' => pis_1p8_gate, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
 
-# pis_1p8_dw (1.8V PIS capacitor (inside DNWEL)
-logger.info('Extracting pis_1p8_dw device')
-extract_devices(capacitor('piscap_1p8_dw', 4.4e-15, PisCap),
+# cap_pis_01v8_dn (1.8V PIS capacitor (inside DNWEL)
+logger.info('Extracting cap_pis_01v8_dn device')
+extract_devices(capacitor('cap_pis_01v8_dn', 4.4e-15, PisCap),
                 { 'P1' => pis_1p8_dw_gate, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
 
-# pis_6p0 (6V PIS capacitor (outside DNWELL))
-logger.info('Extracting pis_6p0 device')
-extract_devices(capacitor('piscap_6p0', 4.4e-15, PisCap),
+# cap_pis_06v0 (6V PIS capacitor (outside DNWELL))
+logger.info('Extracting cap_pis_06v0 device')
+extract_devices(capacitor('cap_pis_06v0', 4.4e-15, PisCap),
                 { 'P1' => pis_6p0_gate, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
 
-# pis_6p0_dw (6V PIS capacitor (inside DNWEL)
-logger.info('Extracting pis_6p0_dw device')
-extract_devices(capacitor('piscap_6p0_dw', 4.4e-15, PisCap),
+# cap_pis_06v0_dn (6V PIS capacitor (inside DNWEL)
+logger.info('Extracting cap_pis_06v0_dn device')
+extract_devices(capacitor('cap_pis_06v0_dn', 4.4e-15, PisCap),
                 { 'P1' => pis_6p0_dw_gate, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs b/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
index b67122c..0de6a85 100644
--- a/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
@@ -20,32 +20,36 @@
 
 logger.info('Starting VARACTOR DERIVATIONS')
 
-exclude_layers = v5_xtor.or(fusetop).or(polyfuse).or(dualgate)
-                    .or(lvs_bjt).or(drc_bjt).or(sab).or(esd).or(resistor).or(res_mk)
-                    .or(cap_mk).or(nat).or(fhres).or(fusewindow_d).or(diode_mk)
-                    .or(piscap).or(mos_cap_mk).or(mim_l_mk)
+var_exclude = v5_xtor.join(fusetop).join(polyfuse)
+                     .join(dualgate).join(lvs_bjt).join(drc_bjt)
+                     .join(sab).join(esd).join(resistor)
+                     .join(res_mk).join(cap_mk).join(nat)
+                     .join(fhres).join(fusewindow_d).join(diode_mk)
+                     .join(piscap).join(mos_cap_mk).join(mim_l_mk)
+
+var_pcomp = pcomp.and(nwell).and(lvs_rf).not(var_exclude)            
+var_ngate = nplus.and(tgate).and(nwell).and(lvs_rf).not(var_exclude)
 
 # pn_varactor_1p8
-pn_varactor_1p8_tp = pcomp.outside(dnwell).inside(nwell).and(lvs_rf).not(dv2).not(exclude_layers)
+pn_varactor_1p8_tp = var_pcomp.not(dnwell).not(dv2)
 
 # pn_varactor_1p8_dw
-pn_varactor_1p8_dw_tp = pcomp.inside(dnwell).inside(nwell).and(lvs_rf).not(dv2).not(exclude_layers)
+pn_varactor_1p8_dw_tp = var_pcomp.and(dnwell).not(dv2)
 
 # pn_varactor_6p0
-pn_varactor_6p0_tp = pcomp.outside(dnwell).inside(nwell).and(lvs_rf).and(dv2).not(exclude_layers)
+pn_varactor_6p0_tp = var_pcomp.not(dnwell).and(dv2)
 
 # pn_varactor_6p0_dw
-pn_varactor_6p0_dw_tp = pcomp.inside(dnwell).inside(nwell).and(lvs_rf).and(dv2).not(exclude_layers)
+pn_varactor_6p0_dw_tp = var_pcomp.and(dnwell).and(dv2)
         
-
 # mos_varactor_1p8
-mos_varactor_1p8_g = ngate.inside(nwell).outside(dnwell).and(lvs_rf).not(dv2).not(exclude_layers)
+mos_varactor_1p8_g = var_ngate.not(dnwell).not(dv2)
 
 # mos_varactor_1p8_dw
-mos_varactor_1p8_dw_g = ngate.inside(nwell).inside(dnwell).and(lvs_rf).not(dv2).not(exclude_layers)
+mos_varactor_1p8_dw_g = var_ngate.and(dnwell).not(dv2)
 
 # mos_varactor_6p0
-mos_varactor_6p0_g = ngate.inside(nwell).outside(dnwell).and(lvs_rf).and(dv2).not(exclude_layers)
+mos_varactor_6p0_g = var_ngate.not(dnwell).and(dv2)
 
 # mos_varactor_6p0_dw
-mos_varactor_6p0_dw_g = ngate.inside(nwell).inside(dnwell).and(lvs_rf).and(dv2).not(exclude_layers)
\ No newline at end of file
+mos_varactor_6p0_dw_g = var_ngate.and(dnwell).and(dv2)
diff --git a/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs b/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
index f9e4e3a..36d709a 100644
--- a/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
+++ b/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
@@ -20,50 +20,50 @@
 
 logger.info('Starting VARACTOR EXTRACTION')
 
-# pn_varactor_1p8
-logger.info('Extracting pn_varactor_1p8')
-extract_devices(capacitor('pn_varactor_1p8', 4.4e-15, VarCap),
+# cap_var_pd2nw_01v8
+logger.info('Extracting cap_var_pd2nw_01v8')
+extract_devices(capacitor('cap_var_pd2nw_01v8', 4.4e-15, VarCap),
                  { "P1" => pn_varactor_1p8_tp, "P2" => nwell_con,
                   "tA" => pn_varactor_1p8_tp, "tB" => nwell_con })
 
-# pn_varactor_1p8_dw
-logger.info('Extracting pn_varactor_1p8_dw')
-extract_devices(capacitor('pn_varactor_1p8_dw', 4.4e-15, VarCap),
+# cap_var_pd2nw_01v8_dn
+logger.info('Extracting cap_var_pd2nw_01v8_dn')
+extract_devices(capacitor('cap_var_pd2nw_01v8_dn', 4.4e-15, VarCap),
                  { "P1" => pn_varactor_1p8_dw_tp, "P2" => dnwell,
                   "tA" => pn_varactor_1p8_dw_tp, "tB" => dnwell })
 
-# pn_varactor_6p0
-logger.info('Extracting pn_varactor_6p0')
-extract_devices(capacitor('pn_varactor_6p0', 4.4e-15, VarCap),
+# cap_var_pd2nw_06v0
+logger.info('Extracting cap_var_pd2nw_06v0')
+extract_devices(capacitor('cap_var_pd2nw_06v0', 4.4e-15, VarCap),
                  { "P1" => pn_varactor_6p0_tp, "P2" => nwell_con,
                   "tA" => pn_varactor_6p0_tp, "tB" => nwell_con })
 
-# pn_varactor_6p0_dw
-logger.info('Extracting pn_varactor_6p0_dw')
-extract_devices(capacitor('pn_varactor_6p0_dw', 4.4e-15, VarCap),
+# cap_var_pd2nw_06v0_dn
+logger.info('Extracting cap_var_pd2nw_06v0_dn')
+extract_devices(capacitor('cap_var_pd2nw_06v0_dn', 4.4e-15, VarCap),
                  { "P1" => pn_varactor_6p0_dw_tp, "P2" => dnwell,
                   "tA" => pn_varactor_6p0_dw_tp, "tB" => dnwell })
 
-# mos_varactor_1p8
-logger.info('Extracting mos_varactor_1p8')
-extract_devices(capacitor('mos_varactor_1p8', 4.4e-15, VarCap),
+# cap_var_fet_01v8
+logger.info('Extracting cap_var_fet_01v8')
+extract_devices(capacitor('cap_var_fet_01v8', 4.4e-15, VarCap),
                 { 'P1' => mos_varactor_1p8_g, 'P2' => nwell_con,
                  'tA' => poly2_con, 'tB' => ntap })
 
-# mos_varactor_1p8_dw
-logger.info('Extracting mos_varactor_1p8_dw')
-extract_devices(capacitor('mos_varactor_1p8_dw', 4.4e-15, VarCap),
+# cap_var_fet_01v8_dn
+logger.info('Extracting cap_var_fet_01v8_dn')
+extract_devices(capacitor('cap_var_fet_01v8_dn', 4.4e-15, VarCap),
                 { 'P1' => mos_varactor_1p8_dw_g, 'P2' => dnwell,
                  'tA' => poly2_con, 'tB' => ntap })
 
-# mos_varactor_6p0
-logger.info('Extracting mos_varactor_6p0')
-extract_devices(capacitor('mos_varactor_6p0', 4.4e-15, VarCap),
+# cap_var_fet_06v0
+logger.info('Extracting cap_var_fet_06v0')
+extract_devices(capacitor('cap_var_fet_06v0', 4.4e-15, VarCap),
                 { 'P1' => mos_varactor_6p0_g, 'P2' => nwell_con,
                  'tA' => poly2_con, 'tB' => ntap })
 
-# mos_varactor_6p0_dw
-logger.info('Extracting mos_varactor_6p0_dw')
-extract_devices(capacitor('mos_varactor_6p0_dw', 4.4e-15, VarCap),
+# cap_var_fet_06v0_dn
+logger.info('Extracting cap_var_fet_06v0_dn')
+extract_devices(capacitor('cap_var_fet_06v0_dn', 4.4e-15, VarCap),
                 { 'P1' => mos_varactor_6p0_dw_g, 'P2' => dnwell,
                  'tA' => poly2_con, 'tB' => ntap })
diff --git a/ULL/klayout/lvs/testing/run_regression.py b/ULL/klayout/lvs/testing/run_regression.py
index 71a5540..1271f2a 100644
--- a/ULL/klayout/lvs/testing/run_regression.py
+++ b/ULL/klayout/lvs/testing/run_regression.py
@@ -20,7 +20,7 @@
 
 Options:
     --help -h                      Print this help message.
-    --device_name=<device_name>    Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, MOSCAP, MOS_SAB, EFUSE).
+    --device_name=<device_name>    Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, MOSCAP, PISCAP, VARACTOR, MOS_SAB).
     --mp=<num>                     The number of threads used in run.
     --run_name=<run_name>          Select your run name.
 """
@@ -519,11 +519,11 @@
     )
 
     ## selected device
-    allowed_devices = ["MOS", "BJT", "DIODE", "RES", "MIMCAP", "MOSCAP", "MOS_SAB", "EFUSE"]
+    allowed_devices = ["MOS", "BJT", "DIODE", "RES", "MIMCAP", "MOSCAP", "PISCAP", "VARACTOR", "MOS_SAB"]
     target_device_group = args["--device_name"]
 
     if target_device_group and target_device_group not in allowed_devices:
-        logging.error("Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, MOSCAP, MOS_SAB, EFUSE) only")
+        logging.error("Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, MOSCAP, PISCAP, VARACTOR, MOS_SAB) only")
         exit(1)
 
     # Calling main function
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8.gds
similarity index 96%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8.gds
index 16ab300..c193a17 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dn.gds
similarity index 99%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dw.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dn.gds
index 3559daf..46fc02a 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dw.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dn.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dnwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dnwell.gds
similarity index 99%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dnwell.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dnwell.gds
index 07997de..f3a4ec5 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dnwell.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dnwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_nwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_nwell.gds
similarity index 99%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_nwell.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_nwell.gds
index d409b7f..0cabff4 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_nwell.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_nwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0.gds
similarity index 96%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0.gds
index b7b05bb..6663609 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dn.gds
similarity index 99%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dw.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dn.gds
index 14b3eab..25b51a6 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dw.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dn.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dnwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dnwell.gds
similarity index 99%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dnwell.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dnwell.gds
index b4c9a71..86c0bce 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dnwell.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dnwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_nwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_nwell.gds
similarity index 99%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_nwell.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_nwell.gds
index 86d96d4..e6709dd 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_nwell.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_nwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8.gds
similarity index 99%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8.gds
index 08d8d04..fea8432 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8_dn.gds
similarity index 98%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8_dw.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8_dn.gds
index c7f73a6..3538313 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8_dw.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8_dn.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0.gds
similarity index 98%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0.gds
index 0e678ed..b8e8712 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0_dn.gds
similarity index 97%
rename from ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0_dw.gds
rename to ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0_dn.gds
index e0bd3fd..2a0fa02 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0_dw.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0_dn.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8.cdl
new file mode 100644
index 0000000..72b5531
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_nmos_01v8
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_nmos_01v8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_nmos_01v8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_01v8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_01v8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_01v8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_01v8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_01v8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_01v8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_01v8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_01v8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_01v8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_01v8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dn.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dn.cdl
new file mode 100644
index 0000000..dfc0b41
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_nmos_01v8_dn
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:12:27 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_nmos_01v8_dn
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_nmos_01v8_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_01v8_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_01v8_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_01v8_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_01v8_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_01v8_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_01v8_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_01v8_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_01v8_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_01v8_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_01v8_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dnwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dnwell.cdl
new file mode 100644
index 0000000..b199a3e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dnwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_nmos_01v8_dnwell
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:11:11 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_nmos_01v8_dnwell
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_nmos_01v8_dnwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_01v8_dnwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_01v8_dnwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_01v8_dnwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_01v8_dnwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_01v8_dnwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_01v8_dnwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_01v8_dnwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_01v8_dnwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_01v8_dnwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_01v8_dnwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_nwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_nwell.cdl
new file mode 100644
index 0000000..2671210
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_nwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_nmos_01v8_nwell
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:11:11 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_nmos_01v8_nwell
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_nmos_01v8_nwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_01v8_nwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_01v8_nwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_01v8_nwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_01v8_nwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_01v8_nwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_01v8_nwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_01v8_nwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_01v8_nwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_01v8_nwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_01v8_nwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0.cdl
new file mode 100644
index 0000000..bf895e5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_nmos_06v0
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:13:17 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_nmos_06v0
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_nmos_06v0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_06v0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_06v0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_06v0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_06v0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_06v0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_06v0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_06v0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_06v0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_06v0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_06v0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dn.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dn.cdl
new file mode 100644
index 0000000..a810f36
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_nmos_06v0_dn
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:15:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_nmos_06v0_dn
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_nmos_06v0_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_06v0_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_06v0_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_06v0_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_06v0_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_06v0_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_06v0_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_06v0_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_06v0_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_06v0_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_06v0_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dnwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dnwell.cdl
new file mode 100644
index 0000000..b74909f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dnwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_nmos_06v0_dnwell
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:14:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_nmos_06v0_dnwell
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_nmos_06v0_dnwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_06v0_dnwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_06v0_dnwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_06v0_dnwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_06v0_dnwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_06v0_dnwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_06v0_dnwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_06v0_dnwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_06v0_dnwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_06v0_dnwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_06v0_dnwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_nwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_nwell.cdl
new file mode 100644
index 0000000..13fff36
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_nwell.cdl
@@ -0,0 +1,48 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_nmos_06v0_nwell
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:14:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_nmos_06v0_nwell
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_nmos_06v0_nwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_06v0_nwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_06v0_nwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_06v0_nwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_06v0_nwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_06v0_nwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_06v0_nwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_06v0_nwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_06v0_nwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_06v0_nwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_06v0_nwell m=1 l=5u w=5u
+.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8.cdl
new file mode 100644
index 0000000..fb8e48f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_pmos_01v8
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:44:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_pmos_01v8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_pmos_01v8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_pmos_01v8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_pmos_01v8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_pmos_01v8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_pmos_01v8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_pmos_01v8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_pmos_01v8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_pmos_01v8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_pmos_01v8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_pmos_01v8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_pmos_01v8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8_dn.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8_dn.cdl
new file mode 100644
index 0000000..ca920ad
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_pmos_01v8_dn
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:45:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_pmos_01v8_dn
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_pmos_01v8_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_pmos_01v8_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_pmos_01v8_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_pmos_01v8_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_pmos_01v8_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_pmos_01v8_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_pmos_01v8_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_pmos_01v8_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_pmos_01v8_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_pmos_01v8_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_pmos_01v8_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0.cdl
new file mode 100644
index 0000000..c34a2f1
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_pmos_06v0
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:48:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_pmos_06v0
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_pmos_06v0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_pmos_06v0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_pmos_06v0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_pmos_06v0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_pmos_06v0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_pmos_06v0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_pmos_06v0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_pmos_06v0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_pmos_06v0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_pmos_06v0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_pmos_06v0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0_dn.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0_dn.cdl
new file mode 100644
index 0000000..c6377d9
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_pmos_06v0_dn
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:47:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_pmos_06v0_dn
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_pmos_06v0_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_pmos_06v0_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_pmos_06v0_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_pmos_06v0_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_pmos_06v0_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_pmos_06v0_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_pmos_06v0_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_pmos_06v0_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_pmos_06v0_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_pmos_06v0_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_pmos_06v0_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8.cdl
deleted file mode 100644
index d0f6935..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: nmoscap_1p8
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:07:52 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    nmoscap_1p8
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT nmoscap_1p8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8 m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8 m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8 m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8 m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8 m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8 m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8 m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8 m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8 m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D nmoscap_1p8 m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dnwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dnwell.cdl
deleted file mode 100644
index 0e7e9ad..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dnwell.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: nmoscap_1p8_dnwell
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:11:11 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    nmoscap_1p8_dnwell
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT nmoscap_1p8_dnwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8_dnwell m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8_dnwell m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8_dnwell m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8_dnwell m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8_dnwell m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8_dnwell m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8_dnwell m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8_dnwell m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8_dnwell m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D nmoscap_1p8_dnwell m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dw.cdl
deleted file mode 100644
index e5823d4..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dw.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: nmoscap_1p8_dw
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:12:27 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    nmoscap_1p8_dw
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT nmoscap_1p8_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8_dw m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8_dw m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8_dw m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8_dw m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8_dw m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8_dw m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8_dw m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8_dw m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8_dw m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D nmoscap_1p8_dw m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_nwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_nwell.cdl
deleted file mode 100644
index 648f007..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_nwell.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: nmoscap_1p8_nwell
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:11:11 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    nmoscap_1p8_nwell
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT nmoscap_1p8_nwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8_nwell m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8_nwell m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8_nwell m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8_nwell m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8_nwell m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8_nwell m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8_nwell m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8_nwell m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8_nwell m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D nmoscap_1p8_nwell m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0.cdl
deleted file mode 100644
index 508a56c..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: nmoscap_6p0
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:13:17 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    nmoscap_6p0
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT nmoscap_6p0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0 m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0 m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0 m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0 m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0 m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0 m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0 m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0 m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0 m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D nmoscap_6p0 m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dnwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dnwell.cdl
deleted file mode 100644
index 9e8092b..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dnwell.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: nmoscap_6p0_dnwell
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:14:31 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    nmoscap_6p0_dnwell
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT nmoscap_6p0_dnwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0_dnwell m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0_dnwell m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0_dnwell m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0_dnwell m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0_dnwell m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0_dnwell m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0_dnwell m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0_dnwell m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0_dnwell m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D nmoscap_6p0_dnwell m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dw.cdl
deleted file mode 100644
index 2515b81..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dw.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: nmoscap_6p0_dw
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:15:20 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    nmoscap_6p0_dw
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT nmoscap_6p0_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0_dw m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0_dw m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0_dw m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0_dw m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0_dw m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0_dw m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0_dw m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0_dw m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0_dw m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D nmoscap_6p0_dw m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_nwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_nwell.cdl
deleted file mode 100644
index e618d63..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_nwell.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: nmoscap_6p0_nwell
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:14:31 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    nmoscap_6p0_nwell
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT nmoscap_6p0_nwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0_nwell m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0_nwell m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0_nwell m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0_nwell m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0_nwell m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0_nwell m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0_nwell m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0_nwell m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0_nwell m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D nmoscap_6p0_nwell m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8.cdl
deleted file mode 100644
index 3f04861..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: pmoscap_1p8
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:44:20 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    pmoscap_1p8
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT pmoscap_1p8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_1p8 m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_1p8 m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_1p8 m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_1p8 m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_1p8 m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_1p8 m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_1p8 m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_1p8 m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_1p8 m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D pmoscap_1p8 m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8_dw.cdl
deleted file mode 100644
index bcd13a6..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8_dw.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: pmoscap_1p8_dw
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:45:53 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    pmoscap_1p8_dw
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT pmoscap_1p8_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_1p8_dw m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_1p8_dw m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_1p8_dw m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_1p8_dw m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_1p8_dw m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_1p8_dw m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_1p8_dw m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_1p8_dw m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_1p8_dw m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D pmoscap_1p8_dw m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0.cdl
deleted file mode 100644
index f9c0f84..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: pmoscap_6p0
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:47:13 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    pmoscap_6p0
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT pmoscap_6p0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_6p0 m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_6p0 m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_6p0 m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_6p0 m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_6p0 m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_6p0 m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_6p0 m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_6p0 m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_6p0 m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D pmoscap_6p0 m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0_dw.cdl
deleted file mode 100644
index 01d0eb8..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0_dw.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: pmoscap_6p0_dw
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:48:31 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    pmoscap_6p0_dw
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT pmoscap_6p0_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
-+ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
-+ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
-+ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
-*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I 
-*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I 
-*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
-*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
-*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_6p0_dw m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_6p0_dw m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_6p0_dw m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_6p0_dw m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_6p0_dw m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_6p0_dw m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_6p0_dw m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_6p0_dw m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_6p0_dw m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D pmoscap_6p0_dw m=1 l=5u w=5u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds
new file mode 100644
index 0000000..6c008e9
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds
new file mode 100644
index 0000000..939e7ed
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds
new file mode 100644
index 0000000..7c78db5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds
new file mode 100644
index 0000000..fb735a7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds
deleted file mode 100644
index d6a4e5f..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds
+++ /dev/null
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds
deleted file mode 100644
index 26bb5ed..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds
+++ /dev/null
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds
deleted file mode 100644
index c91e63c..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds
+++ /dev/null
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds
deleted file mode 100644
index 1638d1c..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds
+++ /dev/null
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl
similarity index 69%
copy from ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
copy to ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl
index 88262cb..e70e083 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl
@@ -2,7 +2,7 @@
 * auCdl Netlist:
 * 
 * Library Name:  TCG_Library
-* Top Cell Name: piscap_1p8_dw
+* Top Cell Name: cap_pis_01v8
 * View Name:     schematic
 * Netlisted on:  Nov 24 09:07:52 2021
 ************************************************************************
@@ -22,13 +22,12 @@
 
 ************************************************************************
 * Library Name: TCG_Library
-* Cell Name:    piscap_1p8_dw
+* Cell Name:    cap_pis_01v8
 * View Name:    schematic
 ************************************************************************
 
-.SUBCKT piscap_1p8_dw I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+.SUBCKT cap_pis_01v8 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
 
-C1 I1_0_0_R0_G I1_0_0_R0_D piscap_1p8_dw m=1 l=1.88u w=1.000u
-C2 I1_default_G I1_default_D piscap_1p8_dw m=1 l=5.88u w=5u
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_01v8 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_01v8 m=1 l=5.88u w=5u
 .ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl
similarity index 68%
copy from ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
copy to ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl
index 88262cb..834803f 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl
@@ -2,7 +2,7 @@
 * auCdl Netlist:
 * 
 * Library Name:  TCG_Library
-* Top Cell Name: piscap_1p8_dw
+* Top Cell Name: cap_pis_01v8_dn
 * View Name:     schematic
 * Netlisted on:  Nov 24 09:07:52 2021
 ************************************************************************
@@ -22,13 +22,13 @@
 
 ************************************************************************
 * Library Name: TCG_Library
-* Cell Name:    piscap_1p8_dw
+* Cell Name:    cap_pis_01v8_dn
 * View Name:    schematic
 ************************************************************************
 
-.SUBCKT piscap_1p8_dw I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+.SUBCKT cap_pis_01v8_dn I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
 
-C1 I1_0_0_R0_G I1_0_0_R0_D piscap_1p8_dw m=1 l=1.88u w=1.000u
-C2 I1_default_G I1_default_D piscap_1p8_dw m=1 l=5.88u w=5u
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_01v8_dn m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_01v8_dn m=1 l=5.88u w=5u
 .ENDS
 
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl
similarity index 69%
rename from ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
rename to ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl
index 88262cb..66e879a 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl
@@ -2,7 +2,7 @@
 * auCdl Netlist:
 * 
 * Library Name:  TCG_Library
-* Top Cell Name: piscap_1p8_dw
+* Top Cell Name: cap_pis_06v0
 * View Name:     schematic
 * Netlisted on:  Nov 24 09:07:52 2021
 ************************************************************************
@@ -22,13 +22,12 @@
 
 ************************************************************************
 * Library Name: TCG_Library
-* Cell Name:    piscap_1p8_dw
+* Cell Name:    cap_pis_06v0
 * View Name:    schematic
 ************************************************************************
 
-.SUBCKT piscap_1p8_dw I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+.SUBCKT cap_pis_06v0 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
 
-C1 I1_0_0_R0_G I1_0_0_R0_D piscap_1p8_dw m=1 l=1.88u w=1.000u
-C2 I1_default_G I1_default_D piscap_1p8_dw m=1 l=5.88u w=5u
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_06v0 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_06v0 m=1 l=5.88u w=5u
 .ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl
similarity index 68%
copy from ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
copy to ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl
index 88262cb..ab6e6da 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl
@@ -2,7 +2,7 @@
 * auCdl Netlist:
 * 
 * Library Name:  TCG_Library
-* Top Cell Name: piscap_1p8_dw
+* Top Cell Name: cap_pis_06v0_dn
 * View Name:     schematic
 * Netlisted on:  Nov 24 09:07:52 2021
 ************************************************************************
@@ -22,13 +22,12 @@
 
 ************************************************************************
 * Library Name: TCG_Library
-* Cell Name:    piscap_1p8_dw
+* Cell Name:    cap_pis_06v0_dn
 * View Name:    schematic
 ************************************************************************
 
-.SUBCKT piscap_1p8_dw I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+.SUBCKT cap_pis_06v0_dn I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
 
-C1 I1_0_0_R0_G I1_0_0_R0_D piscap_1p8_dw m=1 l=1.88u w=1.000u
-C2 I1_default_G I1_default_D piscap_1p8_dw m=1 l=5.88u w=5u
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_06v0_dn m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_06v0_dn m=1 l=5.88u w=5u
 .ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl
deleted file mode 100644
index 811a4ce..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl
+++ /dev/null
@@ -1,33 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: piscap_1p8
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:07:52 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    piscap_1p8
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT piscap_1p8 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
-
-C1 I1_0_0_R0_G I1_0_0_R0_D piscap_1p8 m=1 l=1.88u w=1.000u
-C2 I1_default_G I1_default_D piscap_1p8 m=1 l=5.88u w=5u
-.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl
deleted file mode 100644
index a8bc9a5..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl
+++ /dev/null
@@ -1,33 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: piscap_6p0
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:07:52 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    piscap_6p0
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT piscap_6p0 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
-
-C1 I1_0_0_R0_G I1_0_0_R0_D piscap_6p0 m=1 l=1.88u w=1.000u
-C2 I1_default_G I1_default_D piscap_6p0 m=1 l=5.88u w=5u
-.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl
deleted file mode 100644
index ad8c71e..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl
+++ /dev/null
@@ -1,33 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: piscap_6p0_dw
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:07:52 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    piscap_6p0_dw
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT piscap_6p0_dw I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
-
-C1 I1_0_0_R0_G I1_0_0_R0_D piscap_6p0_dw m=1 l=1.88u w=1.000u
-C2 I1_default_G I1_default_D piscap_6p0_dw m=1 l=5.88u w=5u
-.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8.gds
similarity index 96%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8.gds
index 7efb14d..84cabe1 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8_dn.gds
similarity index 99%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8_dn.gds
index 6893fe8..66bec81 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8_dn.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0.gds
similarity index 96%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0.gds
index 7a85d9f..55c8f3e 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0_dn.gds
similarity index 99%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0_dn.gds
index 280f16e..81fb77f 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0_dn.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8.gds
similarity index 88%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8.gds
index 0bcb398..a6e0cc7 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8_dn.gds
similarity index 89%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8_dn.gds
index 576a490..1ac8e8b 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8_dn.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0.gds
similarity index 74%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0.gds
index a91f22d..b755906 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0_dn.gds
similarity index 98%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0_dn.gds
index ddbf511..8b04994 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0_dn.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8.cdl
similarity index 61%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8.cdl
index 80daea9..aac3115 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8.cdl
@@ -2,7 +2,7 @@
 * auCdl Netlist:
 * 
 * Library Name:  TCG_Library
-* Top Cell Name: mos_varactor_1p8
+* Top Cell Name: cap_var_fet_01v8
 * View Name:     schematic
 * Netlisted on:  Nov 24 09:07:52 2021
 ************************************************************************
@@ -22,11 +22,11 @@
 
 ************************************************************************
 * Library Name: TCG_Library
-* Cell Name:    mos_varactor_1p8
+* Cell Name:    cap_var_fet_01v8
 * View Name:    schematic
 ************************************************************************
 
-.SUBCKT mos_varactor_1p8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
+.SUBCKT cap_var_fet_01v8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
 + I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
 + I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
 + I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G 
@@ -35,15 +35,15 @@
 *.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
 *.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
 *.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_1p8 m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_1p8 m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_1p8 m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_1p8 m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_1p8 m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_1p8 m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_1p8 m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_1p8 m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_1p8 m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D mos_varactor_1p8 m=1 l=5u w=5u
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_01v8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_01v8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_01v8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_01v8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_01v8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_01v8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_01v8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_01v8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_01v8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_01v8 m=1 l=5u w=5u
 .ENDS
 
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8_dn.cdl
similarity index 61%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8_dn.cdl
index 918db43..16d2038 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8_dn.cdl
@@ -2,7 +2,7 @@
 * auCdl Netlist:
 * 
 * Library Name:  TCG_Library
-* Top Cell Name: mos_varactor_1p8_dw
+* Top Cell Name: cap_var_fet_01v8_dn
 * View Name:     schematic
 * Netlisted on:  Nov 24 09:12:27 2021
 ************************************************************************
@@ -22,11 +22,11 @@
 
 ************************************************************************
 * Library Name: TCG_Library
-* Cell Name:    mos_varactor_1p8_dw
+* Cell Name:    cap_var_fet_01v8_dn
 * View Name:    schematic
 ************************************************************************
 
-.SUBCKT mos_varactor_1p8_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
+.SUBCKT cap_var_fet_01v8_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
 + I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
 + I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
 + I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G 
@@ -35,15 +35,15 @@
 *.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
 *.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
 *.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D mos_varactor_1p8_dw m=1 l=5u w=5u
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_01v8_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_01v8_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_01v8_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_01v8_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_01v8_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_01v8_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_01v8_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_01v8_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_01v8_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_01v8_dn m=1 l=5u w=5u
 .ENDS
 
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0.cdl
similarity index 61%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0.cdl
index 47c6313..99613b1 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0.cdl
@@ -2,7 +2,7 @@
 * auCdl Netlist:
 * 
 * Library Name:  TCG_Library
-* Top Cell Name: mos_varactor_6p0
+* Top Cell Name: cap_var_fet_06v0
 * View Name:     schematic
 * Netlisted on:  Nov 24 09:13:17 2021
 ************************************************************************
@@ -22,11 +22,11 @@
 
 ************************************************************************
 * Library Name: TCG_Library
-* Cell Name:    mos_varactor_6p0
+* Cell Name:    cap_var_fet_06v0
 * View Name:    schematic
 ************************************************************************
 
-.SUBCKT mos_varactor_6p0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
+.SUBCKT cap_var_fet_06v0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
 + I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
 + I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
 + I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
@@ -35,15 +35,15 @@
 *.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
 *.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
 *.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_6p0 m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_6p0 m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_6p0 m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_6p0 m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_6p0 m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_6p0 m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_6p0 m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_6p0 m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_6p0 m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D mos_varactor_6p0 m=1 l=5u w=5u
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_06v0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_06v0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_06v0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_06v0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_06v0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_06v0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_06v0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_06v0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_06v0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_06v0 m=1 l=5u w=5u
 .ENDS
 
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0_dn.cdl
similarity index 61%
rename from ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl
rename to ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0_dn.cdl
index 05f01ad..b2b34ba 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0_dn.cdl
@@ -2,7 +2,7 @@
 * auCdl Netlist:
 * 
 * Library Name:  TCG_Library
-* Top Cell Name: mos_varactor_6p0_dw
+* Top Cell Name: cap_var_fet_06v0_dn
 * View Name:     schematic
 * Netlisted on:  Nov 24 09:15:20 2021
 ************************************************************************
@@ -22,11 +22,11 @@
 
 ************************************************************************
 * Library Name: TCG_Library
-* Cell Name:    mos_varactor_6p0_dw
+* Cell Name:    cap_var_fet_06v0_dn
 * View Name:    schematic
 ************************************************************************
 
-.SUBCKT mos_varactor_6p0_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
+.SUBCKT cap_var_fet_06v0_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G 
 + I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G 
 + I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G 
 + I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
@@ -35,15 +35,15 @@
 *.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I 
 *.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I 
 *.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
-CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=50.000u
-CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=12.350u
-CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=1.000u
-CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=50.000u
-CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=12.350u
-CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=1.000u
-CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=50.000u
-CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=12.350u
-CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=1.000u
-CI1_default I1_default_G I1_default_D mos_varactor_6p0_dw m=1 l=5u w=5u
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_06v0_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_06v0_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_06v0_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_06v0_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_06v0_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_06v0_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_06v0_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_06v0_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_06v0_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_06v0_dn m=1 l=5u w=5u
 .ENDS
 
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8.cdl
new file mode 100644
index 0000000..09d3dea
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_var_pd2nw_01v8
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:49:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_var_pd2nw_01v8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_01v8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS 
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS 
++ I1_default_MINUS I1_default_PLUS 
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_01v8 m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8_dn.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8_dn.cdl
new file mode 100644
index 0000000..b7c1439
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8_dn.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_var_pd2nw_01v8_dn
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:50:00 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_var_pd2nw_01v8_dn
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_01v8_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS 
++ I1_default_PLUS I1_default_MINUS 
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_01v8_dn m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0.cdl
new file mode 100644
index 0000000..723bda2
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_var_pd2nw_06v0
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:50:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_var_pd2nw_06v0
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_06v0 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS 
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS 
++ I1_default_MINUS I1_default_PLUS 
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_06v0 m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0_dn.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0_dn.cdl
new file mode 100644
index 0000000..2783ab4
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0_dn.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+* 
+* Library Name:  TCG_Library
+* Top Cell Name: cap_var_pd2nw_06v0_dn
+* View Name:     schematic
+* Netlisted on:  Nov 24 09:51:10 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000 
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name:    cap_var_pd2nw_06v0_dn
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_06v0_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS 
++ I1_default_PLUS I1_default_MINUS 
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_06v0_dn m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl
deleted file mode 100644
index 5395cc5..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl
+++ /dev/null
@@ -1,44 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: pn_varactor_1p8
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:49:28 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    pn_varactor_1p8
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT pn_varactor_1p8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
-+ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
-+ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS 
-+ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS 
-+ I1_default_MINUS I1_default_PLUS 
-
-
-CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS pn_varactor_1p8 m=1 L=1.1u W=1.1u
-CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=1.1u
-CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=100u
-CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=13.2u
-CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=1.1u
-CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=0.565u
-CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_1p8 m=1 L=1u W=1u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl
deleted file mode 100644
index adc3e1b..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl
+++ /dev/null
@@ -1,40 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: pn_varactor_1p8_dw
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:50:00 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    pn_varactor_1p8_dw
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT pn_varactor_1p8_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
-+ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
-+ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS 
-+ I1_default_PLUS I1_default_MINUS 
-
-CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=100u
-CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=13.2u
-CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=1.1u
-CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=0.565u
-CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_1p8_dw m=1 L=1u W=1u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl
deleted file mode 100644
index 7a8a560..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl
+++ /dev/null
@@ -1,44 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: pn_varactor_6p0
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:50:38 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    pn_varactor_6p0
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT pn_varactor_6p0 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
-+ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
-+ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS 
-+ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS 
-+ I1_default_MINUS I1_default_PLUS 
-
-
-CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS pn_varactor_6p0 m=1 L=1.1u W=1.1u
-CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=1.1u
-CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=100u
-CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=13.2u
-CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=1.1u
-CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=0.565u
-CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_6p0 m=1 L=1u W=1u
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl
deleted file mode 100644
index e7361a4..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl
+++ /dev/null
@@ -1,40 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-* 
-* Library Name:  TCG_Library
-* Top Cell Name: pn_varactor_6p0_dw
-* View Name:     schematic
-* Netlisted on:  Nov 24 09:51:10 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000 
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name:    pn_varactor_6p0_dw
-* View Name:    schematic
-************************************************************************
-
-.SUBCKT pn_varactor_6p0_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS 
-+ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS 
-+ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS 
-+ I1_default_PLUS I1_default_MINUS 
-
-CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=100u
-CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=13.2u
-CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=1.1u
-CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=0.565u
-CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_6p0_dw m=1 L=1u W=1u
-.ENDS
-