Merge pull request #95 from mabrains/ic_varactors
Adding Varactors testcases for IC
diff --git a/IC/klayout/lvs/rule_decks/custom_classes.lvs b/IC/klayout/lvs/rule_decks/custom_classes.lvs
index 932217c..d0e84fd 100644
--- a/IC/klayout/lvs/rule_decks/custom_classes.lvs
+++ b/IC/klayout/lvs/rule_decks/custom_classes.lvs
@@ -148,4 +148,13 @@
enable_parameter('A', true)
enable_parameter('P', true)
end
+ end
+
+ class VarCap < RBA::DeviceClassCapacitorWithBulk
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
end
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/pn_varactor_extraction.lvs b/IC/klayout/lvs/rule_decks/pn_varactor_extraction.lvs
index 5f1d9e2..634fad1 100644
--- a/IC/klayout/lvs/rule_decks/pn_varactor_extraction.lvs
+++ b/IC/klayout/lvs/rule_decks/pn_varactor_extraction.lvs
@@ -21,4 +21,6 @@
# pnvar_1p8 varactor
logger.info('Extracting pnvar_1p8')
-extract_devices(diode('pnvar_1p8'), { 'N' => pnvar_1p8_terminal_n, 'P' => pnvar_1p8_terminal_p })
\ No newline at end of file
+extract_devices(capacitor_with_bulk("pnvar_1p8", 4.4e-15, VarCap),
+ { "P1" => pnvar_1p8_terminal_p, "P2" => pnvar_1p8_terminal_n,
+ "W" => sub})
\ No newline at end of file
diff --git a/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/layout/pnvar_1p8.gds b/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/layout/pnvar_1p8.gds
new file mode 100644
index 0000000..0770ae8
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/layout/pnvar_1p8.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/netlist/pnvar_1p8.cdl b/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/netlist/pnvar_1p8.cdl
new file mode 100644
index 0000000..7ff65b0
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/netlist/pnvar_1p8.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pnvar_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:16:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pnvar_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pnvar_1p8 I1_0_2_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS
++ I1_0_0_0_0_R0_MINUS I1_default_MINUS
++ I1_0_2_0_0_R0_PLUS I1_0_1_0_0_R0_PLUS I1_0_0_0_0_R0_PLUS I1_default_PLUS
+
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pnvar_1p8 AREA=4.752p PJ=27.12u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pnvar_1p8 AREA=396f PJ=2.92u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pnvar_1p8 AREA=203.4f PJ=1.85u
+CI1_default I1_default_PLUS I1_default_MINUS pnvar_1p8 AREA=1p PJ=4u
+.ENDS
+
