Merge pull request #100 from mabrains/ull_piscap
Adding PISCAP for ULL
diff --git a/.github/workflows/regression.yml b/.github/workflows/drc_regression.yml
similarity index 80%
rename from .github/workflows/regression.yml
rename to .github/workflows/drc_regression.yml
index 8026e5f..0db8498 100644
--- a/.github/workflows/regression.yml
+++ b/.github/workflows/drc_regression.yml
@@ -12,7 +12,7 @@
# See the License for the specific language governing permissions and
# limitations under the License.
-name: regression testing
+name: DRC regression testing
# Prevent keeping resources busy when a branch/PR is updated
# https://docs.github.com/en/actions/using-jobs/using-concurrency
@@ -76,21 +76,4 @@
run: |
make test-"$(python3 -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
- lvs_regression:
- runs-on: ${{ fromJSON('["ubuntu-latest", "self-hosted"]')[github.repository == 'github/docs-internal'] }}
- strategy:
- fail-fast: false
- matrix:
- include:
- - { tool: klayout, part: lvs, test: main }
- - { tool: klayout, part: lvs, test: switch }
- name: ${{ matrix.part }} | ${{ matrix.test }}
-
- steps:
- - uses: actions/checkout@v3
- with:
- submodules: 'recursive'
- - name: Testing ${{ matrix.part }} for ${{ matrix.test }}
- run: |
- make test-"$(python3 -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
diff --git a/.github/workflows/lvs_regression.yml b/.github/workflows/lvs_regression.yml
new file mode 100644
index 0000000..3b26c9f
--- /dev/null
+++ b/.github/workflows/lvs_regression.yml
@@ -0,0 +1,77 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: LVS regression testing
+
+# Prevent keeping resources busy when a branch/PR is updated
+# https://docs.github.com/en/actions/using-jobs/using-concurrency
+concurrency:
+ group: ${{ github.repository }}-${{ github.workflow }}-${{ github.ref }}
+ cancel-in-progress: true
+
+on:
+ push:
+ pull_request:
+ workflow_dispatch:
+
+jobs:
+ lvs_switch:
+ runs-on: ubuntu-latest
+ strategy:
+ fail-fast: false
+ matrix:
+ include:
+ - { tool: klayout, part: lvs, test: switch }
+
+ name: ${{ matrix.part }} | ${{ matrix.test }}
+
+ steps:
+ - uses: actions/checkout@v3
+ with:
+ submodules: 'recursive'
+ - name: Testing ${{ matrix.part }} for ${{ matrix.test }}
+ run: |
+ make test-"$(python -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
+
+ build_lvs-matrix:
+ runs-on: ubuntu-latest
+ outputs:
+ lvs_table: ${{ steps.set-matrix.outputs.lvs_table }}
+ steps:
+ - uses: actions/checkout@v3
+ - id: set-matrix
+ run: |
+ lvs_table=`find -iname '*_extraction.lvs' | grep -i rule_decks | grep -v main | grep -v tail | awk -F'/' '{printf "\"%s-%s\",", $2, $NF}' | sed -e "s/^/[/g" -e "s/,$/]/g" -e "s/_extraction.lvs//g"`
+ lvs_table=`echo $lvs_table | jq -c .`
+ echo $lvs_table
+ echo "lvs_table=$lvs_table" >>$GITHUB_OUTPUT
+
+ lvs_regression:
+ needs: build_lvs-matrix
+ runs-on: ubuntu-latest
+ strategy:
+ fail-fast: false
+ matrix:
+ part: [lvs]
+ test: ${{ fromJson(needs.build_lvs-matrix.outputs.lvs_table) }}
+
+ name: ${{ matrix.part }} | ${{ matrix.test }}
+
+ steps:
+ - uses: actions/checkout@v3
+ with:
+ submodules: 'recursive'
+ - name: Testing ${{ matrix.part }} for ${{ matrix.test }}
+ run: |
+ make test-"$(python -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
diff --git a/Makefile b/Makefile
index 7b38c0d..6273977 100644
--- a/Makefile
+++ b/Makefile
@@ -22,6 +22,8 @@
# https://docs.conda.io/projects/conda/en/latest/user-guide/tasks/manage-environments.html
ENVIRONMENT_FILE := pdk_regression.yml
+KLAYOUT_LVS_TESTS := klayout/lvs/testing/
+
include third_party/make-env/conda.mk
# Lint python code
@@ -63,10 +65,28 @@
################################################################################
## LVS Regression section
################################################################################
-# LVS main testing
-test-LVS-main: | $(CONDA_ENV_PYTHON)
- @$(IN_CONDA_ENV) klayout -v
+#=================================
+# ----- test-LVS_regression ------
+#=================================
-# LVS main testing
-test-LVS-switch: | $(CONDA_ENV_PYTHON)
- @$(IN_CONDA_ENV) klayout -v
+# run regression on all variants` devices
+.ONESHELL:
+test-LVS-main: | $(CONDA_ENV_PYTHON)
+ @$(IN_CONDA_ENV) cd IC/$(KLAYOUT_LVS_TESTS) && make test-LVS-main
+ @$(IN_CONDA_ENV) cd ULL/$(KLAYOUT_LVS_TESTS) && make test-LVS-main
+ @$(IN_CONDA_ENV) cd BCDLite/$(KLAYOUT_LVS_TESTS) && make test-LVS-main
+
+.ONESHELL:
+test-LVS-% : | $(CONDA_ENV_PYTHON)
+ @which python3
+ifeq ($(findstring ULL, $($*)), ULL)
+ cd ULL/$(KLAYOUT_LVS_TESTS) && make test-LVS-$(subst ULL-,,$($*))
+endif
+
+ifeq ($(findstring IC, $($*)), IC)
+ cd IC/$(KLAYOUT_LVS_TESTS) && make test-LVS-$(subst IC-,,$($*))
+endif
+
+ifeq ($(findstring BCDLite, $($*)), BCDLite)
+ cd BCDLite/$(KLAYOUT_LVS_TESTS) && make test-LVS-$(subst BCDLite-,,$($*))
+endif
\ No newline at end of file
diff --git a/ULL/klayout/lvs/gf180ull.lvs b/ULL/klayout/lvs/gf180ull.lvs
index 554b08c..341633b 100644
--- a/ULL/klayout/lvs/gf180ull.lvs
+++ b/ULL/klayout/lvs/gf180ull.lvs
@@ -271,6 +271,24 @@
# %include 'rule_decks/diode_derivations.lvs'
+#================================
+# ------ MOSCAP DERIVATIONS -----
+#================================
+
+# %include 'rule_decks/moscap_derivations.lvs'
+
+#===================================
+# ------ Varactor DERIVATIONS ------
+#===================================
+
+# %include 'rule_decks/varactor_derivations.lvs'
+
+#===================================
+# ------ PISCAP DERIVATIONS ------
+#===================================
+
+# %include 'rule_decks/piscap_derivations.lvs'
+
#================================================
#------------ DEVICES CONNECTIVITY --------------
#================================================
@@ -302,11 +320,29 @@
# %include 'rule_decks/res_extraction.lvs'
#================================
-# ------- Diode EXTRACTION --------
+# ------- Diode EXTRACTION ------
#================================
# %include 'rule_decks/diode_extraction.lvs'
+#================================
+# ------- MOSCAP EXTRACTION -----
+#================================
+
+# %include 'rule_decks/moscap_extraction.lvs'
+
+#================================
+# ----- Varactor EXTRACTION ----
+#================================
+
+# %include 'rule_decks/varactor_extraction.lvs'
+
+#================================
+# ------ PISCAP EXTRACTION -----
+#================================
+
+# %include 'rule_decks/piscap_extraction.lvs'
+
#================================================
#------------- COMPARISON OPTIONS ---------------
#================================================
diff --git a/ULL/klayout/lvs/rule_decks/custom_classes.lvs b/ULL/klayout/lvs/rule_decks/custom_classes.lvs
index 23f3250..11fcf5d 100644
--- a/ULL/klayout/lvs/rule_decks/custom_classes.lvs
+++ b/ULL/klayout/lvs/rule_decks/custom_classes.lvs
@@ -158,3 +158,23 @@
enable_parameter('P', true)
end
end
+
+# Varactor class
+class VarCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
+end
+
+# PISCAP class
+class PisCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
+end
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/devices_connections.lvs b/ULL/klayout/lvs/rule_decks/devices_connections.lvs
index 9f86dd1..a0d119c 100644
--- a/ULL/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/ULL/klayout/lvs/rule_decks/devices_connections.lvs
@@ -65,7 +65,7 @@
# Attaching labels
connect(metal1, metal1_label)
-connect(metal2, metal2_label)
+connect(metal2_ncap, metal2_label)
if METAL_LEVEL != '2LM'
connect(metal3_ncap, metal3_label)
if METAL_LEVEL != '3LM'
@@ -249,4 +249,13 @@
connect(nplus_cont, contact)
connect(pplus_cont, contact)
-connect(pplus_dw_cont, contact)
\ No newline at end of file
+connect(pplus_dw_cont, contact)
+
+#================================
+# ---- Varactor CONNECTIONS -----
+#================================
+
+connect(pn_varactor_1p8_tp ,contact)
+connect(pn_varactor_1p8_dw_tp ,contact)
+connect(pn_varactor_6p0_tp ,contact)
+connect(pn_varactor_6p0_dw_tp ,contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs b/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
new file mode 100644
index 0000000..b2ff75a
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
@@ -0,0 +1,51 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor DERIVATIONS ----
+#================================
+
+logger.info('Starting VARACTOR DERIVATIONS')
+
+exclude_layers = v5_xtor.or(fusetop).or(polyfuse).or(dualgate)
+ .or(lvs_bjt).or(drc_bjt).or(sab).or(esd).or(resistor).or(res_mk)
+ .or(cap_mk).or(nat).or(fhres).or(fusewindow_d).or(diode_mk)
+ .or(piscap).or(mos_cap_mk).or(mim_l_mk)
+
+# pn_varactor_1p8
+pn_varactor_1p8_tp = pcomp.outside(dnwell).inside(nwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# pn_varactor_1p8_dw
+pn_varactor_1p8_dw_tp = pcomp.inside(dnwell).inside(nwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# pn_varactor_6p0
+pn_varactor_6p0_tp = pcomp.outside(dnwell).inside(nwell).and(lvs_rf).and(dv2).not(exclude_layers)
+
+# pn_varactor_6p0_dw
+pn_varactor_6p0_dw_tp = pcomp.inside(dnwell).inside(nwell).and(lvs_rf).and(dv2).not(exclude_layers)
+
+
+# mos_varactor_1p8
+mos_varactor_1p8_g = ngate.inside(nwell).outside(dnwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# mos_varactor_1p8_dw
+mos_varactor_1p8_dw_g = ngate.inside(nwell).inside(dnwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# mos_varactor_6p0
+mos_varactor_6p0_g = ngate.inside(nwell).outside(dnwell).and(lvs_rf).and(dv2).not(exclude_layers)
+
+# mos_varactor_6p0_dw
+mos_varactor_6p0_dw_g = ngate.inside(nwell).inside(dnwell).and(lvs_rf).and(dv2).not(exclude_layers)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs b/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
new file mode 100644
index 0000000..1ef4ffe
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
@@ -0,0 +1,69 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor EXTRACTION ----
+#================================
+
+logger.info('Starting VARACTOR EXTRACTION')
+
+# pn_varactor_1p8
+logger.info('Extracting pn_varactor_1p8')
+extract_devices(capacitor('pn_varactor_1p8', 4.4e-15, VarCap),
+ { "P1" => pn_varactor_1p8_tp, "P2" => nwell_con,
+ "tA" => pn_varactor_1p8_tp, "tB" => nwell_con })
+
+# pn_varactor_1p8_dw
+logger.info('Extracting pn_varactor_1p8_dw')
+extract_devices(capacitor('pn_varactor_1p8_dw', 4.4e-15, VarCap),
+ { "P1" => pn_varactor_1p8_dw_tp, "P2" => dnwell,
+ "tA" => pn_varactor_1p8_dw_tp, "tB" => dnwell })
+
+# pn_varactor_6p0
+logger.info('Extracting pn_varactor_6p0')
+extract_devices(capacitor('pn_varactor_6p0', 4.4e-15, VarCap),
+ { "P1" => pn_varactor_6p0_tp, "P2" => nwell_con,
+ "tA" => pn_varactor_6p0_tp, "tB" => nwell_con })
+
+# pn_varactor_6p0_dw
+logger.info('Extracting pn_varactor_6p0_dw')
+extract_devices(capacitor('pn_varactor_6p0_dw', 4.4e-15, VarCap),
+ { "P1" => pn_varactor_6p0_dw_tp, "P2" => dnwell,
+ "tA" => pn_varactor_6p0_dw_tp, "tB" => dnwell })
+
+# mos_varactor_1p8
+logger.info('Extracting mos_varactor_1p8')
+extract_devices(capacitor('mos_varactor_1p8', 4.4e-15, VarCap),
+ { 'P1' => mos_varactor_1p8_g, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# mos_varactor_1p8_dw
+logger.info('Extracting mos_varactor_1p8_dw')
+extract_devices(capacitor('mos_varactor_1p8_dw', 4.4e-15, VarCap),
+ { 'P1' => mos_varactor_1p8_dw_g, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# mos_varactor_6p0
+logger.info('Extracting mos_varactor_6p0')
+extract_devices(capacitor('mos_varactor_6p0', 4.4e-15, VarCap),
+ { 'P1' => mos_varactor_6p0_g, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# mos_varactor_6p0_dw
+logger.info('Extracting mos_varactor_6p0_dw')
+extract_devices(capacitor('mos_varactor_6p0_dw', 4.4e-15, VarCap),
+ { 'P1' => mos_varactor_6p0_dw_g, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds
new file mode 100644
index 0000000..7efb14d
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds
new file mode 100644
index 0000000..6893fe8
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds
new file mode 100644
index 0000000..7a85d9f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds
new file mode 100644
index 0000000..280f16e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds
new file mode 100644
index 0000000..0bcb398
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds
new file mode 100644
index 0000000..576a490
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds
new file mode 100644
index 0000000..a91f22d
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds
new file mode 100644
index 0000000..ddbf511
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl
new file mode 100644
index 0000000..80daea9
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mos_varactor_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mos_varactor_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mos_varactor_1p8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_1p8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_1p8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_1p8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_1p8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_1p8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_1p8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_1p8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_1p8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_1p8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_1p8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl
new file mode 100644
index 0000000..918db43
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mos_varactor_1p8_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:12:27 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mos_varactor_1p8_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mos_varactor_1p8_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_1p8_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl
new file mode 100644
index 0000000..47c6313
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mos_varactor_6p0
+* View Name: schematic
+* Netlisted on: Nov 24 09:13:17 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mos_varactor_6p0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mos_varactor_6p0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_6p0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_6p0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_6p0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_6p0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_6p0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_6p0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_6p0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_6p0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_6p0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_6p0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl
new file mode 100644
index 0000000..05f01ad
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mos_varactor_6p0_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:15:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mos_varactor_6p0_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mos_varactor_6p0_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_6p0_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl
new file mode 100644
index 0000000..5395cc5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pn_varactor_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:49:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pn_varactor_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pn_varactor_1p8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_default_MINUS I1_default_PLUS
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS pn_varactor_1p8 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_1p8 m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl
new file mode 100644
index 0000000..adc3e1b
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pn_varactor_1p8_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:00 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pn_varactor_1p8_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pn_varactor_1p8_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS
++ I1_default_PLUS I1_default_MINUS
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_1p8_dw m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl
new file mode 100644
index 0000000..7a8a560
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pn_varactor_6p0
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pn_varactor_6p0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pn_varactor_6p0 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_default_MINUS I1_default_PLUS
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS pn_varactor_6p0 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_6p0 m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl
new file mode 100644
index 0000000..e7361a4
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pn_varactor_6p0_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:51:10 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pn_varactor_6p0_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pn_varactor_6p0_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS
++ I1_default_PLUS I1_default_MINUS
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_6p0_dw m=1 L=1u W=1u
+.ENDS
+
