Merge branch 'main' of https://github.com/mabrains/gf180_technology_dev into ic_diode_testcases
diff --git a/.github/workflows/regression.yml b/.github/workflows/drc_regression.yml
similarity index 80%
rename from .github/workflows/regression.yml
rename to .github/workflows/drc_regression.yml
index 8026e5f..0db8498 100644
--- a/.github/workflows/regression.yml
+++ b/.github/workflows/drc_regression.yml
@@ -12,7 +12,7 @@
# See the License for the specific language governing permissions and
# limitations under the License.
-name: regression testing
+name: DRC regression testing
# Prevent keeping resources busy when a branch/PR is updated
# https://docs.github.com/en/actions/using-jobs/using-concurrency
@@ -76,21 +76,4 @@
run: |
make test-"$(python3 -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
- lvs_regression:
- runs-on: ${{ fromJSON('["ubuntu-latest", "self-hosted"]')[github.repository == 'github/docs-internal'] }}
- strategy:
- fail-fast: false
- matrix:
- include:
- - { tool: klayout, part: lvs, test: main }
- - { tool: klayout, part: lvs, test: switch }
- name: ${{ matrix.part }} | ${{ matrix.test }}
-
- steps:
- - uses: actions/checkout@v3
- with:
- submodules: 'recursive'
- - name: Testing ${{ matrix.part }} for ${{ matrix.test }}
- run: |
- make test-"$(python3 -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
diff --git a/.github/workflows/lvs_regression.yml b/.github/workflows/lvs_regression.yml
new file mode 100644
index 0000000..3b26c9f
--- /dev/null
+++ b/.github/workflows/lvs_regression.yml
@@ -0,0 +1,77 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: LVS regression testing
+
+# Prevent keeping resources busy when a branch/PR is updated
+# https://docs.github.com/en/actions/using-jobs/using-concurrency
+concurrency:
+ group: ${{ github.repository }}-${{ github.workflow }}-${{ github.ref }}
+ cancel-in-progress: true
+
+on:
+ push:
+ pull_request:
+ workflow_dispatch:
+
+jobs:
+ lvs_switch:
+ runs-on: ubuntu-latest
+ strategy:
+ fail-fast: false
+ matrix:
+ include:
+ - { tool: klayout, part: lvs, test: switch }
+
+ name: ${{ matrix.part }} | ${{ matrix.test }}
+
+ steps:
+ - uses: actions/checkout@v3
+ with:
+ submodules: 'recursive'
+ - name: Testing ${{ matrix.part }} for ${{ matrix.test }}
+ run: |
+ make test-"$(python -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
+
+ build_lvs-matrix:
+ runs-on: ubuntu-latest
+ outputs:
+ lvs_table: ${{ steps.set-matrix.outputs.lvs_table }}
+ steps:
+ - uses: actions/checkout@v3
+ - id: set-matrix
+ run: |
+ lvs_table=`find -iname '*_extraction.lvs' | grep -i rule_decks | grep -v main | grep -v tail | awk -F'/' '{printf "\"%s-%s\",", $2, $NF}' | sed -e "s/^/[/g" -e "s/,$/]/g" -e "s/_extraction.lvs//g"`
+ lvs_table=`echo $lvs_table | jq -c .`
+ echo $lvs_table
+ echo "lvs_table=$lvs_table" >>$GITHUB_OUTPUT
+
+ lvs_regression:
+ needs: build_lvs-matrix
+ runs-on: ubuntu-latest
+ strategy:
+ fail-fast: false
+ matrix:
+ part: [lvs]
+ test: ${{ fromJson(needs.build_lvs-matrix.outputs.lvs_table) }}
+
+ name: ${{ matrix.part }} | ${{ matrix.test }}
+
+ steps:
+ - uses: actions/checkout@v3
+ with:
+ submodules: 'recursive'
+ - name: Testing ${{ matrix.part }} for ${{ matrix.test }}
+ run: |
+ make test-"$(python -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
diff --git a/BCDLite/klayout/lvs/gf180BCDLite.lvs b/BCDLite/klayout/lvs/gf180BCDLite.lvs
index 7937bfe..e489b67 100644
--- a/BCDLite/klayout/lvs/gf180BCDLite.lvs
+++ b/BCDLite/klayout/lvs/gf180BCDLite.lvs
@@ -183,6 +183,21 @@
logger.info("METAL_STACK Selected is #{METAL_LEVEL}")
+# POLY_RES
+POLY_RES = $poly_res || '1k'
+
+logger.info("POLY_RES Selected is #{POLY_RES}")
+
+# MIM
+MIM_OPTION = $mim_option || 'B'
+
+logger.info("MIM Option selected: #{MIM_OPTION}")
+
+# MIM
+MIM_CAP = $mim_cap || '2'
+
+logger.info("MIM CAP selected: #{MIM_CAP}")
+
#================================================
# --------------- CUSTOM CLASSES ----------------
#================================================
@@ -209,10 +224,10 @@
end
#================================================
-#------------- LAYERS DERIVATIONS ---------------
+#------------- LAYERS DEFINITIONS ---------------
#================================================
-%include rule_decks/layers_definitions.lvs
+# %include rule_decks/layers_definition.lvs
#================================================================
#------------------------- MAIN RUNSET --------------------------
@@ -224,25 +239,49 @@
#------------- LAYERS DERIVATIONS ---------------
#================================================
-logger.info('Starting deriving base layers.')
+logger.info('Starting base layers derivations')
#==================================
# ------ GENERAL DERIVATIONS ------
#==================================
-%include rule_decks/general_derivations.lvs
+# %include rule_decks/general_derivations.lvs
#================================
# ------ BJT DERIVATIONS --------
#================================
-%include rule_decks/bjt_derivations.lvs
+# %include rule_decks/bjt_derivations.lvs
+
+#=================================
+# ------ DIODE DERIVATIONS -------
+#=================================
+
+# %include rule_decks/diode_derivations.lvs
+
+#==================================
+# ------ MIMCAP DERIVATIONS -------
+#==================================
+
+# %include rule_decks/mimcap_derivations.lvs
+
+#====================================
+# ------ VARACTOR DERIVATIONS -------
+#====================================
+
+# %include rule_decks/varactor_derivations.lvs
+
+#==================================
+# ------ PISCAP DERIVATIONS -------
+#==================================
+
+# %include rule_decks/piscap_derivations.lvs
#================================================
#------------ DEVICES CONNECTIVITY --------------
#================================================
-%include rule_decks/devices_connections.lvs
+# %include rule_decks/devices_connections.lvs
#================================================
#------------- DEVICES EXTRACTION ---------------
@@ -254,7 +293,31 @@
# ------- BJT EXTRACTION --------
#================================
-%include rule_decks/bjt_extraction.lvs
+# %include rule_decks/bjt_extraction.lvs
+
+#=================================
+# ------- DIODE EXTRACTION -------
+#=================================
+
+# %include rule_decks/diode_extraction.lvs
+
+#==================================
+# ------- MIMCAP EXTRACTION -------
+#==================================
+
+# %include rule_decks/mimcap_extraction.lvs
+
+#====================================
+# ------- VARACTOR EXTRACTION -------
+#====================================
+
+# %include rule_decks/varactor_extraction.lvs
+
+#=================================
+# ------- PICAP EXTRACTION -------
+#=================================
+
+# %include rule_decks/piscap_extraction.lvs
#================================================
#------------- COMPARISON OPTIONS ---------------
diff --git a/BCDLite/klayout/lvs/rule_decks/bjt_connections.lvs b/BCDLite/klayout/lvs/rule_decks/bjt_connections.lvs
new file mode 100644
index 0000000..5d1e477
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/bjt_connections.lvs
@@ -0,0 +1,73 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ------ BJT CONNECTIONS --------
+#================================
+logger.info('Starting LVS BJT CONNECTIONS')
+
+# ==============
+# ---- vnpn ----
+# ==============
+
+# npn_05p00x05p00 nodes connections
+connect(npn_05p00x05p00_e, contact)
+connect(npn_05p00x05p00_b, contact)
+connect(npn_05p00x05p00_c, contact)
+
+# npn_00p54x16p00 nodes connections
+connect(npn_00p54x16p00_e, contact)
+connect(npn_00p54x16p00_b, contact)
+connect(npn_00p54x16p00_c, contact)
+
+# npn_00p54x08p00 nodes connections
+connect(npn_00p54x08p00_e, contact)
+connect(npn_00p54x08p00_b, contact)
+connect(npn_00p54x08p00_c, contact)
+
+# npn_00p54x02p00 nodes connections
+connect(npn_00p54x02p00_e, contact)
+connect(npn_00p54x02p00_b, contact)
+connect(npn_00p54x02p00_c, contact)
+
+# ==============
+# ---- vpnp ----
+# ==============
+
+# pnp_10p00x10p00_06v0 nodes connections
+connect(pnp_10p00x10p00_06v0_e, contact)
+connect(pnp_10p00x10p00_06v0_b, contact)
+connect(pnp_10p00x10p00_06v0_c, contact)
+
+# pnp_05p00x05p00_06v0 nodes connections
+connect(pnp_05p00x05p00_06v0_e, contact)
+connect(pnp_05p00x05p00_06v0_b, contact)
+connect(pnp_05p00x05p00_06v0_c, contact)
+
+# pnp_00p42x20p00_06v0 nodes connections
+connect(pnp_00p42x20p00_06v0_e, contact)
+connect(pnp_00p42x20p00_06v0_b, contact)
+connect(pnp_00p42x20p00_06v0_c, contact)
+
+# pnp_00p42x10p00_06v0 nodes connections
+connect(pnp_00p42x10p00_06v0_e, contact)
+connect(pnp_00p42x10p00_06v0_b, contact)
+connect(pnp_00p42x10p00_06v0_c, contact)
+
+# pnp_00p42x05p00_06v0 nodes connections
+connect(pnp_00p42x05p00_06v0_e, contact)
+connect(pnp_00p42x05p00_06v0_b, contact)
+connect(pnp_00p42x05p00_06v0_c, contact)
diff --git a/BCDLite/klayout/lvs/rule_decks/bjt_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/bjt_derivations.lvs
index 8bf3f8f..21e4a69 100644
--- a/BCDLite/klayout/lvs/rule_decks/bjt_derivations.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/bjt_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -25,10 +25,17 @@
# ==============
logger.info('Starting vnpn layers DERIVATIONS')
+bjt_exclude_layers = resistor.or(esd).or(sab).or(dni).or(pwhv).or(fusewindow_d).or(polyfuse)
+ .or(schottky_diode).or(zener).or(piscap).or(res_mk).or(diode_mk)
+ .or(v5_xtor).or(nat).or(fhres).or(mos_cap_mk).or(mvsd).or(mvpsd)
+ .or(elmd_mk).or(elmd2_mk).or(lvs_rf).or(lvs_source).or(mk_35v)
+ .or(lvs_35v).or(well_diode_mk).or(esd_hbm_mk).or(mos_mk_type1)
+ .or(swfet_mk).or(mom_mk).or(hvnddd).or(hvpddd).or(hvpolyrs).or(ldmos_xtor)
+
# vnpn general nodes DERIVATIONS
-vnpn_e = ncomp_mv.interacting(lvs_bjt).and(dnwell)
-vnpn_b = pcomp_mv.and(drc_bjt).and(lvpwell).and(dnwell)
-vnpn_c = ncomp_mv.and(drc_bjt).not(lvs_bjt).and(dnwell)
+vnpn_e = ncomp_mv.interacting(lvs_bjt).and(dnwell).and(dualgate2_d).not(bjt_exclude_layers)
+vnpn_b = pcomp_mv.and(drc_bjt).and(lvpwell).and(dnwell).and(dualgate2_d).not(bjt_exclude_layers)
+vnpn_c = ncomp_mv.and(drc_bjt).not(lvs_bjt).and(dnwell).and(dualgate2_d).not(bjt_exclude_layers)
# npn_05p00x05p00 nodes DERIVATIONS
npn_05p00x05p00_e = vnpn_e.with_area(24.5.um, 25.5.um).interacting(vnpn_e.edges.with_length(4.8.um, 5.2.um))
@@ -56,9 +63,9 @@
logger.info('Starting vpnp layers DERIVATIONS')
# vpnp general nodes DERIVATIONS
-vpnp_e = pcomp_mv.and(nwell).interacting(lvs_bjt).not(dnwell)
-vpnp_b = ncomp_mv.and(nwell).and(drc_bjt).not(dnwell)
-vpnp_c = ptap_mv.not(lvs_bjt).and(drc_bjt).not(dnwell)
+vpnp_e = pcomp_mv.and(nwell).interacting(lvs_bjt).not(dnwell).and(dualgate2_d).not(bjt_exclude_layers)
+vpnp_b = ncomp_mv.and(nwell).and(drc_bjt).not(dnwell).and(dualgate2_d).not(bjt_exclude_layers)
+vpnp_c = ptap_mv.not(lvs_bjt).and(drc_bjt).not(dnwell).and(dualgate2_d).not(bjt_exclude_layers)
# pnp_10p00x10p00_06v0 nodes DERIVATIONS
pnp_10p00x10p00_06v0_e = vpnp_e.with_area(99.5.um, 100.5.um).interacting(vpnp_e.edges.with_length(9.8.um, 10.2.um))
diff --git a/BCDLite/klayout/lvs/rule_decks/bjt_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/bjt_extraction.lvs
index a28bd75..775eed1 100644
--- a/BCDLite/klayout/lvs/rule_decks/bjt_extraction.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/bjt_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -25,10 +25,10 @@
# ====================
logger.info('Starting vnpn BJT EXTRACTION')
-# npn_05p00x05p00 BJT
-ignore_parameter('npn_05p00x05p00', 'AE')
-logger.info('Extracting npn_05p00x05p00 BJT')
-extract_devices(bjt4('npn_05p00x05p00'), { 'C' => npn_05p00x05p00_c.extents,
+# vnpn_5x5 BJT
+ignore_parameter('vnpn_5x5', 'AE')
+logger.info('Extracting vnpn_5x5 BJT')
+extract_devices(bjt4('vnpn_5x5'), { 'C' => npn_05p00x05p00_c.extents,
'B' => npn_05p00x05p00_b.extents,
'E' => npn_05p00x05p00_e,
'S' => sub.extents,
@@ -37,10 +37,10 @@
'tE' => npn_05p00x05p00_e,
'tS' => sub })
-# npn_00p54x16p00 BJT
-ignore_parameter('npn_00p54x16p00', 'AE')
-logger.info('Extracting npn_00p54x16p00 BJT')
-extract_devices(bjt4('npn_00p54x16p00'), { 'C' => npn_00p54x16p00_c.extents,
+# vnpn_0p54x16 BJT
+ignore_parameter('vnpn_0p54x16', 'AE')
+logger.info('Extracting vnpn_0p54x16 BJT')
+extract_devices(bjt4('vnpn_0p54x16'), { 'C' => npn_00p54x16p00_c.extents,
'B' => npn_00p54x16p00_b.extents,
'E' => npn_00p54x16p00_e,
'S' => sub.extents,
@@ -49,10 +49,10 @@
'tE' => npn_00p54x16p00_e,
'tS' => sub })
-# npn_00p54x08p00 BJT
-ignore_parameter('npn_00p54x08p00', 'AE')
-logger.info('Extracting npn_00p54x08p00 BJT')
-extract_devices(bjt4('npn_00p54x08p00'), { 'C' => npn_00p54x08p00_c.extents,
+# vnpn_0p54x8 BJT
+ignore_parameter('vnpn_0p54x8', 'AE')
+logger.info('Extracting vnpn_0p54x8 BJT')
+extract_devices(bjt4('vnpn_0p54x8'), { 'C' => npn_00p54x08p00_c.extents,
'B' => npn_00p54x08p00_b.extents,
'E' => npn_00p54x08p00_e,
'S' => sub.extents,
@@ -61,10 +61,10 @@
'tE' => npn_00p54x08p00_e,
'tS' => sub })
-# npn_00p54x02p00 BJT
-ignore_parameter('npn_00p54x02p00', 'AE')
-logger.info('Extracting npn_00p54x02p00 BJT')
-extract_devices(bjt4('npn_00p54x02p00'), { 'C' => npn_00p54x02p00_c.extents,
+# vnpn_0p54x2 BJT
+ignore_parameter('vnpn_0p54x2', 'AE')
+logger.info('Extracting vnpn_0p54x2 BJT')
+extract_devices(bjt4('vnpn_0p54x2'), { 'C' => npn_00p54x02p00_c.extents,
'B' => npn_00p54x02p00_b.extents,
'E' => npn_00p54x02p00_e,
'S' => sub.extents,
@@ -78,49 +78,49 @@
# ====================
logger.info('Starting vpnp BJT EXTRACTION')
-# pnp_10p00x10p00_06v0 BJT
-ignore_parameter('pnp_10p00x10p00_06v0', 'AE')
-logger.info('Extracting pnp_10p00x10p00_06v0 BJT')
-extract_devices(bjt3('pnp_10p00x10p00_06v0'), { 'C' => pnp_10p00x10p00_06v0_c.extents,
+# vpnp_6p0_10x10 BJT
+ignore_parameter('vpnp_6p0_10x10', 'AE')
+logger.info('Extracting vpnp_6p0_10x10 BJT')
+extract_devices(bjt3('vpnp_6p0_10x10'), { 'C' => pnp_10p00x10p00_06v0_c.extents,
'B' => pnp_10p00x10p00_06v0_b.extents,
'E' => pnp_10p00x10p00_06v0_e,
'tC' => pnp_10p00x10p00_06v0_c,
'tB' => pnp_10p00x10p00_06v0_b,
'tE' => pnp_10p00x10p00_06v0_e })
-# pnp_05p00x05p00_06v0 BJT
-ignore_parameter('pnp_05p00x05p00_06v0', 'AE')
-logger.info('Extracting pnp_05p00x05p00_06v0 BJT')
-extract_devices(bjt3('pnp_05p00x05p00_06v0'), { 'C' => pnp_05p00x05p00_06v0_c.extents,
+# vpnp_6p0_5x5 BJT
+ignore_parameter('vpnp_6p0_5x5', 'AE')
+logger.info('Extracting vpnp_6p0_5x5 BJT')
+extract_devices(bjt3('vpnp_6p0_5x5'), { 'C' => pnp_05p00x05p00_06v0_c.extents,
'B' => pnp_05p00x05p00_06v0_b.extents,
'E' => pnp_05p00x05p00_06v0_e,
'tC' => pnp_05p00x05p00_06v0_c,
'tB' => pnp_05p00x05p00_06v0_b,
'tE' => pnp_05p00x05p00_06v0_e })
-# pnp_00p42x20p00_06v0 BJT
-ignore_parameter('pnp_00p42x20p00_06v0', 'AE')
-logger.info('Extracting pnp_00p42x20p00_06v0 BJT')
-extract_devices(bjt3('pnp_00p42x20p00_06v0'), { 'C' => pnp_00p42x20p00_06v0_c.extents,
+# vpnp_6p0_0p42x20 BJT
+ignore_parameter('vpnp_6p0_0p42x20', 'AE')
+logger.info('Extracting vpnp_6p0_0p42x20 BJT')
+extract_devices(bjt3('vpnp_6p0_0p42x20'), { 'C' => pnp_00p42x20p00_06v0_c.extents,
'B' => pnp_00p42x20p00_06v0_b.extents,
'E' => pnp_00p42x20p00_06v0_e,
'tC' => pnp_00p42x20p00_06v0_c,
'tB' => pnp_00p42x20p00_06v0_b,
'tE' => pnp_00p42x20p00_06v0_e })
-# pnp_00p42x10p00_06v0 BJT
-ignore_parameter('pnp_00p42x10p00_06v0', 'AE')
-logger.info('Extracting pnp_00p42x10p00_06v0 BJT')
-extract_devices(bjt3('pnp_00p42x10p00_06v0'), { 'C' => pnp_00p42x10p00_06v0_c.extents,
+# vpnp_6p0_0p42x10 BJT
+ignore_parameter('vpnp_6p0_0p42x10', 'AE')
+logger.info('Extracting vpnp_6p0_0p42x10 BJT')
+extract_devices(bjt3('vpnp_6p0_0p42x10'), { 'C' => pnp_00p42x10p00_06v0_c.extents,
'B' => pnp_00p42x10p00_06v0_b.extents,
'E' => pnp_00p42x10p00_06v0_e,
'tC' => pnp_00p42x10p00_06v0_c,
'tB' => pnp_00p42x10p00_06v0_b,
'tE' => pnp_00p42x10p00_06v0_e })
-# pnp_00p42x05p00_06v0 BJT
-ignore_parameter('pnp_00p42x05p00_06v0', 'AE')
-logger.info('Extracting pnp_00p42x05p00_06v0 BJT')
-extract_devices(bjt3('pnp_00p42x05p00_06v0'), { 'C' => pnp_00p42x05p00_06v0_c.extents,
+# vpnp_6p0_0p42x5 BJT
+ignore_parameter('vpnp_6p0_0p42x5', 'AE')
+logger.info('Extracting vpnp_6p0_0p42x5 BJT')
+extract_devices(bjt3('vpnp_6p0_0p42x5'), { 'C' => pnp_00p42x05p00_06v0_c.extents,
'B' => pnp_00p42x05p00_06v0_b.extents,
'E' => pnp_00p42x05p00_06v0_e,
'tC' => pnp_00p42x05p00_06v0_c,
diff --git a/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs b/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs
new file mode 100644
index 0000000..333f1e2
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/custom_classes.lvs
@@ -0,0 +1,180 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================================
+# --------------- CUSTOM CLASSES ----------------
+#================================================
+
+#=========== CUSTOM READER ===========
+class SubcircuitModelsReader < RBA::NetlistSpiceReaderDelegate
+ def parse_element(sup, element)
+ begin
+ super
+ rescue
+ case element
+ when 'C'
+ super("#{sup} C=2e-16", element)
+ when 'R'
+ super("#{sup} R=0", element)
+ else
+ super
+ end
+ end
+ end
+
+ # implements the delegate interface:
+ # take and translate the element
+ def element(circuit, ele, name, model, value, nets, params)
+ case ele
+ when 'C'
+ error('Capacitor needs two nodes') if nets.size != 2
+
+ # provide a device class
+ cls = circuit.netlist.device_class_by_name(model)
+ unless cls
+ cls = RBA::DeviceClassCapacitor.new
+ cls.name = model
+ circuit.netlist.add(cls)
+ end
+
+ # create a device
+ device = circuit.create_device(cls, name)
+
+ # and configure the device
+ %w[A B].each_with_index do |t, index|
+ device.connect_terminal(t, nets[index])
+ end
+
+ # parameters in the model are given in micrometer units, so
+ # we need to translate the parameter values from SI to um values:
+ device.set_parameter('A', ((params['W'] || 0.0) * (params['L'] || 0.0)) * 1e12)
+ device.set_parameter('P', ((params['W'] || 0.0) + (params['L'] || 0.0)) * 2e6)
+ device.set_parameter('C', (params['C'] || 0.0))
+
+ when 'R'
+ case nets.size
+ when 3
+ # provide a device class
+ cls = circuit.netlist.device_class_by_name(model)
+ unless cls
+ cls = RBA::DeviceClassResistorWithBulk.new
+ cls.name = model
+ circuit.netlist.add(cls)
+ end
+
+ # create a device
+ device = circuit.create_device(cls, name)
+
+ # and configure the device
+ %w[A B W].each_with_index do |t, index|
+ device.connect_terminal(t, nets[index])
+ end
+
+ when 2
+ # provide a device class
+ cls = circuit.netlist.device_class_by_name(model)
+ unless cls
+ cls = RBA::DeviceClassResistor.new
+ cls.name = model
+ circuit.netlist.add(cls)
+ end
+
+ # create a device
+ device = circuit.create_device(cls, name)
+
+ # and configure the device
+ %w[A B].each_with_index do |t, index|
+ device.connect_terminal(t, nets[index])
+ end
+
+ else
+ error('Resistor needs two or three nodes')
+
+ end
+
+ # parameters in the model are given in micrometer units, so
+ # we need to translate the parameter values from SI to um values:
+ device.set_parameter('W', ((params['W'] || 0.0) * (params['PAR'] || 1.0)) * 1e6)
+ device.set_parameter('L', ((params['L'] || 0.0) * (params['S'] || 1.0)) * 1e6)
+ device.set_parameter('R', (params['R'] * (params['S'] || 1.0) / (params['PAR'] || 1.0)))
+
+ else
+ return super
+
+ end
+ true
+ end
+end
+
+# 4 terminals resistor device extractor
+class BResistor < RBA::DeviceClassResistorWithBulk
+ def initialize
+ super
+ enable_parameter('R', false)
+ enable_parameter('W', true)
+ enable_parameter('L', true)
+ end
+end
+
+# 3 terminals resistor device extractor
+class NResistor < RBA::DeviceClassResistor
+ def initialize
+ super
+ enable_parameter('R', false)
+ enable_parameter('W', true)
+ enable_parameter('L', true)
+ end
+end
+
+# MosCap device extractor
+class MosCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter('C', false)
+ enable_parameter('A', true)
+ enable_parameter('P', true)
+ end
+end
+
+# MIMCAP device extractor
+class MIMCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter('C', true)
+ enable_parameter('A', true)
+ enable_parameter('P', true)
+ end
+end
+
+# VARACTOR device extractor
+class VarCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
+end
+
+# PISCAP device extractor
+class PisCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
+end
diff --git a/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs b/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs
index 7b2ed18..ac9fab0 100644
--- a/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -24,124 +24,28 @@
# ----- GENERAL CONNECTIONS -----
#================================
-logger.info('Starting GF180 LVS connectivity setup (Inter-layer)')
-
-# Inter-layer
-connect(sub, ptap)
-connect(lvpwell_con, ptap)
-connect(lvpwell_con, ptap_dw)
-connect(dnwell, ntap_dw)
-connect(nwell_con, ntap)
-connect(ptap, contact)
-connect(ptap_dw, contact)
-connect(ntap, contact)
-connect(ntap_dw, contact)
-connect(psd, contact)
-connect(psd_dw, contact)
-connect(nsd, contact)
-connect(poly2_con, contact)
-connect(contact, metal1_con)
-connect(metal1_con, via1)
-connect(via1, metal2_ncap)
-if METAL_LEVEL != '2LM'
- connect(metal2_ncap, via2)
- connect(via2, metal3_ncap)
- if METAL_LEVEL != '3LM'
- connect(metal3_ncap, via3)
- connect(via3, metal4_ncap)
- if METAL_LEVEL != '4LM'
- connect(metal4_ncap, via4)
- connect(via4, metal5_ncap)
- if METAL_LEVEL != '5LM'
- connect(metal5_ncap, via5)
- connect(via5, metaltop_con)
- end
- end
- end
-end
-
-logger.info('Starting GF180 LVS connectivity setup (Attaching labels)')
-
-# Attaching labels
-connect(comp, comp_label)
-connect(poly2_con, poly2_label)
-connect(metal1_con, metal1_label)
-connect(metal2_ncap, metal2_label)
-if METAL_LEVEL != '2LM'
- connect(metal3_ncap, metal3_label)
- if METAL_LEVEL != '3LM'
- connect(metal4_ncap, metal4_label)
- if METAL_LEVEL != '4LM'
- connect(metal5_ncap, metal5_label)
- connect(metaltop_con, metaltop_label) if METAL_LEVEL != '5LM'
- end
- end
-end
-
-logger.info('Starting GF180 LVS connectivity setup (Global)')
-
-# Global
-connect_global(sub, substrate_name)
-
-logger.info('Starting GF180 LVS connectivity setup (Multifinger Devices)')
-
-# Multifinger Devices
-connect_implicit('*')
+# %include general_connections.lvs
#================================
# ------ BJT CONNECTIONS --------
#================================
-logger.info('Starting LVS BJT CONNECTIONS')
-# ==============
-# ---- vnpn ----
-# ==============
+# %include bjt_connections.lvs
-# npn_05p00x05p00 nodes connections
-connect(npn_05p00x05p00_e, contact)
-connect(npn_05p00x05p00_b, contact)
-connect(npn_05p00x05p00_c, contact)
+#=================================
+# ------ DIODE CONNECTIONS -------
+#=================================
-# npn_00p54x16p00 nodes connections
-connect(npn_00p54x16p00_e, contact)
-connect(npn_00p54x16p00_b, contact)
-connect(npn_00p54x16p00_c, contact)
+# %include diode_connections.lvs
-# npn_00p54x08p00 nodes connections
-connect(npn_00p54x08p00_e, contact)
-connect(npn_00p54x08p00_b, contact)
-connect(npn_00p54x08p00_c, contact)
+#==================================
+# ------ MIMCAP CONNECTIONS -------
+#==================================
-# npn_00p54x02p00 nodes connections
-connect(npn_00p54x02p00_e, contact)
-connect(npn_00p54x02p00_b, contact)
-connect(npn_00p54x02p00_c, contact)
+# %include mimcap_connections.lvs
-# ==============
-# ---- vpnp ----
-# ==============
+#====================================
+# ------ VARACTOR CONNECTIONS -------
+#====================================
-# pnp_10p00x10p00_06v0 nodes connections
-connect(pnp_10p00x10p00_06v0_e, contact)
-connect(pnp_10p00x10p00_06v0_b, contact)
-connect(pnp_10p00x10p00_06v0_c, contact)
-
-# pnp_05p00x05p00_06v0 nodes connections
-connect(pnp_05p00x05p00_06v0_e, contact)
-connect(pnp_05p00x05p00_06v0_b, contact)
-connect(pnp_05p00x05p00_06v0_c, contact)
-
-# pnp_00p42x20p00_06v0 nodes connections
-connect(pnp_00p42x20p00_06v0_e, contact)
-connect(pnp_00p42x20p00_06v0_b, contact)
-connect(pnp_00p42x20p00_06v0_c, contact)
-
-# pnp_00p42x10p00_06v0 nodes connections
-connect(pnp_00p42x10p00_06v0_e, contact)
-connect(pnp_00p42x10p00_06v0_b, contact)
-connect(pnp_00p42x10p00_06v0_c, contact)
-
-# pnp_00p42x05p00_06v0 nodes connections
-connect(pnp_00p42x05p00_06v0_e, contact)
-connect(pnp_00p42x05p00_06v0_b, contact)
-connect(pnp_00p42x05p00_06v0_c, contact)
+# %include varactor_connections.lvs
diff --git a/BCDLite/klayout/lvs/rule_decks/diode_connections.lvs b/BCDLite/klayout/lvs/rule_decks/diode_connections.lvs
new file mode 100644
index 0000000..c0be24e
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/diode_connections.lvs
@@ -0,0 +1,142 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- DIODE CONNECTIONS -------
+#================================
+
+logger.info('Starting LVS DIODE CONNECTIONS')
+
+#=====================
+# --- NP 1P8 DIODE ---
+#=====================
+
+# diode_nd2ps_01v8: Model for 1.8V P+/Nwell diode (outside DNWELL) [np_1p8]
+connect(diode_nd2ps_01v8_terminal_n, contact)
+
+# diode_nd2ps_01v8_dn: Model for 1.8V N+/Psub diode (inside DNWELL) [np_1p8_dw]
+connect(diode_nd2ps_01v8_dn_terminal_n, contact)
+
+#=====================
+# --- PN 1P8 DIODE ---
+#=====================
+
+# diode_pd2nw_01v8: Model for 1.8V P+/Nwell diode (outside DNWELL) [pn_1p8]
+connect(diode_pd2nw_01v8_terminal_p, contact)
+
+# diode_pd2nw_01v8_dn: Model for 1.8V P+/Nwell diode (inside DNWELL) [pn_1p8_dw]
+connect(diode_pd2nw_01v8_dn_terminal_p, contact)
+
+#=====================
+# --- NP 6P0 DIODE ---
+#=====================
+
+# diode_nd2ps_06v0: Model for 6V N+/Pwell diode (outside DNWELL) [np_6p0]
+connect(diode_nd2ps_06v0_terminal_n, contact)
+
+# diode_nd2ps_06v0_dn: Model for 6V N+/Psub diode (inside DNWELL) [np_6p0_dw]
+connect(diode_nd2ps_06v0_dn_terminal_n, contact)
+
+#=====================
+# --- PN 6P0 DIODE ---
+#=====================
+
+# diode_pd2nw_06v0: Model for 6V P+/Nwell diode (outside DNWELL) [pn_6p0]
+connect(diode_pd2nw_06v0_terminal_p, contact)
+
+# diode_pd2nw_06v0_dn: Model for 6V P+/Nwell diode (inside DNWELL) [pn_6p0_dw]
+connect(diode_pd2nw_06v0_dn_terminal_p, contact)
+
+#======================
+# --- NWP 6P0 DIODE ---
+#======================
+
+# diode_nw2ps_06v0: Model for Nwell/Psub diode (applicable for both 1.8V/6V) [nwp_6p0]
+connect(diode_nw2ps_06v0_terminal_p, contact)
+connect(diode_nw2ps_06v0_terminal_n, nwell)
+
+#====================
+# --- DNWPW DIODE ---
+#====================
+
+# diode_pw2dw: Model for LVPWELL/DNWELL diode (applicable for both 1.8V/6V) [dnwpw]
+connect(diode_pw2dw_terminal_p, contact)
+
+#======================
+# --- DNWPWHV DIODE ---
+#======================
+
+# diode_pw2dw_hv: Model for NW/PWHV diode (10V diode) [dnwpwhv]
+connect(diode_pw2dw_hv_terminal_n, contact)
+connect(diode_pw2dw_hv_terminal_p, contact)
+
+#=======================
+# --- DPWHVDNW DIODE ---
+#=======================
+
+# diode_pw2dnw_hv: Model for PWHV/DNW diode [dpwhvdnw]
+connect(diode_pw2dnw_hv_terminal_n, contact)
+connect(diode_pw2dnw_hv_terminal_p, contact)
+
+#======================
+# --- NP 30P0 DIODE ---
+#======================
+
+# diode_nd2ps_30v0: Model for HVNDDD/Psub diode [np_30p0]
+connect(diode_nd2ps_30v0_terminal_n, contact)
+connect(diode_nd2ps_30v0_terminal_p, contact)
+
+#======================
+# --- PN 30P0 DIODE ---
+#======================
+
+# diode_pd2nw_30v0: Model for HVPDDD/DNWELL diode [np_30p0]
+connect(diode_pd2nw_30v0_terminal_n, contact)
+
+#====================
+# --- DNWPS DIODE ---
+#====================
+
+# diode_dw2ps: Model for DNWELL/Psub diode(1.8V/6V) [dnwps]
+connect(diode_dw2ps_terminal_p, contact)
+
+#=================
+# --- SC DIODE ---
+#=================
+
+# diode_sc: Model for schottky diode [sc_diode]
+connect(diode_sc_terminal_n, contact)
+connect(diode_sc_terminal_p, schottky_diode)
+
+#====================
+# --- ZENER DIODE ---
+#====================
+
+# diode_zener: Model for zener diode outside DNWELL [zener_diode]
+connect(diode_zener_terminal_n, contact)
+connect(diode_zener_terminal_p, zener)
+
+# diode_zener_dn: Model for zener diode inside DNWELL [zener_diode_dw]
+connect(diode_zener_dn_terminal_n, contact)
+connect(diode_zener_dn_terminal_p, zener)
+
+#===================
+# --- POLY DIODE ---
+#===================
+
+# diode_poly: Model for poly diode [poly_diode]
+connect(diode_poly_terminal_n, contact)
+connect(diode_poly_terminal_p, contact)
diff --git a/BCDLite/klayout/lvs/rule_decks/diode_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/diode_derivations.lvs
new file mode 100644
index 0000000..be7cc47
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/diode_derivations.lvs
@@ -0,0 +1,225 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- DIODE DERIVATIONS -------
+#================================
+
+logger.info('Starting DIODE DERIVATIONS')
+
+#================================
+# ------ DIODE DERIVATIONS ------
+#================================
+
+#======================
+# --- DIODE EXCLUDE ---
+#======================
+
+diode_exclude = resistor.join(esd).join(sab).join(fusewindow_d)
+ .join(polyfuse).join(piscap).join(v5_xtor)
+ .join(drc_bjt).join(nat).join(fhres).join(dni)
+ .join(mos_cap_mk).join(mvpsd).join(elmd_mk)
+ .join(elmd2_mk).join(lvs_rf).join(lvs_source)
+ .join(mk_35v).join(lvs_35v).join(esd_hbm_mk)
+ .join(mos_mk_type1).join(swfet_mk).join(hvpolyrs)
+
+diode_nd2ps_pd2nw_exclude = diode_exclude.join(poly2).join(pwhv)
+ .join(schottky_diode).join(zener).join(res_mk)
+ .join(mvsd).join(hvnddd).join(hvpddd)
+ .join(ldmos_xtor)
+#=====================
+# --- NP 1P8 DIODE ---
+#=====================
+
+diode_nd2ps_01v8_exclude = diode_nd2ps_pd2nw_exclude.join(nwell).join(pplus).join(dualgate2_d)
+diode_nd2ps_01v8 = ncomp.and(diode_mk).not(diode_nd2ps_01v8_exclude)
+
+# diode_nd2ps_01v8: Model for 1.8V N+/Psub diode (outside DNWELL) [np_1p8]
+diode_nd2ps_01v8_terminal_n = diode_nd2ps_01v8.not(dnwell)
+
+# diode_nd2ps_01v8_dn: Model for 1.8V N+/Psub diode (inside DNWELL) [np_1p8_dw]
+diode_nd2ps_01v8_dn_terminal_n = diode_nd2ps_01v8.and(dnwell)
+
+#=====================
+# --- PN 1P8 DIODE ---
+#=====================
+
+diode_pd2nw_01v8_exclude = diode_nd2ps_pd2nw_exclude.join(lvpwell).join(nplus).join(dualgate2_d)
+diode_pd2nw_01v8 = pcomp.and(diode_mk).not(diode_pd2nw_01v8_exclude)
+
+# diode_pd2nw_01v8: Model for 1.8V P+/Nwell diode (outside DNWELL) [pn_1p8]
+diode_pd2nw_01v8_terminal_p = diode_pd2nw_01v8.not(dnwell)
+
+# diode_pd2nw_01v8_dn: Model for 1.8V P+/Nwell diode (inside DNWELL) [pn_1p8_dw]
+diode_pd2nw_01v8_dn_terminal_p = diode_pd2nw_01v8.and(dnwell)
+
+#=====================
+# --- NP 6P0 DIODE ---
+#=====================
+
+diode_nd2ps_06v0_exclude = diode_nd2ps_pd2nw_exclude.join(nwell).join(pplus)
+diode_nd2ps_06v0 = ncomp.and(diode_mk).and(dualgate2_d).not(diode_nd2ps_06v0_exclude)
+
+# diode_nd2ps_06v0: Model for 6V N+/Pwell diode (outside DNWELL) [np_6p0]
+diode_nd2ps_06v0_terminal_n = diode_nd2ps_06v0.not(dnwell)
+
+# diode_nd2ps_06v0_dn: Model for 6V N+/Psub diode (inside DNWELL) [np_6p0_dw]
+diode_nd2ps_06v0_dn_terminal_n = diode_nd2ps_06v0.and(dnwell)
+
+#=====================
+# --- PN 6P0 DIODE ---
+#=====================
+
+diode_pd2nw_06v0_exclude = diode_nd2ps_pd2nw_exclude.join(lvpwell).join(nplus)
+diode_pd2nw_06v0 = pcomp.and(diode_mk).and(dualgate2_d).not(diode_pd2nw_06v0_exclude)
+
+# diode_pd2nw_06v0: Model for 6V P+/Nwell diode (outside DNWELL) [pn_6p0]
+diode_pd2nw_06v0_terminal_p = diode_pd2nw_06v0.not(dnwell)
+
+# diode_pd2nw_06v0_dn: Model for 6V P+/Nwell diode (inside DNWELL) [pn_6p0_dw]
+diode_pd2nw_06v0_dn_terminal_p = diode_pd2nw_06v0.and(dnwell)
+
+#======================
+# --- NWP 6P0 DIODE ---
+#======================
+
+diode_nw2ps_06v0_exclude = diode_nd2ps_pd2nw_exclude.join(dnwell).join(lvpwell)
+
+# diode_nw2ps_06v0: Model for Nwell/Psub diode (applicable for both 1.8V/6V) [nwp_6p0]
+diode_nw2ps_06v0_terminal_p = pcomp.and(diode_mk).not(diode_nw2ps_06v0_exclude)
+diode_nw2ps_06v0_terminal_n = diode_mk.covering(nwell.covering(ncomp)).not(diode_nw2ps_06v0_exclude)
+
+#====================
+# --- DNWPW DIODE ---
+#====================
+
+diode_pw2dw_exclude = diode_nd2ps_pd2nw_exclude.join(nwell).join(nplus)
+
+# diode_pw2dw: Model for LVPWELL/DNWELL diode (applicable for both 1.8V/6V) [dnwpw]
+diode_pw2dw_terminal_p = lvpwell.interacting(pcomp).and(well_diode_mk).not(diode_pw2dw_exclude)
+
+#======================
+# --- DNWPWHV DIODE ---
+#======================
+
+diode_pw2dw_hv_exclude = diode_exclude.join(lvpwell).join(poly2)
+ .join(pplus).join(schottky_diode).join(zener)
+ .join(res_mk).join(hvnddd).join(hvpddd)
+ .join(nwell)
+
+# diode_pw2dw_hv: Model for NW/PWHV diode (10V diode) [dnwpwhv]
+dnwell_hv = dnwell.and(dualgate2_d)
+diode_pw2dw_hv_terminal_p = pwhv.and(well_diode_mk).and(ldmos_xtor).not(diode_pw2dw_hv_exclude)
+diode_pw2dw_hv_terminal_n = well_diode_mk.covering(dnwell_hv.covering(ncomp)).and(ldmos_xtor)
+ .interacting(mvsd).not(diode_pw2dw_hv_exclude)
+
+#=======================
+# --- DPWHVDNW DIODE ---
+#=======================
+
+diode_pw2dnw_hv_exclude = diode_exclude.join(lvpwell).join(poly2)
+ .join(nplus).join(schottky_diode).join(zener)
+ .join(res_mk).join(hvnddd).join(hvpddd)
+ .join(nwell)
+
+# diode_pw2dnw_hv: Model for PWHV/DNW diode [dpwhvdnw]
+diode_pw2dnw_hv_terminal_p = pwhv.and(well_diode_mk).and(ldmos_xtor).not(diode_pw2dnw_hv_exclude)
+diode_pw2dnw_hv_terminal_n = well_diode_mk.covering(dnwell_hv.covering(pcomp)).and(ldmos_xtor)
+ .interacting(mvsd).not(diode_pw2dnw_hv_exclude)
+
+#======================
+# --- NP 30P0 DIODE ---
+#======================
+
+diode_nd2ps_30v0_exclude = diode_exclude.join(dnwell).join(nwell)
+ .join(lvpwell).join(poly2)
+
+# diode_nd2ps_30v0: Model for HVNDDD/Psub diode [np_30p0]
+diode_nd2ps_30v0_terminal_n = dualgate2_d.covering(hvnddd.and(diode_mk)).not(diode_nd2ps_30v0_exclude)
+diode_nd2ps_30v0_terminal_p = pcomp.and(diode_mk).not(diode_nd2ps_30v0_exclude)
+
+#======================
+# --- PN 30P0 DIODE ---
+#======================
+
+diode_pd2nw_30v0_exclude = diode_exclude.join(nwell).join(lvpwell).join(poly2)
+
+# diode_pd2nw_30v0: Model for HVPDDD/DNWELL diode [np_30p0]
+diode_pd2nw_30v0_terminal_n = hvpddd.and(diode_mk).and(dualgate2_d).not(diode_pd2nw_30v0_exclude)
+
+#====================
+# --- DNWPS DIODE ---
+#====================
+
+# diode_dw2ps: Model for DNWELL/Psub diode(1.8V/6V) [dnwps]
+diode_dw2ps_exclude = diode_exclude.join(nwell).join(lvpwell)
+ .join(poly2).join(pwhv).join(schottky_diode)
+ .join(zener).join(mvsd).join(hvnddd)
+ .join(hvpddd).join(ldmos_xtor)
+
+diode_dw2ps_terminal_p = pcomp.and(dualgate2_d).and(dnwell).and(well_diode_mk)
+ .not(diode_dw2ps_exclude)
+
+#=================
+# --- SC DIODE ---
+#=================
+
+diode_sc_exclude = diode_exclude.join(lvpwell).join(poly2)
+ .join(pplus).join(zener).join(res_mk)
+ .join(hvnddd).join(hvpddd).join(ldmos_xtor)
+
+# diode_sc: Model for schottky diode [sc_diode]
+diode_sc_terminal_n = ncomp.and(dnwell).and(schottky_diode).not(diode_sc_exclude)
+diode_sc_terminal_p = metal1.and(dnwell).not_interacting(diode_sc_terminal_n).not(diode_sc_exclude)
+
+#====================
+# --- ZENER DIODE ---
+#====================
+
+diode_zener_exclude = diode_exclude.join(lvpwell).join(poly2)
+ .join(pplus).join(zener).join(res_mk)
+ .join(hvnddd).join(hvpddd).join(ldmos_xtor)
+
+# diode_zener: Model for zener diode outside DNWELL [zener_diode]
+zener_mv = zener.and(dualgate2_d)
+diode_zener_terminal_n = ncomp.and(zener_mv).not(dnwell).not(diode_zener_exclude)
+diode_zener_terminal_p = nwell.and(zener_mv).not(dnwell).covering(pcomp).and(diode_mk).not(diode_zener_exclude)
+
+# diode_zener_dn: Model for zener diode inside DNWELL [zener_diode_dw]
+diode_zener_dn_terminal_n = ncomp.and(zener_mv).and(dnwell).and(diode_mk).not(diode_zener_exclude)
+diode_zener_dn_terminal_p = nwell.and(zener_mv).and(dnwell).covering(pcomp).and(diode_mk).not(diode_zener_exclude)
+
+
+#===================
+# --- POLY DIODE ---
+#===================
+
+# diode_poly: Model for poly diode [poly_diode]
+diode_poly_exclude = comp.join(resistor).join(esd)
+ .join(pwhv).join(polyfuse).join(fusewindow_d)
+ .join(schottky_diode).join(piscap).join(zener)
+ .join(res_mk).join(v5_xtor).join(nat)
+ .join(fhres).join(mvsd).join(mvpsd)
+ .join(elmd_mk).join(elmd2_mk).join(lvs_rf)
+ .join(lvs_source).join(lvs_35v).join(mk_35v)
+ .join(well_diode_mk).join(esd_hbm_mk).join(mos_mk_type1)
+ .join(hvnddd).join(hvpddd).join(hvpolyrs)
+ .join(ldmos_xtor)
+
+diode_poly_terminal_p = poly2.and(sab).interacting(nplus).interacting(pplus)
+ .and(diode_mk).not(diode_poly_exclude)
+diode_poly_terminal_n = diode_mk.covering(diode_poly_terminal_p)
+
diff --git a/BCDLite/klayout/lvs/rule_decks/diode_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/diode_extraction.lvs
new file mode 100644
index 0000000..c598159
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/diode_extraction.lvs
@@ -0,0 +1,154 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ------ DIODE EXTRACTION -------
+#================================
+
+logger.info('Starting DIODE EXTRACTION')
+
+#=====================
+# --- NP 1P8 DIODE ---
+#=====================
+
+# diode_nd2ps_01v8: Model for 1.8V N+/Psub diode (outside DNWELL) [np_1p8]
+logger.info('Extracting diode_nd2ps_01v8')
+extract_devices(diode('diode_nd2ps_01v8'), { 'N' => diode_nd2ps_01v8_terminal_n, 'P' => lvpwell_con })
+
+# diode_nd2ps_01v8_dn: Model for 1.8V N+/Psub diode (inside DNWELL) [np_1p8_dw]
+logger.info('Extracting diode_nd2ps_01v8_dn')
+extract_devices(diode('diode_nd2ps_01v8_dn'), { 'N' => diode_nd2ps_01v8_dn_terminal_n, 'P' => lvpwell_con })
+
+#=====================
+# --- PN 1P8 DIODE ---
+#=====================
+
+# diode_pd2nw_01v8: Model for 1.8V P+/Nwell diode (outside DNWELL) [pn_1p8]
+logger.info('Extracting diode_pd2nw_01v8')
+extract_devices(diode('diode_pd2nw_01v8'), { 'N' => nwell_con, 'P' => diode_pd2nw_01v8_terminal_p })
+
+# diode_pd2nw_01v8_dn: Model for 1.8V P+/Nwell diode (inside DNWELL) [pn_1p8_dw]
+logger.info('Extracting diode_pd2nw_01v8_dn')
+extract_devices(diode('diode_pd2nw_01v8_dn'), { 'N' => nwell_con, 'P' => diode_pd2nw_01v8_dn_terminal_p })
+
+#=====================
+# --- NP 6P0 DIODE ---
+#=====================
+
+# diode_nd2ps_06v0: Model for 6V N+/Pwell diode (outside DNWELL) [np_6p0]
+logger.info('Extracting diode_nd2ps_06v0')
+extract_devices(diode('diode_nd2ps_06v0'), { 'N' => diode_nd2ps_06v0_terminal_n, 'P' => lvpwell_con })
+
+# diode_nd2ps_06v0_dn: Model for 6V N+/Psub diode (inside DNWELL) [np_6p0_dw]
+logger.info('Extracting diode_nd2ps_06v0_dn')
+extract_devices(diode('diode_nd2ps_06v0_dn'), { 'N' => diode_nd2ps_06v0_dn_terminal_n, 'P' => lvpwell_con })
+
+#=====================
+# --- PN 6P0 DIODE ---
+#=====================
+
+# diode_pd2nw_06v0: Model for 6V P+/Nwell diode (outside DNWELL) [pn_6p0]
+logger.info('Extracting diode_pd2nw_06v0')
+extract_devices(diode('diode_pd2nw_06v0'), { 'N' => nwell_con, 'P' => diode_pd2nw_06v0_terminal_p })
+
+# diode_pd2nw_06v0_dn: Model for 6V P+/Nwell diode (inside DNWELL) [pn_6p0_dw]
+logger.info('Extracting diode_pd2nw_06v0_dn')
+extract_devices(diode('diode_pd2nw_06v0_dn'), { 'N' => nwell_con, 'P' => diode_pd2nw_06v0_dn_terminal_p })
+
+#======================
+# --- NWP 6P0 DIODE ---
+#======================
+
+# diode_nw2ps_06v0: Model for Nwell/Psub diode (applicable for both 1.8V/6V) [nwp_6p0]
+logger.info('Extracting diode_nw2ps_06v0 diode')
+extract_devices(diode('diode_nw2ps_06v0'), { 'N' => diode_nw2ps_06v0_terminal_n, 'P' => diode_nw2ps_06v0_terminal_p })
+
+#====================
+# --- DNWPW DIODE ---
+#====================
+
+# diode_pw2dw: Model for LVPWELL/DNWELL diode (applicable for both 1.8V/6V) [dnwpw]
+logger.info('Extracting diode_pw2dw diode')
+extract_devices(diode('diode_pw2dw'), { 'N' => dnwell, 'P' => diode_pw2dw_terminal_p })
+
+#======================
+# --- DNWPWHV DIODE ---
+#======================
+
+# diode_pw2dw_hv: Model for NW/PWHV diode (10V diode) [dnwpwhv]
+logger.info('Extracting diode_pw2dw_hv diode')
+extract_devices(diode('diode_pw2dw_hv'), { 'N' => diode_pw2dw_hv_terminal_n, 'P' => diode_pw2dw_hv_terminal_p })
+
+#=======================
+# --- DPWHVDNW DIODE ---
+#=======================
+
+# diode_pw2dnw_hv: Model for PWHV/DNW diode [dpwhvdnw]
+logger.info('Extracting diode_pw2dnw_hv diode')
+extract_devices(diode('diode_pw2dnw_hv'), { 'N' => diode_pw2dnw_hv_terminal_n, 'P' => diode_pw2dnw_hv_terminal_p })
+
+#======================
+# --- NP 30P0 DIODE ---
+#======================
+
+# diode_nd2ps_30v0: Model for HVNDDD/Psub diode [np_30p0]
+logger.info('Extracting diode_nd2ps_30v0 diode')
+extract_devices(diode('diode_nd2ps_30v0'), { 'N' => diode_nd2ps_30v0_terminal_n, 'P' => diode_nd2ps_30v0_terminal_p })
+
+#======================
+# --- PN 30P0 DIODE ---
+#======================
+
+# diode_pd2nw_30v0: Model for HVPDDD/DNWELL diode [np_30p0]
+logger.info('Extracting diode_pd2nw_30v0 diode')
+extract_devices(diode('diode_pd2nw_30v0'), { 'N' => diode_pd2nw_30v0_terminal_n, 'P' => dnwell })
+
+#====================
+# --- DNWPS DIODE ---
+#====================
+
+# diode_dw2ps: Model for DNWELL/Psub diode(1.8V/6V) [dnwps]
+logger.info('Extracting diode_dw2ps diode')
+extract_devices(diode('diode_dw2ps'), { 'N' => dnwell, 'P' => diode_dw2ps_terminal_p })
+
+#=================
+# --- SC DIODE ---
+#=================
+
+# diode_sc: Model for schottky diode [sc_diode]
+logger.info('Extracting diode_sc diode')
+extract_devices(diode('diode_sc'), { 'N' => diode_sc_terminal_n, 'P' => schottky_diode })
+
+#====================
+# --- ZENER DIODE ---
+#====================
+
+# diode_zener: Model for zener diode outside DNWELL [zener_diode]
+logger.info('Extracting diode_zener diode')
+extract_devices(diode('diode_zener'), { 'N' => diode_zener_terminal_n, 'P' => zener })
+
+# diode_zener_dn: Model for zener diode inside DNWELL [zener_diode_dw]
+logger.info('Extracting diode_zener_dn diode')
+extract_devices(diode('diode_zener_dn'), { 'N' => diode_zener_dn_terminal_n, 'P' => zener })
+
+#===================
+# --- POLY DIODE ---
+#===================
+
+# diode_poly: Model for poly diode [poly_diode]
+logger.info('Extracting diode_poly diode')
+extract_devices(diode('diode_poly'), { 'N' => diode_poly_terminal_n, 'P' => diode_poly_terminal_p })
+
diff --git a/BCDLite/klayout/lvs/rule_decks/general_connections.lvs b/BCDLite/klayout/lvs/rule_decks/general_connections.lvs
new file mode 100644
index 0000000..ce0d606
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/general_connections.lvs
@@ -0,0 +1,88 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================================
+#------------ DEVICES CONNECTIVITY --------------
+#================================================
+
+logger.info('Starting GF180BCDLite LVS connectivity setup')
+
+#================================
+# ----- GENERAL CONNECTIONS -----
+#================================
+
+logger.info('Starting GF180BCDLite LVS connectivity setup (Inter-layer)')
+
+# Inter-layer
+connect(sub, ptap)
+connect(lvpwell_con, ptap)
+connect(lvpwell_con, ptap_dw)
+connect(dnwell, ntap_dw)
+connect(nwell_con, ntap)
+connect(ptap, contact)
+connect(ptap_dw, contact)
+connect(ntap, contact)
+connect(ntap_dw, contact)
+connect(psd, contact)
+connect(psd_dw, contact)
+connect(nsd, contact)
+connect(poly2_con, contact)
+connect(contact, metal1_con)
+connect(metal1_con, via1)
+connect(via1, metal2_con)
+
+case METAL_LEVEL
+when '3LM', '4LM', '5LM', '6LM'
+ connect(metal2_con, via2_n_cap)
+ connect(via2_n_cap, metal3_con)
+ connect(metal3_con, metal3_label)
+end
+case METAL_LEVEL
+when '4LM', '5LM', '6LM'
+ connect(metal3_con, via3_n_cap)
+ connect(via3_n_cap, metal4_con)
+ connect(metal4_con, metal4_label)
+end
+case METAL_LEVEL
+when '5LM', '6LM'
+ connect(metal4_con, via4_n_cap)
+ connect(via4_n_cap, metal5_con)
+ connect(metal5_con, metal5_label)
+end
+case METAL_LEVEL
+when '6LM'
+ connect(metal5_con, via5_n_cap)
+ connect(via5_n_cap, metaltop_con)
+ connect(metaltop_con, metaltop_label)
+end
+connect(top_via, top_metal_con)
+connect(top_metal, top_metal_label)
+
+# Attaching labels
+connect(comp, comp_label)
+connect(poly2_con, poly2_label)
+connect(metal1_con, metal1_label)
+connect(metal2_ncap, metal2_label)
+
+logger.info('Starting GF180BCDLite LVS connectivity setup (Global)')
+
+# Global
+connect_global(sub, substrate_name)
+
+logger.info('Starting GF180BCDLite LVS connectivity setup (Multifinger Devices)')
+
+# Multifinger Devices
+connect_implicit('*')
diff --git a/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs
index f3c0ba3..bea0ccd 100644
--- a/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs
@@ -1,7 +1,5 @@
-# frozen_string_literal: true
-
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -52,36 +50,56 @@
lvpwell_con = lvpwell.not(res_mk)
poly2_con = poly2.not(res_mk).not(plfuse)
-metal1_con = metal1.not(metal1_res)
-metal2_con = metal2.not(metal2_res)
+metal1_con = metal1.not(mom_mk).not(mom_m1_mk)
+metal2_con = metal2.not(mom_mk).not(mom_m2_mk)
-metal3_con = metal3.not(metal3_res) if METAL_LEVEL != '2LM'
+case METAL_LEVEL
+when '3LM', '4LM', '5LM', '6LM'
+ metal3_con = metal3.not(mom_mk).not(mom_m3_mk)
+ via2_n_cap = via2.not(fusetop)
+ via2_cap = via2.and(fusetop)
+end
+case METAL_LEVEL
+when '4LM', '5LM', '6LM'
+ metal4_con = metal4.not(mom_mk).not(mom_m4_mk)
+ via3_n_cap = via3.not(fusetop)
+ via3_cap = via3.and(fusetop)
+end
+case METAL_LEVEL
+when '5LM', '6LM'
+ metal5_con = metal5.not(mom_mk).not(mom_m5_mk)
+ via4_n_cap = via4.not(fusetop)
+ via4_cap = via4.and(fusetop)
+end
+case METAL_LEVEL
+when '6LM'
+ metaltop_con = metaltop.not(mom_mk)
+ via5_n_cap = via5.not(fusetop)
+ via5_cap = via5.and(fusetop)
+end
-metaltop_con = metaltop.not(metal6_res) if METAL_LEVEL == '6LM'
-
-#=====================================================
-#------------- BASE LAYERS DERIVATIONS ---------------
-#=====================================================
-
-dnwell_n = dnwell.not(lvpwell)
-dnwell_p = dnwell.and(lvpwell)
-
-all_nwell = dnwell_n.join(nwell)
-ntap = ncomp.and(all_nwell).not(res_mk)
-ptap = pcomp.not(all_nwell).not(res_mk)
-
-## DV2_D (Medium Voltage Gate Oxide)
-nom_gate = tgate.not(dualgate2_d)
-thick_gate = tgate.and(dualgate2_d)
-
-ngate_56v = ngate.and(dualgate2_d)
-pgate_56v = pgate.and(dualgate2_d)
-
-ngate_5v = ngate_56v.and(v5_xtor)
-pgate_5v = pgate_56v.and(v5_xtor)
-
-ngate_6v = ngate_56v.not(v5_xtor)
-pgate_6v = pgate_56v.not(v5_xtor)
-
-lvpwell_dn = lvpwell.interacting(dnwell)
-lvpwell_out = lvpwell.not_interacting(dnwell)
+case METAL_LEVEL
+when '2LM'
+ top_metal_con = metal2_con
+ top_via_n_cap = via1.not(fusetop)
+ top_via_cap = via1.and(fusetop)
+when '3LM'
+ top_metal_con = metal3_con
+ top_via_n_cap = via2.not(fusetop)
+ top_via_cap = via2.and(fusetop)
+when '4LM'
+ top_metal_con = metal4.not(mom_mk).not(mom_m4_mk)
+ top_via_n_cap = via3.not(fusetop)
+ top_via_cap = via3.and(fusetop)
+when '5LM'
+ top_metal_con = metal5.not(mom_mk).not(mom_m5_mk)
+ top_via_n_cap = via4.not(fusetop)
+ top_via_cap = via4.and(fusetop)
+when '6LM'
+ top_metal_con = metaltop.not(mom_mk)
+ top_via_n_cap = via5.not(fusetop)
+ top_via_cap = via5.and(fusetop)
+else
+ logger.error("Unknown metal stack #{METAL_LEVEL}")
+ raise
+end
diff --git a/BCDLite/klayout/lvs/rule_decks/layers_definition.lvs b/BCDLite/klayout/lvs/rule_decks/layers_definition.lvs
index 237686a..0bf1d1b 100644
--- a/BCDLite/klayout/lvs/rule_decks/layers_definition.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/layers_definition.lvs
@@ -1,7 +1,5 @@
-# frozen_string_literal: true
-
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -24,7 +22,7 @@
logger.info('Read in polygons from layers.')
def get_polygons(layer, data_type)
- ps = get_polygons(layer, data_type)
+ ps = polygons(layer, data_type)
$run_mode == 'deep' ? ps : ps.merged
end
@@ -320,7 +318,7 @@
metal1 = metal1_drawn + metal1_dummy
-metal1_label = get_polygons(34, 10)
+metal1_label = labels(34, 10)
count = metal1_label.count
logger.info("metal1_label has #{count} polygons")
polygons_count += count
@@ -352,7 +350,7 @@
metal2 = metal2_drawn + metal2_dummy
-metal2_label = get_polygons(36, 10)
+metal2_label = labels(36, 10)
count = metal2_label.count
logger.info("metal2_label has #{count} polygons")
polygons_count += count
@@ -367,17 +365,8 @@
logger.info("metal2_blk has #{count} polygons")
polygons_count += count
-if METAL_LEVEL == '2LM'
-
- top_via = via1
- topmin1_via = contact
- top_metal = metal2
- topmin1_metal = metal1
- top_metal_slot = metal2_slot
- topmin1_metal_slot = metal1_slot
-
-else
-
+case METAL_LEVEL
+when '3LM', '4LM', '5LM', '6LM'
via2 = get_polygons(38, 0)
count = via2.count
logger.info("via2 has #{count} polygons")
@@ -395,7 +384,7 @@
metal3 = metal3_drawn + metal3_dummy
- metal3_label = get_polygons(42, 10)
+ metal3_label = labels(42, 10)
count = metal3_label.count
logger.info("metal3_label has #{count} polygons")
polygons_count += count
@@ -409,171 +398,147 @@
count = metal3_blk.count
logger.info("metal3_blk has #{count} polygons")
polygons_count += count
+end
- if METAL_LEVEL == '3LM'
+case METAL_LEVEL
+when '4LM', '5LM', '6LM'
+ via3 = get_polygons(40, 0)
+ count = via3.count
+ logger.info("via3 has #{count} polygons")
+ polygons_count += count
- top_via = via2
- topmin1_via = via1
- top_metal = metal3
- topmin1_metal = metal2
- top_metal_slot = metal3_slot
- topmin1_metal_slot = metal2_slot
- else
+ metal4_drawn = get_polygons(46, 0)
+ count = metal4_drawn.count
+ logger.info("metal4_drawn has #{count} polygons")
+ polygons_count += count
- via3 = get_polygons(40, 0)
- count = via3.count
- logger.info("via3 has #{count} polygons")
- polygons_count += count
+ metal4_dummy = get_polygons(46, 4)
+ count = metal4_dummy.count
+ logger.info("metal4_dummy has #{count} polygons")
+ polygons_count += count
- metal4_drawn = get_polygons(46, 0)
- count = metal4_drawn.count
- logger.info("metal4_drawn has #{count} polygons")
- polygons_count += count
+ metal4 = metal4_drawn + metal4_dummy
- metal4_dummy = get_polygons(46, 4)
- count = metal4_dummy.count
- logger.info("metal4_dummy has #{count} polygons")
- polygons_count += count
+ metal4_label = labels(46, 10)
+ count = metal4_label.count
+ logger.info("metal4_label has #{count} polygons")
+ polygons_count += count
- metal4 = metal4_drawn + metal4_dummy
+ metal4_slot = get_polygons(46, 3)
+ count = metal4_slot.count
+ logger.info("metal4_slot has #{count} polygons")
+ polygons_count += count
- metal4_label = get_polygons(46, 10)
- count = metal4_label.count
- logger.info("metal4_label has #{count} polygons")
- polygons_count += count
+ metal4_blk = get_polygons(46, 5)
+ count = metal4_blk.count
+ logger.info("metal4_blk has #{count} polygons")
+ polygons_count += count
+end
- metal4_slot = get_polygons(46, 3)
- count = metal4_slot.count
- logger.info("metal4_slot has #{count} polygons")
- polygons_count += count
+case METAL_LEVEL
+when '5LM', '6LM'
+ via4 = get_polygons(41, 0)
+ count = via4.count
+ logger.info("via4 has #{count} polygons")
+ polygons_count += count
- metal4_blk = get_polygons(46, 5)
- count = metal4_blk.count
- logger.info("metal4_blk has #{count} polygons")
- polygons_count += count
+ metal5_drawn = get_polygons(81, 0)
+ count = metal5_drawn.count
+ logger.info("metal5_drawn has #{count} polygons")
+ polygons_count += count
- if METAL_LEVEL == '4LM'
+ metal5_dummy = get_polygons(81, 4)
+ count = metal5_dummy.count
+ logger.info("metal5_dummy has #{count} polygons")
+ polygons_count += count
- top_via = via3
- topmin1_via = via2
- top_metal = metal4
- topmin1_metal = metal3
- top_metal_slot = metal4_slot
- topmin1_metal_slot = metal3_slot
- else
+ metal5 = metal5_drawn + metal5_dummy
- via4 = get_polygons(41, 0)
- count = via4.count
- logger.info("via4 has #{count} polygons")
- polygons_count += count
+ metal5_label = labels(81, 10)
+ count = metal5_label.count
+ logger.info("metal5_label has #{count} polygons")
+ polygons_count += count
- case METAL_LEVEL
- when '5LM'
- metal5_drawn = get_polygons(81, 0)
- count = metal5_drawn.count
- logger.info("metal5_drawn has #{count} polygons")
- polygons_count += count
+ metal5_slot = get_polygons(81, 3)
+ count = metal5_slot.count
+ logger.info("metal5_slot has #{count} polygons")
+ polygons_count += count
- metal5_dummy = get_polygons(81, 4)
- count = metal5_dummy.count
- logger.info("metal5_dummy has #{count} polygons")
- polygons_count += count
+ metal5_blk = get_polygons(81, 5)
+ count = metal5_blk.count
+ logger.info("metal5_blk has #{count} polygons")
+ polygons_count += count
+end
- metal5 = metal5_drawn + metal5_dummy
+case METAL_LEVEL
+when '6LM'
+ via5 = get_polygons(82, 0)
+ count = via5.count
+ logger.info("via5 has #{count} polygons")
+ polygons_count += count
- metal5_label = get_polygons(81, 10)
- count = metal5_label.count
- logger.info("metal5_label has #{count} polygons")
- polygons_count += count
+ metaltop_drawn = get_polygons(53, 0)
+ count = metaltop_drawn.count
+ logger.info("metaltop_drawn has #{count} polygons")
+ polygons_count += count
- metal5_slot = get_polygons(81, 3)
- count = metal5_slot.count
- logger.info("metal5_slot has #{count} polygons")
- polygons_count += count
+ metaltop_dummy = get_polygons(53, 4)
+ count = metaltop_dummy.count
+ logger.info("metaltop_dummy has #{count} polygons")
+ polygons_count += count
- metal5_blk = get_polygons(81, 5)
- count = metal5_blk.count
- logger.info("metal5_blk has #{count} polygons")
- polygons_count += count
+ metaltop = metaltop_drawn + metaltop_dummy
- top_via = via4
- topmin1_via = via3
- top_metal = metal5
- topmin1_metal = metal4
- top_metal_slot = metal5_slot
- topmin1_metal_slot = metal4_slot
- when '6LM'
- metal5_drawn = get_polygons(81, 0)
- count = metal5_drawn.count
- logger.info("metal5_drawn has #{count} polygons")
- polygons_count += count
+ metaltop_label = labels(53, 10)
+ count = metaltop_label.count
+ logger.info("metaltop_label has #{count} polygons")
+ polygons_count += count
- metal5_dummy = get_polygons(81, 4)
- count = metal5_dummy.count
- logger.info("metal5_dummy has #{count} polygons")
- polygons_count += count
+ metaltop_slot = get_polygons(53, 3)
+ count = metaltop_slot.count
+ logger.info("metaltop_slot has #{count} polygons")
+ polygons_count += count
- metal5 = metal5_drawn + metal5_dummy
+ metaltop_blk = get_polygons(53, 5)
+ count = metaltop_blk.count
+ logger.info("metaltop_blk has #{count} polygons")
+ polygons_count += count
+end
- metal5_label = get_polygons(81, 10)
- count = metal5_label.count
- logger.info("metal5_label has #{count} polygons")
- polygons_count += count
-
- metal5_slot = get_polygons(81, 3)
- count = metal5_slot.count
- logger.info("metal5_slot has #{count} polygons")
- polygons_count += count
-
- metal5_blk = get_polygons(81, 5)
- count = metal5_blk.count
- logger.info("metal5_blk has #{count} polygons")
- polygons_count += count
-
- via5 = get_polygons(82, 0)
- count = via5.count
- logger.info("via5 has #{count} polygons")
- polygons_count += count
-
- metaltop_drawn = get_polygons(53, 0)
- count = metaltop_drawn.count
- logger.info("metaltop_drawn has #{count} polygons")
- polygons_count += count
-
- metaltop_dummy = get_polygons(53, 4)
- count = metaltop_dummy.count
- logger.info("metaltop_dummy has #{count} polygons")
- polygons_count += count
-
- metaltop = metaltop_drawn + metaltop_dummy
-
- metaltop_label = get_polygons(53, 10)
- count = metaltop_label.count
- logger.info("metaltop_label has #{count} polygons")
- polygons_count += count
-
- metaltop_slot = get_polygons(53, 3)
- count = metaltop_slot.count
- logger.info("metaltop_slot has #{count} polygons")
- polygons_count += count
-
- metaltop_blk = get_polygons(53, 5)
- count = metaltop_blk.count
- logger.info("metaltop_blk has #{count} polygons")
- polygons_count += count
-
- top_via = via5
- topmin1_via = via4
- top_metal = metaltop
- topmin1_metal = metal5
- top_metal_slot = metaltop_slot
- topmin1_metal_slot = metal5_slot
- else
- logger.error("Unknown metal stack #{METAL_LEVEL}")
- raise
- end
- end
- end
+case METAL_LEVEL
+when '2LM'
+ top_via = via1
+ topmin1_via = contact
+ top_metal = metal2
+ topmin1_metal = metal1
+ top_metal_label = metal2_label
+when '3LM'
+ top_via = via2
+ topmin1_via = via1
+ top_metal = metal3
+ topmin1_metal = metal2
+ top_metal_label = metal3_label
+when '4LM'
+ top_via = via3
+ topmin1_via = via2
+ top_metal = metal4
+ topmin1_metal = metal3
+ top_metal_label = metal4_label
+when '5LM'
+ top_via = via4
+ topmin1_via = via3
+ top_metal = metal5
+ topmin1_metal = metal4
+ top_metal_label = metal5_label
+when '6LM'
+ top_via = via5
+ topmin1_via = via4
+ top_metal = metaltop
+ topmin1_metal = metal5
+ top_metal_label = metaltop_label
+else
+ logger.error("Unknown metal stack #{METAL_LEVEL}")
+ raise
end
piscap = get_polygons(120, 0)
@@ -851,3 +816,7 @@
polygons_count += count
logger.info("Total no. of polygons in the design is #{polygons_count}")
+
+
+#=== BULK LAYER ===
+sub = polygon_layer
\ No newline at end of file
diff --git a/BCDLite/klayout/lvs/rule_decks/mimcap_connections.lvs b/BCDLite/klayout/lvs/rule_decks/mimcap_connections.lvs
new file mode 100644
index 0000000..ae533fa
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/mimcap_connections.lvs
@@ -0,0 +1,38 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MIMCAP CONNECTIONS -------
+#==================================
+
+logger.info('Starting LVS MIMCAP CONNECTIONS')
+
+case MIM_OPTION
+
+#==================
+# --- MIM-A CAP ---
+#==================
+when 'A'
+ connect(metal2, mim_virtual)
+ connect(fuse_cap, via2_cap)
+
+#==================
+# --- MIM-B CAP ---
+#==================
+when 'B'
+ connect(topmin1_metal, mimtm_virtual)
+ connect(fuse_cap, top_via_cap)
+end
diff --git a/BCDLite/klayout/lvs/rule_decks/mimcap_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/mimcap_derivations.lvs
new file mode 100644
index 0000000..3da4c70
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/mimcap_derivations.lvs
@@ -0,0 +1,41 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MIMCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting MIMCAP DERIVATIONS')
+
+#==================
+# --- MIM-A CAP ---
+#==================
+
+mim_a_exclude = tanres.join(tanres_mk).join(tanres_l_mk)
+ .join(drc_bjt).join(lvs_rf).join(esd_hbm_mk)
+ .join(mom_mk).join(mom_m1_mk).join(mom_m2_mk)
+ .join(mom_m3_mk).join(mom_m4_mk).join(mom_m5_mk)
+
+mim_virtual = fusetop.sized(1.06.um).and(metal2.interacting(fusetop)).not(mim_a_exclude)
+metal2_ncap = metal2_con.not(mim_virtual)
+fuse_cap = fusetop.interacting(cap_mk).interacting(mim_l_mk).not(mim_a_exclude)
+
+#==================
+# --- MIM-B CAP ---
+#==================
+
+mim_b_exclude = mim_a_exclude.join(fusewindow_d).join(polyfuse)
+mimtm_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop)).not(mim_b_exclude)
diff --git a/BCDLite/klayout/lvs/rule_decks/mimcap_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/mimcap_extraction.lvs
new file mode 100644
index 0000000..ca5a1f6
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/mimcap_extraction.lvs
@@ -0,0 +1,131 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- MIMCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting MIMCAP EXTRACTION')
+
+case MIM_OPTION
+
+#==================
+# --- MIM-A CAP ---
+#==================
+when 'A'
+
+ case MIM_CAP
+ when '0.85'
+ # cap_mim_0f85 capacitor: 0.85fF/um2 MIM capacitor (usable for Volts <= 32V across capacitor) [mim_0p85fF]
+ logger.info('Extracting cap_mim_0f85 capacitor')
+ extract_devices(capacitor('cap_mim_0f85_m2m3_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_0f85_m2m3_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # cap_mim_1f0 capacitor: 1fF/um2 MIM capacitor (usable for Volts <= 20V across capacitor) [mim_1p0fF]
+ logger.info('Extracting cap_mim_1f0 capacitor')
+ extract_devices(capacitor('cap_mim_1f0_m2m3_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m2m3_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # cap_mim_1f5 capacitor: 1.5fF/um2 MIM capacitor (usable for Volts <= 6V across capacitor) [mim_1p5fF]
+ logger.info('Extracting cap_mim_1f5 capacitor')
+ extract_devices(capacitor('cap_mim_1f5_m2m3_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m2m3_noshield', 'C', relative: 0.25)
+ end
+
+#==================
+# --- MIM-B CAP ---
+#==================
+when 'B'
+ case METAL_LEVEL
+ when '6LM'
+
+ case MIM_CAP
+ when '0.85'
+ # cap_mim_0f85_tm capacitor: 0.85fF/um2 MIM capacitor (usable for Volts <= 32V across capacitor) (For MIM option-B case) [mim_0p85fF_tm]
+ logger.info('Extracting cap_mim_0f85 capacitor')
+ extract_devices(capacitor('cap_mim_0f85_m5m6_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_0f85_m5m6_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # cap_mim_1f0 capacitor: 1fF/um2 MIM capacitor (usable for Volts <= 20V across capacitor) (For MIM option-B case) [mim_1p0fF_tm]
+ logger.info('Extracting cap_mim_1f0 capacitor')
+ extract_devices(capacitor('cap_mim_1f0_m5m6_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m5m6_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # cap_mim_1f5 capacitor: 1.5fF/um2 MIM capacitor (usable for Volts <= 6V across capacitor) (For MIM option-B case) [mim_1p5fF_tm]
+ logger.info('Extracting cap_mim_1f5 capacitor')
+ extract_devices(capacitor('cap_mim_1f5_m5m6_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m5m6_noshield', 'C', relative: 0.25)
+ end
+
+ when '5LM'
+ case MIM_CAP
+ when '0.85'
+ # cap_mim_0f85 capacitor: 0.85fF/um2 MIM capacitor (usable for Volts <= 32V across capacitor) (For MIM option-B case) [mim_0p85fF_tm]
+ logger.info('Extracting cap_mim_0f85 capacitor')
+ extract_devices(capacitor('cap_mim_0f85_m4m5_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_0f85_m4m5_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # cap_mim_1f0 capacitor: 1fF/um2 MIM capacitor (usable for Volts <= 20V across capacitor) (For MIM option-B case) [mim_1p0fF_tm]
+ logger.info('Extracting cap_mim_1f0 capacitor')
+ extract_devices(capacitor('cap_mim_1f0_m4m5_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m4m5_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # cap_mim_1f5 capacitor: 1.5fF/um2 MIM capacitor (usable for Volts <= 6V across capacitor) (For MIM option-B case) [mim_1p5fF_tm]
+ logger.info('Extracting cap_mim_1f5 capacitor')
+ extract_devices(capacitor('cap_mim_1f5_m4m5_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m4m5_noshield', 'C', relative: 0.25)
+ end
+
+ when '4LM'
+ case MIM_CAP
+ when '0.85'
+ # cap_mim_0f85 capacitor: 0.85fF/um2 MIM capacitor (usable for Volts <= 32V across capacitor) (For MIM option-B case) [mim_0p85fF_tm]
+ logger.info('Extracting cap_mim_0f85 capacitor')
+ extract_devices(capacitor('cap_mim_0f85_m3m4_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_0f85_m3m4_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # cap_mim_1f0 capacitor: 1fF/um2 MIM capacitor (usable for Volts <= 20V across capacitor) (For MIM option-B case) [mim_1p0fF_tm]
+ logger.info('Extracting cap_mim_1f0 capacitor')
+ extract_devices(capacitor('cap_mim_1f0_m3m4_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m3m4_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # cap_mim_1f5 capacitor: 1.5fF/um2 MIM capacitor (usable for Volts <= 6V across capacitor) (For MIM option-B case) [mim_1p5fF_tm]
+ logger.info('Extracting cap_mim_1f5 capacitor')
+ extract_devices(capacitor('cap_mim_1f5_m3m4_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m3m4_noshield', 'C', relative: 0.25)
+ end
+ end
+end
diff --git a/BCDLite/klayout/lvs/rule_decks/mos_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/mos_derivations.lvs
new file mode 100644
index 0000000..4ce6104
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/mos_derivations.lvs
@@ -0,0 +1,174 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MOSFET DERIVATIONS -------
+#==================================
+
+logger.info('Starting MOSFET DERIVATIONS')
+
+# general derivations used in MOS devices
+nsd_sab = nsd.and(sab)
+mos_exclude_layers = resistor.or(esd).or(pwhv).or(fusewindow_d).or(polyfuse)
+ .or(schottky_diode).or(zener).or(piscap).or(res_mk)
+ .or(fhres).or(mos_cap_mk).or(mvsd).or(mvpsd)
+ .or(lvs_rf).or(lvs_source).or(mk_35v)
+ .or(lvs_35v).or(esd_hbm_mk).or(hvpolyrs)
+ .or(swfet_mk).or(hvnddd).or(hvpddd)
+
+# =======================
+# ---- LV MOS Devices ----
+# =======================
+logger.info('Starting LV MOS layers DERIVATIONS')
+
+# LV NMOS transistor outside DNWELL
+nmos_1p8_g = ngate.not(dnwell).not(v5_xtor).not(dualgate2_d).not(ldmos_xtor).not(mos_mk_type1)
+ .not(mos_exclude_layers).not(sab).not(nwell).not(nat).not_interacting(dni)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk)
+
+# LV NMOS transistor inside DNWELL
+nmos_1p8_dw_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).not(dualgate2_d).not(ldmos_xtor)
+ .not(mos_exclude_layers).not(sab).not(nwell).not(nat).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# LV NAT NMOS transistor outside DNWELL
+nmos_1p8_nat_g = ngate.not(dnwell).and(nat).not(v5_xtor).not(dualgate2_d).not(ldmos_xtor)
+ .not(mos_exclude_layers).not(sab).not(nwell).not(lvpwell).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# LV NMOS with drain sab outside DNWELL
+nmos_1p8_sab_g = ngate.not(dnwell).interacting(elmd2_mk).interacting(sab).not(dualgate2_d)
+ .not(mos_exclude_layers).not(nwell).not(nat).not(v5_xtor).not(mos_mk_type1)
+ .not_interacting(elmd_mk).not(ldmos_xtor).not_interacting(dni)
+
+# LV NMOS with drain sab inside DNWELL
+nmos_1p8_dw_sab_g = ngate.and(dnwell).interacting(elmd2_mk).interacting(sab).and(lvpwell)
+ .not(mos_exclude_layers).not(nwell).not(nat).not(v5_xtor).not(dualgate2_d)
+ .not_interacting(elmd_mk).not(mos_mk_type1).not(ldmos_xtor).not_interacting(dni)
+
+# LV PMOS transistor outside DNWELL
+pmos_1p8_g = pgate.not(dnwell).and(nwell).not(v5_xtor).not(dualgate2_d).not(ldmos_xtor)
+ .not(mos_exclude_layers).not(sab).not(nat).not(lvpwell).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# LV PMOS transistor inside DNWELL
+pmos_1p8_dw_g = pgate.and(dnwell).not(v5_xtor).not(dualgate2_d).not(ldmos_xtor).not(lvpwell)
+ .not(mos_exclude_layers).not(sab).not(nat).not(mos_mk_type1).not_interacting(dni)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk)
+
+
+# ========================
+# ---- MV MOS Devices ----
+# ========================
+logger.info('Starting MV MOS layers DERIVATIONS')
+
+# 5V NMOS transistor outside DNWELL
+nmos_5p0_g = ngate.not(dnwell).and(v5_xtor).and(dualgate2_d).not(ldmos_xtor).not(mos_mk_type1)
+ .not(mos_exclude_layers).not(sab).not(nwell).not(nat).not_interacting(dni)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk)
+
+# 5V NMOS transistor inside DNWELL
+nmos_5p0_dw_g = ngate.and(dnwell).and(lvpwell).and(v5_xtor).and(dualgate2_d).not(ldmos_xtor)
+ .not(mos_exclude_layers).not(sab).not(nwell).not(nat).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# 5V PMOS transistor outside DNWELL
+pmos_5p0_g = pgate.not(dnwell).and(nwell).and(v5_xtor).and(dualgate2_d).not(ldmos_xtor)
+ .not(mos_exclude_layers).not(sab).not(nat).not(lvpwell).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# 5V PMOS transistor inside DNWELL
+pmos_5p0_dw_g = pgate.and(dnwell).and(v5_xtor).and(dualgate2_d).not(ldmos_xtor).not(lvpwell)
+ .not(mos_exclude_layers).not(sab).not(nat).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# 6V NMOS transistor outside DNWELL
+nmos_6p0_g = ngate.not(dnwell).not(v5_xtor).and(dualgate2_d).not(ldmos_xtor).not(mos_mk_type1)
+ .not(mos_exclude_layers).not(sab).not(nwell).not(nat)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# 6V NMOS transistor inside DNWELL
+nmos_6p0_dw_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).not(ldmos_xtor)
+ .not(mos_exclude_layers).not(sab).not(nwell).not(nat).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# 6V PMOS transistor outside DNWELL
+pmos_6p0_g = pgate.not(dnwell).and(nwell).not(v5_xtor).and(dualgate2_d).not(ldmos_xtor)
+ .not(mos_exclude_layers).not(sab).not(nat).not(lvpwell).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# 6V PMOS transistor inside DNWELL
+pmos_6p0_dw_g = pgate.and(dnwell).not(v5_xtor).and(dualgate2_d).not(ldmos_xtor).not(lvpwell)
+ .not(mos_exclude_layers).not(sab).not(nat).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# 6V NAT NMOS transistor outside DNWELL
+nmos_6p0_nat_g = ngate.not(dnwell).and(nat).not(v5_xtor).and(dualgate2_d).not(ldmos_xtor)
+ .not(mos_exclude_layers).not(sab).not(nwell).not(lvpwell).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# 6V NAT PMOS transistor inside DNWELL
+pmos_6p0_nat_dw_g = pgate.and(dnwell).not(v5_xtor).and(dualgate2_d).and(nat).not(ldmos_xtor)
+ .not(mos_exclude_layers).not(sab).not(lvpwell).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not_interacting(dni)
+
+# 6V Extended LDD NMOS
+nmos_eldd_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).interacting(elmd_mk)
+ .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not(ldmos_xtor).not_interacting(dni)
+
+# 6V DDD MV NMOS
+nmos_ddd_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).interacting(dni)
+ .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not_interacting(elmd_mk).not(ldmos_xtor)
+
+# 6V NMOS with drain sab outside DNWELL
+nmos_6p0_sab_g = ngate.not(dnwell).not(nwell).not(v5_xtor).and(dualgate2_d).not_interacting(elmd_mk)
+ .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not(ldmos_xtor).not_interacting(dni)
+
+# 6V NMOS with drain sab inside DNWELL
+nmos_6p0_dw_sab_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).not_interacting(elmd_mk)
+ .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not(ldmos_xtor).not_interacting(dni)
+
+# 5V NMOS with drain sab outside DNWELL
+nmos_5p0_sab_g = ngate.not(dnwell).not(nwell).and(v5_xtor).and(dualgate2_d).not_interacting(elmd_mk)
+ .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not(ldmos_xtor).not_interacting(dni)
+
+# 5V NMOS with drain sab inside DNWELL
+nmos_5p0_dw_sab_g = ngate.and(dnwell).and(lvpwell).and(v5_xtor).and(dualgate2_d).not_interacting(elmd_mk)
+ .not(mos_exclude_layers).interacting(sab).not(nwell).not(nat).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not(ldmos_xtor).not_interacting(dni)
+
+# 4.2V Hybrid NMOS inside DNWELL
+nmos_4p2_dw_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).interacting(mos_mk_type4)
+ .interacting(mos_source_type1).not_interacting(dni).not_interacting(elmd_mk)
+ .not(mos_exclude_layers).not_interacting(sab).not(nwell).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not(ldmos_xtor).not(nat)
+
+# 4.2V Hybrid PMOS inside DNWELL
+pmos_4p2_dw_g = pgate.and(dnwell).not(v5_xtor).and(dualgate2_d).interacting(mos_mk_type4)
+ .interacting(mos_source_type1).not_interacting(dni).not_interacting(elmd_mk)
+ .not(mos_exclude_layers).not_interacting(sab).not(nwell).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not(ldmos_xtor).not(nat)
+
+# 4.2V Hybrid SAB NMOS inside DNWELL
+nmos_4p2_dw_sab_g = ngate.and(dnwell).and(lvpwell).not(v5_xtor).and(dualgate2_d).interacting(mos_mk_type4)
+ .interacting(mos_source_type1).not_interacting(dni).not_interacting(elmd_mk)
+ .not(mos_exclude_layers).interacting(sab).not(nwell).not(mos_mk_type1)
+ .not_interacting(elmd2_mk).not(ldmos_xtor).not(nat)
\ No newline at end of file
diff --git a/BCDLite/klayout/lvs/rule_decks/mos_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/mos_extraction.lvs
new file mode 100644
index 0000000..c0afada
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/mos_extraction.lvs
@@ -0,0 +1,172 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- MOSFET EXTRACTION -------
+#================================
+
+logger.info('Starting MOSFET EXTRACTION')
+
+# =======================
+# ---- LV MOS Devices ----
+# =======================
+logger.info('Starting LV MOS EXTRACTION')
+
+# LV NMOS transistor outside DNWELL
+logger.info('Extracting LV NMOS transistor outside DNWELL')
+extract_devices(mos4('nmos_1p8'),
+ { 'SD' => nsd, 'G' => nmos_1p8_g, 'tS' => nsd, 'tD' => nsd,
+ 'tG' => poly2_con, 'W' => sub })
+
+# LV NMOS transistor inside DNWELL
+logger.info('Extracting LV NMOS transistor inside DNWELL')
+extract_devices(mos4('nmos_1p8_dw'),
+ { 'SD' => nsd, 'G' => nmos_1p8_dw_g, 'tS' => nsd, 'tD' => nsd,
+ 'tG' => poly2_con, 'W' => lvpwell_con })
+
+# LV NAT NMOS transistor outside DNWELL
+logger.info('Extracting LV NAT NMOS transistor outside DNWELL')
+extract_devices(mos4('nmos_1p8_nat'),
+ { 'SD' => nsd, 'G' => nmos_1p8_nat_g, 'tS' => nsd, 'tD' => nsd,
+ 'tG' => poly2_con, 'W' => sub })
+
+# LV NMOS with drain sab outside DNWELL
+logger.info('Extracting LV NMOS with drain sab outside DNWELL')
+extract_devices(mos4('nmos_1p8_sab'),
+ { 'S' => nsd, 'D' => nsd_sab, 'G' => nmos_1p8_sab_g, 'tS' => nsd,
+ 'tD' => nsd_sab, 'tG' => poly2_con, 'W' => sub })
+
+# LV NMOS with drain sab inside DNWELL
+logger.info('Extracting LV NMOS with drain sab inside DNWELL')
+extract_devices(mos4('nmos_1p8_dw_sab'),
+ { 'S' => nsd, 'D' => nsd_sab, 'G' => nmos_1p8_dw_sab_g, 'tS' => nsd,
+ 'tD' => nsd_sab, 'tG' => poly2_con, 'W' => lvpwell_con })
+
+# LV PMOS transistor outside DNWELL
+logger.info('Extracting LV PMOS transistor outside DNWELL')
+extract_devices(mos4('pmos_1p8'),
+ { 'SD' => psd, 'G' => pmos_1p8_g, 'tS' => psd, 'tD' => psd,
+ 'tG' => poly2_con, 'W' => nwell_con })
+
+# LV PMOS transistor inside DNWELL
+logger.info('Extracting LV PMOS transistor inside DNWELL')
+extract_devices(mos4('pmos_1p8_dw'),
+ { 'SD' => psd_dw, 'G' => pmos_1p8_dw_g, 'tS' => psd_dw, 'tD' => psd_dw,
+ 'tG' => poly2_con, 'W' => dnwell })
+
+
+# ========================
+# ---- MV MOS Devices ----
+# ========================
+logger.info('Starting MV MOS EXTRACTION')
+
+# 5V NMOS transistor outside DNWELL
+logger.info('Extracting 5V NMOS transistor outside DNWELL')
+extract_devices(mos4('nmos_5p0'),
+ { 'SD' => nsd, 'G' => nmos_5p0_g, 'tS' => nsd, 'tD' => nsd,
+ 'tG' => poly2_con, 'W' => sub })
+
+# 5V NMOS transistor inside DNWELL
+logger.info('Extracting 5V NMOS transistor inside DNWELL')
+extract_devices(mos4('nmos_5p0_dw'),
+ { 'SD' => nsd, 'G' => nmos_5p0_dw_g, 'tS' => nsd, 'tD' => nsd,
+ 'tG' => poly2_con, 'W' => lvpwell_con })
+
+# 5V PMOS transistor outside DNWELL
+logger.info('Extracting 5V PMOS transistor outside DNWELL')
+extract_devices(mos4('pmos_5p0'),
+ { 'SD' => psd, 'G' => pmos_5p0_g, 'tS' => psd, 'tD' => psd,
+ 'tG' => poly2_con, 'W' => nwell_con })
+
+# 5V PMOS transistor inside DNWELL
+logger.info('Extracting 5V PMOS transistor inside DNWELL')
+extract_devices(mos4('pmos_5p0_dw'),
+ { 'SD' => psd_dw, 'G' => pmos_5p0_dw_g, 'tS' => psd_dw, 'tD' => psd_dw,
+ 'tG' => poly2_con, 'W' => dnwell })
+
+# 6V NMOS transistor outside DNWELL
+logger.info('Extracting 6V NMOS transistor outside DNWELL')
+extract_devices(mos4('nmos_6p0'),
+ { 'SD' => nsd, 'G' => nmos_6p0_g, 'tS' => nsd, 'tD' => nsd,
+ 'tG' => poly2_con, 'W' => sub })
+
+# 6V NMOS transistor inside DNWELL
+logger.info('Extracting 6V NMOS transistor inside DNWELL')
+extract_devices(mos4('nmos_6p0_dw'),
+ { 'SD' => nsd, 'G' => nmos_6p0_dw_g, 'tS' => nsd, 'tD' => nsd,
+ 'tG' => poly2_con, 'W' => lvpwell_con })
+
+# 6V PMOS transistor outside DNWELL
+logger.info('Extracting 6V PMOS transistor outside DNWELL')
+extract_devices(mos4('pmos_6p0'),
+ { 'SD' => psd, 'G' => pmos_6p0_g, 'tS' => psd, 'tD' => psd,
+ 'tG' => poly2_con, 'W' => nwell_con })
+
+# 6V PMOS transistor inside DNWELL
+logger.info('Extracting 6V PMOS transistor inside DNWELL')
+extract_devices(mos4('pmos_6p0_dw'),
+ { 'SD' => psd_dw, 'G' => pmos_6p0_dw_g, 'tS' => psd_dw, 'tD' => psd_dw,
+ 'tG' => poly2_con, 'W' => dnwell })
+
+# 6V NAT NMOS transistor outside DNWELL
+logger.info('Extracting 6V NAT NMOS transistor outside DNWELL')
+extract_devices(mos4('nmos_6p0_nat'),
+ { 'SD' => nsd, 'G' => nmos_6p0_nat_g, 'tS' => nsd, 'tD' => nsd,
+ 'tG' => poly2_con, 'W' => sub })
+
+# 6V NAT PMOS transistor inside DNWELL
+logger.info('Extracting 6V NAT PMOS transistor inside DNWELL')
+extract_devices(mos4('pmos_6p0_nat_dw'),
+ { 'SD' => psd_dw, 'G' => pmos_6p0_nat_dw_g, 'tS' => psd_dw, 'tD' => psd_dw,
+ 'tG' => poly2_con, 'W' => dnwell })
+
+# 6V Extended LDD NMOS
+logger.info('Extracting 6V Extended LDD NMOS')
+extract_devices(mos4('nmos_eldd'),
+ { 'S' => nsd, 'D' => nsd_sab, 'G' => nmos_eldd_g, 'tS' => nsd,
+ 'tD' => nsd_sab, 'tG' => poly2_con, 'W' => lvpwell_con })
+
+# 6V DDD MV NMOS
+logger.info('Extracting 6V DDD MV NMOS')
+extract_devices(mos4('nmos_ddd'),
+ { 'S' => nsd, 'D' => nsd_sab, 'G' => nmos_ddd_g, 'tS' => nsd,
+ 'tD' => nsd_sab, 'tG' => poly2_con, 'W' => lvpwell_con })
+
+# 6V NMOS with drain sab outside DNWELL
+logger.info('Extracting 6V NMOS with drain sab outside DNWELL')
+extract_devices(mos4('nmos_6p0_sab'),
+ { 'S' => nsd, 'D' => nsd_sab, 'G' => nmos_6p0_sab_g, 'tS' => nsd,
+ 'tD' => nsd_sab, 'tG' => poly2_con, 'W' => sub })
+
+# 6V NMOS with drain sab inside DNWELL
+logger.info('Extracting 6V NMOS with drain sab inside DNWELL')
+extract_devices(mos4('nmos_6p0_dw_sab'),
+ { 'S' => nsd, 'D' => nsd_sab, 'G' => nmos_6p0_dw_sab_g, 'tS' => nsd,
+ 'tD' => nsd_sab, 'tG' => poly2_con, 'W' => lvpwell_con })
+
+# 5V NMOS with drain sab outside DNWELL
+logger.info('Extracting 5V NMOS with drain sab outside DNWELL')
+extract_devices(mos4('nmos_5p0_sab'),
+ { 'S' => nsd, 'D' => nsd_sab, 'G' => nmos_5p0_sab_g, 'tS' => nsd,
+ 'tD' => nsd_sab, 'tG' => poly2_con, 'W' => sub })
+
+# 5V NMOS with drain sab inside DNWELL
+logger.info('Extracting 5V NMOS with drain sab inside DNWELL')
+extract_devices(mos4('nmos_5p0_dw_sab'),
+ { 'S' => nsd, 'D' => nsd_sab, 'G' => nmos_5p0_dw_sab_g, 'tS' => nsd,
+ 'tD' => nsd_sab, 'tG' => poly2_con, 'W' => lvpwell_con })
+
+
diff --git a/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs
new file mode 100644
index 0000000..72dea73
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/piscap_derivations.lvs
@@ -0,0 +1,58 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ PISCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting PISCAP DERIVATIONS')
+
+piscap_exclude = lvpwell.join(pplus).join(resistor)
+ .join(esd).join(sab).join(dni)
+ .join(pwhv).join(fusewindow_d).join(polyfuse)
+ .join(schottky_diode).join(zener).join(res_mk)
+ .join(diode_mk).join(v5_xtor).join(drc_bjt)
+ .join(nat).join(fhres).join(mos_cap_mk)
+ .join(mvsd).join(mvpsd).join(elmd_mk)
+ .join(elmd2_mk).join(lvs_rf).join(lvs_source)
+ .join(mk_35v).join(well_diode_mk).join(esd_hbm_mk)
+ .join(mos_mk_type1).join(swfet_mk).join(lvs_35v)
+ .join(hvpddd).join(hvpolyrs).join(ldmos_xtor)
+
+ngate_nw = ngate.and(piscap).and(nwell).not(piscap_exclude)
+
+ngate_nw_lv = ngate_nw.not(dualgate2_d)
+ngate_nw_mv = ngate_nw.and(dualgate2_d)
+
+#====================
+# --- PIS 1P8 CAP ---
+#====================
+
+# cap_pis_01v8: Model for 1.8V PIS capacitor (outside DNWELL) [pis_1p8]
+cap_pis_01v8_gate = ngate_nw_lv.not(dnwell)
+
+# cap_pis_01v8_dn: Model for (1.8V PIS capacitor (inside DNWEL) [pis_1p8_dw]
+cap_pis_01v8_dn_gate = ngate_nw_lv.and(dnwell)
+
+#====================
+# --- PIS 6P0 CAP ---
+#====================
+
+# cap_pis_06v0: Model for 6V PIS capacitor (outside DNWELL) [pis_6p0]
+cap_pis_06v0_gate = ngate_nw_mv.not(dnwell)
+
+# cap_pis_06v0_dn: Model for 6V PIS capacitor (inside DNWEL) [pis_6p0_dw]
+cap_pis_06v0_dn_gate = ngate_nw_mv.and(dnwell)
diff --git a/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs
new file mode 100644
index 0000000..16a21aa
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/piscap_extraction.lvs
@@ -0,0 +1,53 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- PISCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting PISCAP EXTRACTION')
+
+#====================
+# --- PIS 1P8 CAP ---
+#====================
+
+# cap_pis_01v8: Model for 1.8V PIS capacitor (outside DNWELL) [pis_1p8]
+logger.info('Extracting cap_pis_01v8 device')
+extract_devices(capacitor('cap_pis_01v8', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_01v8_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_pis_01v8_dn: Model for (1.8V PIS capacitor (inside DNWEL) [pis_1p8_dw]
+logger.info('Extracting cap_pis_01v8_dn device')
+extract_devices(capacitor('cap_pis_01v8_dn', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_01v8_dn_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+#====================
+# --- PIS 6P0 CAP ---
+#====================
+
+# cap_pis_06v0: Model for 6V PIS capacitor (outside DNWELL) [pis_6p0]
+logger.info('Extracting cap_pis_06v0 device')
+extract_devices(capacitor('cap_pis_06v0', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_06v0_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_pis_06v0_dn: Model for 6V PIS capacitor (inside DNWEL) [pis_6p0_dw]
+logger.info('Extracting cap_pis_06v0_dn device')
+extract_devices(capacitor('cap_pis_06v0_dn', 4.4e-15, PisCap),
+ { 'P1' => cap_pis_06v0_dn_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs
new file mode 100644
index 0000000..abfc448
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_connections.lvs
@@ -0,0 +1,47 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor CONNECTIONS -----
+#================================
+
+#========================
+# --- PN 1P8 VARACTOR ---
+#========================
+
+connect(cap_var_pd2nw_01v8_terminal_p ,contact)
+connect(cap_var_pd2nw_01v8_dn_terminal_p ,contact)
+
+#========================
+# --- PN 6P0 VARACTOR ---
+#========================
+
+connect(cap_var_pd2nw_06v0_terminal_p ,contact)
+connect(cap_var_pd2nw_06v0_dn_terminal_p ,contact)
+
+#=========================
+# --- MOS 1P8 VARACTOR ---
+#=========================
+
+connect(cap_var_fet_01v8_gate ,contact)
+connect(cap_var_fet_01v8_dn_gate ,contact)
+
+#=========================
+# --- MOS 6P0 VARACTOR ---
+#=========================
+
+connect(cap_var_fet_06v0_gate ,contact)
+connect(cap_var_fet_06v0_dn_gate ,contact)
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
new file mode 100644
index 0000000..aff1b79
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_derivations.lvs
@@ -0,0 +1,90 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor DERIVATIONS ----
+#================================
+
+logger.info('Starting VARACTOR DERIVATIONS')
+
+#=========================
+# --- VARACTOR EXCLUDE ---
+#=========================
+
+var_exclude = lvpwell.join(resistor).join(esd)
+ .join(sab).join(fusetop).join(tanres)
+ .join(dni).join(pwhv).join(fusewindow_d)
+ .join(polyfuse).join(schottky_diode).join(piscap)
+ .join(zener).join(res_mk).join(diode_mk)
+ .join(v5_xtor).join(drc_bjt).join(nat)
+ .join(fhres).join(mos_cap_mk).join(tanres_mk)
+ .join(tanres_l_mk).join(mvsd).join(mvpsd)
+ .join(elmd_mk).join(elmd2_mk).join(lvs_source)
+ .join(mk_35v).join(well_diode_mk).join(esd_hbm_mk)
+ .join(mos_mk_type1).join(swfet_mk).join(mom_mk)
+ .join(mom_m1_mk).join(mom_m2_mk).join(mom_m3_mk)
+ .join(mom_m4_mk).join(mom_m5_mk).join(hvnddd)
+ .join(hvpddd).join(hvpolyrs).join(ldmos_xtor)
+
+pcomp_nw_var = pcomp.and(nwell).and(lvs_rf).not(poly2).not(var_exclude)
+ngate_nw_var = ngate.and(nwell).and(lvs_rf).not(var_exclude)
+
+pcomp_nw_var_lv = pcomp_nw_var.not(dualgate2_d)
+pcomp_nw_var_mv = pcomp_nw_var.and(dualgate2_d)
+
+ngate_nw_var_lv = ngate_nw_var.not(dualgate2_d)
+ngate_nw_var_mv = ngate_nw_var.and(dualgate2_d)
+
+#========================
+# --- PN 1P8 VARACTOR ---
+#========================
+
+# cap_var_pd2nw_01v8: Model for 1.8V Scalable PN-varactor (outside DNWELL) [pn_varactor_1p8]
+cap_var_pd2nw_01v8_terminal_p = pcomp_nw_var_lv.not(dnwell)
+
+# cap_var_pd2nw_01v8_dn: Model for 1.8V Scalable PN-varactor (inside DNWELL) [pn_varactor_1p8_dw]
+cap_var_pd2nw_01v8_dn_terminal_p = pcomp_nw_var_lv.and(dnwell)
+
+#========================
+# --- PN 6P0 VARACTOR ---
+#========================
+
+# cap_var_pd2nw_06v0: Model for 6V Scalable PN-varactor (outside DNWELL) [pn_varactor_6p0]
+cap_var_pd2nw_06v0_terminal_p = pcomp_nw_var_mv.not(dnwell)
+
+# cap_var_pd2nw_06v0_dn: Model for 6V Scalable PN-varactor (inside DNWELL) [pn_varactor_6p0_dw]
+cap_var_pd2nw_06v0_dn_terminal_p = pcomp_nw_var_mv.and(dnwell)
+
+#=========================
+# --- MOS 1P8 VARACTOR ---
+#=========================
+
+# cap_var_fet_01v8: Model for 1.8V Scalable MOS-varactor (outside DNWELL) [mos_varactor_1p8]
+cap_var_fet_01v8_gate = ngate_nw_var_lv.not(dnwell)
+
+# cap_var_fet_01v8_dn: Model for 1.8V Scalable MOS-varactor (inside DNWELL) [mos_varactor_1p8_dw]
+cap_var_fet_01v8_dn_gate = ngate_nw_var_lv.and(dnwell)
+
+#=========================
+# --- MOS 6P0 VARACTOR ---
+#=========================
+
+# cap_var_fet_06v0: Model for 6V Scalable MOS-varactor (outside DNWELL) [mos_varactor_6p0]
+cap_var_fet_06v0_gate = ngate_nw_var_mv.not(dnwell)
+
+# cap_var_fet_06v0_dn: Model for 6V Scalable MOS-varactor (inside DNWELL) [mos_varactor_6p0_dw]
+cap_var_fet_06v0_dn_gate = ngate_nw_var_mv.and(dnwell)
+
diff --git a/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs
new file mode 100644
index 0000000..098d0d9
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/varactor_extraction.lvs
@@ -0,0 +1,85 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor EXTRACTION ----
+#================================
+
+logger.info('Starting VARACTOR EXTRACTION')
+
+#========================
+# --- PN 1P8 VARACTOR ---
+#========================
+
+# cap_var_pd2nw_01v8: Model for 1.8V Scalable PN-varactor (outside DNWELL) [pn_varactor_1p8]
+logger.info('Extracting cap_var_pd2nw_01v8 varactor')
+extract_devices(capacitor('cap_var_pd2nw_01v8', 4.4e-15, VarCap),
+ { "P1" => cap_var_pd2nw_01v8_terminal_p, "P2" => nwell_con,
+ "tA" => cap_var_pd2nw_01v8_terminal_p, "tB" => nwell_con })
+
+# cap_var_pd2nw_01v8_dn: Model for 1.8V Scalable PN-varactor (inside DNWELL) [pn_varactor_1p8_dw]
+logger.info('Extracting cap_var_pd2nw_01v8_dn')
+extract_devices(capacitor('cap_var_pd2nw_01v8_dn', 4.4e-15, VarCap),
+ { "P1" => cap_var_pd2nw_01v8_dn_terminal_p, "P2" => dnwell,
+ "tA" => cap_var_pd2nw_01v8_dn_terminal_p, "tB" => dnwell })
+
+#========================
+# --- PN 6P0 VARACTOR ---
+#========================
+
+# cap_var_pd2nw_06v0: Model for 6V Scalable PN-varactor (outside DNWELL) [pn_varactor_6p0]
+logger.info('Extracting cap_var_pd2nw_06v0')
+extract_devices(capacitor('cap_var_pd2nw_06v0', 4.4e-15, VarCap),
+ { "P1" => cap_var_pd2nw_06v0_terminal_p, "P2" => nwell_con,
+ "tA" => cap_var_pd2nw_06v0_terminal_p, "tB" => nwell_con })
+
+# cap_var_pd2nw_06v0_dn: Model for 6V Scalable PN-varactor (inside DNWELL) [pn_varactor_6p0_dw]
+logger.info('Extracting cap_var_pd2nw_06v0_dn')
+extract_devices(capacitor('cap_var_pd2nw_06v0_dn', 4.4e-15, VarCap),
+ { "P1" => cap_var_pd2nw_06v0_dn_terminal_p, "P2" => dnwell,
+ "tA" => cap_var_pd2nw_06v0_dn_terminal_p, "tB" => dnwell })
+
+#=========================
+# --- MOS 1P8 VARACTOR ---
+#=========================
+
+# cap_var_fet_01v8: Model for 1.8V Scalable MOS-varactor (outside DNWELL) [mos_varactor_1p8]
+logger.info('Extracting cap_var_fet_01v8')
+extract_devices(capacitor('cap_var_fet_01v8', 4.4e-15, VarCap),
+ { 'P1' => cap_var_fet_01v8_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_var_fet_01v8_dn: Model for 1.8V Scalable MOS-varactor (inside DNWELL) [mos_varactor_1p8_dw]
+logger.info('Extracting cap_var_fet_01v8_dn')
+extract_devices(capacitor('cap_var_fet_01v8_dn', 4.4e-15, VarCap),
+ { 'P1' => cap_var_fet_01v8_dn_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+#=========================
+# --- MOS 6P0 VARACTOR ---
+#=========================
+
+# cap_var_fet_06v0: Model for 6V Scalable MOS-varactor (outside DNWELL) [mos_varactor_6p0]
+logger.info('Extracting cap_var_fet_06v0')
+extract_devices(capacitor('cap_var_fet_06v0', 4.4e-15, VarCap),
+ { 'P1' => cap_var_fet_06v0_gate, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# cap_var_fet_06v0_dn: Model for 6V Scalable MOS-varactor (inside DNWELL) [mos_varactor_6p0_dw]
+logger.info('Extracting cap_var_fet_06v0_dn')
+extract_devices(capacitor('cap_var_fet_06v0_dn', 4.4e-15, VarCap),
+ { 'P1' => cap_var_fet_06v0_dn_gate, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
diff --git a/BCDLite/klayout/lvs/testing/Makefile b/BCDLite/klayout/lvs/testing/Makefile
new file mode 100644
index 0000000..270b923
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/Makefile
@@ -0,0 +1,38 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+#=========================================================================
+# ---------------------------------- LVS ---------------------------------
+#=========================================================================
+
+SHELL := /bin/bash
+Testing_DIR ?= $(shell pwd)
+
+.DEFAULT_GOAL := all
+
+all: test-LVS
+
+test-LVS: test-LVS-main
+
+#=================================
+# ----- test-LVS_regression ------
+#=================================
+
+.ONESHELL:
+test-LVS-main: test-LVS-MOS test-LVS-BJT test-LVS-DIODE test-LVS-RES test-LVS-MIMCAP test-LVS-APMOMCAP test-LVS-VARACTOR test-LVS-MOSCAP test-LVS-ESD test-LVS-EFUSE
+
+.ONESHELL:
+test-LVS-%:
+ @ python3 run_regression.py --device_name=$*
+
diff --git a/BCDLite/klayout/lvs/testing/README.md b/BCDLite/klayout/lvs/testing/README.md
new file mode 100644
index 0000000..59f45c8
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/README.md
@@ -0,0 +1,33 @@
+# Globalfoundries 180nm BCDLite LVS Testing
+
+Explains how to test GF180nm LVS rule decks.
+
+## Folder Structure
+
+```text
+📁 testing
+ ┣ 📜Makefile
+ ┣ 📜README.md
+ ┣ 📜run_regression.py
+ ┗ 📜testcases
+ ```
+
+## Prerequisites
+
+At a minimum:
+
+- Git 2.34.1+
+- Python 3.9.12+
+- KLayout 0.28.6+
+
+## Usage
+
+To make a full test for GF180nm LVS rule deck, you could use the following command in testing directory:
+
+```bash
+make all
+```
+
+## **Regression Outputs**
+
+- Final results will appear at the end of the run logs.
diff --git a/BCDLite/klayout/lvs/testing/run_regression.py b/BCDLite/klayout/lvs/testing/run_regression.py
new file mode 100644
index 0000000..814058b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/run_regression.py
@@ -0,0 +1,530 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""Run GlobalFoundries 180nm BCDLite LVS Regression.
+
+Usage:
+ run_regression.py (--help| -h)
+ run_regression.py [--device_name=<device_name>] [--mp=<num>] [--run_name=<run_name>]
+
+Options:
+ --help -h Print this help message.
+ --device_name=<device_name> Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, PISCAP, ESD, EFUSE).
+ --mp=<num> The number of threads used in run.
+ --run_name=<run_name> Select your run name.
+"""
+
+from subprocess import check_call
+from subprocess import Popen, PIPE
+import concurrent.futures
+import traceback
+import yaml
+from docopt import docopt
+import os
+from datetime import datetime
+import xml.etree.ElementTree as ET
+import time
+import pandas as pd
+import logging
+import glob
+from pathlib import Path
+from tqdm import tqdm
+import re
+import errno
+import numpy as np
+from collections import defaultdict
+import shutil
+
+SUPPORTED_TC_EXT = "gds"
+SUPPORTED_SPICE_EXT = "cdl"
+SUPPORTED_SW_EXT = "yaml"
+
+
+def check_klayout_version():
+ """
+ check_klayout_version checks klayout version and makes sure it would work with the DRC.
+ """
+ # ======= Checking Klayout version =======
+ klayout_v_ = os.popen("klayout -b -v").read()
+ klayout_v_ = klayout_v_.split("\n")[0]
+ klayout_v_list = []
+
+ if klayout_v_ == "":
+ logging.error("Klayout is not found. Please make sure klayout is installed.")
+ exit(1)
+ else:
+ klayout_v_list = [int(v) for v in klayout_v_.split(" ")[-1].split(".")]
+
+ if len(klayout_v_list) < 1 or len(klayout_v_list) > 3:
+ logging.error("Was not able to get klayout version properly.")
+ exit(1)
+ elif len(klayout_v_list) >= 2 or len(klayout_v_list) <= 3:
+ if klayout_v_list[1] < 28 or (klayout_v_list[1] == 28 and klayout_v_list[2] <= 3):
+ logging.error("Prerequisites at a minimum: KLayout 0.28.4")
+ logging.error(
+ "Using this klayout version is not supported in this development."
+ )
+ exit(1)
+
+ logging.info(f"Your Klayout version is: {klayout_v_}")
+
+
+def parse_existing_devices(rule_deck_path, output_path, target_device_group=None):
+ """
+ This function collects the rule names from the existing drc rule decks.
+
+ Parameters
+ ----------
+ rule_deck_path : string or Path object
+ Path string to the LVS directory where all the LVS files are located.
+ output_path : string or Path
+ Path of the run location to store the output analysis file.
+ target_device_group : string Optional
+ Name of the device group to be in testing
+
+ Returns
+ -------
+ pd.DataFrame
+ A pandas DataFrame with the rule and rule deck used.
+ """
+
+ if target_device_group is None:
+ lvs_files = glob.glob(os.path.join(rule_deck_path, "rule_decks", "*_extraction.lvs"))
+ else:
+ table_device_file = os.path.join(
+ rule_deck_path, "rule_decks", f"{str(target_device_group).lower()}_extraction.lvs"
+ )
+ if not os.path.isfile(table_device_file):
+ raise FileNotFoundError(
+ errno.ENOENT, os.strerror(errno.ENOENT), table_device_file
+ )
+
+ lvs_files = [table_device_file]
+
+ rules_data = list()
+
+ for runset in lvs_files:
+ with open(runset, "r") as f:
+ for line in f:
+ if "extract_devices" in line:
+ line_list = line.split("'")
+ rule_info = dict()
+ rule_info["device_group"] = os.path.basename(runset).replace(
+ "_extraction.lvs", ""
+ ).upper()
+ rule_info["device_name"] = line_list[1]
+ rule_info["in_rule_deck"] = 1
+ rules_data.append(rule_info)
+
+ df = pd.DataFrame(rules_data)
+ df.drop_duplicates(inplace=True)
+ df.to_csv(os.path.join(output_path, "rule_deck_rules.csv"), index=False)
+ return df
+
+
+def build_tests_dataframe(unit_test_cases_dir, target_device_group):
+ """
+ This function is used for getting all test cases available in a formated dataframe before running.
+
+ Parameters
+ ----------
+ unit_test_cases_dir : str
+ Path string to the location of unit test cases path.
+ target_device_group : str or None
+ Name of device group that we want to run regression for. If None, run all found.
+
+ Returns
+ -------
+ pd.DataFrame
+ A DataFrame that has all the targetted test cases that we need to run.
+ """
+ all_unit_test_cases_layout = sorted(
+ Path(unit_test_cases_dir).rglob("*.{}".format(SUPPORTED_TC_EXT))
+ )
+ logging.info(
+ "## Total number of gds files test cases found: {}".format(len(all_unit_test_cases_layout))
+ )
+
+ all_unit_test_cases_netlist = sorted(
+ Path(unit_test_cases_dir).rglob("*.{}".format(SUPPORTED_SPICE_EXT))
+ )
+ logging.info(
+ "## Total number of spice files test cases found: {}".format(len(all_unit_test_cases_netlist))
+ )
+
+ if len(all_unit_test_cases_netlist) != len(all_unit_test_cases_layout):
+ logging.error(
+ "## Each testcase should have Layout and Netlist file"
+ )
+ exit(1)
+
+ # Get test cases df from test cases
+ tc_df = pd.DataFrame({"test_layout_path": all_unit_test_cases_layout , "test_netlist_path": all_unit_test_cases_netlist})
+ tc_df["device_name"] = tc_df["test_layout_path"].apply(lambda x: x.name.replace(".gds", ""))
+ tc_df["device_group"] = tc_df["test_layout_path"].apply(lambda x: x.parent.parent.name.replace("_devices", "").upper())
+
+ if target_device_group is not None:
+ tc_df = tc_df[tc_df["device_group"] == target_device_group]
+ if len(tc_df) < 1:
+ logging.error("No test cases remaining after filtering.")
+ exit(1)
+
+ tc_df["run_id"] = range(len(tc_df))
+ return tc_df
+
+
+def get_switches(yaml_file, rule_name):
+ """Parse yaml file and extract switches data
+ Parameters
+ ----------
+ yaml_file : str
+ yaml config file path given py the user.
+ Returns
+ -------
+ yaml_dic : dictionary
+ dictionary containing switches data.
+ """
+
+ # load yaml config data
+ with open(yaml_file, "r") as stream:
+ try:
+ yaml_dic = yaml.safe_load(stream)
+ except yaml.YAMLError as exc:
+ print(exc)
+
+ return [f"{param}={value}" for param, value in yaml_dic[rule_name].items()]
+
+
+def run_test_case(
+ lvs_dir,
+ layout_path,
+ netlist_path,
+ run_dir,
+ device_name,
+):
+ """
+ This function run a single test case using the correct DRC file.
+
+ Parameters
+ ----------
+ lvs_dir : string or Path
+ Path to the location where all runsets exist.
+ layout_path : stirng or Path object
+ Path string to the layout of the test pattern we want to test.
+ netlist_path : stirng or Path object
+ Path string to the netlist of the test pattern we want to test.
+ run_dir : stirng or Path object
+ Path to the location where is the regression run is done.
+ device_name : string
+ Device name that we are running on.
+
+ Returns
+ -------
+ dict
+ A dict with all rule counts
+ """
+
+ # Get switches used for each run
+ sw_file = os.path.join(
+ Path(layout_path.parent).absolute(), f"{device_name}.{SUPPORTED_SW_EXT}"
+ )
+
+ if os.path.exists(sw_file):
+ switches = " ".join(get_switches(sw_file, device_name))
+ else:
+ # Get switches
+ switches = " -rd lvs_sub=sub!" if device_name == "sample_ggnfet_06v0_dss" else " -rd lvs_sub=vdd!" # default switch
+
+ # Creating run folder structure and copy testcases in it
+ pattern_clean = ".".join(os.path.basename(layout_path).split(".")[:-1])
+ output_loc = os.path.join(run_dir, device_name)
+ pattern_log = os.path.join(output_loc, f"{pattern_clean}_lvs.log")
+ os.makedirs(output_loc, exist_ok=True)
+ layout_path_run = os.path.join(run_dir, device_name, f"{device_name}.gds")
+ netlist_path_run = os.path.join(run_dir, device_name, f"{device_name}.cdl")
+ shutil.copyfile(layout_path, layout_path_run)
+ shutil.copyfile(netlist_path, netlist_path_run)
+
+ # command to run drc
+ call_str = f"klayout -b -r {lvs_dir}/gf180BCDLite.lvs -rd input={layout_path_run} -rd schematic={device_name}.cdl -rd report={device_name}.lvsdb -rd target_netlist={device_name}_extracted.cir {switches} > {pattern_log} 2>&1"
+
+ # Starting klayout run
+ try:
+ check_call(call_str, shell=True)
+ except Exception as e:
+ pattern_results = glob.glob(os.path.join(output_loc, f"{pattern_clean}*.lvsdb"))
+ if len(pattern_results) < 1:
+ logging.error("%s generated an exception: %s" % (pattern_clean, e))
+ traceback.print_exc()
+ raise Exception("Failed DRC run.")
+
+ # dumping log into output to make CI have the log
+ if os.path.isfile(pattern_log):
+ with open(pattern_log, "r") as f:
+ result = f.read()
+ for line in f:
+ line = line.strip()
+ logging.info(f"{line}")
+
+ # checking device status
+ device_status = 'Failed'
+ if "Congratulations! Netlists match" in result:
+ logging.info(f"{device_name} testcase passed")
+ device_status = 'Passed'
+ else:
+ logging.error(f"{device_name} testcase failed.")
+ logging.error(f"Please recheck {layout_path} file.")
+ else:
+ logging.error("Klayout LVS run failed, there is no log file is generated")
+ exit(1)
+
+ return device_status
+
+
+def run_all_test_cases(tc_df, lvs_dir, run_dir, num_workers):
+ """
+ This function run all test cases from the input dataframe.
+
+ Parameters
+ ----------
+ tc_df : pd.DataFrame
+ DataFrame that holds all the test cases information for running.
+ lvs_dir : string or Path
+ Path string to the location of the lvs runsets.
+ run_dir : string or Path
+ Path string to the location of the testing code and output.
+ num_workers : int
+ Number of workers to use for running the regression.
+
+ Returns
+ -------
+ pd.DataFrame
+ A pandas DataFrame with all test cases information post running.
+ """
+
+ tc_df["device_status"] = "no status"
+
+ with concurrent.futures.ThreadPoolExecutor(max_workers=num_workers) as executor:
+ future_to_run_id = dict()
+ for i, row in tc_df.iterrows():
+ future_to_run_id[
+ executor.submit(
+ run_test_case,
+ lvs_dir,
+ row["test_layout_path"],
+ row["test_netlist_path"],
+ run_dir,
+ row["device_name"],
+ )
+ ] = row["run_id"]
+
+ for future in concurrent.futures.as_completed(future_to_run_id):
+ run_id = future_to_run_id[future]
+ try:
+ tc_df.loc[tc_df["run_id"] == run_id, "device_status"] = future.result()
+ except Exception as exc:
+ logging.error("%d generated an exception: %s" % (run_id, exc))
+ traceback.print_exc()
+ tc_df.loc[tc_df["run_id"] == run_id, "device_status"] = "exception"
+
+ return tc_df
+
+
+def aggregate_results(
+ results_df: pd.DataFrame, devices_df: pd.DataFrame
+):
+ """
+ aggregate_results Aggregate the results for all runs.
+
+ Parameters
+ ----------
+ results_df : pd.DataFrame
+ Dataframe that holds the information about the unit test rules.
+ devices_df : pd.DataFrame
+ Dataframe that holds the information about all the devices implemented in the rule deck.
+
+ Returns
+ -------
+ pd.DataFrame
+ A DataFrame that has all data analysis aggregated into one.
+ """
+ if len(devices_df) < 1 and len(results_df) < 1:
+ logging.error("## There are no rules for analysis or run.")
+ exit(1)
+ elif len(devices_df) < 1 and len(results_df) > 0:
+ df = results_df
+ elif len(devices_df) > 0 and len(results_df) < 1:
+ df = devices_df
+ else:
+ df = results_df.merge(devices_df, how="outer", on=["device_group", "device_name"])
+
+ df.loc[(df["device_status"] != 'Passed'), "device_status"] = "Failed"
+
+ return df
+
+
+def run_regression(lvs_dir, output_path, target_device_group, cpu_count):
+ """
+ Running Regression Procedure.
+
+ This function runs the full regression on all test cases.
+
+ Parameters
+ ----------
+ lvs_dir : string
+ Path string to the LVS directory where all the LVS files are located.
+ output_path : str
+ Path string to the location of the output results of the run.
+ target_device_group : str or None
+ Name of device group that we want to run regression for. If None, run all found.
+ cpu_count : int
+ Number of cpus to use in running testcases.
+ Returns
+ -------
+ bool
+ If all regression passed, it returns true. If any of the rules failed it returns false.
+ """
+
+ ## Parse Existing Rules
+ devices_df = parse_existing_devices(lvs_dir, output_path, target_device_group)
+ logging.info(
+ "## Total number of devices found in rule decks: {}".format(len(devices_df))
+ )
+ logging.info("## Parsed devices: \n" + str(devices_df))
+
+ ## Get all test cases available in the repo.
+ test_cases_path = os.path.join(lvs_dir, "testing/testcases")
+ unit_test_cases_path = os.path.join(test_cases_path, "unit")
+ tc_df = build_tests_dataframe(unit_test_cases_path, target_device_group)
+ logging.info("## Total table gds files found: {}".format(len(tc_df)))
+ logging.info("## Found testcases: \n" + str(tc_df))
+
+ ## Run all test cases.
+ results_df = run_all_test_cases(tc_df, lvs_dir, output_path, cpu_count)
+ logging.info("## Testcases found results: \n" + str(results_df))
+
+ ## Aggregate all dataframes into one
+ df = aggregate_results(results_df, devices_df)
+ df.drop_duplicates(inplace=True)
+ df.drop('run_id', inplace=True, axis=1)
+ logging.info("## Final analysis table: \n" + str(df))
+
+ ## Generate error if there are any missing info or fails.
+ df.to_csv(os.path.join(output_path, "all_test_cases_results.csv"), index=False)
+
+ ## Check if there any rules that generated false positive or false negative
+ failing_results = df[~df["device_status"].isin(["Passed"])]
+ logging.info("## Failing test cases: \n" + str(failing_results))
+
+ if len(failing_results) > 0:
+ logging.error("## Some test cases failed .....")
+ return False
+ else:
+ logging.info("## All testcases passed.")
+ return True
+
+
+def main(lvs_dir, output_path, target_device_group):
+ """
+ Main Procedure.
+
+ This function is the main execution procedure
+
+ Parameters
+ ----------
+ lvs_dir : str
+ Path string to the LVS directory where all the LVS files are located.
+ output_path : str
+ Path string to the location of the output results of the run.
+ target_device_group : str or None
+ Name of device group that we want to run regression for. If None, run all found.
+ Returns
+ -------
+ bool
+ If all regression passed, it returns true. If any of the rules failed it returns false.
+ """
+
+ # No. of threads
+ cpu_count = os.cpu_count() if args["--mp"] is None else int(args["--mp"])
+
+ # Pandas printing setup
+ pd.set_option("display.max_columns", None)
+ pd.set_option("display.max_rows", None)
+ pd.set_option("max_colwidth", None)
+ pd.set_option("display.width", 1000)
+
+ # info logs for args
+ logging.info("## Run folder is: {}".format(run_name))
+ logging.info("## Target device is: {}".format(target_device_group))
+
+ # Start of execution time
+ t0 = time.time()
+
+ ## Check Klayout version
+ check_klayout_version()
+
+ # Calling regression function
+ run_status = run_regression(lvs_dir, output_path, target_device_group, cpu_count)
+
+ # End of execution time
+ logging.info("Total execution time {}s".format(time.time() - t0))
+
+ if run_status:
+ logging.info("Test completed successfully.")
+ else:
+ logging.error("Test failed.")
+ exit(1)
+
+
+if __name__ == "__main__":
+
+ # docopt reader
+ args = docopt(__doc__, version="LVS Regression: 0.2")
+
+ # arguments
+ run_name = args["--run_name"]
+
+ # run name
+ if run_name is None:
+ run_name = datetime.utcnow().strftime("unit_tests_%Y_%m_%d_%H_%M_%S")
+
+ # Paths of regression dirs
+ testing_dir = os.path.dirname(os.path.abspath(__file__))
+ lvs_dir = os.path.dirname(testing_dir)
+ output_path = os.path.join(testing_dir, run_name)
+
+ # Creating output dir
+ os.makedirs(output_path, exist_ok=True)
+
+ # logs format
+ logging.basicConfig(
+ level=logging.DEBUG,
+ handlers=[
+ logging.FileHandler(os.path.join(output_path, "{}.log".format(run_name))),
+ logging.StreamHandler(),
+ ],
+ format="%(asctime)s | %(levelname)-7s | %(message)s",
+ datefmt="%d-%b-%Y %H:%M:%S",
+ )
+
+ ## selected device
+ allowed_devices = ["MOS", "BJT", "DIODE", "RES", "MIMCAP", "MOSCAP", "PISCAP", "APMOMCAP", "VARACTOR" , "EFUSE", "ESD"]
+ target_device_group = args["--device_name"]
+
+ if target_device_group and target_device_group not in allowed_devices:
+ logging.error("Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, PISCAP, ESD, EFUSE) only")
+ exit(1)
+
+ # Calling main function
+ run_status = main(lvs_dir, output_path, target_device_group)
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x16.gds b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x16.gds
new file mode 100644
index 0000000..4a91319
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x16.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x2.gds b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x2.gds
new file mode 100644
index 0000000..7b26685
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x2.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x8.gds
new file mode 100644
index 0000000..84d711b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_5x5.gds b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_5x5.gds
new file mode 100644
index 0000000..1ad6cdd
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_5x5.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x10.gds b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x10.gds
new file mode 100644
index 0000000..f6474e6
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x10.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x20.gds b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x20.gds
new file mode 100644
index 0000000..692ccc1
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x20.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x5.gds b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x5.gds
new file mode 100644
index 0000000..b2b60fc
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x5.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_10x10.gds b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_10x10.gds
new file mode 100644
index 0000000..83d1ce6
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_10x10.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_5x5.gds b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_5x5.gds
new file mode 100644
index 0000000..2ea4827
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_5x5.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16.cdl
new file mode 100644
index 0000000..35213d6
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16.cdl
@@ -0,0 +1,34 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: vnpn_0p54x16
+* View Name: schematic
+* Netlisted on: Nov 24 10:25:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: vnpn_0p54x16
+* View Name: schematic
+************************************************************************
+
+.SUBCKT vnpn_0p54x16 I1_default_B I1_default_C I1_default_E I1_default_S
+*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_0p54x16
++ m=1
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2.cdl
new file mode 100644
index 0000000..a2046bf
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: vnpn_0p54x2
+* View Name: schematic
+* Netlisted on: Nov 24 10:21:29 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: vnpn_0p54x2
+* View Name: schematic
+************************************************************************
+
+.SUBCKT vnpn_0p54x2 I1_default_B I1_default_C I1_default_E I1_default_S
+*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_0p54x2 m=1
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x8.cdl
new file mode 100644
index 0000000..ef185ba
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x8.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: vnpn_0p54x8
+* View Name: schematic
+* Netlisted on: Nov 24 10:24:33 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: vnpn_0p54x8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT vnpn_0p54x8 I1_default_B I1_default_C I1_default_E I1_default_S
+*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_0p54x8 m=1
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5.cdl
new file mode 100644
index 0000000..d22f81b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: vnpn_5x5
+* View Name: schematic
+* Netlisted on: Nov 24 10:26:06 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: vnpn_5x5
+* View Name: schematic
+************************************************************************
+
+.SUBCKT vnpn_5x5 I1_default_B I1_default_C I1_default_E I1_default_S
+*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_5x5 m=1
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x10.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x10.cdl
new file mode 100644
index 0000000..2b6a54c
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x10.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: vpnp_6p0_0p42x10
+* View Name: schematic
+* Netlisted on: Nov 24 10:34:45 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: vpnp_6p0_0p42x10
+* View Name: schematic
+************************************************************************
+
+.SUBCKT vpnp_6p0_0p42x10 I1_default_B I1_default_C I1_default_E
+*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
+QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_0p42x10 m=1
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x20.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x20.cdl
new file mode 100644
index 0000000..c50226a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x20.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: vpnp_6p0_0p42x20
+* View Name: schematic
+* Netlisted on: Nov 24 10:34:45 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: vpnp_6p0_0p42x20
+* View Name: schematic
+************************************************************************
+
+.SUBCKT vpnp_6p0_0p42x20 I1_default_B I1_default_C I1_default_E
+*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
+QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_0p42x20 m=1
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
new file mode 100644
index 0000000..12736c4
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: vpnp_6p0_0p42x5
+* View Name: schematic
+* Netlisted on: Nov 24 10:34:45 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: vpnp_6p0_0p42x5
+* View Name: schematic
+************************************************************************
+
+.SUBCKT vpnp_6p0_0p42x5 I1_default_B I1_default_C I1_default_E
+*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
+QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_0p42x5 m=1
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_10x10.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_10x10.cdl
new file mode 100644
index 0000000..5eb6971
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_10x10.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: vpnp_6p0_10x10
+* View Name: schematic
+* Netlisted on: Nov 24 10:34:45 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: vpnp_6p0_10x10
+* View Name: schematic
+************************************************************************
+
+.SUBCKT vpnp_6p0_10x10 I1_default_B I1_default_C I1_default_E
+*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
+QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_10x10 m=1
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_5x5.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_5x5.cdl
new file mode 100644
index 0000000..22dcf35
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_5x5.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: vpnp_6p0_5x5
+* View Name: schematic
+* Netlisted on: Nov 24 10:34:45 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: vpnp_6p0_5x5
+* View Name: schematic
+************************************************************************
+
+.SUBCKT vpnp_6p0_5x5 I1_default_B I1_default_C I1_default_E
+*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
+QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_5x5 m=1
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8.gds
new file mode 100644
index 0000000..284da06
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8_dn.gds
new file mode 100644
index 0000000..f0d50cd
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0.gds
new file mode 100644
index 0000000..a84a81b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0_dn.gds
new file mode 100644
index 0000000..11fde57
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nw2ps_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nw2ps_06v0.gds
new file mode 100644
index 0000000..e2da907
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nw2ps_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8.gds
new file mode 100644
index 0000000..8b2356f
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8_dn.gds
new file mode 100644
index 0000000..c2eba47
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0.gds
new file mode 100644
index 0000000..b47a9d8
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0_dn.gds
new file mode 100644
index 0000000..c6ba90b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8.cdl
new file mode 100644
index 0000000..0f81e63
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:16:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_01v8 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=1.32n PJ=226.4u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=110p PJ=202.2u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=36p PJ=200.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=1.32n PJ=226.4u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=4.752p PJ=27.12u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=110p PJ=202.2u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=1.21p PJ=4.4u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=396f PJ=2.92u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=36p PJ=200.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=4.752p PJ=27.12u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=396f PJ=2.92u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=203.4f PJ=1.85u
+DI1_default vdd! I1_default_MINUS diode_nd2ps_01v8 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8_dn.cdl
new file mode 100644
index 0000000..9fa6328
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8_dn.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:17:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_01v8_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_nd2ps_01v8_dn m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_nd2ps_01v8_dn m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0.cdl
new file mode 100644
index 0000000..283a244
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:18:14 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_06v0 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=1.32n PJ=226.4u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=110p PJ=202.2u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=36p PJ=200.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=1.32n PJ=226.4u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=4.752p PJ=27.12u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=110p PJ=202.2u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=1.21p PJ=4.4u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=396f PJ=2.92u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=36p PJ=200.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=4.752p PJ=27.12u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=396f PJ=2.92u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nd2ps_06v0 m=1 AREA=203.4f PJ=1.85u
+DI1_default vdd! I1_default_MINUS diode_nd2ps_06v0 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0_dn.cdl
new file mode 100644
index 0000000..d34964b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_06v0_dn.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:18:59 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_06v0_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_nd2ps_06v0_dn m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_nd2ps_06v0_dn m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nw2ps_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nw2ps_06v0.cdl
new file mode 100644
index 0000000..4da7be2
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nw2ps_06v0.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nw2ps_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:43:35 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nw2ps_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nw2ps_06v0 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=1.21n PJ=224.2u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=123p PJ=202.46u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=86p PJ=201.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=1.21n PJ=224.2u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=146.41p PJ=48.4u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=14.883p PJ=26.66u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=10.406p PJ=25.92u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=123p PJ=202.46u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=14.883p PJ=26.66u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=1.5129p PJ=4.92u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=1.0578p PJ=4.18u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=86p PJ=201.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=10.406p PJ=25.92u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=1.0578p PJ=4.18u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nw2ps_06v0 m=1 AREA=739.6f PJ=3.44u
+DI1_default vdd! I1_default_MINUS diode_nw2ps_06v0 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8.cdl
new file mode 100644
index 0000000..8f87022
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pd2nw_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:49:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pd2nw_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pd2nw_01v8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=36p
++ PJ=200.72u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=174.24p
++ PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=36p
++ PJ=200.72u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=203.4f
++ PJ=1.85u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pd2nw_01v8 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8_dn.cdl
new file mode 100644
index 0000000..472e9a9
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8_dn.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pd2nw_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:00 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pd2nw_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pd2nw_01v8_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pd2nw_01v8_dn m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pd2nw_01v8_dn m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0.cdl
new file mode 100644
index 0000000..60c1eb1
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pd2nw_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pd2nw_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pd2nw_06v0 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=36p
++ PJ=200.72u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=174.24p
++ PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=36p
++ PJ=200.72u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pd2nw_06v0 m=1 AREA=203.4f
++ PJ=1.85u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pd2nw_06v0 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0_dn.cdl
new file mode 100644
index 0000000..8b38902
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_06v0_dn.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pd2nw_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:51:10 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pd2nw_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pd2nw_06v0_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pd2nw_06v0_dn m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pd2nw_06v0_dn m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.gds
new file mode 100644
index 0000000..683b329
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.yaml
new file mode 100644
index 0000000..46c3411
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_0f85_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "0.85"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.gds
new file mode 100644
index 0000000..04d7f53
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.yaml
new file mode 100644
index 0000000..c273392
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_0f85_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "0.85"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.gds
new file mode 100644
index 0000000..889daa5
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.yaml
new file mode 100644
index 0000000..f58e8ed
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_0f85_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "0.85"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.gds
new file mode 100644
index 0000000..8c8e2c6
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.yaml
new file mode 100644
index 0000000..e8458e4
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_0f85_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_0f85_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "0.85"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds
new file mode 100644
index 0000000..5ca7b27
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml
new file mode 100644
index 0000000..5cdd347
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "1"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds
new file mode 100644
index 0000000..f7aa6d5
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml
new file mode 100644
index 0000000..652e54d
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "1"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds
new file mode 100644
index 0000000..98d4a1d
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml
new file mode 100644
index 0000000..4718dcb
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "1"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds
new file mode 100644
index 0000000..3e256ac
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml
new file mode 100644
index 0000000..e77a318
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "1"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds
new file mode 100644
index 0000000..54a51f1
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml
new file mode 100644
index 0000000..a4ade5d
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml
@@ -0,0 +1,5 @@
+cap_mim_1f5_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "1.5"
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds
new file mode 100644
index 0000000..926dd7c
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml
new file mode 100644
index 0000000..847938a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "1.5"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds
new file mode 100644
index 0000000..2d5f3f0
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml
new file mode 100644
index 0000000..353ebb4
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "1.5"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds
new file mode 100644
index 0000000..4023827
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml
new file mode 100644
index 0000000..781fbe8
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "1.5"
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m2m3_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m2m3_noshield.cdl
new file mode 100644
index 0000000..85b2338
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_0f85_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:39:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_0f85_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_0f85_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_0f85_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_0f85_m2m3_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m3m4_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m3m4_noshield.cdl
new file mode 100644
index 0000000..19ee6d1
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_0f85_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_0f85_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_0f85_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_0f85_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_0f85_m3m4_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m4m5_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m4m5_noshield.cdl
new file mode 100644
index 0000000..5682262
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_0f85_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_0f85_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_0f85_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_0f85_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_0f85_m4m5_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m5m6_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m5m6_noshield.cdl
new file mode 100644
index 0000000..f28729e
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_0f85_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_0f85_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_0f85_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_0f85_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_0f85_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_0f85_m5m6_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl
new file mode 100644
index 0000000..ba2c560
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:39:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m2m3_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl
new file mode 100644
index 0000000..674d7e6
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m3m4_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl
new file mode 100644
index 0000000..4918d52
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m4m5_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl
new file mode 100644
index 0000000..4bfabb6
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m5m6_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl
new file mode 100644
index 0000000..262610a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:42:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m2m3_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl
new file mode 100644
index 0000000..22327d8
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m3m4_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl
new file mode 100644
index 0000000..aa81915
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m4m5_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl
new file mode 100644
index 0000000..d657f55
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m5m6_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds
new file mode 100644
index 0000000..9979044
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds
new file mode 100644
index 0000000..81e3719
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds
new file mode 100644
index 0000000..0349a37
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds
new file mode 100644
index 0000000..6d24d7a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/layout/cap_pis_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl
new file mode 100644
index 0000000..e70e083
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_01v8 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_01v8 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_01v8 m=1 l=5.88u w=5u
+.ENDS
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl
new file mode 100644
index 0000000..834803f
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_01v8_dn.cdl
@@ -0,0 +1,34 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_01v8_dn I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_01v8_dn m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_01v8_dn m=1 l=5.88u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl
new file mode 100644
index 0000000..66e879a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_06v0 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_06v0 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_06v0 m=1 l=5.88u w=5u
+.ENDS
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl
new file mode 100644
index 0000000..ab6e6da
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/cap_pis_06v0_dn.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pis_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pis_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pis_06v0_dn I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D cap_pis_06v0_dn m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D cap_pis_06v0_dn m=1 l=5.88u w=5u
+.ENDS
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8.gds
new file mode 100644
index 0000000..1b8269c
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8_dn.gds
new file mode 100644
index 0000000..2bb01f9
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0.gds
new file mode 100644
index 0000000..8057fcf
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0_dn.gds
new file mode 100644
index 0000000..dcbc03b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_fet_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8.gds
new file mode 100644
index 0000000..a9bd13e
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8_dn.gds
new file mode 100644
index 0000000..d7d181d
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0.gds
new file mode 100644
index 0000000..22d79d3
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0_dn.gds
new file mode 100644
index 0000000..3535905
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/layout/cap_var_pd2nw_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8.cdl
new file mode 100644
index 0000000..aac3115
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_fet_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_fet_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_fet_01v8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_01v8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_01v8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_01v8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_01v8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_01v8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_01v8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_01v8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_01v8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_01v8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_01v8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8_dn.cdl
new file mode 100644
index 0000000..16d2038
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_01v8_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_fet_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:12:27 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_fet_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_fet_01v8_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_01v8_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_01v8_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_01v8_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_01v8_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_01v8_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_01v8_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_01v8_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_01v8_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_01v8_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_01v8_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0.cdl
new file mode 100644
index 0000000..99613b1
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_fet_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:13:17 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_fet_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_fet_06v0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_06v0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_06v0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_06v0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_06v0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_06v0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_06v0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_06v0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_06v0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_06v0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_06v0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0_dn.cdl
new file mode 100644
index 0000000..b2b34ba
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_fet_06v0_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_fet_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:15:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_fet_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_fet_06v0_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_var_fet_06v0_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_var_fet_06v0_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_var_fet_06v0_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_var_fet_06v0_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_var_fet_06v0_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_var_fet_06v0_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_var_fet_06v0_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_var_fet_06v0_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_var_fet_06v0_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_var_fet_06v0_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8.cdl
new file mode 100644
index 0000000..09d3dea
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_pd2nw_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:49:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_pd2nw_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_01v8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_default_MINUS I1_default_PLUS
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_01v8 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_01v8 m=1 L=1u W=1u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8_dn.cdl
new file mode 100644
index 0000000..b7c1439
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_01v8_dn.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_pd2nw_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:00 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_pd2nw_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_01v8_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS
++ I1_default_PLUS I1_default_MINUS
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_01v8_dn m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_01v8_dn m=1 L=1u W=1u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0.cdl
new file mode 100644
index 0000000..723bda2
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_pd2nw_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_pd2nw_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_06v0 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_default_MINUS I1_default_PLUS
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_06v0 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_06v0 m=1 L=1u W=1u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0_dn.cdl
new file mode 100644
index 0000000..2783ab4
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/cap_var_pd2nw_06v0_dn.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_var_pd2nw_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:51:10 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_var_pd2nw_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_var_pd2nw_06v0_dn I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS
++ I1_default_PLUS I1_default_MINUS
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS cap_var_pd2nw_06v0_dn m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS cap_var_pd2nw_06v0_dn m=1 L=1u W=1u
+.ENDS
+
diff --git a/IC/klayout/lvs/gf180ic.lvs b/IC/klayout/lvs/gf180ic.lvs
index ac05839..c15c0b8 100644
--- a/IC/klayout/lvs/gf180ic.lvs
+++ b/IC/klayout/lvs/gf180ic.lvs
@@ -188,11 +188,11 @@
logger.info("MIM Option selected: #{MIM_OPTION}")
# MIM
-MIM_CAP = $mim_cap || '2'
+MIM_CAP = $mim_cap || '0'
logger.info("MIM CAP selected: #{MIM_CAP}")
-MIM_CAP_STACK = $mim_cap_stack || '2'
+MIM_CAP_STACK = $mim_cap_stack || '0'
logger.info("STACKED MIM CAP selected: #{MIM_CAP_STACK}")
@@ -211,24 +211,21 @@
when '6LM'
cap_mim1f0 = 'cap_mim_1f0_m5m6_noshield'
cap_mim1f5 = 'cap_mim_1f5_m5m6_noshield'
- cap_mim2f0 = 'cap_mim_2f0_m5m6_noshield'
cap_mim_single_2f0 = 'cap_mim_single_2f0_m5m6_noshield'
- cap_mim2f0 = 'cap_mim_2f0_m5m6_noshield'
- cap_mim3f0 = 'cap_mim_3f0_m5m6_noshield'
+ cap_mim2f0 = 'cap_mim_2f0_m4m6_noshield'
+ cap_mim3f0 = 'cap_mim_3f0_m4m6_noshield'
when '5LM'
cap_mim1f0 = 'cap_mim_1f0_m4m5_noshield'
cap_mim1f5 = 'cap_mim_1f5_m4m5_noshield'
- cap_mim2f0 = 'cap_mim_2f0_m4m5_noshield'
cap_mim_single_2f0 = 'cap_mim_single_2f0_m4m5_noshield'
- cap_mim2f0 = 'cap_mim_2f0_m4m5_noshield'
- cap_mim3f0 = 'cap_mim_3f0_m4m5_noshield'
+ cap_mim2f0 = 'cap_mim_2f0_m3m5_noshield'
+ cap_mim3f0 = 'cap_mim_3f0_m3m5_noshield'
when '4LM'
cap_mim1f0 = 'cap_mim_1f0_m3m4_noshield'
cap_mim1f5 = 'cap_mim_1f5_m3m4_noshield'
- cap_mim2f0 = 'cap_mim_2f0_m3m4_noshield'
cap_mim_single_2f0 = 'cap_mim_single_2f0_m3m4_noshield'
- cap_mim2f0 = 'cap_mim_2f0_m3m4_noshield'
- cap_mim3f0 = 'cap_mim_3f0_m3m4_noshield'
+ cap_mim2f0 = 'cap_mim_2f0_m2m4_noshield'
+ cap_mim3f0 = 'cap_mim_3f0_m2m4_noshield'
end
end
diff --git a/IC/klayout/lvs/rule_decks/bjt_connection.lvs b/IC/klayout/lvs/rule_decks/bjt_connection.lvs
new file mode 100644
index 0000000..5e21220
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/bjt_connection.lvs
@@ -0,0 +1,68 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ------ BJT CONNECTIONS --------
+#================================
+logger.info('Starting LVS BJT CONNECTIONS')
+
+# ==============
+# ---- vnpn ----
+# ==============
+
+# npn_02p00x02p00 nodes connections
+connect(npn_02p00x02p00_e, contact)
+connect(npn_02p00x02p00_b, contact)
+connect(npn_02p00x02p00_c, contact)
+
+# npn_05p00x05p00 nodes connections
+connect(npn_05p00x05p00_e, contact)
+connect(npn_05p00x05p00_b, contact)
+connect(npn_05p00x05p00_c, contact)
+
+# ==============
+# ---- vpnp ----
+# ==============
+
+# pnp_10p00x10p00 nodes connections
+connect(pnp_10p00x10p00_e, contact)
+connect(pnp_10p00x10p00_b, contact)
+connect(pnp_10p00x10p00_c, contact)
+
+# pnp_05p00x05p00 nodes connections
+connect(pnp_05p00x05p00_e, contact)
+connect(pnp_05p00x05p00_b, contact)
+connect(pnp_05p00x05p00_c, contact)
+
+# pnp_05p00x00p42 nodes connections
+connect(pnp_05p00x00p42_e, contact)
+connect(pnp_05p00x00p42_b, contact)
+connect(pnp_05p00x00p42_c, contact)
+
+# pnp_1p2x2p5 nodes connections
+connect(pnp_1p2x2p5_e, contact)
+connect(pnp_1p2x2p5_b, contact)
+connect(pnp_1p2x2p5_c, contact)
+
+# pnp_00p46x1p2 nodes connections
+connect(pnp_00p46x1p2_e, contact)
+connect(pnp_00p46x1p2_b, contact)
+connect(pnp_00p46x1p2_c, contact)
+
+# pnp_00p46x00p46 nodes connections
+connect(pnp_00p46x00p46_e, contact)
+connect(pnp_00p46x00p46_b, contact)
+connect(pnp_00p46x00p46_c, contact)
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/custom_classes.lvs b/IC/klayout/lvs/rule_decks/custom_classes.lvs
index 932217c..d0e84fd 100644
--- a/IC/klayout/lvs/rule_decks/custom_classes.lvs
+++ b/IC/klayout/lvs/rule_decks/custom_classes.lvs
@@ -148,4 +148,13 @@
enable_parameter('A', true)
enable_parameter('P', true)
end
+ end
+
+ class VarCap < RBA::DeviceClassCapacitorWithBulk
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
end
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/devices_connections.lvs b/IC/klayout/lvs/rule_decks/devices_connections.lvs
index a72f4b7..d4f6b9d 100644
--- a/IC/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/IC/klayout/lvs/rule_decks/devices_connections.lvs
@@ -40,19 +40,27 @@
connect(poly2_con, contact)
connect(contact, metal1)
connect(metal1, via1)
-connect(via1, metal2_ncap)
+connect(via1, metal2)
if METAL_LEVEL != '2LM'
- connect(metal2_ncap, via2)
- connect(via2, metal3_ncap)
+ connect(metal2, via2_ncap)
+ connect(via2_ncap, metal3)
+ connect(via2_cap, fusetop)
+ connect(via2_cap, fusetop2)
if METAL_LEVEL != '3LM'
- connect(metal3_ncap, via3)
- connect(via3, metal4_ncap)
+ connect(metal3, via3_ncap)
+ connect(via3_ncap, metal4)
+ connect(via3_cap, fusetop)
+ connect(via3_cap, fusetop2)
if METAL_LEVEL != '4LM'
- connect(metal4_ncap, via4)
- connect(via4, metal5_ncap)
+ connect(metal4, via4_ncap)
+ connect(via4_ncap, metal5)
+ connect(via4_cap, fusetop)
+ connect(via4_cap, fusetop2)
if METAL_LEVEL != '5LM'
- connect(metal5_ncap, via5)
- connect(via5, metaltop)
+ connect(metal5, via5_ncap)
+ connect(via5_ncap, metaltop)
+ connect(via5_cap, fusetop)
+ connect(via5_cap, fusetop2)
end
end
end
@@ -64,13 +72,13 @@
connect(comp, comp_label)
connect(poly2_con, poly2_label)
connect(metal1, metal1_label)
-connect(metal2_ncap, metal2_label)
+connect(metal2, metal2_label)
if METAL_LEVEL != '2LM'
- connect(metal3_ncap, metal3_label)
+ connect(metal3, metal3_label)
if METAL_LEVEL != '3LM'
- connect(metal4_ncap, metal4_label)
+ connect(metal4, metal4_label)
if METAL_LEVEL != '4LM'
- connect(metal5_ncap, metal5_label)
+ connect(metal5, metal5_label)
connect(metaltop, metaltop_label) if METAL_LEVEL != '5LM'
end
end
@@ -90,132 +98,29 @@
#================================
# ------ BJT CONNECTIONS --------
#================================
-logger.info('Starting LVS BJT CONNECTIONS')
-# ==============
-# ---- vnpn ----
-# ==============
-
-# npn_02p00x02p00 nodes connections
-connect(npn_02p00x02p00_e, contact)
-connect(npn_02p00x02p00_b, contact)
-connect(npn_02p00x02p00_c, contact)
-
-# npn_05p00x05p00 nodes connections
-connect(npn_05p00x05p00_e, contact)
-connect(npn_05p00x05p00_b, contact)
-connect(npn_05p00x05p00_c, contact)
-
-# ==============
-# ---- vpnp ----
-# ==============
-
-# pnp_10p00x10p00 nodes connections
-connect(pnp_10p00x10p00_e, contact)
-connect(pnp_10p00x10p00_b, contact)
-connect(pnp_10p00x10p00_c, contact)
-
-# pnp_05p00x05p00 nodes connections
-connect(pnp_05p00x05p00_e, contact)
-connect(pnp_05p00x05p00_b, contact)
-connect(pnp_05p00x05p00_c, contact)
-
-# pnp_05p00x00p42 nodes connections
-connect(pnp_05p00x00p42_e, contact)
-connect(pnp_05p00x00p42_b, contact)
-connect(pnp_05p00x00p42_c, contact)
-
-# pnp_1p2x2p5 nodes connections
-connect(pnp_1p2x2p5_e, contact)
-connect(pnp_1p2x2p5_b, contact)
-connect(pnp_1p2x2p5_c, contact)
-
-# pnp_00p46x1p2 nodes connections
-connect(pnp_00p46x1p2_e, contact)
-connect(pnp_00p46x1p2_b, contact)
-connect(pnp_00p46x1p2_c, contact)
-
-# pnp_00p46x00p46 nodes connections
-connect(pnp_00p46x00p46_e, contact)
-connect(pnp_00p46x00p46_b, contact)
-connect(pnp_00p46x00p46_c, contact)
-
+# %include bjt_connection.lvs
#================================
# ----- DIODE CONNECTIONS -------
#================================
-logger.info('Starting LVS DIODE CONNECTIONS')
-
-# diode_np_1p8
-connect(diode_np_1p8_terminal_n, contact)
-
-# diode_pn_1p8
-connect(diode_pn_1p8_terminal_p, contact)
-
-# diode_np_3p3
-connect(diode_np_3p3_terminal_n, contact)
-
-# diode_pn_3p3
-connect(diode_pn_3p3_terminal_p, contact)
-
-# diode_nwp
-connect(diode_nwp_terminal_n, contact)
-connect(diode_nwp_terminal_p, contact)
-
-# diode_np_1p8_nat
-connect(diode_np_1p8_nat_terminal_n, contact)
-
-# diode_np_3p3_nat
-connect(diode_np_3p3_nat_terminal_n, contact)
-
-# diode_dnwpw
-connect(diode_dnwpw_terminal_p, contact)
-
-# diode_dnwps
-connect(diode_dnwps_terminal_p, contact)
-
+# %include diode_connection.lvs
#==================================
# ------ MIMCAP CONNECTIONS -------
#==================================
-logger.info('Starting LVS MIMCAP CONNECTIONS')
-
-case MIM_OPTION
-when 'A'
- if MIM_CAP
- connect(metal2, mim_virtual)
- connect(fuse_cap, via2)
- end
-when 'B'
- if MIM_CAP
- connect(topmin1_metal, mimtm_virtual)
- connect(fuse_cap, top_via)
- end
- if MIM_CAP_STACK
- connect(topmin1_metal, mimtm_stack1_virtual)
- connect(fuse_cap, top_via)
- connect(topmin2_metal, mimtm_stack2_virtual)
- connect(fuse2_cap, topmin1_via)
- end
-end
-
+# %include mimcap_connection.lvs
#========================================
# ------ PN Varactors CONNECTIONS -------
#========================================
-# pnvar_1p8 varactor nodes connections
-connect(pnvar_1p8_terminal_n, contact)
-connect(pnvar_1p8_terminal_p, contact)
-
+# %include pn_varactor_connection.lvs
#================================
# ---- RESISTOR DERIVATIONS -----
#================================
-logger.info('Starting LVS RESISTOR CONNECTIONS')
-
-connect(nplus_cont, contact)
-connect(pplus_cont, contact)
\ No newline at end of file
+# %include res_connection.lvs
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/diode_connection.lvs b/IC/klayout/lvs/rule_decks/diode_connection.lvs
new file mode 100644
index 0000000..2bd1560
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/diode_connection.lvs
@@ -0,0 +1,55 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- DIODE CONNECTIONS -------
+#================================
+
+logger.info('Starting LVS DIODE CONNECTIONS')
+
+# diode_np_1p8
+connect(diode_np_1p8_terminal_n, contact)
+connect(diode_np_1p8_terminal_p, contact)
+
+# diode_pn_1p8
+connect(diode_pn_1p8_terminal_n, contact)
+connect(diode_pn_1p8_terminal_p, contact)
+
+# diode_np_3p3
+connect(diode_np_3p3_terminal_n, contact)
+connect(diode_np_3p3_terminal_p, contact)
+
+# diode_pn_3p3
+connect(diode_pn_3p3_terminal_n, contact)
+connect(diode_pn_3p3_terminal_p, contact)
+
+# diode_nwp
+connect(diode_nwp_terminal_n, contact)
+connect(diode_nwp_terminal_p, contact)
+
+# diode_np_1p8_nat
+connect(diode_np_1p8_nat_terminal_n, contact)
+connect(diode_np_1p8_nat_terminal_p, contact)
+
+# diode_np_3p3_nat
+connect(diode_np_3p3_nat_terminal_n, contact)
+connect(diode_np_3p3_nat_terminal_p, contact)
+
+# diode_dnwpw
+connect(diode_dnwps_terminal_p, contact)
+
+# diode_dnwps
+connect(diode_dnwps_terminal_p, contact)
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/general_derivations.lvs b/IC/klayout/lvs/rule_decks/general_derivations.lvs
index 3ab99e9..efd371d 100644
--- a/IC/klayout/lvs/rule_decks/general_derivations.lvs
+++ b/IC/klayout/lvs/rule_decks/general_derivations.lvs
@@ -39,3 +39,24 @@
psd_dw = pcomp.and(dnwell).interacting(pgate).not(pgate).not(res_mk)
nwell_con = nwell.not(res_mk)
poly2_con = poly2.not(res_mk).not(plfuse)
+
+
+# Splitting vias into cap-vias, ncap-vias
+
+if METAL_LEVEL != '2LM'
+ via2_ncap = via2.not(fusetop.or(fusetop2))
+ via2_cap = via2.and(fusetop.or(fusetop2))
+ if METAL_LEVEL != '3LM'
+ via3_ncap = via3.not(fusetop.or(fusetop2))
+ via3_cap = via3.and(fusetop.or(fusetop2))
+ if METAL_LEVEL != '4LM'
+ via4_ncap = via4.not(fusetop.or(fusetop2))
+ via4_cap = via4.and(fusetop.or(fusetop2))
+ if METAL_LEVEL != '5LM'
+ via5_ncap = via5.not(fusetop.or(fusetop2))
+ via5_cap = via5.and(fusetop.or(fusetop2))
+ end
+ end
+ end
+end
+
diff --git a/IC/klayout/lvs/rule_decks/lateral_bjt_derivations.lvs b/IC/klayout/lvs/rule_decks/lateral_bjt_derivations.lvs
new file mode 100644
index 0000000..1d8878c
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/lateral_bjt_derivations.lvs
@@ -0,0 +1,58 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ------ BJT DERIVATIONS --------
+#================================
+
+logger.info('Starting BJT DERIVATIONS')
+
+#===============
+# ---- lpnp ----
+# ==============
+logger.info('Starting lpnp layers DERIVATIONS')
+
+# lpnp general nodes DERIVATIONS
+e_c_layer = pcomp.inside(nwell).outside(dnwell).inside(lvs_bjt).not(dualgate)
+ .not(res_mk).not(nat).not(sab).not(poly2).not(res_mk_type1).not(resistor)
+
+lpnp_b = ncomp.and(nwell).outside(dnwell).interacting(lvs_bjt).covering(e_c_layer)
+ .not(dualgate).not(res_mk).not(nat).not(sab).not(poly2).not(res_mk_type1).not(resistor)
+
+lpnp_c = e_c_layer.inside(lpnp_b)
+
+lpnp_e = e_c_layer.inside(lpnp_b).outside(lpnp_c)
+
+
+# lpnp_1p8_0p54x0p54 nodes DERIVATIONS
+lpnp_1p8_0p54x0p54_e = lpnp_e.with_area(0.2.um, 0.4.um).interacting(vpnp_e.edges.with_length(0.5.um, 0.6.um))
+lpnp_1p8_0p54x0p54_b = lpnp_b.interacting(vpnp_b.extents.interacting(lpnp_1p8_0p54x0p54_e))
+lpnp_1p8_0p54x0p54_c = lpnp_c.interacting(vpnp_c.extents.interacting(lpnp_1p8_0p54x0p54_e))
+
+# lpnp_1p8_0p54x1p2 nodes DERIVATIONS
+lpnp_1p8_0p54x1p2_e = lpnp_e.with_area(0.5.um, 0.8.um).interacting(vpnp_e.edges.with_length(1.um, 1.4.um))
+lpnp_1p8_0p54x1p2_b = lpnp_b.interacting(vpnp_b.extents.interacting(lpnp_1p8_0p54x1p2_e))
+lpnp_1p8_0p54x1p2_c = lpnp_c.interacting(vpnp_c.extents.interacting(lpnp_1p8_0p54x1p2_e))
+
+# lpnp_1p8_1p2x2p5 nodes DERIVATIONS
+lpnp_1p8_1p2x2p5_e = lpnp_e.with_area(2.5.um, 3.5.um).interacting(vpnp_e.edges.with_length(2.3.um, 2.7.um))
+lpnp_1p8_1p2x2p5_b = lpnp_b.interacting(vpnp_b.extents.interacting(lpnp_1p8_1p2x2p5_e))
+lpnp_1p8_1p2x2p5_c = lpnp_c.interacting(vpnp_c.extents.interacting(lpnp_1p8_1p2x2p5_e))
+
+# lpnp_1p8_05p00x05p00 nodes DERIVATIONS
+lpnp_1p8_05p00x05p00_e = lpnp_e.with_area(24.5.um, 25.5.um).interacting(vpnp_e.edges.with_length(4.8.um, 5.2.um))
+lpnp_1p8_05p00x05p00_b = lpnp_b.interacting(vpnp_b.extents.interacting(lpnp_1p8_1p2x2p5_e))
+lpnp_1p8_05p00x05p00_c = lpnp_c.interacting(vpnp_c.extents.interacting(lpnp_1p8_1p2x2p5_e))
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/lateral_bjt_extraction.lvs b/IC/klayout/lvs/rule_decks/lateral_bjt_extraction.lvs
new file mode 100644
index 0000000..591275a
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/lateral_bjt_extraction.lvs
@@ -0,0 +1,75 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ------- BJT EXTRACTION --------
+#================================
+
+
+# ====================
+# ------- lpnp--------
+# ====================
+logger.info('Starting lpnp BJT EXTRACTION')
+
+# lpnp_1p8_0p54x0p54 BJT
+ignore_parameter('lpnp_1p8_0p54x0p54', 'AE')
+logger.info('Extracting lpnp_1p8_0p54x0p54 BJT')
+extract_devices(bjt4('lpnp_1p8_0p54x0p54'), { 'C' => lpnp_1p8_0p54x0p54_c.extents,
+ 'B' => lpnp_1p8_0p54x0p54_b.extents,
+ 'E' => lpnp_1p8_0p54x0p54_e,
+ 'S' => sub.extents,
+ 'tC' => lpnp_1p8_0p54x0p54_c,
+ 'tB' => lpnp_1p8_0p54x0p54_b,
+ 'tE' => lpnp_1p8_0p54x0p54_e
+ 'tS' => sub })
+
+# lpnp_1p8_0p54x1p2 BJT
+ignore_parameter('lpnp_1p8_0p54x1p2', 'AE')
+logger.info('Extracting lpnp_1p8_0p54x1p2 BJT')
+extract_devices(bjt4('lpnp_1p8_0p54x1p2'), { 'C' => lpnp_1p8_0p54x1p2_c.extents,
+ 'B' => lpnp_1p8_0p54x1p2_b.extents,
+ 'E' => lpnp_1p8_0p54x1p2_e,
+ 'S' => sub.extents,
+ 'tC' => lpnp_1p8_0p54x1p2_c,
+ 'tB' => lpnp_1p8_0p54x1p2_b,
+ 'tE' => lpnp_1p8_0p54x1p2_e
+ 'tS' => sub })
+
+# lpnp_1p8_1p2x2p5 BJT
+ignore_parameter('lpnp_1p8_1p2x2p5', 'AE')
+logger.info('Extracting lpnp_1p8_1p2x2p5 BJT')
+extract_devices(bjt4('lpnp_1p8_1p2x2p5'), { 'C' => lpnp_1p8_1p2x2p5_c.extents,
+ 'B' => lpnp_1p8_1p2x2p5_b.extents,
+ 'E' => lpnp_1p8_1p2x2p5_e,
+ 'S' => sub.extents,
+ 'tC' => lpnp_1p8_1p2x2p5_c,
+ 'tB' => lpnp_1p8_1p2x2p5_b,
+ 'tE' => lpnp_1p8_1p2x2p5_e
+ 'tS' => sub})
+
+
+# lpnp_1p8_05p00x05p00 BJT
+ignore_parameter('lpnp_1p8_05p00x05p00', 'AE')
+logger.info('Extracting lpnp_1p8_05p00x05p00 BJT')
+extract_devices(bjt4('lpnp_1p8_05p00x05p00'), { 'C' => lpnp_1p8_05p00x05p00_c.extents,
+ 'B' => lpnp_1p8_05p00x05p00_b.extents,
+ 'E' => lpnp_1p8_05p00x05p00_e,
+ 'S' => sub.extents,
+ 'tC' => lpnp_1p8_05p00x05p00_c,
+ 'tB' => lpnp_1p8_05p00x05p00_b,
+ 'tE' => lpnp_1p8_05p00x05p00_e
+ 'tS' => sub})
+
diff --git a/IC/klayout/lvs/rule_decks/mimcap_connection.lvs b/IC/klayout/lvs/rule_decks/mimcap_connection.lvs
new file mode 100644
index 0000000..c2e6646
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/mimcap_connection.lvs
@@ -0,0 +1,34 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MIMCAP CONNECTIONS -------
+#==================================
+
+logger.info('Starting LVS MIMCAP CONNECTIONS')
+
+case MIM_OPTION
+when 'A'
+ connect(metal2, mim_virtual)
+ connect(fuse_cap, via2)
+
+when 'B'
+ connect(topmin1_metal, mimtm_virtual)
+ connect(fuse_cap, top_via)
+ connect(topmin1_metal, mimtm_stack1_virtual)
+ connect(topmin2_metal, mimtm_stack2_virtual)
+ connect(fuse2_cap, topmin1_via)
+end
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs b/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
index 6ced825..de22dc7 100644
--- a/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
+++ b/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
@@ -23,7 +23,6 @@
# mim option A
# stacked mim cannot exist in 2LM
mim_virtual = fusetop.sized(1.06.um).and(metal2.interacting(fusetop)).not(fusetop2)
-metal2_ncap = metal2.not(mim_virtual)
fuse_cap = fusetop.interacting(lvs_cap)
fuse2_cap = fusetop2.interacting(lvs_cap)
@@ -32,16 +31,3 @@
mimtm_stack1_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop))
mimtm_stack2_virtual = fusetop2.sized(1.06.um).and(topmin2_metal.interacting(fusetop2))
-
-if METAL_LEVEL != '2LM'
- metal3_ncap = metal3.not(mimtm_virtual).not(mimtm_stack2_virtual).not(mimtm_stack1_virtual)
-
- if METAL_LEVEL != '3LM'
- metal4_ncap = metal4.not(mimtm_virtual).not(mimtm_virtual).not(mimtm_stack2_virtual).not(mimtm_stack1_virtual)
- end
-
- if METAL_LEVEL != '4LM'
- metal5_ncap = metal5.not(mimtm_virtual).not(mimtm_virtual).not(mimtm_stack2_virtual).not(mimtm_stack1_virtual)
- end
-
-end
diff --git a/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs b/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs
index 11cb015..0f0a15b 100644
--- a/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs
+++ b/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs
@@ -74,6 +74,7 @@
end
case MIM_CAP_STACK
+
when '2'
# cap_mim2f0 capacitor
@@ -81,8 +82,6 @@
extract_devices(capacitor(cap_mim2f0, 2.0e-15, MIMCap), { 'P1' => mimtm_stack1_virtual,
'P2' => fuse_cap, })
- tolerance(cap_mim2f0, 'C', relative: 0.25)
-
extract_devices(capacitor(cap_mim2f0, 2.0e-15, MIMCap), { 'P1' => mimtm_stack2_virtual,
'P2' => fuse2_cap, })
tolerance(cap_mim2f0, 'C', relative: 0.25)
@@ -94,8 +93,6 @@
extract_devices(capacitor(cap_mim3f0, 3.0e-15, MIMCap), { 'P1' => mimtm_stack1_virtual,
'P2' => fuse_cap, })
- tolerance(cap_mim3f0, 'C', relative: 0.25)
-
extract_devices(capacitor(cap_mim3f0, 3.0e-15, MIMCap), { 'P1' => mimtm_stack2_virtual,
'P2' => fuse2_cap, })
tolerance(cap_mim3f0, 'C', relative: 0.25)
diff --git a/IC/klayout/lvs/rule_decks/pn_varactor_connection.lvs b/IC/klayout/lvs/rule_decks/pn_varactor_connection.lvs
new file mode 100644
index 0000000..8f4c111
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/pn_varactor_connection.lvs
@@ -0,0 +1,23 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#========================================
+# ------ PN Varactors CONNECTIONS -------
+#========================================
+
+# pnvar_1p8 varactor nodes connections
+connect(pnvar_1p8_terminal_n, contact)
+connect(pnvar_1p8_terminal_p, contact)
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/pn_varactor_extraction.lvs b/IC/klayout/lvs/rule_decks/pn_varactor_extraction.lvs
index 5f1d9e2..634fad1 100644
--- a/IC/klayout/lvs/rule_decks/pn_varactor_extraction.lvs
+++ b/IC/klayout/lvs/rule_decks/pn_varactor_extraction.lvs
@@ -21,4 +21,6 @@
# pnvar_1p8 varactor
logger.info('Extracting pnvar_1p8')
-extract_devices(diode('pnvar_1p8'), { 'N' => pnvar_1p8_terminal_n, 'P' => pnvar_1p8_terminal_p })
\ No newline at end of file
+extract_devices(capacitor_with_bulk("pnvar_1p8", 4.4e-15, VarCap),
+ { "P1" => pnvar_1p8_terminal_p, "P2" => pnvar_1p8_terminal_n,
+ "W" => sub})
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/res_connection.lvs b/IC/klayout/lvs/rule_decks/res_connection.lvs
new file mode 100644
index 0000000..813bd1b
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/res_connection.lvs
@@ -0,0 +1,24 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- RESISTOR DERIVATIONS -----
+#================================
+
+logger.info('Starting LVS RESISTOR CONNECTIONS')
+
+connect(nplus_cont, contact)
+connect(pplus_cont, contact)
\ No newline at end of file
diff --git a/IC/klayout/lvs/testing/Makefile b/IC/klayout/lvs/testing/Makefile
index 946c29c..198c2a7 100644
--- a/IC/klayout/lvs/testing/Makefile
+++ b/IC/klayout/lvs/testing/Makefile
@@ -23,14 +23,14 @@
all: test-LVS
-test-LVS: test-LVS-switch test-LVS-main
+test-LVS: test-LVS-main
#=================================
# ----- test-LVS_regression ------
#=================================
.ONESHELL:
-test-LVS-main: test-LVS-MOS test-LVS-BJT test-LVS-DIODE test-LVS-RES test-LVS-MIMCAP test-LVS-PN-VARACTOR test-LVS-MOS-VARACTOR
+test-LVS-main: test-LVS-MOS test-LVS-BJT test-LVS-DIODE test-LVS-RES test-LVS-MIMCAP test-LVS-PN_VARACTOR test-LVS-MOS_VARACTOR
.ONESHELL:
test-LVS-%:
diff --git a/IC/klayout/lvs/testing/run_regression.py b/IC/klayout/lvs/testing/run_regression.py
index b38a260..9b81be9 100644
--- a/IC/klayout/lvs/testing/run_regression.py
+++ b/IC/klayout/lvs/testing/run_regression.py
@@ -20,7 +20,7 @@
Options:
--help -h Print this help message.
- --device_name=<device_name> Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, PN-VARACTOR, MOS-VARACTOR).
+ --device_name=<device_name> Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, PN_VARACTOR, MOS_VARACTOR).
--mp=<num> The number of threads used in run.
--run_name=<run_name> Select your run name.
"""
@@ -532,14 +532,14 @@
"DIODE",
"RES",
"MIMCAP",
- "PN-VARACTOR",
- "MOS-VARACTOR",
+ "PN_VARACTOR",
+ "MOS_VARACTOR",
]
target_device_group = args["--device_name"]
if target_device_group and target_device_group not in allowed_devices:
logging.error(
- "Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, PN-VARACTOR, MOS-VARACTOR) only"
+ "Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, PN_VARACTOR, MOS_VARACTOR) only"
)
exit(1)
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds
new file mode 100644
index 0000000..fd1709c
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml
new file mode 100644
index 0000000..5cdd347
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "1"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds
new file mode 100644
index 0000000..415d044
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml
new file mode 100644
index 0000000..652e54d
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "1"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds
new file mode 100644
index 0000000..9777d8c
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml
new file mode 100644
index 0000000..4718dcb
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "1"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds
new file mode 100644
index 0000000..97f0ad7
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml
new file mode 100644
index 0000000..e77a318
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f0_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f0_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "1"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds
new file mode 100644
index 0000000..c36c36e
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml
new file mode 100644
index 0000000..a4ade5d
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m2m3_noshield.yaml
@@ -0,0 +1,5 @@
+cap_mim_1f5_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "1.5"
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds
new file mode 100644
index 0000000..0d275d1
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml
new file mode 100644
index 0000000..847938a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "1.5"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds
new file mode 100644
index 0000000..83be00c
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml
new file mode 100644
index 0000000..353ebb4
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "1.5"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds
new file mode 100644
index 0000000..54039ae
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml
new file mode 100644
index 0000000..781fbe8
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_1f5_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_1f5_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "1.5"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.gds
new file mode 100644
index 0000000..0b9ce22
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.yaml
new file mode 100644
index 0000000..d6d92ba
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_2f0_m2m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap_stack: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.gds
new file mode 100644
index 0000000..183a4f5
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.yaml
new file mode 100644
index 0000000..b16f754
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_2f0_m3m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap_stack: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.gds
new file mode 100644
index 0000000..94fb19d
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.yaml
new file mode 100644
index 0000000..7e1db3f
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_2f0_m4m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap_stack: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.gds
new file mode 100644
index 0000000..3e95cd6
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.yaml
new file mode 100644
index 0000000..a347fd3
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_3f0_m2m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap_stack: "3"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.gds
new file mode 100644
index 0000000..913993f
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.yaml
new file mode 100644
index 0000000..9cd5c50
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_3f0_m3m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap_stack: "3"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.gds
new file mode 100644
index 0000000..6b8701a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.yaml
new file mode 100644
index 0000000..1798498
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_3f0_m4m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap_stack: "3"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.gds
new file mode 100644
index 0000000..2499b86
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.yaml
new file mode 100644
index 0000000..8447ef4
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_single_2f0_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.gds
new file mode 100644
index 0000000..0efcff6
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.yaml
new file mode 100644
index 0000000..f98ba7a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_single_2f0_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.gds
new file mode 100644
index 0000000..1cde1f1
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.yaml
new file mode 100644
index 0000000..8f4830f
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_single_2f0_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.gds
new file mode 100644
index 0000000..1c81603
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.yaml
new file mode 100644
index 0000000..a816f4a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+cap_mim_single_2f0_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl
new file mode 100644
index 0000000..ba2c560
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:39:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m2m3_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl
new file mode 100644
index 0000000..674d7e6
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m3m4_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl
new file mode 100644
index 0000000..4918d52
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m4m5_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl
new file mode 100644
index 0000000..4bfabb6
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f0_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f0_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f0_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f0_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f0_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f0_m5m6_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl
new file mode 100644
index 0000000..262610a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m2m3_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:42:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m2m3_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl
new file mode 100644
index 0000000..22327d8
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m3m4_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m3m4_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl
new file mode 100644
index 0000000..aa81915
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m4m5_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m4m5_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl
new file mode 100644
index 0000000..d657f55
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_1f5_m5m6_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_1f5_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_1f5_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_1f5_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_1f5_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_1f5_m5m6_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m4_noshield.cdl
new file mode 100644
index 0000000..888a326
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m4_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_2f0_m2m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_2f0_m2m4_noshield
+* View Name: schematic
+************************************************************************
+.SUBCKT cap_mim_2f0_m2m4_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m2m4_noshield M=1 l=100.000u
++ w=100.000u c=2e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m2m4_noshield M=1 l=100.000u
++ w=100.000u c=2e-11
+
+.ENDS cap_mim_2f0_m2m4_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m5_noshield.cdl
new file mode 100644
index 0000000..1350b61
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m5_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_2f0_m3m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_2f0_m3m5_noshield
+* View Name: schematic
+************************************************************************
+.SUBCKT cap_mim_2f0_m3m5_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m3m5_noshield M=1 l=100.000u
++ w=100.000u c=2e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m3m5_noshield M=1 l=100.000u
++ w=100.000u c=2e-11
+
+.ENDS cap_mim_2f0_m3m5_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m6_noshield.cdl
new file mode 100644
index 0000000..a19b204
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m6_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_2f0_m4m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_2f0_m4m6_noshield
+* View Name: schematic
+************************************************************************
+.SUBCKT cap_mim_2f0_m4m6_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m4m6_noshield M=1 l=100.000u
++ w=100.000u c=2e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m4m6_noshield M=1 l=100.000u
++ w=100.000u c=2e-11
+
+.ENDS cap_mim_2f0_m4m6_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m2m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m2m4_noshield.cdl
new file mode 100644
index 0000000..0ab1cdb
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m2m4_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_3f0_m2m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_3f0_m2m4_noshield
+* View Name: schematic
+************************************************************************
+.SUBCKT cap_mim_3f0_m2m4_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_3f0_m2m4_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_3f0_m2m4_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+.ENDS cap_mim_3f0_m2m4_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m3m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m3m5_noshield.cdl
new file mode 100644
index 0000000..1a9f274
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m3m5_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_3f0_m3m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_3f0_m3m5_noshield
+* View Name: schematic
+************************************************************************
+.SUBCKT cap_mim_3f0_m3m5_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_3f0_m3m5_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_3f0_m3m5_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+.ENDS cap_mim_3f0_m3m5_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m4m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m4m6_noshield.cdl
new file mode 100644
index 0000000..aea33a7
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m4m6_noshield.cdl
@@ -0,0 +1,36 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_3f0_m4m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_3f0_m4m6_noshield
+* View Name: schematic
+************************************************************************
+.SUBCKT cap_mim_3f0_m4m6_noshield
+
+CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_3f0_m4m6_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_3f0_m4m6_noshield M=1 l=100.000u
++ w=100.000u c=3e-11
+
+.ENDS cap_mim_3f0_m4m6_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m2m3_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m2m3_noshield.cdl
new file mode 100644
index 0000000..523b1ac
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_single_2f0_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:53:54 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_single_2f0_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_single_2f0_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m3m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m3m4_noshield.cdl
new file mode 100644
index 0000000..4689f50
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_single_2f0_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_single_2f0_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_single_2f0_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m4m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m4m5_noshield.cdl
new file mode 100644
index 0000000..30e708a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_single_2f0_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_single_2f0_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_single_2f0_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m5m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m5m6_noshield.cdl
new file mode 100644
index 0000000..a5d4e30
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_single_2f0_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_single_2f0_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_single_2f0_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/layout/pnvar_1p8.gds b/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/layout/pnvar_1p8.gds
new file mode 100644
index 0000000..0770ae8
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/layout/pnvar_1p8.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/netlist/pnvar_1p8.cdl b/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/netlist/pnvar_1p8.cdl
new file mode 100644
index 0000000..7ff65b0
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/netlist/pnvar_1p8.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pnvar_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:16:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pnvar_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pnvar_1p8 I1_0_2_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS
++ I1_0_0_0_0_R0_MINUS I1_default_MINUS
++ I1_0_2_0_0_R0_PLUS I1_0_1_0_0_R0_PLUS I1_0_0_0_0_R0_PLUS I1_default_PLUS
+
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pnvar_1p8 AREA=4.752p PJ=27.12u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pnvar_1p8 AREA=396f PJ=2.92u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pnvar_1p8 AREA=203.4f PJ=1.85u
+CI1_default I1_default_PLUS I1_default_MINUS pnvar_1p8 AREA=1p PJ=4u
+.ENDS
+
diff --git a/Makefile b/Makefile
index 7b38c0d..6273977 100644
--- a/Makefile
+++ b/Makefile
@@ -22,6 +22,8 @@
# https://docs.conda.io/projects/conda/en/latest/user-guide/tasks/manage-environments.html
ENVIRONMENT_FILE := pdk_regression.yml
+KLAYOUT_LVS_TESTS := klayout/lvs/testing/
+
include third_party/make-env/conda.mk
# Lint python code
@@ -63,10 +65,28 @@
################################################################################
## LVS Regression section
################################################################################
-# LVS main testing
-test-LVS-main: | $(CONDA_ENV_PYTHON)
- @$(IN_CONDA_ENV) klayout -v
+#=================================
+# ----- test-LVS_regression ------
+#=================================
-# LVS main testing
-test-LVS-switch: | $(CONDA_ENV_PYTHON)
- @$(IN_CONDA_ENV) klayout -v
+# run regression on all variants` devices
+.ONESHELL:
+test-LVS-main: | $(CONDA_ENV_PYTHON)
+ @$(IN_CONDA_ENV) cd IC/$(KLAYOUT_LVS_TESTS) && make test-LVS-main
+ @$(IN_CONDA_ENV) cd ULL/$(KLAYOUT_LVS_TESTS) && make test-LVS-main
+ @$(IN_CONDA_ENV) cd BCDLite/$(KLAYOUT_LVS_TESTS) && make test-LVS-main
+
+.ONESHELL:
+test-LVS-% : | $(CONDA_ENV_PYTHON)
+ @which python3
+ifeq ($(findstring ULL, $($*)), ULL)
+ cd ULL/$(KLAYOUT_LVS_TESTS) && make test-LVS-$(subst ULL-,,$($*))
+endif
+
+ifeq ($(findstring IC, $($*)), IC)
+ cd IC/$(KLAYOUT_LVS_TESTS) && make test-LVS-$(subst IC-,,$($*))
+endif
+
+ifeq ($(findstring BCDLite, $($*)), BCDLite)
+ cd BCDLite/$(KLAYOUT_LVS_TESTS) && make test-LVS-$(subst BCDLite-,,$($*))
+endif
\ No newline at end of file
diff --git a/ULL/klayout/lvs/gf180ull.lvs b/ULL/klayout/lvs/gf180ull.lvs
index 554b08c..f15323e 100644
--- a/ULL/klayout/lvs/gf180ull.lvs
+++ b/ULL/klayout/lvs/gf180ull.lvs
@@ -260,17 +260,35 @@
# %include 'rule_decks/mos_derivations.lvs'
#================================
-# ------ RES DERIVATIONS --------
-#================================
-
-# %include 'rule_decks/res_derivations.lvs'
-
-#================================
# ------ DIODE DERIVATIONS --------
#================================
# %include 'rule_decks/diode_derivations.lvs'
+#================================
+# ------ MOSCAP DERIVATIONS -----
+#================================
+
+# %include 'rule_decks/moscap_derivations.lvs'
+
+#===================================
+# ------ Varactor DERIVATIONS ------
+#===================================
+
+# %include 'rule_decks/varactor_derivations.lvs'
+
+#===================================
+# ------ PISCAP DERIVATIONS ------
+#===================================
+
+# %include 'rule_decks/piscap_derivations.lvs'
+
+#===================================
+# ------ MIMCAP DERIVATIONS ------
+#===================================
+
+# %include 'rule_decks/mimcap_derivations.lvs'
+
#================================================
#------------ DEVICES CONNECTIVITY --------------
#================================================
@@ -296,17 +314,35 @@
# %include 'rule_decks/mos_extraction.lvs'
#================================
-# ------- RES EXTRACTION --------
-#================================
-
-# %include 'rule_decks/res_extraction.lvs'
-
-#================================
-# ------- Diode EXTRACTION --------
+# ------- Diode EXTRACTION ------
#================================
# %include 'rule_decks/diode_extraction.lvs'
+#================================
+# ------- MOSCAP EXTRACTION -----
+#================================
+
+# %include 'rule_decks/moscap_extraction.lvs'
+
+#================================
+# ----- Varactor EXTRACTION ----
+#================================
+
+# %include 'rule_decks/varactor_extraction.lvs'
+
+#================================
+# ------ PISCAP EXTRACTION -----
+#================================
+
+# %include 'rule_decks/piscap_extraction.lvs'
+
+#================================
+# ------ MIMCAP EXTRACTION -----
+#================================
+
+# %include 'rule_decks/mimcap_extraction.lvs'
+
#================================================
#------------- COMPARISON OPTIONS ---------------
#================================================
diff --git a/ULL/klayout/lvs/rule_decks/bjt_connection.lvs b/ULL/klayout/lvs/rule_decks/bjt_connection.lvs
new file mode 100644
index 0000000..d0a894f
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/bjt_connection.lvs
@@ -0,0 +1,98 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ------ BJT CONNECTIONS --------
+#================================
+logger.info('Starting LVS BJT CONNECTIONS')
+
+# ========================================
+# ---- VNPN (isolated collector) (5V) ----
+# ========================================
+
+# vnpn_5x5 nodes connections
+connect(npn_05p00x05p00_e, contact)
+connect(npn_05p00x05p00_b, contact)
+connect(npn_05p00x05p00_c, contact)
+
+# vnpn_0p54x16 nodes connections
+connect(npn_00p54x16p00_e, contact)
+connect(npn_00p54x16p00_b, contact)
+connect(npn_00p54x16p00_c, contact)
+
+# vnpn_0p54x8 nodes connections
+connect(npn_00p54x08p00_e, contact)
+connect(npn_00p54x08p00_b, contact)
+connect(npn_00p54x08p00_c, contact)
+
+# vnpn_0p54x2 nodes connections
+connect(npn_00p54x02p00_e, contact)
+connect(npn_00p54x02p00_b, contact)
+connect(npn_00p54x02p00_c, contact)
+
+# ===========================================
+# ---- VNPN (isolated collector) (3.3V) ----
+# ===========================================
+
+# vnpn_5x5_3p3 nodes connections
+connect(npn_05p00x05p00_e_3p3, contact)
+connect(npn_05p00x05p00_b_3p3, contact)
+connect(npn_05p00x05p00_c_3p3, contact)
+
+# vnpn_0p54x16_3p3 nodes connections
+connect(npn_00p54x16p00_e_3p3, contact)
+connect(npn_00p54x16p00_b_3p3, contact)
+connect(npn_00p54x16p00_c_3p3, contact)
+
+# vnpn_0p54x8_3p3 nodes connections
+connect(npn_00p54x08p00_e_3p3, contact)
+connect(npn_00p54x08p00_b_3p3, contact)
+connect(npn_00p54x08p00_c_3p3, contact)
+
+# vnpn_0p54x2_3p3 nodes connections
+connect(npn_00p54x02p00_e_3p3, contact)
+connect(npn_00p54x02p00_b_3p3, contact)
+connect(npn_00p54x02p00_c_3p3, contact)
+
+
+# ========================================
+# ---- VPNP (Psub as collector) (6V) ----
+# ========================================
+
+# vpnp_6p0_10x10 nodes connections
+connect(pnp_10p00x10p00_e, contact)
+connect(pnp_10p00x10p00_b, contact)
+connect(pnp_10p00x10p00_c, contact)
+
+# vpnp_6p0_5x5 nodes connections
+connect(pnp_05p00x05p00_e, contact)
+connect(pnp_05p00x05p00_b, contact)
+connect(pnp_05p00x05p00_c, contact)
+
+# vpnp_6p0_0p42x20 nodes connections
+connect(pnp_00p42x20p00_e, contact)
+connect(pnp_00p42x20p00_b, contact)
+connect(pnp_00p42x20p00_c, contact)
+
+# vpnp_6p0_0p42x10 nodes connections
+connect(pnp_00p42x10p00_e, contact)
+connect(pnp_00p42x10p00_b, contact)
+connect(pnp_00p42x10p00_c, contact)
+
+# vpnp_6p0_0p42x5 nodes connections
+connect(pnp_00p42x05p00_e, contact)
+connect(pnp_00p42x05p00_b, contact)
+connect(pnp_00p42x05p00_c, contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/custom_classes.lvs b/ULL/klayout/lvs/rule_decks/custom_classes.lvs
index 23f3250..11fcf5d 100644
--- a/ULL/klayout/lvs/rule_decks/custom_classes.lvs
+++ b/ULL/klayout/lvs/rule_decks/custom_classes.lvs
@@ -158,3 +158,23 @@
enable_parameter('P', true)
end
end
+
+# Varactor class
+class VarCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
+end
+
+# PISCAP class
+class PisCap < RBA::DeviceClassCapacitor
+ def initialize
+ super
+ enable_parameter("C", false)
+ enable_parameter("A", true)
+ enable_parameter("P", true)
+ end
+end
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/devices_connections.lvs b/ULL/klayout/lvs/rule_decks/devices_connections.lvs
index 9f86dd1..1cd89c1 100644
--- a/ULL/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/ULL/klayout/lvs/rule_decks/devices_connections.lvs
@@ -42,19 +42,23 @@
connect(poly2_con, contact)
connect(contact, metal1)
connect(metal1, via1)
-connect(via1, metal2_ncap)
+connect(via1, metal2)
if METAL_LEVEL != '2LM'
- connect(metal2_ncap, via2)
- connect(via2, metal3_ncap)
+ connect(metal2, via2_ncap)
+ connect(via2_ncap, metal3)
+ connect(via2_cap, fusetop)
if METAL_LEVEL != '3LM'
- connect(metal3_ncap, via3)
- connect(via3, metal4_ncap)
+ connect(metal3, via3_ncap)
+ connect(via3_ncap, metal4)
+ connect(via3_cap, fusetop)
if METAL_LEVEL != '4LM'
- connect(metal4_ncap, via4)
- connect(via4, metal5_ncap)
+ connect(metal4, via4_ncap)
+ connect(via4_ncap, metal5)
+ connect(via4_cap, fusetop)
if METAL_LEVEL != '5LM'
- connect(metal5_ncap, via5)
- connect(via5, metaltop)
+ connect(metal5, via5_ncap)
+ connect(via5_ncap, metaltop)
+ connect(via5_cap, fusetop)
end
end
end
@@ -67,11 +71,11 @@
connect(metal1, metal1_label)
connect(metal2, metal2_label)
if METAL_LEVEL != '2LM'
- connect(metal3_ncap, metal3_label)
+ connect(metal3, metal3_label)
if METAL_LEVEL != '3LM'
- connect(metal4_ncap, metal4_label)
+ connect(metal4, metal4_label)
if METAL_LEVEL != '4LM'
- connect(metal5_ncap, metal5_label)
+ connect(metal5, metal5_label)
connect(metaltop, metaltop_label) if METAL_LEVEL != '5LM'
end
end
@@ -90,163 +94,30 @@
#================================
# ----- MOSFET CONNECTIONS ------
#================================
-logger.info('Starting LVS MOSFET CONNECTIONS')
-connect(psd_dw, contact)
-
+# %include mos_connection.lvs
#================================
# ------ BJT CONNECTIONS --------
#================================
-logger.info('Starting LVS BJT CONNECTIONS')
-# ========================================
-# ---- VNPN (isolated collector) (5V) ----
-# ========================================
-
-# vnpn_5x5 nodes connections
-connect(npn_05p00x05p00_e, contact)
-connect(npn_05p00x05p00_b, contact)
-connect(npn_05p00x05p00_c, contact)
-
-# vnpn_0p54x16 nodes connections
-connect(npn_00p54x16p00_e, contact)
-connect(npn_00p54x16p00_b, contact)
-connect(npn_00p54x16p00_c, contact)
-
-# vnpn_0p54x8 nodes connections
-connect(npn_00p54x08p00_e, contact)
-connect(npn_00p54x08p00_b, contact)
-connect(npn_00p54x08p00_c, contact)
-
-# vnpn_0p54x2 nodes connections
-connect(npn_00p54x02p00_e, contact)
-connect(npn_00p54x02p00_b, contact)
-connect(npn_00p54x02p00_c, contact)
-
-# ===========================================
-# ---- VNPN (isolated collector) (3.3V) ----
-# ===========================================
-
-# vnpn_5x5_3p3 nodes connections
-connect(npn_05p00x05p00_e_3p3, contact)
-connect(npn_05p00x05p00_b_3p3, contact)
-connect(npn_05p00x05p00_c_3p3, contact)
-
-# vnpn_0p54x16_3p3 nodes connections
-connect(npn_00p54x16p00_e_3p3, contact)
-connect(npn_00p54x16p00_b_3p3, contact)
-connect(npn_00p54x16p00_c_3p3, contact)
-
-# vnpn_0p54x8_3p3 nodes connections
-connect(npn_00p54x08p00_e_3p3, contact)
-connect(npn_00p54x08p00_b_3p3, contact)
-connect(npn_00p54x08p00_c_3p3, contact)
-
-# vnpn_0p54x2_3p3 nodes connections
-connect(npn_00p54x02p00_e_3p3, contact)
-connect(npn_00p54x02p00_b_3p3, contact)
-connect(npn_00p54x02p00_c_3p3, contact)
-
-
-# ========================================
-# ---- VPNP (Psub as collector) (6V) ----
-# ========================================
-
-# vpnp_6p0_10x10 nodes connections
-connect(pnp_10p00x10p00_e, contact)
-connect(pnp_10p00x10p00_b, contact)
-connect(pnp_10p00x10p00_c, contact)
-
-# vpnp_6p0_5x5 nodes connections
-connect(pnp_05p00x05p00_e, contact)
-connect(pnp_05p00x05p00_b, contact)
-connect(pnp_05p00x05p00_c, contact)
-
-# vpnp_6p0_0p42x20 nodes connections
-connect(pnp_00p42x20p00_e, contact)
-connect(pnp_00p42x20p00_b, contact)
-connect(pnp_00p42x20p00_c, contact)
-
-# vpnp_6p0_0p42x10 nodes connections
-connect(pnp_00p42x10p00_e, contact)
-connect(pnp_00p42x10p00_b, contact)
-connect(pnp_00p42x10p00_c, contact)
-
-# vpnp_6p0_0p42x5 nodes connections
-connect(pnp_00p42x05p00_e, contact)
-connect(pnp_00p42x05p00_b, contact)
-connect(pnp_00p42x05p00_c, contact)
-
+# %include bjt_connection.lvs
#================================
# ----- DIODE CONNECTIONS -------
#================================
-logger.info('Starting LVS DIODE CONNECTIONS')
+# %include diode_connection.lvs
#================================
-# ---- LV DIODE DERIVATIONS ----
+# ---- Varactor CONNECTIONS -----
#================================
-# diode_np_1p8
-connect(diode_np_1p8_terminal_n, contact)
-
-# diode_np_1p8_dw
-connect(diode_np_1p8_dw_terminal_n, contact)
-
-# diode_pn_1p8
-connect(diode_pn_1p8_terminal_p, contact)
-
-# diode_pn_1p8_dw
-connect(diode_pn_1p8_dw_terminal_p, contact)
-
-#================================
-# ---- MV DIODE DERIVATIONS ----
-#================================
-
-# diode_np_3p3
-connect(diode_np_3p3_terminal_n, contact)
-
-# diode_pn_3p3
-connect(diode_pn_3p3_terminal_p, contact)
-
-# diode_np_3p3_dw
-connect(diode_np_3p3_dw_terminal_n, contact)
-
-# diode_pn_3p3_dw
-connect(diode_pn_3p3_dw_terminal_p, contact)
-
-# diode_np_6p0
-connect(diode_np_6p0_terminal_n, contact)
-
-# diode_pn_6p0
-connect(diode_pn_6p0_terminal_p, contact)
-
-# diode_np_6p0_dw
-connect(diode_np_6p0_dw_terminal_n, contact)
-
-# diode_pn_6p0_dw
-connect(diode_pn_6p0_dw_terminal_p, contact)
-
-# diode_nwp_6p0
-connect(diode_nwp_6p0_terminal_n, nwell)
-connect(diode_nwp_6p0_terminal_p, contact)
-
-# diode_dnwpw
-connect(diode_dnwpw_terminal_p, contact)
-
-# diode_dnwps
-connect(diode_dnwps_terminal_p, contact)
+# %include varactor_connection.lvs
+#==================================
+# ------ MIMCAP CONNECTIONS -------
+#==================================
-#================================
-# ---- RESISTOR CONNECTIONS -----
-#================================
-
-logger.info('Starting LVS RESISTOR CONNECTIONS')
-
-connect(nplus_cont, contact)
-connect(pplus_cont, contact)
-connect(pplus_dw_cont, contact)
\ No newline at end of file
+# %include mimcap_connection.lvs
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/diode_connection.lvs b/ULL/klayout/lvs/rule_decks/diode_connection.lvs
new file mode 100644
index 0000000..a8c8769
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/diode_connection.lvs
@@ -0,0 +1,75 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- DIODE CONNECTIONS -------
+#================================
+
+logger.info('Starting LVS DIODE CONNECTIONS')
+
+#================================
+# ---- LV DIODE DERIVATIONS ----
+#================================
+
+# diode_np_1p8
+connect(diode_np_1p8_terminal_n, contact)
+
+# diode_np_1p8_dw
+connect(diode_np_1p8_dw_terminal_n, contact)
+
+# diode_pn_1p8
+connect(diode_pn_1p8_terminal_p, contact)
+
+# diode_pn_1p8_dw
+connect(diode_pn_1p8_dw_terminal_p, contact)
+
+#================================
+# ---- MV DIODE DERIVATIONS ----
+#================================
+
+# diode_np_3p3
+connect(diode_np_3p3_terminal_n, contact)
+
+# diode_pn_3p3
+connect(diode_pn_3p3_terminal_p, contact)
+
+# diode_np_3p3_dw
+connect(diode_np_3p3_dw_terminal_n, contact)
+
+# diode_pn_3p3_dw
+connect(diode_pn_3p3_dw_terminal_p, contact)
+
+# diode_np_6p0
+connect(diode_np_6p0_terminal_n, contact)
+
+# diode_pn_6p0
+connect(diode_pn_6p0_terminal_p, contact)
+
+# diode_np_6p0_dw
+connect(diode_np_6p0_dw_terminal_n, contact)
+
+# diode_pn_6p0_dw
+connect(diode_pn_6p0_dw_terminal_p, contact)
+
+# diode_nwp_6p0
+connect(diode_nwp_6p0_terminal_n, nwell)
+connect(diode_nwp_6p0_terminal_p, contact)
+
+# diode_dnwpw
+connect(diode_dnwpw_terminal_p, contact)
+
+# diode_dnwps
+connect(diode_dnwps_terminal_p, contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/diode_derivations.lvs b/ULL/klayout/lvs/rule_decks/diode_derivations.lvs
index c1a5139..7203bff 100644
--- a/ULL/klayout/lvs/rule_decks/diode_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/diode_derivations.lvs
@@ -54,63 +54,51 @@
#================================
# diode_np_3p3 (Model for 3.3V N+/Pwell diode outside DNwell)
-diode_np_3p3_terminal_n = ncomp.outside(dnwell).outside(nwell).not(v5_xtor).and(dualgate).interacting(diode_mk).not(dv2)
+diode_np_3p3_terminal_n = ncomp.outside(dnwell).outside(nwell).not(v5_xtor).inside(dualgate).interacting(diode_mk).not(dv2)
.not(lvs_bjt).not(drc_bjt).not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse)
.not_interacting(cap_mk).not(nat).outside(fhres).not(fusewindow_d)
.not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
# diode_pn_3p3 (Model for 3.3V P+/Nwell diode outside DNwell)
-diode_pn_3p3_terminal_p = pcomp.outside(dnwell).inside(nwell).not(v5_xtor).and(dualgate).interacting(diode_mk).not(dv2)
+diode_pn_3p3_terminal_p = pcomp.outside(dnwell).inside(nwell).not(v5_xtor).inside(dualgate).interacting(diode_mk).not(dv2)
.not(lvs_bjt).not(drc_bjt).not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse)
.not_interacting(cap_mk).not(nat).outside(fhres).not(fusewindow_d)
.not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
# diode_np_3p3_dw (Model for 3.3V N+/Pwell diode inside DNwell)
-diode_np_3p3_dw_terminal_n = ncomp.inside(dnwell).outside(nwell).not(v5_xtor).and(dualgate).interacting(diode_mk).not(dv2)
+diode_np_3p3_dw_terminal_n = ncomp.inside(dnwell).outside(nwell).not(v5_xtor).inside(dualgate).interacting(diode_mk).not(dv2)
.not(lvs_bjt).not(drc_bjt).not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse)
.not_interacting(cap_mk).not(nat).outside(fhres).not(fusewindow_d)
.not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
# diode_pn_3p3_dw (Model for 3.3V P+/Nwell diode inside DNwell)
-diode_pn_3p3_dw_terminal_p = pcomp.inside(dnwell).inside(nwell).not(v5_xtor).and(dualgate).interacting(diode_mk).not(dv2)
+diode_pn_3p3_dw_terminal_p = pcomp.inside(dnwell).inside(nwell).not(v5_xtor).inside(dualgate).interacting(diode_mk).not(dv2)
.not(lvs_bjt).not(drc_bjt).not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse)
.not_interacting(cap_mk).not(nat).outside(fhres).not(fusewindow_d)
.not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
# diode_np_6p0 (Model for 6V N+/Pwell diode outside Dnwell)
-diode_np_6p0_terminal_n = ncomp.outside(dnwell).outside(nwell).not(v5_xtor).not(dualgate).interacting(diode_mk).and(dv2)
+diode_np_6p0_terminal_n = ncomp.outside(dnwell).outside(nwell).not(v5_xtor).not(dualgate).interacting(diode_mk).inside(dv2)
.not(lvs_bjt).not(drc_bjt).not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse)
.not_interacting(cap_mk).not(nat).outside(fhres).not(fusewindow_d)
.not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
# diode_pn_6p0 (Model for 6V P+/Nwell diode outside DNwell)
-diode_pn_6p0_terminal_p = pcomp.outside(dnwell).inside(nwell).not(v5_xtor).not(dualgate).interacting(diode_mk).and(dv2)
+diode_pn_6p0_terminal_p = pcomp.outside(dnwell).inside(nwell).not(v5_xtor).not(dualgate).interacting(diode_mk).inside(dv2)
.not(lvs_bjt).not(drc_bjt).not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse)
.not_interacting(cap_mk).not(nat).outside(fhres).not(fusewindow_d)
.not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
# diode_np_6p0_dw (Model for 6V N+/Pwell diode inside DNwell)
-diode_np_6p0_dw_terminal_n = ncomp.inside(dnwell).outside(nwell).not(v5_xtor).not(dualgate).interacting(diode_mk).and(dv2)
+diode_np_6p0_dw_terminal_n = ncomp.inside(dnwell).outside(nwell).not(v5_xtor).not(dualgate).interacting(diode_mk).inside(dv2)
.not(lvs_bjt).not(drc_bjt).not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse)
.not_interacting(cap_mk).not(nat).outside(fhres).not(fusewindow_d)
.not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
# diode_pn_6p0_dw (Model for 6V P+/Nwell diode inside DNwell)
-diode_pn_6p0_dw_terminal_p = pcomp.inside(dnwell).inside(nwell).not(v5_xtor).not(dualgate).interacting(diode_mk).and(dv2)
+diode_pn_6p0_dw_terminal_p = pcomp.inside(dnwell).inside(nwell).not(v5_xtor).not(dualgate).interacting(diode_mk).inside(dv2)
.not(lvs_bjt).not(drc_bjt).not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse)
.not_interacting(cap_mk).not(nat).outside(fhres).not(fusewindow_d)
.not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
-# diode_nwp_6p0 (Model for 6V Nwell/Psub diode)
-diode_nwp_6p0_terminal_p = pcomp.outside(lvpwell).outside(dnwell).interacting(diode_mk).not(esd).not(polyfuse)
- .not(fusewindow_d).not_interacting(lvs_bjt).not_interacting(drc_bjt).not(lvs_rf)
-diode_nwp_6p0_terminal_n = nwell_con.and(diode_nwp_6p0_terminal_p)
-
-# diode_dnwpw (Model for pwell/dnwell diode)
-diode_dnwpw_terminal_p = lvpwell.interacting(dnwell).interacting(diode_mk).not(esd).not(polyfuse)
- .not(fusewindow_d).not_interacting(lvs_bjt).not_interacting(drc_bjt).not(lvs_rf)
-
-# diode_dnwps (Model for DNwell/Psub diode)
-diode_dnwps_terminal_p = pcomp.outside(lvpwell).and(dnwell).interacting(diode_mk).not(esd).not(polyfuse)
- .not(fusewindow_d).not_interacting(lvs_bjt).not_interacting(drc_bjt).not(lvs_rf)
diff --git a/ULL/klayout/lvs/rule_decks/diode_extraction.lvs b/ULL/klayout/lvs/rule_decks/diode_extraction.lvs
index 44e14d0..3b131a2 100644
--- a/ULL/klayout/lvs/rule_decks/diode_extraction.lvs
+++ b/ULL/klayout/lvs/rule_decks/diode_extraction.lvs
@@ -76,15 +76,3 @@
# diode_pn_6p0_dw (Model for 6V P+/Nwell diode inside DNwell)
logger.info('Extracting diode_pn_6p0_dw')
extract_devices(diode('diode_pn_6p0_dw'), { 'N' => nwell_con, 'P' => diode_pn_6p0_dw_terminal_p })
-
-# diode_nwp_6p0 (Model for 6V Nwell/Psub diode)
-logger.info('Extracting diode_nwp_6p0')
-extract_devices(diode('diode_nwp_6p0'), { 'N' => diode_nwp_6p0_terminal_n, 'P' => diode_nwp_6p0_terminal_p })
-
-# diode_dnwpw (Model for pwell/dnwell diode)
-logger.info('Extracting diode_dnwpw diode')
-extract_devices(diode('diode_dnwpw'), { 'N' => dnwell, 'P' => diode_dnwpw_terminal_p })
-
-# diode_dnwps (Model for DNwell/Psub diode)
-logger.info('Extracting diode_dnwps')
-extract_devices(diode('diode_dnwps'), { 'N' => dnwell, 'P' => diode_dnwps_terminal_p })
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/general_derivations.lvs b/ULL/klayout/lvs/rule_decks/general_derivations.lvs
index 8e1dabe..d365520 100644
--- a/ULL/klayout/lvs/rule_decks/general_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/general_derivations.lvs
@@ -41,3 +41,22 @@
nwell_con = nwell.not(res_mk)
lvpwell_con = lvpwell.not(res_mk)
poly2_con = poly2.not(res_mk)
+
+
+# Splitting vias into cap-vias(connected to fusetop), ncap-vias(connected to metals)
+if METAL_LEVEL != '2LM'
+ via2_ncap = via2.not(fusetop)
+ via2_cap = via2.and(fusetop)
+ if METAL_LEVEL != '3LM'
+ via3_ncap = via3.not(fusetop)
+ via3_cap = via3.and(fusetop)
+ if METAL_LEVEL != '4LM'
+ via4_ncap = via4.not(fusetop)
+ via4_cap = via4.and(fusetop)
+ if METAL_LEVEL != '5LM'
+ via5_ncap = via5.not(fusetop)
+ via5_cap = via5.and(fusetop)
+ end
+ end
+ end
+ end
diff --git a/ULL/klayout/lvs/rule_decks/mimcap_connection.lvs b/ULL/klayout/lvs/rule_decks/mimcap_connection.lvs
new file mode 100644
index 0000000..886bdc9
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/mimcap_connection.lvs
@@ -0,0 +1,31 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MIMCAP CONNECTIONS -------
+#==================================
+
+logger.info('Starting LVS MIMCAP CONNECTIONS')
+
+case MIM_OPTION
+when 'A'
+ connect(metal2, mim_virtual)
+ connect(fuse_cap, via2)
+
+when 'B'
+ connect(topmin1_metal, mimtm_virtual)
+ connect(fuse_cap, top_via)
+end
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/mimcap_derivations.lvs b/ULL/klayout/lvs/rule_decks/mimcap_derivations.lvs
new file mode 100644
index 0000000..a5e7570
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/mimcap_derivations.lvs
@@ -0,0 +1,37 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MIMCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting MIMCAP DERIVATIONS')
+
+# mim option A
+mim_virtual = fusetop.sized(1.06.um).and(metal2.interacting(fusetop)).not(lvs_rf)
+metal2_ncap = metal2.not(mim_virtual)
+fuse_cap = fusetop.interacting(cap_mk).interacting(mim_l_mk).not(lvs_rf)
+
+# mim_option B
+mimtm_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop)).not(lvs_rf)
+
+if METAL_LEVEL != '2LM'
+ metal3_ncap = metal3.not(mimtm_virtual)
+ if METAL_LEVEL != '3LM'
+ metal4_ncap = metal4.not(mimtm_virtual)
+ metal5_ncap = metal5.not(mimtm_virtual) if METAL_LEVEL != '4LM'
+ end
+end
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/mimcap_extraction.lvs b/ULL/klayout/lvs/rule_decks/mimcap_extraction.lvs
new file mode 100644
index 0000000..54906ab
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/mimcap_extraction.lvs
@@ -0,0 +1,153 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- MIMCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting MIMCAP EXTRACTION')
+
+case MIM_OPTION
+when 'A'
+
+ case MIM_CAP
+ when '0.85'
+ # mim_0p85fF capacitor
+ logger.info('Extracting mim_0p85fF device')
+ extract_devices(capacitor('mim_0p85fF_m2m3_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('mim_0p85fF_m2m3_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # mim_1p0fF capacitor
+ logger.info('Extracting mim_1p0fF device')
+ extract_devices(capacitor('mim_1p0fF_m2m3_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p0fF_m2m3_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # mim_1p5fF capacitor
+ logger.info('Extracting mim_1p5fF device')
+ extract_devices(capacitor('mim_1p5fF_m2m3_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p5fF_m2m3_noshield', 'C', relative: 0.25)
+
+ when '2'
+ # mim_2p0fF capacitor
+ logger.info('Extracting mim_2p0fF device')
+ extract_devices(capacitor('mim_2p0fF_m2m3_noshield', 2.0e-15, MIMCap),
+ { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('mim_2p0fF_m2m3_noshield', 'C', relative: 0.25)
+
+ end
+
+when 'B'
+ case METAL_LEVEL
+ when '6LM'
+
+ case MIM_CAP
+ when '0.85'
+ # mim_0p85fF_tm capacitor
+ logger.info('Extracting mim_0p85fF_tm device')
+ extract_devices(capacitor('mim_0p85fF_tm_m5m6_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_0p85fF_tm_m5m6_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # mim_1p0fF_tm capacitor
+ logger.info('Extracting mim_1p0fF_tm device')
+ extract_devices(capacitor('mim_1p0fF_tm_m5m6_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p0fF_tm_m5m6_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # mim_1p5fF_tm capacitor
+ logger.info('Extracting mim_1p5fF_tm device')
+ extract_devices(capacitor('mim_1p5fF_tm_m5m6_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p5fF_tm_m5m6_noshield', 'C', relative: 0.25)
+
+ when '2'
+ # mim_2p0fF_tm capacitor
+ logger.info('Extracting mim_2p0fF_tm device')
+ extract_devices(capacitor('mim_2p0fF_tm_m5m6_noshield', 2.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_2p0fF_tm_m5m6_noshield', 'C', relative: 0.25)
+ end
+
+ when '5LM'
+ case MIM_CAP
+ when '0.85'
+ # mim_0p85fF_tm capacitor
+ logger.info('Extracting mim_0p85fF_tm device')
+ extract_devices(capacitor('mim_0p85fF_tm_m4m5_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_0p85fF_tm_m4m5_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # mim_1p0fF_tm capacitor
+ logger.info('Extracting mim_1p0fF_tm device')
+ extract_devices(capacitor('mim_1p0fF_tm_m4m5_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p0fF_tm_m4m5_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # mim_1p5fF_tm capacitor
+ logger.info('Extracting mim_1p5fF_tm device')
+ extract_devices(capacitor('mim_1p5fF_tm_m4m5_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p5fF_tm_m4m5_noshield', 'C', relative: 0.25)
+
+ when '2'
+ # mim_2p0fF_tm capacitor
+ logger.info('Extracting mim_2p0fF_tm device')
+ extract_devices(capacitor('mim_2p0fF_tm_m4m5_noshield', 2.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_2p0fF_tm_m4m5_noshield', 'C', relative: 0.25)
+ end
+
+ when '4LM'
+ case MIM_CAP
+ when '0.85'
+ # mim_0p85fF_tm capacitor
+ logger.info('Extracting mim_0p85fF_tm device')
+ extract_devices(capacitor('mim_0p85fF_tm_m3m4_noshield', 0.85e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_0p85fF_tm_m3m4_noshield', 'C', relative: 0.25)
+
+ when '1'
+ # mim_1p0fF_tm capacitor
+ logger.info('Extracting mim_1p0fF_tm device')
+ extract_devices(capacitor('mim_1p0fF_tm_m3m4_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p0fF_tm_m3m4_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # mim_1p5fF_tm capacitor
+ logger.info('Extracting mim_1p5fF_tm device')
+ extract_devices(capacitor('mim_1p5fF_tm_m3m4_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_1p5fF_tm_m3m4_noshield', 'C', relative: 0.25)
+
+ when '2'
+ # mim_2p0fF_tm capacitor
+ logger.info('Extracting mim_2p0fF_tm device')
+ extract_devices(capacitor('mim_2p0fF_tm_m3m4_noshield', 2.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('mim_2p0fF_tm_m3m4_noshield', 'C', relative: 0.25)
+ end
+ end
+end
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/mos_connection.lvs b/ULL/klayout/lvs/rule_decks/mos_connection.lvs
new file mode 100644
index 0000000..862cda2
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/mos_connection.lvs
@@ -0,0 +1,22 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- MOSFET CONNECTIONS ------
+#================================
+logger.info('Starting LVS MOSFET CONNECTIONS')
+
+connect(psd_dw, contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs b/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs
new file mode 100644
index 0000000..8f59869
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs
@@ -0,0 +1,93 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MOSCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting MOSCAP DERIVATIONS')
+
+# nmoscap_1p8 capacitor
+nmos_gate_1p8 = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).not(nwell).not(sab).not(esd)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# nmoscap_1p8_dw capacitor
+nmos_gate_1p8_dw = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).not(nwell).not(sab).not(esd)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# pmoscap_1p8 capacitor
+pmos_gate_1p8 = pgate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).not(sab).not(esd)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# pmoscap_1p8_dw capacitor
+pmos_gate_1p8_dw = pgate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).not(sab).not(esd)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# nmoscap_6p0 capacitor
+nmoscap_6p0_g = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).not(nwell).and(dv2).not(esd)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+
+# nmoscap_6p0_dw capacitor
+nmoscap_6p0_dw_g = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).not(nwell).and(dv2).not(esd)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+
+# pmoscap_6p0 capacitor
+pmoscap_6p0_g = pgate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).and(dv2).not(esd)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+
+# pmoscap_6p0_dw capacitor
+pmoscap_6p0_dw_g = pgate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).and(dv2).not(esd)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+
+# nmoscap_1p8_nwell capacitor
+nmoscap_1p8_nwell_g = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).not(sab)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# nmoscap_1p8_dnwell capacitor
+nmoscap_1p8_dnwell_g = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).and(nwell).not(sab)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(dv2).not(resistor)
+
+# nmoscap_6p0_nwell capacitor
+nmoscap_6p0_nwell_g = ngate.not(dualgate).outside(dnwell).interacting(mos_cap_mk).and(nwell).and(dv2)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
+
+# nmoscap_6p0_dnwell capacitor
+nmoscap_6p0_dnwell_g = ngate.not(dualgate).inside(dnwell).interacting(mos_cap_mk).and(nwell).and(dv2)
+ .not(polyfuse).not_interacting(cap_mk).not_interacting(diode_mk).not(nat)
+ .not(v5_xtor).not(drc_bjt).not(lvs_bjt).not(fhres).not(fusewindow_d).not(esd)
+ .not(piscap).not_interacting(mim_l_mk).not(fusetop).not(sab).not(resistor)
diff --git a/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs b/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs
new file mode 100644
index 0000000..99c0318
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs
@@ -0,0 +1,84 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- MOSCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting MOSCAP EXTRACTION')
+
+# nmoscap_1p8
+logger.info('Extracting nmoscap_1p8 device')
+extract_devices(capacitor('nmoscap_1p8', 4.4e-15, MosCap),
+ { 'P1' => nmos_gate_1p8, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+# nmoscap_1p8_dw
+logger.info('Extracting nmoscap_1p8_dw device')
+extract_devices(capacitor('nmoscap_1p8_dw', 4.4e-15, MosCap),
+ { 'P1' => nmos_gate_1p8_dw, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+# pmoscap_1p8
+logger.info('Extracting pmoscap_1p8 device')
+extract_devices(capacitor('pmoscap_1p8', 4.4e-15, MosCap),
+ { 'P1' => pmos_gate_1p8, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => psd })
+
+# pmoscap_1p8_dw
+logger.info('Extracting pmoscap_1p8_dw device')
+extract_devices(capacitor('pmoscap_1p8_dw', 4.4e-15, MosCap),
+ { 'P1' => pmos_gate_1p8_dw, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => psd_dw })
+
+# nmoscap_6p0
+logger.info('Extracting nmoscap_6p0 device')
+extract_devices(capacitor('nmoscap_6p0', 2.3e-15, MosCap),
+ { 'P1' => nmoscap_6p0_g, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+# nmoscap_6p0_dw
+logger.info('Extracting nmoscap_6p0_dw device')
+extract_devices(capacitor('nmoscap_6p0_dw', 2.3e-15, MosCap),
+ { 'P1' => nmoscap_6p0_dw_g, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+# pmoscap_6p0
+logger.info('Extracting pmoscap_6p0 device')
+extract_devices(capacitor('pmoscap_6p0', 2.3e-15, MosCap),
+ { 'P1' => pmoscap_6p0_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => psd })
+
+# pmoscap_6p0_dw
+logger.info('Extracting pmoscap_6p0_dw device')
+extract_devices(capacitor('pmoscap_6p0_dw', 2.3e-15, MosCap),
+ { 'P1' => pmoscap_6p0_dw_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => psd_dw })
+
+
+# nmoscap_1p8_nwell capacitor
+logger.info('Extracting nmoscap_1p8_nwell device')
+extract_devices(capacitor('nmoscap_1p8_nwell', 4.4e-15, MosCap),
+ { 'P1' => nmoscap_1p8_nwell_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+# nmoscap_1p8_dnwell capacitor
+logger.info('Extracting nmoscap_1p8_dnwell device')
+extract_devices(capacitor('nmoscap_1p8_dnwell', 4.4e-15, MosCap),
+ { 'P1' => nmoscap_1p8_dnwell_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
+
+# nmoscap_6p0_nwell capacitor
+logger.info('Extracting nmoscap_6p0_nwell device')
+extract_devices(capacitor('nmoscap_6p0_nwell', 2.3e-15, MosCap),
+ { 'P1' => nmoscap_6p0_nwell_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+# nmoscap_6p0_dnwell capacitor
+logger.info('Extracting nmoscap_6p0_dnwell device')
+extract_devices(capacitor('nmoscap_6p0_dnwell', 2.3e-15, MosCap),
+ { 'P1' => nmoscap_6p0_dnwell_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
+
+
diff --git a/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs b/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
new file mode 100644
index 0000000..1ace25a
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
@@ -0,0 +1,41 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ PISCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting PISCAP DERIVATIONS')
+
+piscap_exclude_layers = mos_cap_mk.or(sab).or(esd).or(polyfuse).or(cap_mk).or(diode_mk).or(nat)
+ .or(v5_xtor).or(drc_bjt).or(lvs_bjt).or(fhres)
+ .or(fusewindow_d).or(lvs_rf).or(fusetop).or(resistor)
+
+# pis_1p8 (1.8V PIS capacitor (outside DNWELL))
+pis_1p8_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).not(dnwell)
+ .not(dualgate).not(dv2).not(piscap_exclude_layers)
+
+# pis_1p8_dw (1.8V PIS capacitor (inside DNWEL)
+pis_1p8_dw_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).inside(dnwell)
+ .not(dualgate).not(dv2).not(piscap_exclude_layers)
+
+# pis_6p0 (6V PIS capacitor (outside DNWELL))
+pis_6p0_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).not(dnwell)
+ .and(dv2).not(piscap_exclude_layers)
+
+# pis_6p0_dw (6V PIS capacitor (inside DNWEL)
+pis_6p0_dw_gate = ngate.and(piscap).interacting(mim_l_mk).inside(nwell).inside(dnwell)
+ .and(dv2).not(piscap_exclude_layers)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs b/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
new file mode 100644
index 0000000..d24e852
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
@@ -0,0 +1,41 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- PISCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting PISCAP EXTRACTION')
+
+# pis_1p8 (1.8V PIS capacitor (outside DNWELL))
+logger.info('Extracting pis_1p8 device')
+extract_devices(capacitor('piscap_1p8', 4.4e-15, PisCap),
+ { 'P1' => pis_1p8_gate, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+# pis_1p8_dw (1.8V PIS capacitor (inside DNWEL)
+logger.info('Extracting pis_1p8_dw device')
+extract_devices(capacitor('piscap_1p8_dw', 4.4e-15, PisCap),
+ { 'P1' => pis_1p8_dw_gate, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
+
+# pis_6p0 (6V PIS capacitor (outside DNWELL))
+logger.info('Extracting pis_6p0 device')
+extract_devices(capacitor('piscap_6p0', 4.4e-15, PisCap),
+ { 'P1' => pis_6p0_gate, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+# pis_6p0_dw (6V PIS capacitor (inside DNWEL)
+logger.info('Extracting pis_6p0_dw device')
+extract_devices(capacitor('piscap_6p0_dw', 4.4e-15, PisCap),
+ { 'P1' => pis_6p0_dw_gate, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/res_connection.lvs b/ULL/klayout/lvs/rule_decks/res_connection.lvs
new file mode 100644
index 0000000..8f716d5
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/res_connection.lvs
@@ -0,0 +1,25 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- RESISTOR CONNECTIONS -----
+#================================
+
+logger.info('Starting LVS RESISTOR CONNECTIONS')
+
+connect(nplus_cont, contact)
+connect(pplus_cont, contact)
+connect(pplus_dw_cont, contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/res_derivations.lvs b/ULL/klayout/lvs/rule_decks/res_derivations.lvs
new file mode 100644
index 0000000..d4a71f7
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/res_derivations.lvs
@@ -0,0 +1,185 @@
+
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- RESISTOR DERIVATIONS -----
+#================================
+
+logger.info('Starting RESISTOR DERIVATIONS')
+
+#====================
+# ---- Diff RES ----
+#====================
+
+# general diffusion contacts derivations
+nplus_cont = ncomp.outside(nwell).not_interacting(ngate).interacting(res_mk).not(res_mk).not_interacting(diode_mk)
+ .not(esd).not(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not(pplus)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+pplus_cont = pcomp.inside(nwell).not_interacting(pgate).interacting(res_mk).not(res_mk).not_interacting(diode_mk)
+ .not(esd).not(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+pplus_dw_cont = pcomp.not(lvpwell).and(dnwell).not_interacting(pgate).interacting(res_mk).not(res_mk)
+ .not(esd).not(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+
+# nplus_u (3-terminal unsalicided n+ diffusion resistor (outside DNWELL))
+nplus_u_layer = ncomp.and(lvpwell).and(sab).and(res_mk).not(dnwell).not(nat).interacting(nplus_cont)
+
+# nplus_u_dw (3-terminal unsalicided n+ diffusion resistor (inside DNWELL))
+nplus_u_dw_layer = ncomp.and(lvpwell).and(sab).and(res_mk).and(dnwell).not(nat).interacting(nplus_cont)
+
+# pplus_u (3-terminal unsalicided P+ diffusion resistor (outside DNWELL))
+pplus_u_layer = pcomp.and(nwell).and(sab).and(res_mk).not(dnwell).outside(lvpwell).not(nat).interacting(pplus_cont)
+
+# pplus_u_dw (3-terminal unsalicided P+ diffusion resistor (inside DNWELL))
+pplus_u_dw_layer = pcomp.and(sab).and(res_mk).and(dnwell).interacting(pplus_dw_cont)
+
+# nplus_s (3-terminal salicided N+ diffusion resistor (outside DNWELL))
+nplus_s_layer = ncomp.and(lvpwell).and(res_mk).not_interacting(sab).not(dnwell).interacting(nplus_cont)
+
+# nplus_s_dw (3-terminal salicided N+ diffusion resistor (inside DNWELL))
+nplus_s_dw_layer = ncomp.and(lvpwell).and(res_mk).and(dnwell).not_interacting(sab).interacting(nplus_cont)
+
+# pplus_s (3-terminal salicided P+ diffusion resistor (outside DNWELL))
+pplus_s_layer = pcomp.and(nwell).and(res_mk).not_interacting(sab).not(dnwell).interacting(nplus_cont)
+
+# pplus_s_dw (3-terminal salicided P+ diffusion resistor (inside DNWELL))
+pplus_s_dw_layer = pcomp.not_interacting(sab).and(res_mk).and(dnwell).not_interacting(sab)
+
+
+#====================
+# ---- PWELL RES ----
+#====================
+
+# pwell (3-terminal low voltage pwell resistor for 1.8V/6V process (inside DNWELL only))
+pwell_res = lvpwell.and(res_mk).and(dnwell).not_covering(comp).not(poly2).outside(lvs_rf)
+ .not(esd).not_interacting(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+
+#====================
+# ---- POLY RES ----
+#====================
+
+# npolyf_u (3-terminal unsalicided n+ poly resistor (outside DNWELL))
+npolyf_u_layer = nplus.and(poly2).and(sab).and(res_mk).not(dnwell).outside(comp)
+ .not(esd).not_interacting(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+# npolyf_u_dw (3-terminal unsalicided n+ poly resistor (inside DNWELL))
+npolyf_u_dw_layer = nplus.and(poly2).and(sab).and(res_mk).and(dnwell).outside(comp)
+ .not(esd).not_interacting(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+# ppolyf_u (3-terminal unsalicided p+ poly resistor (outside DNWELL))
+ppolyf_u_layer = pplus.and(poly2).and(sab).and(res_mk).not(dnwell).outside(comp)
+ .not(esd).not_interacting(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+# ppolyf_u_dw (3-terminal unsalicided p+ poly resistor (inside DNWELL))
+ppolyf_u_dw_layer = pplus.and(poly2).and(sab).and(res_mk).and(dnwell).outside(comp)
+ .not(esd).not_interacting(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+# npolyf_s (3-terminal salicided n+ poly resistor (outside DNWELL))
+npolyf_s_layer = nplus.and(poly2).not_interacting(sab).and(res_mk).not(dnwell).outside(comp)
+ .not(esd).not_interacting(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+# npolyf_s_dw (3-terminal salicided n+ poly resistor (inside DNWELL))
+npolyf_s_dw_layer = nplus.and(poly2).not_interacting(sab).and(res_mk).and(dnwell).outside(comp)
+ .not(esd).not_interacting(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+# ppolyf_s (3-terminal salicided p+ poly resistor (outside DNWELL))
+ppolyf_s_layer = pplus.and(poly2).not_interacting(sab).and(res_mk).not(dnwell).outside(comp)
+ .not(esd).not_interacting(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+# ppolyf_s_dw (3-terminal salicided p+ poly resistor (inside DNWELL))
+ppolyf_s_dw_layer = pplus.and(poly2).not_interacting(sab).and(res_mk).and(dnwell).outside(comp)
+ .not(esd).not_interacting(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+
+#========================
+# ---- POLY High RES ----
+#========================
+
+# general derivations for High RES POLY
+poly_hr_layer = pplus.and(poly2).and(sab).and(res_mk).not(dnwell).outside(comp)
+ .not(esd).and(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+poly_hr_dw_layer = pplus.and(poly2).and(sab).and(res_mk).and(dnwell).outside(comp)
+ .not(esd).and(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(fhres).not(fusetop).not_interacting(diode_mk)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+case POLY_RES
+when '1k'
+
+ # ppolyf_u_1k (3-terminal 1k high-Rs p+ poly resistor on field oxide (outside DNWELL))
+ ppolyf_u_1k_layer = poly_hr_layer
+
+ # ppolyf_u_1k_dw (3-terminal 1k high-Rs p+ poly resistor on field oxide (inside DNWELL))
+ ppolyf_u_1k_dw_layer = poly_hr_dw_layer
+
+when '2k'
+
+ # ppolyf_u_2k (3-terminal 2k high-Rs p+ poly resistor on field oxide (outside DNWELL))
+ ppolyf_u_2k_layer = poly_hr_layer
+
+ # ppolyf_u_2k_dw (3-terminal 2k high-Rs p+ poly resistor on field oxide (inside DNWELL))
+ ppolyf_u_2k_dw_layer = poly_hr_dw_layer
+
+end
+
+#=============================
+# ---- POLY Free High RES ----
+#=============================
+
+# ppolyf_u_fhr_16p0_lv (3-terminal free high-Rs p+ poly res. On field oxide (LV/MV area outside DNWELL))
+ppolyf_u_fhr_16p0_lv_layer = pplus.and(poly2).and(sab).and(res_mk).not(dnwell).and(fhres).not_interacting(diode_mk)
+ .not(esd).not(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(comp).not(fusetop)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+# ppolyf_u_fhr_16p0_lv_dw (3-terminal free high-Rs p+ poly res. On field oxide (LV/MV area inside DNWELL))
+ppolyf_u_fhr_16p0_lv_dw_layer = pplus.and(poly2).and(sab).and(res_mk).and(dnwell).and(fhres).not_interacting(diode_mk)
+ .not(esd).not(resistor).not(polyfuse).not_interacting(cap_mk).not(fusewindow_d)
+ .not(polyfuse).not(drc_bjt).not(lvs_bjt).outside(comp).not(fusetop)
+ .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(nat).not(v5_xtor)
+
+
+
diff --git a/ULL/klayout/lvs/rule_decks/res_extraction.lvs b/ULL/klayout/lvs/rule_decks/res_extraction.lvs
new file mode 100644
index 0000000..0dfe9f9
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/res_extraction.lvs
@@ -0,0 +1,164 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- RESISTOR EXTRACTIONS -----
+#================================
+
+logger.info('Starting RESISTOR EXTRACTION')
+
+#====================
+# ---- Diff RES ----
+#====================
+
+# nplus_u (3-terminal unsalicided n+ diffusion resistor (outside DNWELL))
+logger.info('Extracting nplus_u device')
+extract_devices(resistor_with_bulk('nplus_u', 60, BResistor), { 'R' => nplus_u_layer, 'C' => nplus_cont, 'W' => sub })
+
+# nplus_u_dw (3-terminal unsalicided n+ diffusion resistor (inside DNWELL))
+logger.info('Extracting nplus_u_dw device')
+extract_devices(resistor_with_bulk('nplus_u_dw', 60, BResistor),
+ { 'R' => nplus_u_dw_layer, 'C' => nplus_cont, 'W' => lvpwell_con })
+
+# pplus_u (3-terminal unsalicided P+ diffusion resistor (outside DNWELL))
+logger.info('Extracting pplus_u device')
+extract_devices(resistor_with_bulk('pplus_u', 185, BResistor),
+ { 'R' => pplus_u_layer, 'C' => pplus_cont, 'W' => nwell_con })
+
+# pplus_u_dw (3-terminal unsalicided P+ diffusion resistor (inside DNWELL))
+logger.info('Extracting pplus_u_dw device')
+extract_devices(resistor_with_bulk('pplus_u_dw', 185, BResistor),
+ { 'R' => pplus_u_dw_layer, 'C' => pplus_dw_cont, 'W' => dnwell })
+
+# nplus_s (3-terminal salicided N+ diffusion resistor (outside DNWELL))
+logger.info('Extracting nplus_s device')
+extract_devices(resistor_with_bulk('nplus_s', 6.3, BResistor), { 'R' => nplus_s_layer, 'C' => nplus_cont, 'W' => sub })
+
+# nplus_s_dw (3-terminal salicided N+ diffusion resistor (inside DNWELL))
+logger.info('Extracting nplus_s_dw device')
+extract_devices(resistor_with_bulk('nplus_s_dw', 6.3, BResistor),
+ { 'R' => nplus_s_dw_layer, 'C' => nplus_cont, 'W' => lvpwell_con })
+
+# pplus_s (3-terminal salicided P+ diffusion resistor (outside DNWELL))
+logger.info('Extracting pplus_s device')
+extract_devices(resistor_with_bulk('pplus_s', 7, BResistor),
+ { 'R' => pplus_s_layer, 'C' => pplus_cont, 'W' => nwell_con })
+
+# pplus_s_dw (3-terminal salicided P+ diffusion resistor (inside DNWELL))
+logger.info('Extracting pplus_s_dw device')
+extract_devices(resistor_with_bulk('pplus_s_dw', 7, BResistor),
+ { 'R' => pplus_s_dw_layer, 'C' => pplus_dw_cont, 'W' => dnwell })
+
+#====================
+# ---- PWELL RES ----
+#====================
+
+# pwell (3-terminal low voltage pwell resistor for 1.8V/6V process (inside DNWELL only))
+logger.info('Extracting PWELL device')
+extract_devices(resistor_with_bulk('pwell', 1000, BResistor),
+ { 'R' => pwell_res, 'C' => lvpwell_con, 'W' => dnwell })
+
+
+
+#====================
+# ---- POLY RES ----
+#====================
+
+# npolyf_u (3-terminal unsalicided n+ poly resistor (outside DNWELL))
+logger.info('Extracting npolyf_u device')
+extract_devices(resistor_with_bulk('npolyf_u', 310, BResistor),
+ { 'R' => npolyf_u_layer, 'C' => poly2_con, 'W' => sub })
+
+# npolyf_u_dw (3-terminal unsalicided n+ poly resistor (inside DNWELL))
+logger.info('Extracting npolyf_u_dw device')
+extract_devices(resistor_with_bulk('npolyf_u_dw', 310, BResistor),
+ { 'R' => npolyf_u_dw_layer, 'C' => poly2_con, 'W' => dnwell })
+
+# ppolyf_u (3-terminal unsalicided p+ poly resistor (outside DNWELL))
+logger.info('Extracting ppolyf_u device')
+extract_devices(resistor_with_bulk('ppolyf_u', 350, BResistor),
+ { 'R' => ppolyf_u_layer, 'C' => poly2_con, 'W' => sub })
+
+# ppolyf_u_dw (3-terminal unsalicided p+ poly resistor (inside DNWELL))
+logger.info('Extracting ppolyf_u_dw device')
+extract_devices(resistor_with_bulk('ppolyf_u_dw', 350, BResistor),
+ { 'R' => ppolyf_u_dw_layer, 'C' => poly2_con, 'W' => dnwell })
+
+# npolyf_s (3-terminal salicided n+ poly resistor (outside DNWELL))
+logger.info('Extracting npolyf_s device')
+extract_devices(resistor_with_bulk('npolyf_s', 6.8, BResistor),
+ { 'R' => npolyf_s_layer, 'C' => poly2_con, 'W' => sub })
+
+# npolyf_s_dw (3-terminal salicided n+ poly resistor (inside DNWELL))
+logger.info('Extracting npolyf_s_dw device')
+extract_devices(resistor_with_bulk('npolyf_s_dw', 6.8, BResistor),
+ { 'R' => npolyf_s_dw_layer, 'C' => poly2_con, 'W' => dnwell })
+
+# ppolyf_s (3-terminal salicided p+ poly resistor (outside DNWELL))
+logger.info('Extracting ppolyf_s device')
+extract_devices(resistor_with_bulk('ppolyf_s', 7.3, BResistor),
+ { 'R' => ppolyf_s_layer, 'C' => poly2_con, 'W' => sub })
+
+# ppolyf_s_dw (3-terminal salicided p+ poly resistor (inside DNWELL))
+logger.info('Extracting ppolyf_s_dw device')
+extract_devices(resistor_with_bulk('ppolyf_s_dw', 7.3, BResistor),
+ { 'R' => ppolyf_s_dw_layer, 'C' => poly2_con, 'W' => dnwell })
+
+
+#========================
+# ---- POLY High RES ----
+#========================
+
+case POLY_RES
+when '1k'
+
+ # ppolyf_u_1k (3-terminal 1k high-Rs p+ poly resistor on field oxide (outside DNWELL))
+ logger.info('Extracting ppolyf_u_1k device')
+ extract_devices(resistor_with_bulk('ppolyf_u_1k', 1000, BResistor),
+ { 'R' => ppolyf_u_1k_layer, 'C' => poly2_con, 'W' => sub })
+
+ # ppolyf_u_1k_dw (3-terminal 1k high-Rs p+ poly resistor on field oxide (inside DNWELL))
+ logger.info('Extracting ppolyf_u_1k_dw device')
+ extract_devices(resistor_with_bulk('ppolyf_u_1k_dw', 1000, BResistor),
+ { 'R' => ppolyf_u_1k_dw_layer, 'C' => poly2_con, 'W' => dnwell })
+
+
+when '2k'
+
+ # ppolyf_u_2k (3-terminal 2k high-Rs p+ poly resistor on field oxide (outside DNWELL))
+ logger.info('Extracting ppolyf_u_2k device')
+ extract_devices(resistor_with_bulk('ppolyf_u_2k', 2000, BResistor),
+ { 'R' => ppolyf_u_2k_layer, 'C' => poly2_con, 'W' => sub })
+
+ # ppolyf_u_2k_dw (3-terminal 2k high-Rs p+ poly resistor on field oxide (inside DNWELL))
+ logger.info('Extracting ppolyf_u_2k_dw device')
+ extract_devices(resistor_with_bulk('ppolyf_u_2k_dw', 2000, BResistor),
+ { 'R' => ppolyf_u_2k_dw_layer, 'C' => poly2_con, 'W' => dnwell })
+
+end
+#=============================
+# ---- POLY Free High RES ----
+#=============================
+
+# ppolyf_u_fhr_16p0_lv (3-terminal free high-Rs p+ poly res. On field oxide (LV/MV area outside DNWELL))
+logger.info('Extracting ppolyf_u_fhr_16p0_lv device')
+extract_devices(resistor_with_bulk('ppolyf_u_fhr_16p0_lv', 6000, BResistor),
+ { 'R' => ppolyf_u_fhr_16p0_lv_layer, 'C' => poly2_con, 'W' => sub })
+
+# ppolyf_u_fhr_16p0_lv_dw (3-terminal free high-Rs p+ poly res. On field oxide (LV/MV area inside DNWELL))
+logger.info('Extracting ppolyf_u_fhr_16p0_lv_dw device')
+extract_devices(resistor_with_bulk('ppolyf_u_fhr_16p0_lv_dw', 6000, BResistor),
+ { 'R' => ppolyf_u_fhr_16p0_lv_dw_layer, 'C' => poly2_con, 'W' => dnwell })
diff --git a/ULL/klayout/lvs/rule_decks/varactor_connection.lvs b/ULL/klayout/lvs/rule_decks/varactor_connection.lvs
new file mode 100644
index 0000000..68f3f08
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/varactor_connection.lvs
@@ -0,0 +1,24 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor CONNECTIONS -----
+#================================
+
+connect(pn_varactor_1p8_tp ,contact)
+connect(pn_varactor_1p8_dw_tp ,contact)
+connect(pn_varactor_6p0_tp ,contact)
+connect(pn_varactor_6p0_dw_tp ,contact)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs b/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
new file mode 100644
index 0000000..b2ff75a
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
@@ -0,0 +1,51 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor DERIVATIONS ----
+#================================
+
+logger.info('Starting VARACTOR DERIVATIONS')
+
+exclude_layers = v5_xtor.or(fusetop).or(polyfuse).or(dualgate)
+ .or(lvs_bjt).or(drc_bjt).or(sab).or(esd).or(resistor).or(res_mk)
+ .or(cap_mk).or(nat).or(fhres).or(fusewindow_d).or(diode_mk)
+ .or(piscap).or(mos_cap_mk).or(mim_l_mk)
+
+# pn_varactor_1p8
+pn_varactor_1p8_tp = pcomp.outside(dnwell).inside(nwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# pn_varactor_1p8_dw
+pn_varactor_1p8_dw_tp = pcomp.inside(dnwell).inside(nwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# pn_varactor_6p0
+pn_varactor_6p0_tp = pcomp.outside(dnwell).inside(nwell).and(lvs_rf).and(dv2).not(exclude_layers)
+
+# pn_varactor_6p0_dw
+pn_varactor_6p0_dw_tp = pcomp.inside(dnwell).inside(nwell).and(lvs_rf).and(dv2).not(exclude_layers)
+
+
+# mos_varactor_1p8
+mos_varactor_1p8_g = ngate.inside(nwell).outside(dnwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# mos_varactor_1p8_dw
+mos_varactor_1p8_dw_g = ngate.inside(nwell).inside(dnwell).and(lvs_rf).not(dv2).not(exclude_layers)
+
+# mos_varactor_6p0
+mos_varactor_6p0_g = ngate.inside(nwell).outside(dnwell).and(lvs_rf).and(dv2).not(exclude_layers)
+
+# mos_varactor_6p0_dw
+mos_varactor_6p0_dw_g = ngate.inside(nwell).inside(dnwell).and(lvs_rf).and(dv2).not(exclude_layers)
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs b/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
new file mode 100644
index 0000000..1ef4ffe
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
@@ -0,0 +1,69 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ---- Varactor EXTRACTION ----
+#================================
+
+logger.info('Starting VARACTOR EXTRACTION')
+
+# pn_varactor_1p8
+logger.info('Extracting pn_varactor_1p8')
+extract_devices(capacitor('pn_varactor_1p8', 4.4e-15, VarCap),
+ { "P1" => pn_varactor_1p8_tp, "P2" => nwell_con,
+ "tA" => pn_varactor_1p8_tp, "tB" => nwell_con })
+
+# pn_varactor_1p8_dw
+logger.info('Extracting pn_varactor_1p8_dw')
+extract_devices(capacitor('pn_varactor_1p8_dw', 4.4e-15, VarCap),
+ { "P1" => pn_varactor_1p8_dw_tp, "P2" => dnwell,
+ "tA" => pn_varactor_1p8_dw_tp, "tB" => dnwell })
+
+# pn_varactor_6p0
+logger.info('Extracting pn_varactor_6p0')
+extract_devices(capacitor('pn_varactor_6p0', 4.4e-15, VarCap),
+ { "P1" => pn_varactor_6p0_tp, "P2" => nwell_con,
+ "tA" => pn_varactor_6p0_tp, "tB" => nwell_con })
+
+# pn_varactor_6p0_dw
+logger.info('Extracting pn_varactor_6p0_dw')
+extract_devices(capacitor('pn_varactor_6p0_dw', 4.4e-15, VarCap),
+ { "P1" => pn_varactor_6p0_dw_tp, "P2" => dnwell,
+ "tA" => pn_varactor_6p0_dw_tp, "tB" => dnwell })
+
+# mos_varactor_1p8
+logger.info('Extracting mos_varactor_1p8')
+extract_devices(capacitor('mos_varactor_1p8', 4.4e-15, VarCap),
+ { 'P1' => mos_varactor_1p8_g, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# mos_varactor_1p8_dw
+logger.info('Extracting mos_varactor_1p8_dw')
+extract_devices(capacitor('mos_varactor_1p8_dw', 4.4e-15, VarCap),
+ { 'P1' => mos_varactor_1p8_dw_g, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# mos_varactor_6p0
+logger.info('Extracting mos_varactor_6p0')
+extract_devices(capacitor('mos_varactor_6p0', 4.4e-15, VarCap),
+ { 'P1' => mos_varactor_6p0_g, 'P2' => nwell_con,
+ 'tA' => poly2_con, 'tB' => ntap })
+
+# mos_varactor_6p0_dw
+logger.info('Extracting mos_varactor_6p0_dw')
+extract_devices(capacitor('mos_varactor_6p0_dw', 4.4e-15, VarCap),
+ { 'P1' => mos_varactor_6p0_dw_g, 'P2' => dnwell,
+ 'tA' => poly2_con, 'tB' => ntap })
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwps.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwps.gds
new file mode 100644
index 0000000..84df785
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwps.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwpw.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwpw.gds
new file mode 100644
index 0000000..9d5b37f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwpw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8.gds
new file mode 100644
index 0000000..637b381
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8_dw.gds
new file mode 100644
index 0000000..e1aebd0
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3.gds
new file mode 100644
index 0000000..82f3b34
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3_dw.gds
new file mode 100644
index 0000000..aa60938
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_6p0.gds
new file mode 100644
index 0000000..bd82e28
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_6p0_dw.gds
new file mode 100644
index 0000000..73c214a
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nwp_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nwp_6p0.gds
new file mode 100644
index 0000000..eb2312d
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nwp_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_1p8.gds
new file mode 100644
index 0000000..9903014
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_1p8_dw.gds
new file mode 100644
index 0000000..4816efe
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_3p3.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_3p3.gds
new file mode 100644
index 0000000..c873c41
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_3p3.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_3p3_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_3p3_dw.gds
new file mode 100644
index 0000000..f75c075
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_3p3_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_6p0.gds
new file mode 100644
index 0000000..4e47819
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_6p0_dw.gds
new file mode 100644
index 0000000..b406a80
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwps.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwps.cdl
new file mode 100644
index 0000000..4654fe7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwps.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_dnwps
+* View Name: schematic
+* Netlisted on: Nov 24 09:04:18 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_dnwps
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_dnwps I1_0_0_0_0_R0_NEG I1_0_1_0_0_R0_NEG I1_0_2_0_0_R0_NEG
++ I1_1_0_0_0_R0_NEG I1_1_1_0_0_R0_NEG I1_1_2_0_0_R0_NEG I1_2_0_0_0_R0_NEG
++ I1_2_1_0_0_R0_NEG I1_2_2_0_0_R0_NEG I1_default_NEG gnd!
+*.PININFO I1_0_0_0_0_R0_NEG:I I1_0_1_0_0_R0_NEG:I I1_0_2_0_0_R0_NEG:I
+*.PININFO I1_1_0_0_0_R0_NEG:I I1_1_1_0_0_R0_NEG:I I1_1_2_0_0_R0_NEG:I
+*.PININFO I1_2_0_0_0_R0_NEG:I I1_2_1_0_0_R0_NEG:I I1_2_2_0_0_R0_NEG:I
+*.PININFO I1_default_NEG:I gnd!:I
+DI1_2_2_0_0_R0 gnd! I1_2_2_0_0_R0_NEG diode_dnwps AREA=10n PJ=400e-6 m=1
+DI1_2_1_0_0_R0 gnd! I1_2_1_0_0_R0_NEG diode_dnwps AREA=1.034n PJ=220.68e-6 m=1
+DI1_2_0_0_0_R0 gnd! I1_2_0_0_0_R0_NEG diode_dnwps AREA=170p PJ=203.4e-6 m=1
+DI1_1_2_0_0_R0 gnd! I1_1_2_0_0_R0_NEG diode_dnwps AREA=1.034n PJ=220.68e-6 m=1
+DI1_1_1_0_0_R0 gnd! I1_1_1_0_0_R0_NEG diode_dnwps AREA=106.916p PJ=41.36e-6 m=1
+DI1_1_0_0_0_R0 gnd! I1_1_0_0_0_R0_NEG diode_dnwps AREA=17.578p PJ=24.08e-6 m=1
+DI1_0_2_0_0_R0 gnd! I1_0_2_0_0_R0_NEG diode_dnwps AREA=170p PJ=203.4e-6 m=1
+DI1_0_1_0_0_R0 gnd! I1_0_1_0_0_R0_NEG diode_dnwps AREA=17.578p PJ=24.08e-6 m=1
+DI1_0_0_0_0_R0 gnd! I1_0_0_0_0_R0_NEG diode_dnwps AREA=3.1535p PJ=7.11e-6 m=1
+DI1_default gnd! I1_default_NEG diode_dnwps AREA=100e-12 PJ=40e-6 m=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwpw.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwpw.cdl
new file mode 100644
index 0000000..4f085b6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwpw.cdl
@@ -0,0 +1,50 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_dnwpw
+* View Name: schematic
+* Netlisted on: Nov 24 09:06:01 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_dnwpw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_dnwpw I1_0_0_0_0_0_R0_POS I1_0_1_0_0_0_R0_POS I1_0_2_0_0_0_R0_POS
++ I1_1_0_0_0_0_R0_POS I1_1_1_0_0_0_R0_POS I1_1_2_0_0_0_R0_POS
++ I1_2_0_0_0_0_R0_POS I1_2_1_0_0_0_R0_POS I1_2_2_0_0_0_R0_POS I1_default_POS
++ vdd!
+*.PININFO I1_0_0_0_0_0_R0_POS:I I1_0_1_0_0_0_R0_POS:I I1_0_2_0_0_0_R0_POS:I
+*.PININFO I1_1_0_0_0_0_R0_POS:I I1_1_1_0_0_0_R0_POS:I I1_1_2_0_0_0_R0_POS:I
+*.PININFO I1_2_0_0_0_0_R0_POS:I I1_2_1_0_0_0_R0_POS:I I1_2_2_0_0_0_R0_POS:I
+*.PININFO I1_default_POS:I vdd!:I
+DI1_2_2_0_0_0_R0 I1_2_2_0_0_0_R0_POS vdd! diode_dnwpw AREA=10n PJ=400e-6 m=1
+DI1_2_1_0_0_0_R0 I1_2_1_0_0_0_R0_POS vdd! diode_dnwpw AREA=1.023n PJ=220.46e-6 m=1
+DI1_2_0_0_0_0_R0 I1_2_0_0_0_0_R0_POS vdd! diode_dnwpw AREA=60p PJ=201.2e-6 m=1
+DI1_1_2_0_0_0_R0 I1_1_2_0_0_0_R0_POS vdd! diode_dnwpw AREA=1.023n PJ=220.46e-6 m=1
+DI1_1_1_0_0_0_R0 I1_1_1_0_0_0_R0_POS vdd! diode_dnwpw AREA=104.653p PJ=40.92e-6 m=1
+DI1_1_0_0_0_0_R0 I1_1_0_0_0_0_R0_POS vdd! diode_dnwpw AREA=6.138p PJ=21.66e-6 m=1
+DI1_0_2_0_0_0_R0 I1_0_2_0_0_0_R0_POS vdd! diode_dnwpw AREA=60p PJ=201.2e-6 m=1
+DI1_0_1_0_0_0_R0 I1_0_1_0_0_0_R0_POS vdd! diode_dnwpw AREA=6.138p PJ=21.66e-6 m=1
+DI1_0_0_0_0_0_R0 I1_0_0_0_0_0_R0_POS vdd! diode_dnwpw AREA=627f PJ=3.29e-6 m=1
+DI1_default I1_default_POS vdd! diode_dnwpw AREA=100e-12 PJ=40e-6 m=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8.cdl
new file mode 100644
index 0000000..4d94bbb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_np_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:16:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_np_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_np_1p8 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_np_1p8 m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_np_1p8 m=1 AREA=1.32n PJ=226.4u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_np_1p8 m=1 AREA=110p PJ=202.2u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_np_1p8 m=1 AREA=36p PJ=200.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_np_1p8 m=1 AREA=1.32n PJ=226.4u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_np_1p8 m=1 AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_np_1p8 m=1 AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_np_1p8 m=1 AREA=4.752p PJ=27.12u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_np_1p8 m=1 AREA=110p PJ=202.2u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_np_1p8 m=1 AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_np_1p8 m=1 AREA=1.21p PJ=4.4u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_np_1p8 m=1 AREA=396f PJ=2.92u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_np_1p8 m=1 AREA=36p PJ=200.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_np_1p8 m=1 AREA=4.752p PJ=27.12u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_np_1p8 m=1 AREA=396f PJ=2.92u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_np_1p8 m=1 AREA=203.4f PJ=1.85u
+DI1_default vdd! I1_default_MINUS diode_np_1p8 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8_dw.cdl
new file mode 100644
index 0000000..1c9cb7e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8_dw.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_np_1p8_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:17:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_np_1p8_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_np_1p8_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_np_1p8_dw m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_np_1p8_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_np_1p8_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_np_1p8_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_np_1p8_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_np_1p8_dw m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_np_1p8_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_np_1p8_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_np_1p8_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_np_1p8_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_np_1p8_dw m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_np_1p8_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_np_1p8_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_np_1p8_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_np_1p8_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_np_1p8_dw m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_np_1p8_dw m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3.cdl
new file mode 100644
index 0000000..29240ea
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_np_3p3
+* View Name: schematic
+* Netlisted on: Nov 24 09:16:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_np_3p3
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_np_3p3 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_np_3p3 m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_np_3p3 m=1 AREA=1.32n PJ=226.4u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_np_3p3 m=1 AREA=110p PJ=202.2u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_np_3p3 m=1 AREA=36p PJ=200.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_np_3p3 m=1 AREA=1.32n PJ=226.4u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_np_3p3 m=1 AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_np_3p3 m=1 AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_np_3p3 m=1 AREA=4.752p PJ=27.12u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_np_3p3 m=1 AREA=110p PJ=202.2u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_np_3p3 m=1 AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_np_3p3 m=1 AREA=1.21p PJ=4.4u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_np_3p3 m=1 AREA=396f PJ=2.92u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_np_3p3 m=1 AREA=36p PJ=200.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_np_3p3 m=1 AREA=4.752p PJ=27.12u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_np_3p3 m=1 AREA=396f PJ=2.92u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_np_3p3 m=1 AREA=203.4f PJ=1.85u
+DI1_default vdd! I1_default_MINUS diode_np_3p3 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3_dw.cdl
new file mode 100644
index 0000000..c305c9c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3_dw.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_np_3p3_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:17:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_np_3p3_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_np_3p3_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_np_3p3_dw m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_np_3p3_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_np_3p3_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_np_3p3_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_np_3p3_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_np_3p3_dw m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_np_3p3_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_np_3p3_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_np_3p3_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_np_3p3_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_np_3p3_dw m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_np_3p3_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_np_3p3_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_np_3p3_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_np_3p3_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_np_3p3_dw m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_np_3p3_dw m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_6p0.cdl
new file mode 100644
index 0000000..4c9112e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_6p0.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_np_6p0_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:18:14 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_np_6p0_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_np_6p0_dw I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=1.32n PJ=226.4u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=110p PJ=202.2u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=36p PJ=200.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=1.32n PJ=226.4u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=4.752p PJ=27.12u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=110p PJ=202.2u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=1.21p PJ=4.4u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=396f PJ=2.92u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=36p PJ=200.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=4.752p PJ=27.12u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=396f PJ=2.92u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=203.4f PJ=1.85u
+DI1_default vdd! I1_default_MINUS diode_np_6p0_dw m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_6p0_dw.cdl
new file mode 100644
index 0000000..d787047
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_6p0_dw.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_np_6p0_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:18:59 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_np_6p0_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_np_6p0_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_np_6p0_dw m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_np_6p0_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_np_6p0_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_np_6p0_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_np_6p0_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_np_6p0_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_np_6p0_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_np_6p0_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_np_6p0_dw m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_np_6p0_dw m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nwp_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nwp_6p0.cdl
new file mode 100644
index 0000000..b07171d
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nwp_6p0.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nwp_6p0
+* View Name: schematic
+* Netlisted on: Nov 24 09:43:35 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nwp_6p0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nwp_6p0 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=1.21n PJ=224.2u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=123p PJ=202.46u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=86p PJ=201.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=1.21n PJ=224.2u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=146.41p PJ=48.4u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=14.883p PJ=26.66u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=10.406p PJ=25.92u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=123p PJ=202.46u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=14.883p PJ=26.66u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=1.5129p PJ=4.92u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=1.0578p PJ=4.18u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=86p PJ=201.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=10.406p PJ=25.92u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=1.0578p PJ=4.18u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nwp_6p0 m=1 AREA=739.6f PJ=3.44u
+DI1_default vdd! I1_default_MINUS diode_nwp_6p0 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_1p8.cdl
new file mode 100644
index 0000000..f5087d7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_1p8.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pn_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:49:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pn_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pn_1p8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=36p
++ PJ=200.72u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=174.24p
++ PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=36p
++ PJ=200.72u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=203.4f
++ PJ=1.85u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pn_1p8 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_1p8_dw.cdl
new file mode 100644
index 0000000..f3859d2
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_1p8_dw.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pn_1p8_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:00 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pn_1p8_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pn_1p8_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pn_1p8_dw m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pn_1p8_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pn_1p8_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pn_1p8_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pn_1p8_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pn_1p8_dw m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pn_1p8_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pn_1p8_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pn_1p8_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pn_1p8_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pn_1p8_dw m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pn_1p8_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pn_1p8_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pn_1p8_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pn_1p8_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pn_1p8_dw m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pn_1p8_dw m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_3p3.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_3p3.cdl
new file mode 100644
index 0000000..0bb69ae
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_3p3.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pn_3p3
+* View Name: schematic
+* Netlisted on: Nov 24 09:49:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pn_3p3
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pn_3p3 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=36p
++ PJ=200.72u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=174.24p
++ PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=36p
++ PJ=200.72u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=203.4f
++ PJ=1.85u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pn_3p3 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_3p3_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_3p3_dw.cdl
new file mode 100644
index 0000000..e658351
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_3p3_dw.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pn_3p3_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:00 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pn_3p3_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pn_3p3_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pn_3p3_dw m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pn_3p3_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pn_3p3_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pn_3p3_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pn_3p3_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pn_3p3_dw m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pn_3p3_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pn_3p3_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pn_3p3_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pn_3p3_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pn_3p3_dw m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pn_3p3_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pn_3p3_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pn_3p3_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pn_3p3_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pn_3p3_dw m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pn_3p3_dw m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_6p0.cdl
new file mode 100644
index 0000000..9067197
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_6p0.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pn_6p0
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pn_6p0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pn_6p0 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=36p
++ PJ=200.72u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=174.24p
++ PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=36p
++ PJ=200.72u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pn_6p0 m=1 AREA=203.4f
++ PJ=1.85u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pn_6p0 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_6p0_dw.cdl
new file mode 100644
index 0000000..c859aae
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_6p0_dw.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pn_6p0_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:51:10 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pn_6p0_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pn_6p0_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pn_6p0_dw m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pn_6p0_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pn_6p0_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pn_6p0_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pn_6p0_dw m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pn_6p0_dw m=1
++ AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pn_6p0_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pn_6p0_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pn_6p0_dw m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pn_6p0_dw m=1
++ AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pn_6p0_dw m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pn_6p0_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pn_6p0_dw m=1 AREA=56.5p
++ PJ=201.13u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pn_6p0_dw m=1
++ AREA=7.458p PJ=27.53u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pn_6p0_dw m=1
++ AREA=621.5f PJ=3.33u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pn_6p0_dw m=1
++ AREA=319.225f PJ=2.26u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pn_6p0_dw m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.gds
new file mode 100644
index 0000000..fac56eb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.yaml
new file mode 100644
index 0000000..060a3c2
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+mim_0p85fF_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "0.85"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.gds
new file mode 100644
index 0000000..fd7f31e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.yaml
new file mode 100644
index 0000000..64335cc
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+mim_0p85fF_tm_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "0.85"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.gds
new file mode 100644
index 0000000..c1fb759
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.yaml
new file mode 100644
index 0000000..35532ba
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+mim_0p85fF_tm_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "0.85"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.gds
new file mode 100644
index 0000000..7cfaae6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.yaml
new file mode 100644
index 0000000..0c52e94
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_0p85fF_tm_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+mim_0p85fF_tm_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "0.85"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.gds
new file mode 100644
index 0000000..cdcface
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.yaml
new file mode 100644
index 0000000..a3a5244
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p0fF_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "1"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.gds
new file mode 100644
index 0000000..72c62bd
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.yaml
new file mode 100644
index 0000000..00b0fe1
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p0fF_tm_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "1"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.gds
new file mode 100644
index 0000000..7049ddb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.yaml
new file mode 100644
index 0000000..d835d95
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p0fF_tm_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "1"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.gds
new file mode 100644
index 0000000..453c75e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.yaml
new file mode 100644
index 0000000..5825807
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p0fF_tm_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p0fF_tm_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "1"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.gds
new file mode 100644
index 0000000..6d25b72
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.yaml
new file mode 100644
index 0000000..5d0b626
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_m2m3_noshield.yaml
@@ -0,0 +1,5 @@
+mim_1p5fF_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "1.5"
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.gds
new file mode 100644
index 0000000..f85ae78
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.yaml
new file mode 100644
index 0000000..7028012
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p5fF_tm_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "1.5"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.gds
new file mode 100644
index 0000000..6d72e9c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.yaml
new file mode 100644
index 0000000..3426e30
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p5fF_tm_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "1.5"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.gds
new file mode 100644
index 0000000..6c53293
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.yaml
new file mode 100644
index 0000000..e08c7dc
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_1p5fF_tm_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+mim_1p5fF_tm_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "1.5"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.gds
new file mode 100644
index 0000000..020b0e6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.yaml
new file mode 100644
index 0000000..f9f80c1
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_m2m3_noshield.yaml
@@ -0,0 +1,4 @@
+mim_2p0fF_m2m3_noshield:
+ -rd mim_option: "A"
+ -rd metal_level: "3LM"
+ -rd mim_cap: "2"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.gds
new file mode 100644
index 0000000..2e671ef
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.yaml
new file mode 100644
index 0000000..2b0309b
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m3m4_noshield.yaml
@@ -0,0 +1,4 @@
+mim_2p0fF_tm_m3m4_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "4LM"
+ -rd mim_cap: "2"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.gds
new file mode 100644
index 0000000..b0291da
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.yaml
new file mode 100644
index 0000000..ab478fe
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m4m5_noshield.yaml
@@ -0,0 +1,4 @@
+mim_2p0fF_tm_m4m5_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "5LM"
+ -rd mim_cap: "2"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.gds b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.gds
new file mode 100644
index 0000000..7d359f1
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.yaml b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.yaml
new file mode 100644
index 0000000..a7d59a4
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/mim_2p0fF_tm_m5m6_noshield.yaml
@@ -0,0 +1,4 @@
+mim_2p0fF_tm_m5m6_noshield:
+ -rd mim_option: "B"
+ -rd metal_level: "6LM"
+ -rd mim_cap: "2"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_m2m3_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_m2m3_noshield.cdl
new file mode 100644
index 0000000..808d77a
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_0p85fF_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:39:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_0p85fF_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_0p85fF_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_0p85fF_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT mim_0p85fF_m2m3_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m3m4_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m3m4_noshield.cdl
new file mode 100644
index 0000000..84dcbd3
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_0p85fF_tm_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_0p85fF_tm_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_0p85fF_tm_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT mim_0p85fF_tm_m3m4_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m4m5_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m4m5_noshield.cdl
new file mode 100644
index 0000000..2dbf6ae
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_0p85fF_tm_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_0p85fF_tm_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_0p85fF_tm_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT mim_0p85fF_tm_m4m5_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m5m6_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m5m6_noshield.cdl
new file mode 100644
index 0000000..eeb3db6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_0p85fF_tm_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_0p85fF_tm_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_0p85fF_tm_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_0p85fF_tm_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=50.000u w=50.000u
++ c=2.153475p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=50.000u w=11.560u
++ c=0.51944826p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=50.000u w=5.000u
++ c=0.2405925p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=11.560u w=50.000u
++ c=0.51944826p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=11.560u w=11.560u
++ c=0.125082226p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=11.560u w=5.000u
++ c=0.05778147p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=5.000u w=50.000u
++ c=0.2405925p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=5.000u w=11.560u
++ c=0.05778147p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.02658375p
+CI1_default I1_default_TOP I1_default_BOT mim_0p85fF_tm_m5m6_noshield M=1 l=5u w=5u
++ c=0.02658375p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_m2m3_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_m2m3_noshield.cdl
new file mode 100644
index 0000000..e83fa1f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p0fF_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:39:22 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p0fF_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p0fF_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p0fF_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT mim_1p0fF_m2m3_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m3m4_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m3m4_noshield.cdl
new file mode 100644
index 0000000..a4a4ba7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p0fF_tm_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p0fF_tm_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p0fF_tm_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT mim_1p0fF_tm_m3m4_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m4m5_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m4m5_noshield.cdl
new file mode 100644
index 0000000..6e0ae99
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p0fF_tm_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p0fF_tm_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p0fF_tm_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT mim_1p0fF_tm_m4m5_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m5m6_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m5m6_noshield.cdl
new file mode 100644
index 0000000..eda163d
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p0fF_tm_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p0fF_tm_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:42:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p0fF_tm_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p0fF_tm_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=50.000u w=50.000u
++ c=2.5335p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=50.000u w=11.560u
++ c=0.6111156p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=50.000u w=5.000u
++ c=0.28305p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=11.560u w=50.000u
++ c=0.6111156p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=11.560u w=11.560u
++ c=0.14715556p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=11.560u w=5.000u
++ c=0.0679782p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=5.000u w=50.000u
++ c=0.28305p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=5.000u w=11.560u
++ c=0.0679782p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.031275p
+CI1_default I1_default_TOP I1_default_BOT mim_1p0fF_tm_m5m6_noshield M=1 l=5u w=5u
++ c=0.031275p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_m2m3_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_m2m3_noshield.cdl
new file mode 100644
index 0000000..2fceba7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_m2m3_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p5fF_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:42:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p5fF_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p5fF_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p5fF_m2m3_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT mim_1p5fF_m2m3_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m3m4_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m3m4_noshield.cdl
new file mode 100644
index 0000000..34731c2
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m3m4_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p5fF_tm_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p5fF_tm_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p5fF_tm_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT mim_1p5fF_tm_m3m4_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m4m5_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m4m5_noshield.cdl
new file mode 100644
index 0000000..1ceddc8
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m4m5_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p5fF_tm_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p5fF_tm_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p5fF_tm_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT mim_1p5fF_tm_m4m5_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m5m6_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m5m6_noshield.cdl
new file mode 100644
index 0000000..9a6bad7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_1p5fF_tm_m5m6_noshield.cdl
@@ -0,0 +1,59 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_1p5fF_tm_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 12:03:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_1p5fF_tm_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_1p5fF_tm_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=100.000u w=100.000u
++ c=14.8516p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=100.000u w=12.340u
++ c=1.89913372p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=100.000u w=5.000u
++ c=0.81459p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=12.340u w=100.000u
++ c=1.89913372p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=12.340u w=12.340u
++ c=0.24255257p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=12.340u w=5.000u
++ c=0.10384272p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=5.000u w=100.000u
++ c=0.81459p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=5.000u w=12.340u
++ c=0.10384272p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=5.000u w=5.000u
++ c=0.04433p
+CI1_default I1_default_TOP I1_default_BOT mim_1p5fF_tm_m5m6_noshield M=1 l=5u w=5u c=0.04433p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_m2m3_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_m2m3_noshield.cdl
new file mode 100644
index 0000000..0223463
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_2p0fF_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:53:54 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_2p0fF_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_2p0fF_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_2p0fF_m2m3_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT mim_2p0fF_m2m3_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m3m4_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m3m4_noshield.cdl
new file mode 100644
index 0000000..0cb1eb6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_2p0fF_tm_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_2p0fF_tm_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_2p0fF_tm_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT mim_2p0fF_tm_m3m4_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m4m5_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m4m5_noshield.cdl
new file mode 100644
index 0000000..0dc8b9b
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_2p0fF_tm_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_2p0fF_tm_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_2p0fF_tm_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT mim_2p0fF_tm_m4m5_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m5m6_noshield.cdl b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m5m6_noshield.cdl
new file mode 100644
index 0000000..898b421
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/mim_2p0fF_tm_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mim_2p0fF_tm_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mim_2p0fF_tm_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mim_2p0fF_tm_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT mim_2p0fF_tm_m5m6_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8.gds
new file mode 100644
index 0000000..16ab300
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dnwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dnwell.gds
new file mode 100644
index 0000000..07997de
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dnwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dw.gds
new file mode 100644
index 0000000..3559daf
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_nwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_nwell.gds
new file mode 100644
index 0000000..d409b7f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_1p8_nwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0.gds
new file mode 100644
index 0000000..b7b05bb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dnwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dnwell.gds
new file mode 100644
index 0000000..b4c9a71
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dnwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dw.gds
new file mode 100644
index 0000000..14b3eab
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_nwell.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_nwell.gds
new file mode 100644
index 0000000..86d96d4
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/nmoscap_6p0_nwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8.gds
new file mode 100644
index 0000000..08d8d04
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8_dw.gds
new file mode 100644
index 0000000..c7f73a6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0.gds
new file mode 100644
index 0000000..0e678ed
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0_dw.gds
new file mode 100644
index 0000000..e0bd3fd
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/layout/pmoscap_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8.cdl
new file mode 100644
index 0000000..d0f6935
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nmoscap_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nmoscap_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nmoscap_1p8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_1p8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dnwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dnwell.cdl
new file mode 100644
index 0000000..0e7e9ad
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dnwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nmoscap_1p8_dnwell
+* View Name: schematic
+* Netlisted on: Nov 24 09:11:11 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nmoscap_1p8_dnwell
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nmoscap_1p8_dnwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8_dnwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8_dnwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8_dnwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8_dnwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8_dnwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8_dnwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8_dnwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8_dnwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8_dnwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_1p8_dnwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dw.cdl
new file mode 100644
index 0000000..e5823d4
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nmoscap_1p8_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:12:27 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nmoscap_1p8_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nmoscap_1p8_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_1p8_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_nwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_nwell.cdl
new file mode 100644
index 0000000..648f007
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_1p8_nwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nmoscap_1p8_nwell
+* View Name: schematic
+* Netlisted on: Nov 24 09:11:11 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nmoscap_1p8_nwell
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nmoscap_1p8_nwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_1p8_nwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_1p8_nwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_1p8_nwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_1p8_nwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_1p8_nwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_1p8_nwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_1p8_nwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_1p8_nwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_1p8_nwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_1p8_nwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0.cdl
new file mode 100644
index 0000000..508a56c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nmoscap_6p0
+* View Name: schematic
+* Netlisted on: Nov 24 09:13:17 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nmoscap_6p0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nmoscap_6p0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_6p0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dnwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dnwell.cdl
new file mode 100644
index 0000000..9e8092b
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dnwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nmoscap_6p0_dnwell
+* View Name: schematic
+* Netlisted on: Nov 24 09:14:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nmoscap_6p0_dnwell
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nmoscap_6p0_dnwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0_dnwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0_dnwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0_dnwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0_dnwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0_dnwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0_dnwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0_dnwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0_dnwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0_dnwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_6p0_dnwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dw.cdl
new file mode 100644
index 0000000..2515b81
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nmoscap_6p0_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:15:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nmoscap_6p0_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nmoscap_6p0_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_6p0_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_nwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_nwell.cdl
new file mode 100644
index 0000000..e618d63
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/nmoscap_6p0_nwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nmoscap_6p0_nwell
+* View Name: schematic
+* Netlisted on: Nov 24 09:14:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nmoscap_6p0_nwell
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nmoscap_6p0_nwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D nmoscap_6p0_nwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D nmoscap_6p0_nwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D nmoscap_6p0_nwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D nmoscap_6p0_nwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D nmoscap_6p0_nwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D nmoscap_6p0_nwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D nmoscap_6p0_nwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D nmoscap_6p0_nwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D nmoscap_6p0_nwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D nmoscap_6p0_nwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8.cdl
new file mode 100644
index 0000000..3f04861
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pmoscap_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:44:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pmoscap_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pmoscap_1p8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_1p8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_1p8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_1p8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_1p8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_1p8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_1p8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_1p8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_1p8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_1p8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D pmoscap_1p8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8_dw.cdl
new file mode 100644
index 0000000..bcd13a6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_1p8_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pmoscap_1p8_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:45:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pmoscap_1p8_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pmoscap_1p8_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_1p8_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_1p8_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_1p8_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_1p8_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_1p8_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_1p8_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_1p8_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_1p8_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_1p8_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D pmoscap_1p8_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0.cdl
new file mode 100644
index 0000000..f9c0f84
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pmoscap_6p0
+* View Name: schematic
+* Netlisted on: Nov 24 09:47:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pmoscap_6p0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pmoscap_6p0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_6p0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_6p0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_6p0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_6p0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_6p0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_6p0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_6p0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_6p0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_6p0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D pmoscap_6p0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0_dw.cdl
new file mode 100644
index 0000000..01d0eb8
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/pmoscap_6p0_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pmoscap_6p0_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:48:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pmoscap_6p0_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pmoscap_6p0_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D pmoscap_6p0_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D pmoscap_6p0_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D pmoscap_6p0_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D pmoscap_6p0_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D pmoscap_6p0_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D pmoscap_6p0_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D pmoscap_6p0_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D pmoscap_6p0_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D pmoscap_6p0_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D pmoscap_6p0_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds
new file mode 100644
index 0000000..d6a4e5f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds
new file mode 100644
index 0000000..26bb5ed
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds
new file mode 100644
index 0000000..c91e63c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds
new file mode 100644
index 0000000..1638d1c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/layout/piscap_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl
new file mode 100644
index 0000000..811a4ce
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: piscap_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: piscap_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT piscap_1p8 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_1p8 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_1p8 m=1 l=5.88u w=5u
+.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
new file mode 100644
index 0000000..88262cb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_1p8_dw.cdl
@@ -0,0 +1,34 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: piscap_1p8_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: piscap_1p8_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT piscap_1p8_dw I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_1p8_dw m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_1p8_dw m=1 l=5.88u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl
new file mode 100644
index 0000000..a8bc9a5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: piscap_6p0
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: piscap_6p0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT piscap_6p0 I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_6p0 m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_6p0 m=1 l=5.88u w=5u
+.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl
new file mode 100644
index 0000000..ad8c71e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/piscap_devices/netlist/piscap_6p0_dw.cdl
@@ -0,0 +1,33 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: piscap_6p0_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: piscap_6p0_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT piscap_6p0_dw I1_0_0_R0_G I1_0_0_R0_D I1_default_G I1_default_D
+
+C1 I1_0_0_R0_G I1_0_0_R0_D piscap_6p0_dw m=1 l=1.88u w=1.000u
+C2 I1_default_G I1_default_D piscap_6p0_dw m=1 l=5.88u w=5u
+.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_s.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_s.gds
new file mode 100644
index 0000000..86025f7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_s.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_s_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_s_dw.gds
new file mode 100644
index 0000000..d5b7cf6
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_s_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_u.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_u.gds
new file mode 100644
index 0000000..33dc444
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_u.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_u_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_u_dw.gds
new file mode 100644
index 0000000..84947cb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/nplus_u_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_s.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_s.gds
new file mode 100644
index 0000000..8de85ee
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_s.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_s_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_s_dw.gds
new file mode 100644
index 0000000..227e797
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_s_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_u.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_u.gds
new file mode 100644
index 0000000..328c751
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_u.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_u_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_u_dw.gds
new file mode 100644
index 0000000..e4a3622
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/npolyf_u_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_s.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_s.gds
new file mode 100644
index 0000000..48a1652
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_s.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_s_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_s_dw.gds
new file mode 100644
index 0000000..391cd72
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_s_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_u.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_u.gds
new file mode 100644
index 0000000..11db435
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_u.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_u_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_u_dw.gds
new file mode 100644
index 0000000..d019e2c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pplus_u_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_s.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_s.gds
new file mode 100644
index 0000000..9139447
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_s.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_s_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_s_dw.gds
new file mode 100644
index 0000000..4992508
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_s_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u.gds
new file mode 100644
index 0000000..d2fc3fd
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k.gds
new file mode 100644
index 0000000..688e147
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k.yaml b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k.yaml
new file mode 100644
index 0000000..1e3edd5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k.yaml
@@ -0,0 +1,2 @@
+ppolyf_u_1k:
+ -rd poly_res: "1k"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k_dw.gds
new file mode 100644
index 0000000..76a7ce5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k_dw.yaml b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k_dw.yaml
new file mode 100644
index 0000000..e48d991
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_1k_dw.yaml
@@ -0,0 +1,2 @@
+ppolyf_u_1k_dw:
+ -rd poly_res: "1k"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k.gds
new file mode 100644
index 0000000..183a260
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k.yaml b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k.yaml
new file mode 100644
index 0000000..c0672c2
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k.yaml
@@ -0,0 +1,2 @@
+ppolyf_u_2k:
+ -rd poly_res: "2k"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k_dw.gds
new file mode 100644
index 0000000..e4405f5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k_dw.yaml b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k_dw.yaml
new file mode 100644
index 0000000..b0924f7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_2k_dw.yaml
@@ -0,0 +1,2 @@
+ppolyf_u_2k_dw:
+ -rd poly_res: "2k"
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_dw.gds
new file mode 100644
index 0000000..2abf185
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_fhr_16p0_lv.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_fhr_16p0_lv.gds
new file mode 100644
index 0000000..8c8fa0f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_fhr_16p0_lv.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_fhr_16p0_lv_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_fhr_16p0_lv_dw.gds
new file mode 100644
index 0000000..7624ff8
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/ppolyf_u_fhr_16p0_lv_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pwell.gds b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pwell.gds
new file mode 100644
index 0000000..c6c430e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/layout/pwell.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_s.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_s.cdl
new file mode 100644
index 0000000..1345128
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_s.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nplus_s
+* View Name: schematic
+* Netlisted on: Nov 24 09:19:41 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nplus_s
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nplus_s I1_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_R0_MINUS I1_0_0_0_1_0_R0_PLUS I1_0_0_1_0_0_R0_MINUS
++ I1_0_0_1_0_0_R0_PLUS I1_0_0_1_1_0_R0_MINUS I1_0_0_1_1_0_R0_PLUS
++ I1_0_0_2_0_0_R0_MINUS I1_0_0_2_0_0_R0_PLUS I1_0_0_2_1_0_R0_MINUS
++ I1_0_0_2_1_0_R0_PLUS I1_0_1_0_0_0_R0_MINUS I1_0_1_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_R0_MINUS I1_0_1_0_1_0_R0_PLUS I1_0_1_1_0_0_R0_MINUS
++ I1_0_1_1_0_0_R0_PLUS I1_0_1_1_1_0_R0_MINUS I1_0_1_1_1_0_R0_PLUS
++ I1_0_1_2_0_0_R0_MINUS I1_0_1_2_0_0_R0_PLUS I1_0_1_2_1_0_R0_MINUS
++ I1_0_1_2_1_0_R0_PLUS I1_0_2_0_0_0_R0_MINUS I1_0_2_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_R0_MINUS I1_0_2_0_1_0_R0_PLUS I1_0_2_1_0_0_R0_MINUS
++ I1_0_2_1_0_0_R0_PLUS I1_0_2_1_1_0_R0_MINUS I1_0_2_1_1_0_R0_PLUS
++ I1_0_2_2_0_0_R0_MINUS I1_0_2_2_0_0_R0_PLUS I1_0_2_2_1_0_R0_MINUS
++ I1_0_2_2_1_0_R0_PLUS I1_1_0_0_0_0_R0_MINUS I1_1_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_R0_MINUS I1_1_0_0_1_0_R0_PLUS I1_1_0_1_0_0_R0_MINUS
++ I1_1_0_1_0_0_R0_PLUS I1_1_0_1_1_0_R0_MINUS I1_1_0_1_1_0_R0_PLUS
++ I1_1_0_2_0_0_R0_MINUS I1_1_0_2_0_0_R0_PLUS I1_1_0_2_1_0_R0_MINUS
++ I1_1_0_2_1_0_R0_PLUS I1_1_1_0_0_0_R0_MINUS I1_1_1_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_R0_MINUS I1_1_1_0_1_0_R0_PLUS I1_1_1_1_0_0_R0_MINUS
++ I1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_R0_MINUS I1_1_1_1_1_0_R0_PLUS
++ I1_1_1_2_0_0_R0_MINUS I1_1_1_2_0_0_R0_PLUS I1_1_1_2_1_0_R0_MINUS
++ I1_1_1_2_1_0_R0_PLUS I1_1_2_0_0_0_R0_MINUS I1_1_2_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_R0_MINUS I1_1_2_0_1_0_R0_PLUS I1_1_2_1_0_0_R0_MINUS
++ I1_1_2_1_0_0_R0_PLUS I1_1_2_1_1_0_R0_MINUS I1_1_2_1_1_0_R0_PLUS
++ I1_1_2_2_0_0_R0_MINUS I1_1_2_2_0_0_R0_PLUS I1_1_2_2_1_0_R0_MINUS
++ I1_1_2_2_1_0_R0_PLUS I1_2_0_0_0_0_R0_MINUS I1_2_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_R0_MINUS I1_2_0_0_1_0_R0_PLUS I1_2_0_1_0_0_R0_MINUS
++ I1_2_0_1_0_0_R0_PLUS I1_2_0_1_1_0_R0_MINUS I1_2_0_1_1_0_R0_PLUS
++ I1_2_0_2_0_0_R0_MINUS I1_2_0_2_0_0_R0_PLUS I1_2_0_2_1_0_R0_MINUS
++ I1_2_0_2_1_0_R0_PLUS I1_2_1_0_0_0_R0_MINUS I1_2_1_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_R0_MINUS I1_2_1_0_1_0_R0_PLUS I1_2_1_1_0_0_R0_MINUS
++ I1_2_1_1_0_0_R0_PLUS I1_2_1_1_1_0_R0_MINUS I1_2_1_1_1_0_R0_PLUS
++ I1_2_1_2_0_0_R0_MINUS I1_2_1_2_0_0_R0_PLUS I1_2_1_2_1_0_R0_MINUS
++ I1_2_1_2_1_0_R0_PLUS I1_2_2_0_0_0_R0_MINUS I1_2_2_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_R0_MINUS I1_2_2_0_1_0_R0_PLUS I1_2_2_1_0_0_R0_MINUS
++ I1_2_2_1_0_0_R0_PLUS I1_2_2_1_1_0_R0_MINUS I1_2_2_1_1_0_R0_PLUS
++ I1_2_2_2_0_0_R0_MINUS I1_2_2_2_0_0_R0_PLUS I1_2_2_2_1_0_R0_MINUS
++ I1_2_2_2_1_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_R0_MINUS:I I1_0_0_0_1_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_R0_MINUS:I I1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_R0_MINUS:I I1_0_0_1_1_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_R0_MINUS:I I1_0_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_R0_MINUS:I I1_0_0_2_1_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_R0_MINUS:I I1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_R0_MINUS:I I1_0_1_0_1_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_R0_MINUS:I I1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_R0_MINUS:I I1_0_1_1_1_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_R0_MINUS:I I1_0_1_2_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_R0_MINUS:I I1_0_1_2_1_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_R0_MINUS:I I1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_R0_MINUS:I I1_0_2_0_1_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_R0_MINUS:I I1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_R0_MINUS:I I1_0_2_1_1_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_R0_MINUS:I I1_0_2_2_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_R0_MINUS:I I1_0_2_2_1_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_R0_MINUS:I I1_1_0_0_1_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_R0_MINUS:I I1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_R0_MINUS:I I1_1_0_1_1_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_R0_MINUS:I I1_1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_R0_MINUS:I I1_1_0_2_1_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_R0_MINUS:I I1_1_1_0_1_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_R0_MINUS:I I1_1_1_1_1_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_R0_MINUS:I I1_1_1_2_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_R0_MINUS:I I1_1_1_2_1_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_R0_MINUS:I I1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_R0_MINUS:I I1_1_2_0_1_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_R0_MINUS:I I1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_R0_MINUS:I I1_1_2_1_1_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_R0_MINUS:I I1_1_2_2_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_R0_MINUS:I I1_1_2_2_1_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_R0_MINUS:I I1_2_0_0_1_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_R0_MINUS:I I1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_R0_MINUS:I I1_2_0_1_1_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_R0_MINUS:I I1_2_0_2_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_R0_MINUS:I I1_2_0_2_1_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_R0_MINUS:I I1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_R0_MINUS:I I1_2_1_0_1_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_R0_MINUS:I I1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_R0_MINUS:I I1_2_1_1_1_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_R0_MINUS:I I1_2_1_2_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_R0_MINUS:I I1_2_1_2_1_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_R0_MINUS:I I1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_R0_MINUS:I I1_2_2_0_1_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_R0_MINUS:I I1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_R0_MINUS:I I1_2_2_1_1_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_R0_MINUS:I I1_2_2_2_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_R0_MINUS:I I1_2_2_2_1_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_R0 I1_2_2_2_1_0_R0_PLUS I1_2_2_2_1_0_R0_MINUS gnd!
++ nplus_s m=8.0 l=50u w=50u r=6.53672 par=8.0 s=1
+RI1_2_2_2_0_0_R0 I1_2_2_2_0_0_R0_PLUS I1_2_2_2_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=50u r=6.53672 par=1.0 s=8
+RI1_2_2_1_1_0_R0 I1_2_2_1_1_0_R0_PLUS I1_2_2_1_1_0_R0_MINUS gnd!
++ nplus_s m=3.0 l=50u w=50u r=6.53672 par=3.0 s=1
+RI1_2_2_1_0_0_R0 I1_2_2_1_0_0_R0_PLUS I1_2_2_1_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=50u r=6.53672 par=1.0 s=3
+RI1_2_2_0_1_0_R0 I1_2_2_0_1_0_R0_PLUS I1_2_2_0_1_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=50u r=6.53672 par=1.0 s=1
+RI1_2_2_0_0_0_R0 I1_2_2_0_0_0_R0_PLUS I1_2_2_0_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=50u r=6.53672 par=1.0 s=1
+RI1_2_1_2_1_0_R0 I1_2_1_2_1_0_R0_PLUS I1_2_1_2_1_0_R0_MINUS gnd!
++ nplus_s m=8.0 l=2.6u w=50u r=567.308m par=8.0 s=1
+RI1_2_1_2_0_0_R0 I1_2_1_2_0_0_R0_PLUS I1_2_1_2_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=50u r=567.308m par=1.0 s=8
+RI1_2_1_1_1_0_R0 I1_2_1_1_1_0_R0_PLUS I1_2_1_1_1_0_R0_MINUS gnd!
++ nplus_s m=3.0 l=2.6u w=50u r=567.308m par=3.0 s=1
+RI1_2_1_1_0_0_R0 I1_2_1_1_0_0_R0_PLUS I1_2_1_1_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=50u r=567.308m par=1.0 s=3
+RI1_2_1_0_1_0_R0 I1_2_1_0_1_0_R0_PLUS I1_2_1_0_1_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=50u r=567.308m par=1.0 s=1
+RI1_2_1_0_0_0_R0 I1_2_1_0_0_0_R0_PLUS I1_2_1_0_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=50u r=567.308m par=1.0 s=1
+RI1_2_0_2_1_0_R0 I1_2_0_2_1_0_R0_PLUS I1_2_0_2_1_0_R0_MINUS gnd!
++ nplus_s m=8.0 l=840n w=50u r=345.658m par=8.0 s=1
+RI1_2_0_2_0_0_R0 I1_2_0_2_0_0_R0_PLUS I1_2_0_2_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=50u r=345.658m par=1.0 s=8
+RI1_2_0_1_1_0_R0 I1_2_0_1_1_0_R0_PLUS I1_2_0_1_1_0_R0_MINUS gnd!
++ nplus_s m=3.0 l=840n w=50u r=345.658m par=3.0 s=1
+RI1_2_0_1_0_0_R0 I1_2_0_1_0_0_R0_PLUS I1_2_0_1_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=50u r=345.658m par=1.0 s=3
+RI1_2_0_0_1_0_R0 I1_2_0_0_1_0_R0_PLUS I1_2_0_0_1_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=50u r=345.658m par=1.0 s=1
+RI1_2_0_0_0_0_R0 I1_2_0_0_0_0_R0_PLUS I1_2_0_0_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=50u r=345.658m par=1.0 s=1
+RI1_1_2_2_1_0_R0 I1_1_2_2_1_0_R0_PLUS I1_1_2_2_1_0_R0_MINUS gnd!
++ nplus_s m=8.0 l=50u w=1.57u r=205.015 par=8.0 s=1
+RI1_1_2_2_0_0_R0 I1_1_2_2_0_0_R0_PLUS I1_1_2_2_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=1.57u r=205.015 par=1.0 s=8
+RI1_1_2_1_1_0_R0 I1_1_2_1_1_0_R0_PLUS I1_1_2_1_1_0_R0_MINUS gnd!
++ nplus_s m=3.0 l=50u w=1.57u r=205.015 par=3.0 s=1
+RI1_1_2_1_0_0_R0 I1_1_2_1_0_0_R0_PLUS I1_1_2_1_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=1.57u r=205.015 par=1.0 s=3
+RI1_1_2_0_1_0_R0 I1_1_2_0_1_0_R0_PLUS I1_1_2_0_1_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=1.57u r=205.015 par=1.0 s=1
+RI1_1_2_0_0_0_R0 I1_1_2_0_0_0_R0_PLUS I1_1_2_0_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=1.57u r=205.015 par=1.0 s=1
+RI1_1_1_2_1_0_R0 I1_1_1_2_1_0_R0_PLUS I1_1_1_2_1_0_R0_MINUS gnd!
++ nplus_s m=8.0 l=2.6u w=1.57u r=17.7928 par=8.0 s=1
+RI1_1_1_2_0_0_R0 I1_1_1_2_0_0_R0_PLUS I1_1_1_2_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=1.57u r=17.7928 par=1.0 s=8
+RI1_1_1_1_1_0_R0 I1_1_1_1_1_0_R0_PLUS I1_1_1_1_1_0_R0_MINUS gnd!
++ nplus_s m=3.0 l=2.6u w=1.57u r=17.7928 par=3.0 s=1
+RI1_1_1_1_0_0_R0 I1_1_1_1_0_0_R0_PLUS I1_1_1_1_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=1.57u r=17.7928 par=1.0 s=3
+RI1_1_1_0_1_0_R0 I1_1_1_0_1_0_R0_PLUS I1_1_1_0_1_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=1.57u r=17.7928 par=1.0 s=1
+RI1_1_1_0_0_0_R0 I1_1_1_0_0_0_R0_PLUS I1_1_1_0_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=1.57u r=17.7928 par=1.0 s=1
+RI1_1_0_2_1_0_R0 I1_1_0_2_1_0_R0_PLUS I1_1_0_2_1_0_R0_MINUS gnd!
++ nplus_s m=8.0 l=840n w=1.57u r=10.8411 par=8.0 s=1
+RI1_1_0_2_0_0_R0 I1_1_0_2_0_0_R0_PLUS I1_1_0_2_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=1.57u r=10.8411 par=1.0 s=8
+RI1_1_0_1_1_0_R0 I1_1_0_1_1_0_R0_PLUS I1_1_0_1_1_0_R0_MINUS gnd!
++ nplus_s m=3.0 l=840n w=1.57u r=10.8411 par=3.0 s=1
+RI1_1_0_1_0_0_R0 I1_1_0_1_0_0_R0_PLUS I1_1_0_1_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=1.57u r=10.8411 par=1.0 s=3
+RI1_1_0_0_1_0_R0 I1_1_0_0_1_0_R0_PLUS I1_1_0_0_1_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=1.57u r=10.8411 par=1.0 s=1
+RI1_1_0_0_0_0_R0 I1_1_0_0_0_0_R0_PLUS I1_1_0_0_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=1.57u r=10.8411 par=1.0 s=1
+RI1_0_2_2_1_0_R0 I1_0_2_2_1_0_R0_PLUS I1_0_2_2_1_0_R0_MINUS gnd!
++ nplus_s m=8.0 l=50u w=420n r=734.83 par=8.0 s=1
+RI1_0_2_2_0_0_R0 I1_0_2_2_0_0_R0_PLUS I1_0_2_2_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=420n r=734.83 par=1.0 s=8
+RI1_0_2_1_1_0_R0 I1_0_2_1_1_0_R0_PLUS I1_0_2_1_1_0_R0_MINUS gnd!
++ nplus_s m=3.0 l=50u w=420n r=734.83 par=3.0 s=1
+RI1_0_2_1_0_0_R0 I1_0_2_1_0_0_R0_PLUS I1_0_2_1_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=420n r=734.83 par=1.0 s=3
+RI1_0_2_0_1_0_R0 I1_0_2_0_1_0_R0_PLUS I1_0_2_0_1_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=420n r=734.83 par=1.0 s=1
+RI1_0_2_0_0_0_R0 I1_0_2_0_0_0_R0_PLUS I1_0_2_0_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=50u w=420n r=734.83 par=1.0 s=1
+RI1_0_1_2_1_0_R0 I1_0_1_2_1_0_R0_PLUS I1_0_1_2_1_0_R0_MINUS gnd!
++ nplus_s m=8.0 l=2.6u w=420n r=63.7743 par=8.0 s=1
+RI1_0_1_2_0_0_R0 I1_0_1_2_0_0_R0_PLUS I1_0_1_2_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=420n r=63.7743 par=1.0 s=8
+RI1_0_1_1_1_0_R0 I1_0_1_1_1_0_R0_PLUS I1_0_1_1_1_0_R0_MINUS gnd!
++ nplus_s m=3.0 l=2.6u w=420n r=63.7743 par=3.0 s=1
+RI1_0_1_1_0_0_R0 I1_0_1_1_0_0_R0_PLUS I1_0_1_1_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=420n r=63.7743 par=1.0 s=3
+RI1_0_1_0_1_0_R0 I1_0_1_0_1_0_R0_PLUS I1_0_1_0_1_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=420n r=63.7743 par=1.0 s=1
+RI1_0_1_0_0_0_R0 I1_0_1_0_0_0_R0_PLUS I1_0_1_0_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=2.6u w=420n r=63.7743 par=1.0 s=1
+RI1_0_0_2_1_0_R0 I1_0_0_2_1_0_R0_PLUS I1_0_0_2_1_0_R0_MINUS gnd!
++ nplus_s m=8.0 l=840n w=420n r=38.8574 par=8.0 s=1
+RI1_0_0_2_0_0_R0 I1_0_0_2_0_0_R0_PLUS I1_0_0_2_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=420n r=38.8574 par=1.0 s=8
+RI1_0_0_1_1_0_R0 I1_0_0_1_1_0_R0_PLUS I1_0_0_1_1_0_R0_MINUS gnd!
++ nplus_s m=3.0 l=840n w=420n r=38.8574 par=3.0 s=1
+RI1_0_0_1_0_0_R0 I1_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=420n r=38.8574 par=1.0 s=3
+RI1_0_0_0_1_0_R0 I1_0_0_0_1_0_R0_PLUS I1_0_0_0_1_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=420n r=38.8574 par=1.0 s=1
+RI1_0_0_0_0_0_R0 I1_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_R0_MINUS gnd!
++ nplus_s m=1.0 l=840n w=420n r=38.8574 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! nplus_s m=1.0
++ l=840.00n w=420.00n r=38.8574 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_s_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_s_dw.cdl
new file mode 100644
index 0000000..9f47539
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_s_dw.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nplus_s_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:25:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nplus_s_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nplus_s_dw I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=8.0 l=50u w=50u r=6.53672 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=50u r=6.53672 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=3.0 l=50u w=50u r=6.53672 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=50u r=6.53672 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=50u r=6.53672 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=50u r=6.53672 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=8.0 l=2.6u w=50u r=567.308m par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=50u r=567.308m par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=3.0 l=2.6u w=50u r=567.308m par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=50u r=567.308m par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=50u r=567.308m par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=50u r=567.308m par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=8.0 l=840n w=50u r=345.658m par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=50u r=345.658m par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=3.0 l=840n w=50u r=345.658m par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=50u r=345.658m par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=50u r=345.658m par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=50u r=345.658m par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=8.0 l=50u w=1.57u r=205.015 par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=1.57u r=205.015 par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=3.0 l=50u w=1.57u r=205.015 par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=1.57u r=205.015 par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=1.57u r=205.015 par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=1.57u r=205.015 par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=8.0 l=2.6u w=1.57u r=17.7928 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=1.57u r=17.7928 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=3.0 l=2.6u w=1.57u r=17.7928 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=1.57u r=17.7928 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=1.57u r=17.7928 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=1.57u r=17.7928 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=8.0 l=840n w=1.57u r=10.8411 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=1.57u r=10.8411 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=3.0 l=840n w=1.57u r=10.8411 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=1.57u r=10.8411 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=1.57u r=10.8411 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=1.57u r=10.8411 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=8.0 l=50u w=420n r=734.83 par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=420n r=734.83 par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=3.0 l=50u w=420n r=734.83 par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=420n r=734.83 par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=420n r=734.83 par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=50u w=420n r=734.83 par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=8.0 l=2.6u w=420n r=63.7743 par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=420n r=63.7743 par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=3.0 l=2.6u w=420n r=63.7743 par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=420n r=63.7743 par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=420n r=63.7743 par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=2.6u w=420n r=63.7743 par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=8.0 l=840n w=420n r=38.8574 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=420n r=38.8574 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=3.0 l=840n w=420n r=38.8574 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=420n r=38.8574 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=420n r=38.8574 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ nplus_s_dw m=1.0 l=840n w=420n r=38.8574 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! nplus_s_dw m=1.0
++ l=840.00n w=420.00n r=38.8574 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_u.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_u.cdl
new file mode 100644
index 0000000..f1c6c45
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_u.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nplus_u
+* View Name: schematic
+* Netlisted on: Nov 24 09:29:33 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nplus_u
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nplus_u I1_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_R0_MINUS I1_0_0_0_1_0_R0_PLUS I1_0_0_1_0_0_R0_MINUS
++ I1_0_0_1_0_0_R0_PLUS I1_0_0_1_1_0_R0_MINUS I1_0_0_1_1_0_R0_PLUS
++ I1_0_0_2_0_0_R0_MINUS I1_0_0_2_0_0_R0_PLUS I1_0_0_2_1_0_R0_MINUS
++ I1_0_0_2_1_0_R0_PLUS I1_0_1_0_0_0_R0_MINUS I1_0_1_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_R0_MINUS I1_0_1_0_1_0_R0_PLUS I1_0_1_1_0_0_R0_MINUS
++ I1_0_1_1_0_0_R0_PLUS I1_0_1_1_1_0_R0_MINUS I1_0_1_1_1_0_R0_PLUS
++ I1_0_1_2_0_0_R0_MINUS I1_0_1_2_0_0_R0_PLUS I1_0_1_2_1_0_R0_MINUS
++ I1_0_1_2_1_0_R0_PLUS I1_0_2_0_0_0_R0_MINUS I1_0_2_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_R0_MINUS I1_0_2_0_1_0_R0_PLUS I1_0_2_1_0_0_R0_MINUS
++ I1_0_2_1_0_0_R0_PLUS I1_0_2_1_1_0_R0_MINUS I1_0_2_1_1_0_R0_PLUS
++ I1_0_2_2_0_0_R0_MINUS I1_0_2_2_0_0_R0_PLUS I1_0_2_2_1_0_R0_MINUS
++ I1_0_2_2_1_0_R0_PLUS I1_1_0_0_0_0_R0_MINUS I1_1_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_R0_MINUS I1_1_0_0_1_0_R0_PLUS I1_1_0_1_0_0_R0_MINUS
++ I1_1_0_1_0_0_R0_PLUS I1_1_0_1_1_0_R0_MINUS I1_1_0_1_1_0_R0_PLUS
++ I1_1_0_2_0_0_R0_MINUS I1_1_0_2_0_0_R0_PLUS I1_1_0_2_1_0_R0_MINUS
++ I1_1_0_2_1_0_R0_PLUS I1_1_1_0_0_0_R0_MINUS I1_1_1_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_R0_MINUS I1_1_1_0_1_0_R0_PLUS I1_1_1_1_0_0_R0_MINUS
++ I1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_R0_MINUS I1_1_1_1_1_0_R0_PLUS
++ I1_1_1_2_0_0_R0_MINUS I1_1_1_2_0_0_R0_PLUS I1_1_1_2_1_0_R0_MINUS
++ I1_1_1_2_1_0_R0_PLUS I1_1_2_0_0_0_R0_MINUS I1_1_2_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_R0_MINUS I1_1_2_0_1_0_R0_PLUS I1_1_2_1_0_0_R0_MINUS
++ I1_1_2_1_0_0_R0_PLUS I1_1_2_1_1_0_R0_MINUS I1_1_2_1_1_0_R0_PLUS
++ I1_1_2_2_0_0_R0_MINUS I1_1_2_2_0_0_R0_PLUS I1_1_2_2_1_0_R0_MINUS
++ I1_1_2_2_1_0_R0_PLUS I1_2_0_0_0_0_R0_MINUS I1_2_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_R0_MINUS I1_2_0_0_1_0_R0_PLUS I1_2_0_1_0_0_R0_MINUS
++ I1_2_0_1_0_0_R0_PLUS I1_2_0_1_1_0_R0_MINUS I1_2_0_1_1_0_R0_PLUS
++ I1_2_0_2_0_0_R0_MINUS I1_2_0_2_0_0_R0_PLUS I1_2_0_2_1_0_R0_MINUS
++ I1_2_0_2_1_0_R0_PLUS I1_2_1_0_0_0_R0_MINUS I1_2_1_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_R0_MINUS I1_2_1_0_1_0_R0_PLUS I1_2_1_1_0_0_R0_MINUS
++ I1_2_1_1_0_0_R0_PLUS I1_2_1_1_1_0_R0_MINUS I1_2_1_1_1_0_R0_PLUS
++ I1_2_1_2_0_0_R0_MINUS I1_2_1_2_0_0_R0_PLUS I1_2_1_2_1_0_R0_MINUS
++ I1_2_1_2_1_0_R0_PLUS I1_2_2_0_0_0_R0_MINUS I1_2_2_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_R0_MINUS I1_2_2_0_1_0_R0_PLUS I1_2_2_1_0_0_R0_MINUS
++ I1_2_2_1_0_0_R0_PLUS I1_2_2_1_1_0_R0_MINUS I1_2_2_1_1_0_R0_PLUS
++ I1_2_2_2_0_0_R0_MINUS I1_2_2_2_0_0_R0_PLUS I1_2_2_2_1_0_R0_MINUS
++ I1_2_2_2_1_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_R0_MINUS:I I1_0_0_0_1_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_R0_MINUS:I I1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_R0_MINUS:I I1_0_0_1_1_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_R0_MINUS:I I1_0_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_R0_MINUS:I I1_0_0_2_1_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_R0_MINUS:I I1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_R0_MINUS:I I1_0_1_0_1_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_R0_MINUS:I I1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_R0_MINUS:I I1_0_1_1_1_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_R0_MINUS:I I1_0_1_2_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_R0_MINUS:I I1_0_1_2_1_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_R0_MINUS:I I1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_R0_MINUS:I I1_0_2_0_1_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_R0_MINUS:I I1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_R0_MINUS:I I1_0_2_1_1_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_R0_MINUS:I I1_0_2_2_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_R0_MINUS:I I1_0_2_2_1_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_R0_MINUS:I I1_1_0_0_1_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_R0_MINUS:I I1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_R0_MINUS:I I1_1_0_1_1_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_R0_MINUS:I I1_1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_R0_MINUS:I I1_1_0_2_1_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_R0_MINUS:I I1_1_1_0_1_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_R0_MINUS:I I1_1_1_1_1_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_R0_MINUS:I I1_1_1_2_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_R0_MINUS:I I1_1_1_2_1_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_R0_MINUS:I I1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_R0_MINUS:I I1_1_2_0_1_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_R0_MINUS:I I1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_R0_MINUS:I I1_1_2_1_1_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_R0_MINUS:I I1_1_2_2_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_R0_MINUS:I I1_1_2_2_1_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_R0_MINUS:I I1_2_0_0_1_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_R0_MINUS:I I1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_R0_MINUS:I I1_2_0_1_1_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_R0_MINUS:I I1_2_0_2_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_R0_MINUS:I I1_2_0_2_1_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_R0_MINUS:I I1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_R0_MINUS:I I1_2_1_0_1_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_R0_MINUS:I I1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_R0_MINUS:I I1_2_1_1_1_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_R0_MINUS:I I1_2_1_2_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_R0_MINUS:I I1_2_1_2_1_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_R0_MINUS:I I1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_R0_MINUS:I I1_2_2_0_1_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_R0_MINUS:I I1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_R0_MINUS:I I1_2_2_1_1_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_R0_MINUS:I I1_2_2_2_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_R0_MINUS:I I1_2_2_2_1_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_R0 I1_2_2_2_1_0_R0_PLUS I1_2_2_2_1_0_R0_MINUS gnd!
++ nplus_u m=8.0 l=50u w=50u r=60.6187 par=8.0 s=1
+RI1_2_2_2_0_0_R0 I1_2_2_2_0_0_R0_PLUS I1_2_2_2_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=50u r=60.6187 par=1.0 s=8
+RI1_2_2_1_1_0_R0 I1_2_2_1_1_0_R0_PLUS I1_2_2_1_1_0_R0_MINUS gnd!
++ nplus_u m=3.0 l=50u w=50u r=60.6187 par=3.0 s=1
+RI1_2_2_1_0_0_R0 I1_2_2_1_0_0_R0_PLUS I1_2_2_1_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=50u r=60.6187 par=1.0 s=3
+RI1_2_2_0_1_0_R0 I1_2_2_0_1_0_R0_PLUS I1_2_2_0_1_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=50u r=60.6187 par=1.0 s=1
+RI1_2_2_0_0_0_R0 I1_2_2_0_0_0_R0_PLUS I1_2_2_0_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=50u r=60.6187 par=1.0 s=1
+RI1_2_1_2_1_0_R0 I1_2_1_2_1_0_R0_PLUS I1_2_1_2_1_0_R0_MINUS gnd!
++ nplus_u m=8.0 l=7.6u w=50u r=9.84027 par=8.0 s=1
+RI1_2_1_2_0_0_R0 I1_2_1_2_0_0_R0_PLUS I1_2_1_2_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=50u r=9.84027 par=1.0 s=8
+RI1_2_1_1_1_0_R0 I1_2_1_1_1_0_R0_PLUS I1_2_1_1_1_0_R0_MINUS gnd!
++ nplus_u m=3.0 l=7.6u w=50u r=9.84027 par=3.0 s=1
+RI1_2_1_1_0_0_R0 I1_2_1_1_0_0_R0_PLUS I1_2_1_1_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=50u r=9.84027 par=1.0 s=3
+RI1_2_1_0_1_0_R0 I1_2_1_0_1_0_R0_PLUS I1_2_1_0_1_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=50u r=9.84027 par=1.0 s=1
+RI1_2_1_0_0_0_R0 I1_2_1_0_0_0_R0_PLUS I1_2_1_0_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=50u r=9.84027 par=1.0 s=1
+RI1_2_0_2_1_0_R0 I1_2_0_2_1_0_R0_PLUS I1_2_0_2_1_0_R0_MINUS gnd!
++ nplus_u m=8.0 l=1.6u w=50u r=2.65464 par=8.0 s=1
+RI1_2_0_2_0_0_R0 I1_2_0_2_0_0_R0_PLUS I1_2_0_2_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=50u r=2.65464 par=1.0 s=8
+RI1_2_0_1_1_0_R0 I1_2_0_1_1_0_R0_PLUS I1_2_0_1_1_0_R0_MINUS gnd!
++ nplus_u m=3.0 l=1.6u w=50u r=2.65464 par=3.0 s=1
+RI1_2_0_1_0_0_R0 I1_2_0_1_0_0_R0_PLUS I1_2_0_1_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=50u r=2.65464 par=1.0 s=3
+RI1_2_0_0_1_0_R0 I1_2_0_0_1_0_R0_PLUS I1_2_0_0_1_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=50u r=2.65464 par=1.0 s=1
+RI1_2_0_0_0_0_R0 I1_2_0_0_0_0_R0_PLUS I1_2_0_0_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=50u r=2.65464 par=1.0 s=1
+RI1_1_2_2_1_0_R0 I1_1_2_2_1_0_R0_PLUS I1_1_2_2_1_0_R0_MINUS gnd!
++ nplus_u m=8.0 l=50u w=3.62u r=816.397 par=8.0 s=1
+RI1_1_2_2_0_0_R0 I1_1_2_2_0_0_R0_PLUS I1_1_2_2_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=3.62u r=816.397 par=1.0 s=8
+RI1_1_2_1_1_0_R0 I1_1_2_1_1_0_R0_PLUS I1_1_2_1_1_0_R0_MINUS gnd!
++ nplus_u m=3.0 l=50u w=3.62u r=816.397 par=3.0 s=1
+RI1_1_2_1_0_0_R0 I1_1_2_1_0_0_R0_PLUS I1_1_2_1_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=3.62u r=816.397 par=1.0 s=3
+RI1_1_2_0_1_0_R0 I1_1_2_0_1_0_R0_PLUS I1_1_2_0_1_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=3.62u r=816.397 par=1.0 s=1
+RI1_1_2_0_0_0_R0 I1_1_2_0_0_0_R0_PLUS I1_1_2_0_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=3.62u r=816.397 par=1.0 s=1
+RI1_1_1_2_1_0_R0 I1_1_1_2_1_0_R0_PLUS I1_1_1_2_1_0_R0_MINUS gnd!
++ nplus_u m=8.0 l=7.6u w=3.62u r=132.526 par=8.0 s=1
+RI1_1_1_2_0_0_R0 I1_1_1_2_0_0_R0_PLUS I1_1_1_2_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=3.62u r=132.526 par=1.0 s=8
+RI1_1_1_1_1_0_R0 I1_1_1_1_1_0_R0_PLUS I1_1_1_1_1_0_R0_MINUS gnd!
++ nplus_u m=3.0 l=7.6u w=3.62u r=132.526 par=3.0 s=1
+RI1_1_1_1_0_0_R0 I1_1_1_1_0_0_R0_PLUS I1_1_1_1_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=3.62u r=132.526 par=1.0 s=3
+RI1_1_1_0_1_0_R0 I1_1_1_0_1_0_R0_PLUS I1_1_1_0_1_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=3.62u r=132.526 par=1.0 s=1
+RI1_1_1_0_0_0_R0 I1_1_1_0_0_0_R0_PLUS I1_1_1_0_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=3.62u r=132.526 par=1.0 s=1
+RI1_1_0_2_1_0_R0 I1_1_0_2_1_0_R0_PLUS I1_1_0_2_1_0_R0_MINUS gnd!
++ nplus_u m=8.0 l=1.6u w=3.62u r=35.752 par=8.0 s=1
+RI1_1_0_2_0_0_R0 I1_1_0_2_0_0_R0_PLUS I1_1_0_2_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=3.62u r=35.752 par=1.0 s=8
+RI1_1_0_1_1_0_R0 I1_1_0_1_1_0_R0_PLUS I1_1_0_1_1_0_R0_MINUS gnd!
++ nplus_u m=3.0 l=1.6u w=3.62u r=35.752 par=3.0 s=1
+RI1_1_0_1_0_0_R0 I1_1_0_1_0_0_R0_PLUS I1_1_0_1_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=3.62u r=35.752 par=1.0 s=3
+RI1_1_0_0_1_0_R0 I1_1_0_0_1_0_R0_PLUS I1_1_0_0_1_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=3.62u r=35.752 par=1.0 s=1
+RI1_1_0_0_0_0_R0 I1_1_0_0_0_0_R0_PLUS I1_1_0_0_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=3.62u r=35.752 par=1.0 s=1
+RI1_0_2_2_1_0_R0 I1_0_2_2_1_0_R0_PLUS I1_0_2_2_1_0_R0_MINUS gnd!
++ nplus_u m=8.0 l=50u w=800n r=3.37444K par=8.0 s=1
+RI1_0_2_2_0_0_R0 I1_0_2_2_0_0_R0_PLUS I1_0_2_2_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=800n r=3.37444K par=1.0 s=8
+RI1_0_2_1_1_0_R0 I1_0_2_1_1_0_R0_PLUS I1_0_2_1_1_0_R0_MINUS gnd!
++ nplus_u m=3.0 l=50u w=800n r=3.37444K par=3.0 s=1
+RI1_0_2_1_0_0_R0 I1_0_2_1_0_0_R0_PLUS I1_0_2_1_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=800n r=3.37444K par=1.0 s=3
+RI1_0_2_0_1_0_R0 I1_0_2_0_1_0_R0_PLUS I1_0_2_0_1_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=800n r=3.37444K par=1.0 s=1
+RI1_0_2_0_0_0_R0 I1_0_2_0_0_0_R0_PLUS I1_0_2_0_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=50u w=800n r=3.37444K par=1.0 s=1
+RI1_0_1_2_1_0_R0 I1_0_1_2_1_0_R0_PLUS I1_0_1_2_1_0_R0_MINUS gnd!
++ nplus_u m=8.0 l=7.6u w=800n r=547.775 par=8.0 s=1
+RI1_0_1_2_0_0_R0 I1_0_1_2_0_0_R0_PLUS I1_0_1_2_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=800n r=547.775 par=1.0 s=8
+RI1_0_1_1_1_0_R0 I1_0_1_1_1_0_R0_PLUS I1_0_1_1_1_0_R0_MINUS gnd!
++ nplus_u m=3.0 l=7.6u w=800n r=547.775 par=3.0 s=1
+RI1_0_1_1_0_0_R0 I1_0_1_1_0_0_R0_PLUS I1_0_1_1_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=800n r=547.775 par=1.0 s=3
+RI1_0_1_0_1_0_R0 I1_0_1_0_1_0_R0_PLUS I1_0_1_0_1_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=800n r=547.775 par=1.0 s=1
+RI1_0_1_0_0_0_R0 I1_0_1_0_0_0_R0_PLUS I1_0_1_0_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=7.6u w=800n r=547.775 par=1.0 s=1
+RI1_0_0_2_1_0_R0 I1_0_0_2_1_0_R0_PLUS I1_0_0_2_1_0_R0_MINUS gnd!
++ nplus_u m=8.0 l=1.6u w=800n r=147.775 par=8.0 s=1
+RI1_0_0_2_0_0_R0 I1_0_0_2_0_0_R0_PLUS I1_0_0_2_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=800n r=147.775 par=1.0 s=8
+RI1_0_0_1_1_0_R0 I1_0_0_1_1_0_R0_PLUS I1_0_0_1_1_0_R0_MINUS gnd!
++ nplus_u m=3.0 l=1.6u w=800n r=147.775 par=3.0 s=1
+RI1_0_0_1_0_0_R0 I1_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=800n r=147.775 par=1.0 s=3
+RI1_0_0_0_1_0_R0 I1_0_0_0_1_0_R0_PLUS I1_0_0_0_1_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=800n r=147.775 par=1.0 s=1
+RI1_0_0_0_0_0_R0 I1_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_R0_MINUS gnd!
++ nplus_u m=1.0 l=1.6u w=800n r=147.775 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! nplus_u m=1.0 l=2u
++ w=1u r=142.7251 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_u_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_u_dw.cdl
new file mode 100644
index 0000000..cc9e2e7
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/nplus_u_dw.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: nplus_u_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:30:25 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: nplus_u_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT nplus_u_dw I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=8.0 l=50u w=50u r=60.6187 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=50u r=60.6187 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=3.0 l=50u w=50u r=60.6187 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=50u r=60.6187 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=50u r=60.6187 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=50u r=60.6187 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=8.0 l=7.6u w=50u r=9.84027 par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=50u r=9.84027 par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=3.0 l=7.6u w=50u r=9.84027 par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=50u r=9.84027 par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=50u r=9.84027 par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=50u r=9.84027 par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=8.0 l=1.6u w=50u r=2.65464 par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=50u r=2.65464 par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=3.0 l=1.6u w=50u r=2.65464 par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=50u r=2.65464 par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=50u r=2.65464 par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=50u r=2.65464 par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=8.0 l=50u w=3.62u r=816.397 par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=3.62u r=816.397 par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=3.0 l=50u w=3.62u r=816.397 par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=3.62u r=816.397 par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=3.62u r=816.397 par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=3.62u r=816.397 par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=8.0 l=7.6u w=3.62u r=132.526 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=3.62u r=132.526 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=3.0 l=7.6u w=3.62u r=132.526 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=3.62u r=132.526 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=3.62u r=132.526 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=3.62u r=132.526 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=8.0 l=1.6u w=3.62u r=35.752 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=3.62u r=35.752 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=3.0 l=1.6u w=3.62u r=35.752 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=3.62u r=35.752 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=3.62u r=35.752 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=3.62u r=35.752 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=8.0 l=50u w=800n r=3.37444K par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=800n r=3.37444K par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=3.0 l=50u w=800n r=3.37444K par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=800n r=3.37444K par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=800n r=3.37444K par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=50u w=800n r=3.37444K par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=8.0 l=7.6u w=800n r=547.775 par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=800n r=547.775 par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=3.0 l=7.6u w=800n r=547.775 par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=800n r=547.775 par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=800n r=547.775 par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=7.6u w=800n r=547.775 par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=8.0 l=1.6u w=800n r=147.775 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=800n r=147.775 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=3.0 l=1.6u w=800n r=147.775 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=800n r=147.775 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=800n r=147.775 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ nplus_u_dw m=1.0 l=1.6u w=800n r=147.775 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! nplus_u_dw m=1.0
++ l=2u w=1u r=142.7251 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_s.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_s.cdl
new file mode 100644
index 0000000..d11c310
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_s.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: npolyf_s
+* View Name: schematic
+* Netlisted on: Nov 24 09:31:03 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: npolyf_s
+* View Name: schematic
+************************************************************************
+
+.SUBCKT npolyf_s I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_s m=8.0 l=50u w=50u r=7.02182 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=50u r=7.02182 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_s m=3.0 l=50u w=50u r=7.02182 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=50u r=7.02182 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=50u r=7.02182 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=50u r=7.02182 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_s m=8.0 l=7.6u w=50u r=1.25392 par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=50u r=1.25392 par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_s m=3.0 l=7.6u w=50u r=1.25392 par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=50u r=1.25392 par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=50u r=1.25392 par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=50u r=1.25392 par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_s m=8.0 l=1.6u w=50u r=437.71m par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=50u r=437.71m par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_s m=3.0 l=1.6u w=50u r=437.71m par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=50u r=437.71m par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=50u r=437.71m par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=50u r=437.71m par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_s m=8.0 l=50u w=3.62u r=97.3107 par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=3.62u r=97.3107 par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_s m=3.0 l=50u w=3.62u r=97.3107 par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=3.62u r=97.3107 par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=3.62u r=97.3107 par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=3.62u r=97.3107 par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_s m=8.0 l=7.6u w=3.62u r=17.3773 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=3.62u r=17.3773 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_s m=3.0 l=7.6u w=3.62u r=17.3773 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=3.62u r=17.3773 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=3.62u r=17.3773 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=3.62u r=17.3773 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_s m=8.0 l=1.6u w=3.62u r=6.06593 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=3.62u r=6.06593 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_s m=3.0 l=1.6u w=3.62u r=6.06593 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=3.62u r=6.06593 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=3.62u r=6.06593 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=3.62u r=6.06593 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_s m=8.0 l=50u w=800n r=445.997 par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=800n r=445.997 par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_s m=3.0 l=50u w=800n r=445.997 par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=800n r=445.997 par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=800n r=445.997 par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=50u w=800n r=445.997 par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_s m=8.0 l=7.6u w=800n r=79.644 par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=800n r=79.644 par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_s m=3.0 l=7.6u w=800n r=79.644 par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=800n r=79.644 par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=800n r=79.644 par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=7.6u w=800n r=79.644 par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_s m=8.0 l=1.6u w=800n r=27.8015 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=800n r=27.8015 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_s m=3.0 l=1.6u w=800n r=27.8015 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=800n r=27.8015 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=800n r=27.8015 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_s m=1.0 l=1.6u w=800n r=27.8015 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! npolyf_s m=1.0
++ l=1.6u w=800.0n r=27.8015 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_s_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_s_dw.cdl
new file mode 100644
index 0000000..528cb97
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_s_dw.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: npolyf_s_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:31:45 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: npolyf_s_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT npolyf_s_dw I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=8.0 l=50u w=50u r=7.02182 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=50u r=7.02182 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=3.0 l=50u w=50u r=7.02182 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=50u r=7.02182 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=50u r=7.02182 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=50u r=7.02182 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=8.0 l=7.6u w=50u r=1.25392 par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=50u r=1.25392 par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=3.0 l=7.6u w=50u r=1.25392 par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=50u r=1.25392 par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=50u r=1.25392 par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=50u r=1.25392 par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=8.0 l=1.6u w=50u r=437.71m par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=50u r=437.71m par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=3.0 l=1.6u w=50u r=437.71m par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=50u r=437.71m par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=50u r=437.71m par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=50u r=437.71m par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=8.0 l=50u w=3.62u r=97.3107 par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=3.62u r=97.3107 par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=3.0 l=50u w=3.62u r=97.3107 par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=3.62u r=97.3107 par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=3.62u r=97.3107 par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=3.62u r=97.3107 par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=8.0 l=7.6u w=3.62u r=17.3773 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=3.62u r=17.3773 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=3.0 l=7.6u w=3.62u r=17.3773 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=3.62u r=17.3773 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=3.62u r=17.3773 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=3.62u r=17.3773 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=8.0 l=1.6u w=3.62u r=6.06593 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=3.62u r=6.06593 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=3.0 l=1.6u w=3.62u r=6.06593 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=3.62u r=6.06593 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=3.62u r=6.06593 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=3.62u r=6.06593 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=8.0 l=50u w=800n r=445.997 par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=800n r=445.997 par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=3.0 l=50u w=800n r=445.997 par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=800n r=445.997 par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=800n r=445.997 par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=50u w=800n r=445.997 par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=8.0 l=7.6u w=800n r=79.644 par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=800n r=79.644 par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=3.0 l=7.6u w=800n r=79.644 par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=800n r=79.644 par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=800n r=79.644 par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=7.6u w=800n r=79.644 par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=8.0 l=1.6u w=800n r=27.8015 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=800n r=27.8015 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=3.0 l=1.6u w=800n r=27.8015 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=800n r=27.8015 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=800n r=27.8015 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_s_dw m=1.0 l=1.6u w=800n r=27.8015 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! npolyf_s_dw m=1.0
++ l=1.6u w=800.0n r=27.8015 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_u.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_u.cdl
new file mode 100644
index 0000000..6b1c7fa
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_u.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: npolyf_u
+* View Name: schematic
+* Netlisted on: Nov 24 09:35:58 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: npolyf_u
+* View Name: schematic
+************************************************************************
+
+.SUBCKT npolyf_u I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_u m=8.0 l=50u w=50u r=311.93 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=50u r=311.93 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_u m=3.0 l=50u w=50u r=311.93 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=50u r=311.93 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=50u r=311.93 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=50u r=311.93 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_u m=8.0 l=7.6u w=50u r=48.7706 par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=50u r=48.7706 par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_u m=3.0 l=7.6u w=50u r=48.7706 par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=50u r=48.7706 par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=50u r=48.7706 par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=50u r=48.7706 par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_u m=8.0 l=1.6u w=50u r=11.5312 par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=50u r=11.5312 par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_u m=3.0 l=1.6u w=50u r=11.5312 par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=50u r=11.5312 par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=50u r=11.5312 par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=50u r=11.5312 par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_u m=8.0 l=50u w=3.62u r=4.3678K par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=3.62u r=4.3678K par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_u m=3.0 l=50u w=3.62u r=4.3678K par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=3.62u r=4.3678K par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=3.62u r=4.3678K par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=3.62u r=4.3678K par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_u m=8.0 l=7.6u w=3.62u r=682.912 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=3.62u r=682.912 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_u m=3.0 l=7.6u w=3.62u r=682.912 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=3.62u r=682.912 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=3.62u r=682.912 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=3.62u r=682.912 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_u m=8.0 l=1.6u w=3.62u r=161.465 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=3.62u r=161.465 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_u m=3.0 l=1.6u w=3.62u r=161.465 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=3.62u r=161.465 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=3.62u r=161.465 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=3.62u r=161.465 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_u m=8.0 l=50u w=800n r=20.8567K par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=800n r=20.8567K par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_u m=3.0 l=50u w=800n r=20.8567K par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=800n r=20.8567K par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=800n r=20.8567K par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=50u w=800n r=20.8567K par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_u m=8.0 l=7.6u w=800n r=3.26097K par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=800n r=3.26097K par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_u m=3.0 l=7.6u w=800n r=3.26097K par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=800n r=3.26097K par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=800n r=3.26097K par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=7.6u w=800n r=3.26097K par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_u m=8.0 l=1.6u w=800n r=771.014 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=800n r=771.014 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_u m=3.0 l=1.6u w=800n r=771.014 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=800n r=771.014 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=800n r=771.014 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_u m=1.0 l=1.6u w=800n r=771.014 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! npolyf_u m=1.0
++ l=1.6u w=800.0n r=771.014 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_u_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_u_dw.cdl
new file mode 100644
index 0000000..f1000fb
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/npolyf_u_dw.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: npolyf_u_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:40:44 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: npolyf_u_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT npolyf_u_dw I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=8.0 l=50u w=50u r=311.93 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=50u r=311.93 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=3.0 l=50u w=50u r=311.93 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=50u r=311.93 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=50u r=311.93 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=50u r=311.93 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=8.0 l=7.6u w=50u r=48.7706 par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=50u r=48.7706 par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=3.0 l=7.6u w=50u r=48.7706 par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=50u r=48.7706 par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=50u r=48.7706 par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=50u r=48.7706 par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=8.0 l=1.6u w=50u r=11.5312 par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=50u r=11.5312 par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=3.0 l=1.6u w=50u r=11.5312 par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=50u r=11.5312 par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=50u r=11.5312 par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=50u r=11.5312 par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=8.0 l=50u w=3.62u r=4.3678K par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=3.62u r=4.3678K par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=3.0 l=50u w=3.62u r=4.3678K par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=3.62u r=4.3678K par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=3.62u r=4.3678K par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=3.62u r=4.3678K par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=8.0 l=7.6u w=3.62u r=682.912 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=3.62u r=682.912 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=3.0 l=7.6u w=3.62u r=682.912 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=3.62u r=682.912 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=3.62u r=682.912 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=3.62u r=682.912 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=8.0 l=1.6u w=3.62u r=161.465 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=3.62u r=161.465 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=3.0 l=1.6u w=3.62u r=161.465 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=3.62u r=161.465 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=3.62u r=161.465 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=3.62u r=161.465 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=8.0 l=50u w=800n r=20.8567K par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=800n r=20.8567K par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=3.0 l=50u w=800n r=20.8567K par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=800n r=20.8567K par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=800n r=20.8567K par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=50u w=800n r=20.8567K par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=8.0 l=7.6u w=800n r=3.26097K par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=800n r=3.26097K par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=3.0 l=7.6u w=800n r=3.26097K par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=800n r=3.26097K par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=800n r=3.26097K par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=7.6u w=800n r=3.26097K par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=8.0 l=1.6u w=800n r=771.014 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=800n r=771.014 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=3.0 l=1.6u w=800n r=771.014 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=800n r=771.014 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=800n r=771.014 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ npolyf_u_dw m=1.0 l=1.6u w=800n r=771.014 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! npolyf_u_dw m=1.0
++ l=1.6u w=800.0n r=771.014 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_s.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_s.cdl
new file mode 100644
index 0000000..a0b8ed1
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_s.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pplus_s
+* View Name: schematic
+* Netlisted on: Nov 24 09:51:48 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pplus_s
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pplus_s I1_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_R0_MINUS I1_0_0_0_1_0_R0_PLUS I1_0_0_1_0_0_R0_MINUS
++ I1_0_0_1_0_0_R0_PLUS I1_0_0_1_1_0_R0_MINUS I1_0_0_1_1_0_R0_PLUS
++ I1_0_0_2_0_0_R0_MINUS I1_0_0_2_0_0_R0_PLUS I1_0_0_2_1_0_R0_MINUS
++ I1_0_0_2_1_0_R0_PLUS I1_0_1_0_0_0_R0_MINUS I1_0_1_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_R0_MINUS I1_0_1_0_1_0_R0_PLUS I1_0_1_1_0_0_R0_MINUS
++ I1_0_1_1_0_0_R0_PLUS I1_0_1_1_1_0_R0_MINUS I1_0_1_1_1_0_R0_PLUS
++ I1_0_1_2_0_0_R0_MINUS I1_0_1_2_0_0_R0_PLUS I1_0_1_2_1_0_R0_MINUS
++ I1_0_1_2_1_0_R0_PLUS I1_0_2_0_0_0_R0_MINUS I1_0_2_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_R0_MINUS I1_0_2_0_1_0_R0_PLUS I1_0_2_1_0_0_R0_MINUS
++ I1_0_2_1_0_0_R0_PLUS I1_0_2_1_1_0_R0_MINUS I1_0_2_1_1_0_R0_PLUS
++ I1_0_2_2_0_0_R0_MINUS I1_0_2_2_0_0_R0_PLUS I1_0_2_2_1_0_R0_MINUS
++ I1_0_2_2_1_0_R0_PLUS I1_1_0_0_0_0_R0_MINUS I1_1_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_R0_MINUS I1_1_0_0_1_0_R0_PLUS I1_1_0_1_0_0_R0_MINUS
++ I1_1_0_1_0_0_R0_PLUS I1_1_0_1_1_0_R0_MINUS I1_1_0_1_1_0_R0_PLUS
++ I1_1_0_2_0_0_R0_MINUS I1_1_0_2_0_0_R0_PLUS I1_1_0_2_1_0_R0_MINUS
++ I1_1_0_2_1_0_R0_PLUS I1_1_1_0_0_0_R0_MINUS I1_1_1_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_R0_MINUS I1_1_1_0_1_0_R0_PLUS I1_1_1_1_0_0_R0_MINUS
++ I1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_R0_MINUS I1_1_1_1_1_0_R0_PLUS
++ I1_1_1_2_0_0_R0_MINUS I1_1_1_2_0_0_R0_PLUS I1_1_1_2_1_0_R0_MINUS
++ I1_1_1_2_1_0_R0_PLUS I1_1_2_0_0_0_R0_MINUS I1_1_2_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_R0_MINUS I1_1_2_0_1_0_R0_PLUS I1_1_2_1_0_0_R0_MINUS
++ I1_1_2_1_0_0_R0_PLUS I1_1_2_1_1_0_R0_MINUS I1_1_2_1_1_0_R0_PLUS
++ I1_1_2_2_0_0_R0_MINUS I1_1_2_2_0_0_R0_PLUS I1_1_2_2_1_0_R0_MINUS
++ I1_1_2_2_1_0_R0_PLUS I1_2_0_0_0_0_R0_MINUS I1_2_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_R0_MINUS I1_2_0_0_1_0_R0_PLUS I1_2_0_1_0_0_R0_MINUS
++ I1_2_0_1_0_0_R0_PLUS I1_2_0_1_1_0_R0_MINUS I1_2_0_1_1_0_R0_PLUS
++ I1_2_0_2_0_0_R0_MINUS I1_2_0_2_0_0_R0_PLUS I1_2_0_2_1_0_R0_MINUS
++ I1_2_0_2_1_0_R0_PLUS I1_2_1_0_0_0_R0_MINUS I1_2_1_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_R0_MINUS I1_2_1_0_1_0_R0_PLUS I1_2_1_1_0_0_R0_MINUS
++ I1_2_1_1_0_0_R0_PLUS I1_2_1_1_1_0_R0_MINUS I1_2_1_1_1_0_R0_PLUS
++ I1_2_1_2_0_0_R0_MINUS I1_2_1_2_0_0_R0_PLUS I1_2_1_2_1_0_R0_MINUS
++ I1_2_1_2_1_0_R0_PLUS I1_2_2_0_0_0_R0_MINUS I1_2_2_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_R0_MINUS I1_2_2_0_1_0_R0_PLUS I1_2_2_1_0_0_R0_MINUS
++ I1_2_2_1_0_0_R0_PLUS I1_2_2_1_1_0_R0_MINUS I1_2_2_1_1_0_R0_PLUS
++ I1_2_2_2_0_0_R0_MINUS I1_2_2_2_0_0_R0_PLUS I1_2_2_2_1_0_R0_MINUS
++ I1_2_2_2_1_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_R0_MINUS:I I1_0_0_0_1_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_R0_MINUS:I I1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_R0_MINUS:I I1_0_0_1_1_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_R0_MINUS:I I1_0_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_R0_MINUS:I I1_0_0_2_1_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_R0_MINUS:I I1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_R0_MINUS:I I1_0_1_0_1_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_R0_MINUS:I I1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_R0_MINUS:I I1_0_1_1_1_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_R0_MINUS:I I1_0_1_2_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_R0_MINUS:I I1_0_1_2_1_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_R0_MINUS:I I1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_R0_MINUS:I I1_0_2_0_1_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_R0_MINUS:I I1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_R0_MINUS:I I1_0_2_1_1_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_R0_MINUS:I I1_0_2_2_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_R0_MINUS:I I1_0_2_2_1_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_R0_MINUS:I I1_1_0_0_1_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_R0_MINUS:I I1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_R0_MINUS:I I1_1_0_1_1_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_R0_MINUS:I I1_1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_R0_MINUS:I I1_1_0_2_1_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_R0_MINUS:I I1_1_1_0_1_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_R0_MINUS:I I1_1_1_1_1_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_R0_MINUS:I I1_1_1_2_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_R0_MINUS:I I1_1_1_2_1_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_R0_MINUS:I I1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_R0_MINUS:I I1_1_2_0_1_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_R0_MINUS:I I1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_R0_MINUS:I I1_1_2_1_1_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_R0_MINUS:I I1_1_2_2_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_R0_MINUS:I I1_1_2_2_1_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_R0_MINUS:I I1_2_0_0_1_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_R0_MINUS:I I1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_R0_MINUS:I I1_2_0_1_1_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_R0_MINUS:I I1_2_0_2_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_R0_MINUS:I I1_2_0_2_1_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_R0_MINUS:I I1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_R0_MINUS:I I1_2_1_0_1_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_R0_MINUS:I I1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_R0_MINUS:I I1_2_1_1_1_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_R0_MINUS:I I1_2_1_2_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_R0_MINUS:I I1_2_1_2_1_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_R0_MINUS:I I1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_R0_MINUS:I I1_2_2_0_1_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_R0_MINUS:I I1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_R0_MINUS:I I1_2_2_1_1_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_R0_MINUS:I I1_2_2_2_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_R0_MINUS:I I1_2_2_2_1_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_R0 I1_2_2_2_1_0_R0_PLUS I1_2_2_2_1_0_R0_MINUS gnd!
++ pplus_s m=8.0 l=50u w=50u r=7.2455 par=8.0 s=1
+RI1_2_2_2_0_0_R0 I1_2_2_2_0_0_R0_PLUS I1_2_2_2_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=50u r=7.2455 par=1.0 s=8
+RI1_2_2_1_1_0_R0 I1_2_2_1_1_0_R0_PLUS I1_2_2_1_1_0_R0_MINUS gnd!
++ pplus_s m=3.0 l=50u w=50u r=7.2455 par=3.0 s=1
+RI1_2_2_1_0_0_R0 I1_2_2_1_0_0_R0_PLUS I1_2_2_1_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=50u r=7.2455 par=1.0 s=3
+RI1_2_2_0_1_0_R0 I1_2_2_0_1_0_R0_PLUS I1_2_2_0_1_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=50u r=7.2455 par=1.0 s=1
+RI1_2_2_0_0_0_R0 I1_2_2_0_0_0_R0_PLUS I1_2_2_0_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=50u r=7.2455 par=1.0 s=1
+RI1_2_1_2_1_0_R0 I1_2_1_2_1_0_R0_PLUS I1_2_1_2_1_0_R0_MINUS gnd!
++ pplus_s m=8.0 l=2.6u w=50u r=622.745m par=8.0 s=1
+RI1_2_1_2_0_0_R0 I1_2_1_2_0_0_R0_PLUS I1_2_1_2_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=50u r=622.745m par=1.0 s=8
+RI1_2_1_1_1_0_R0 I1_2_1_1_1_0_R0_PLUS I1_2_1_1_1_0_R0_MINUS gnd!
++ pplus_s m=3.0 l=2.6u w=50u r=622.745m par=3.0 s=1
+RI1_2_1_1_0_0_R0 I1_2_1_1_0_0_R0_PLUS I1_2_1_1_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=50u r=622.745m par=1.0 s=3
+RI1_2_1_0_1_0_R0 I1_2_1_0_1_0_R0_PLUS I1_2_1_0_1_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=50u r=622.745m par=1.0 s=1
+RI1_2_1_0_0_0_R0 I1_2_1_0_0_0_R0_PLUS I1_2_1_0_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=50u r=622.745m par=1.0 s=1
+RI1_2_0_2_1_0_R0 I1_2_0_2_1_0_R0_PLUS I1_2_0_2_1_0_R0_MINUS gnd!
++ pplus_s m=8.0 l=840n w=50u r=376.837m par=8.0 s=1
+RI1_2_0_2_0_0_R0 I1_2_0_2_0_0_R0_PLUS I1_2_0_2_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=50u r=376.837m par=1.0 s=8
+RI1_2_0_1_1_0_R0 I1_2_0_1_1_0_R0_PLUS I1_2_0_1_1_0_R0_MINUS gnd!
++ pplus_s m=3.0 l=840n w=50u r=376.837m par=3.0 s=1
+RI1_2_0_1_0_0_R0 I1_2_0_1_0_0_R0_PLUS I1_2_0_1_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=50u r=376.837m par=1.0 s=3
+RI1_2_0_0_1_0_R0 I1_2_0_0_1_0_R0_PLUS I1_2_0_0_1_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=50u r=376.837m par=1.0 s=1
+RI1_2_0_0_0_0_R0 I1_2_0_0_0_0_R0_PLUS I1_2_0_0_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=50u r=376.837m par=1.0 s=1
+RI1_1_2_2_1_0_R0 I1_1_2_2_1_0_R0_PLUS I1_1_2_2_1_0_R0_MINUS gnd!
++ pplus_s m=8.0 l=50u w=1.57u r=217.365 par=8.0 s=1
+RI1_1_2_2_0_0_R0 I1_1_2_2_0_0_R0_PLUS I1_1_2_2_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=1.57u r=217.365 par=1.0 s=8
+RI1_1_2_1_1_0_R0 I1_1_2_1_1_0_R0_PLUS I1_1_2_1_1_0_R0_MINUS gnd!
++ pplus_s m=3.0 l=50u w=1.57u r=217.365 par=3.0 s=1
+RI1_1_2_1_0_0_R0 I1_1_2_1_0_0_R0_PLUS I1_1_2_1_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=1.57u r=217.365 par=1.0 s=3
+RI1_1_2_0_1_0_R0 I1_1_2_0_1_0_R0_PLUS I1_1_2_0_1_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=1.57u r=217.365 par=1.0 s=1
+RI1_1_2_0_0_0_R0 I1_1_2_0_0_0_R0_PLUS I1_1_2_0_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=1.57u r=217.365 par=1.0 s=1
+RI1_1_1_2_1_0_R0 I1_1_1_2_1_0_R0_PLUS I1_1_1_2_1_0_R0_MINUS gnd!
++ pplus_s m=8.0 l=2.6u w=1.57u r=18.6823 par=8.0 s=1
+RI1_1_1_2_0_0_R0 I1_1_1_2_0_0_R0_PLUS I1_1_1_2_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=1.57u r=18.6823 par=1.0 s=8
+RI1_1_1_1_1_0_R0 I1_1_1_1_1_0_R0_PLUS I1_1_1_1_1_0_R0_MINUS gnd!
++ pplus_s m=3.0 l=2.6u w=1.57u r=18.6823 par=3.0 s=1
+RI1_1_1_1_0_0_R0 I1_1_1_1_0_0_R0_PLUS I1_1_1_1_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=1.57u r=18.6823 par=1.0 s=3
+RI1_1_1_0_1_0_R0 I1_1_1_0_1_0_R0_PLUS I1_1_1_0_1_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=1.57u r=18.6823 par=1.0 s=1
+RI1_1_1_0_0_0_R0 I1_1_1_0_0_0_R0_PLUS I1_1_1_0_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=1.57u r=18.6823 par=1.0 s=1
+RI1_1_0_2_1_0_R0 I1_1_0_2_1_0_R0_PLUS I1_1_0_2_1_0_R0_MINUS gnd!
++ pplus_s m=8.0 l=840n w=1.57u r=11.3051 par=8.0 s=1
+RI1_1_0_2_0_0_R0 I1_1_0_2_0_0_R0_PLUS I1_1_0_2_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=1.57u r=11.3051 par=1.0 s=8
+RI1_1_0_1_1_0_R0 I1_1_0_1_1_0_R0_PLUS I1_1_0_1_1_0_R0_MINUS gnd!
++ pplus_s m=3.0 l=840n w=1.57u r=11.3051 par=3.0 s=1
+RI1_1_0_1_0_0_R0 I1_1_0_1_0_0_R0_PLUS I1_1_0_1_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=1.57u r=11.3051 par=1.0 s=3
+RI1_1_0_0_1_0_R0 I1_1_0_0_1_0_R0_PLUS I1_1_0_0_1_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=1.57u r=11.3051 par=1.0 s=1
+RI1_1_0_0_0_0_R0 I1_1_0_0_0_0_R0_PLUS I1_1_0_0_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=1.57u r=11.3051 par=1.0 s=1
+RI1_0_2_2_1_0_R0 I1_0_2_2_1_0_R0_PLUS I1_0_2_2_1_0_R0_MINUS gnd!
++ pplus_s m=8.0 l=50u w=420n r=698.076 par=8.0 s=1
+RI1_0_2_2_0_0_R0 I1_0_2_2_0_0_R0_PLUS I1_0_2_2_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=420n r=698.076 par=1.0 s=8
+RI1_0_2_1_1_0_R0 I1_0_2_1_1_0_R0_PLUS I1_0_2_1_1_0_R0_MINUS gnd!
++ pplus_s m=3.0 l=50u w=420n r=698.076 par=3.0 s=1
+RI1_0_2_1_0_0_R0 I1_0_2_1_0_0_R0_PLUS I1_0_2_1_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=420n r=698.076 par=1.0 s=3
+RI1_0_2_0_1_0_R0 I1_0_2_0_1_0_R0_PLUS I1_0_2_0_1_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=420n r=698.076 par=1.0 s=1
+RI1_0_2_0_0_0_R0 I1_0_2_0_0_0_R0_PLUS I1_0_2_0_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=50u w=420n r=698.076 par=1.0 s=1
+RI1_0_1_2_1_0_R0 I1_0_1_2_1_0_R0_PLUS I1_0_1_2_1_0_R0_MINUS gnd!
++ pplus_s m=8.0 l=2.6u w=420n r=59.9991 par=8.0 s=1
+RI1_0_1_2_0_0_R0 I1_0_1_2_0_0_R0_PLUS I1_0_1_2_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=420n r=59.9991 par=1.0 s=8
+RI1_0_1_1_1_0_R0 I1_0_1_1_1_0_R0_PLUS I1_0_1_1_1_0_R0_MINUS gnd!
++ pplus_s m=3.0 l=2.6u w=420n r=59.9991 par=3.0 s=1
+RI1_0_1_1_0_0_R0 I1_0_1_1_0_0_R0_PLUS I1_0_1_1_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=420n r=59.9991 par=1.0 s=3
+RI1_0_1_0_1_0_R0 I1_0_1_0_1_0_R0_PLUS I1_0_1_0_1_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=420n r=59.9991 par=1.0 s=1
+RI1_0_1_0_0_0_R0 I1_0_1_0_0_0_R0_PLUS I1_0_1_0_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=2.6u w=420n r=59.9991 par=1.0 s=1
+RI1_0_0_2_1_0_R0 I1_0_0_2_1_0_R0_PLUS I1_0_0_2_1_0_R0_MINUS gnd!
++ pplus_s m=8.0 l=840n w=420n r=36.3068 par=8.0 s=1
+RI1_0_0_2_0_0_R0 I1_0_0_2_0_0_R0_PLUS I1_0_0_2_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=420n r=36.3068 par=1.0 s=8
+RI1_0_0_1_1_0_R0 I1_0_0_1_1_0_R0_PLUS I1_0_0_1_1_0_R0_MINUS gnd!
++ pplus_s m=3.0 l=840n w=420n r=36.3068 par=3.0 s=1
+RI1_0_0_1_0_0_R0 I1_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=420n r=36.3068 par=1.0 s=3
+RI1_0_0_0_1_0_R0 I1_0_0_0_1_0_R0_PLUS I1_0_0_0_1_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=420n r=36.3068 par=1.0 s=1
+RI1_0_0_0_0_0_R0 I1_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_R0_MINUS gnd!
++ pplus_s m=1.0 l=840n w=420n r=36.3068 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! pplus_s m=1.0
++ l=840.00n w=420.00n r=36.3067 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_s_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_s_dw.cdl
new file mode 100644
index 0000000..189dbce
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_s_dw.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pplus_s_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:52:12 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pplus_s_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pplus_s_dw I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=8.0 l=50u w=50u r=7.2455 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=50u r=7.2455 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=3.0 l=50u w=50u r=7.2455 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=50u r=7.2455 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=50u r=7.2455 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=50u r=7.2455 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=8.0 l=2.6u w=50u r=622.745m par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=50u r=622.745m par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=3.0 l=2.6u w=50u r=622.745m par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=50u r=622.745m par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=50u r=622.745m par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=50u r=622.745m par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=8.0 l=840n w=50u r=376.837m par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=50u r=376.837m par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=3.0 l=840n w=50u r=376.837m par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=50u r=376.837m par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=50u r=376.837m par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=50u r=376.837m par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=8.0 l=50u w=1.57u r=217.365 par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=1.57u r=217.365 par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=3.0 l=50u w=1.57u r=217.365 par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=1.57u r=217.365 par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=1.57u r=217.365 par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=1.57u r=217.365 par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=8.0 l=2.6u w=1.57u r=18.6823 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=1.57u r=18.6823 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=3.0 l=2.6u w=1.57u r=18.6823 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=1.57u r=18.6823 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=1.57u r=18.6823 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=1.57u r=18.6823 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=8.0 l=840n w=1.57u r=11.3051 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=1.57u r=11.3051 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=3.0 l=840n w=1.57u r=11.3051 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=1.57u r=11.3051 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=1.57u r=11.3051 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=1.57u r=11.3051 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=8.0 l=50u w=420n r=698.076 par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=420n r=698.076 par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=3.0 l=50u w=420n r=698.076 par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=420n r=698.076 par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=420n r=698.076 par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=50u w=420n r=698.076 par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=8.0 l=2.6u w=420n r=59.9991 par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=420n r=59.9991 par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=3.0 l=2.6u w=420n r=59.9991 par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=420n r=59.9991 par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=420n r=59.9991 par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=2.6u w=420n r=59.9991 par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=8.0 l=840n w=420n r=36.3068 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=420n r=36.3068 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=3.0 l=840n w=420n r=36.3068 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=420n r=36.3068 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=420n r=36.3068 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ pplus_s_dw m=1.0 l=840n w=420n r=36.3068 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! pplus_s_dw m=1.0
++ l=840.00n w=420.00n r=36.3067 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_u.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_u.cdl
new file mode 100644
index 0000000..4b2a332
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_u.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pplus_u
+* View Name: schematic
+* Netlisted on: Nov 24 09:54:02 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pplus_u
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pplus_u I1_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_R0_MINUS I1_0_0_0_1_0_R0_PLUS I1_0_0_1_0_0_R0_MINUS
++ I1_0_0_1_0_0_R0_PLUS I1_0_0_1_1_0_R0_MINUS I1_0_0_1_1_0_R0_PLUS
++ I1_0_0_2_0_0_R0_MINUS I1_0_0_2_0_0_R0_PLUS I1_0_0_2_1_0_R0_MINUS
++ I1_0_0_2_1_0_R0_PLUS I1_0_1_0_0_0_R0_MINUS I1_0_1_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_R0_MINUS I1_0_1_0_1_0_R0_PLUS I1_0_1_1_0_0_R0_MINUS
++ I1_0_1_1_0_0_R0_PLUS I1_0_1_1_1_0_R0_MINUS I1_0_1_1_1_0_R0_PLUS
++ I1_0_1_2_0_0_R0_MINUS I1_0_1_2_0_0_R0_PLUS I1_0_1_2_1_0_R0_MINUS
++ I1_0_1_2_1_0_R0_PLUS I1_0_2_0_0_0_R0_MINUS I1_0_2_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_R0_MINUS I1_0_2_0_1_0_R0_PLUS I1_0_2_1_0_0_R0_MINUS
++ I1_0_2_1_0_0_R0_PLUS I1_0_2_1_1_0_R0_MINUS I1_0_2_1_1_0_R0_PLUS
++ I1_0_2_2_0_0_R0_MINUS I1_0_2_2_0_0_R0_PLUS I1_0_2_2_1_0_R0_MINUS
++ I1_0_2_2_1_0_R0_PLUS I1_1_0_0_0_0_R0_MINUS I1_1_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_R0_MINUS I1_1_0_0_1_0_R0_PLUS I1_1_0_1_0_0_R0_MINUS
++ I1_1_0_1_0_0_R0_PLUS I1_1_0_1_1_0_R0_MINUS I1_1_0_1_1_0_R0_PLUS
++ I1_1_0_2_0_0_R0_MINUS I1_1_0_2_0_0_R0_PLUS I1_1_0_2_1_0_R0_MINUS
++ I1_1_0_2_1_0_R0_PLUS I1_1_1_0_0_0_R0_MINUS I1_1_1_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_R0_MINUS I1_1_1_0_1_0_R0_PLUS I1_1_1_1_0_0_R0_MINUS
++ I1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_R0_MINUS I1_1_1_1_1_0_R0_PLUS
++ I1_1_1_2_0_0_R0_MINUS I1_1_1_2_0_0_R0_PLUS I1_1_1_2_1_0_R0_MINUS
++ I1_1_1_2_1_0_R0_PLUS I1_1_2_0_0_0_R0_MINUS I1_1_2_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_R0_MINUS I1_1_2_0_1_0_R0_PLUS I1_1_2_1_0_0_R0_MINUS
++ I1_1_2_1_0_0_R0_PLUS I1_1_2_1_1_0_R0_MINUS I1_1_2_1_1_0_R0_PLUS
++ I1_1_2_2_0_0_R0_MINUS I1_1_2_2_0_0_R0_PLUS I1_1_2_2_1_0_R0_MINUS
++ I1_1_2_2_1_0_R0_PLUS I1_2_0_0_0_0_R0_MINUS I1_2_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_R0_MINUS I1_2_0_0_1_0_R0_PLUS I1_2_0_1_0_0_R0_MINUS
++ I1_2_0_1_0_0_R0_PLUS I1_2_0_1_1_0_R0_MINUS I1_2_0_1_1_0_R0_PLUS
++ I1_2_0_2_0_0_R0_MINUS I1_2_0_2_0_0_R0_PLUS I1_2_0_2_1_0_R0_MINUS
++ I1_2_0_2_1_0_R0_PLUS I1_2_1_0_0_0_R0_MINUS I1_2_1_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_R0_MINUS I1_2_1_0_1_0_R0_PLUS I1_2_1_1_0_0_R0_MINUS
++ I1_2_1_1_0_0_R0_PLUS I1_2_1_1_1_0_R0_MINUS I1_2_1_1_1_0_R0_PLUS
++ I1_2_1_2_0_0_R0_MINUS I1_2_1_2_0_0_R0_PLUS I1_2_1_2_1_0_R0_MINUS
++ I1_2_1_2_1_0_R0_PLUS I1_2_2_0_0_0_R0_MINUS I1_2_2_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_R0_MINUS I1_2_2_0_1_0_R0_PLUS I1_2_2_1_0_0_R0_MINUS
++ I1_2_2_1_0_0_R0_PLUS I1_2_2_1_1_0_R0_MINUS I1_2_2_1_1_0_R0_PLUS
++ I1_2_2_2_0_0_R0_MINUS I1_2_2_2_0_0_R0_PLUS I1_2_2_2_1_0_R0_MINUS
++ I1_2_2_2_1_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_R0_MINUS:I I1_0_0_0_1_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_R0_MINUS:I I1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_R0_MINUS:I I1_0_0_1_1_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_R0_MINUS:I I1_0_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_R0_MINUS:I I1_0_0_2_1_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_R0_MINUS:I I1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_R0_MINUS:I I1_0_1_0_1_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_R0_MINUS:I I1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_R0_MINUS:I I1_0_1_1_1_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_R0_MINUS:I I1_0_1_2_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_R0_MINUS:I I1_0_1_2_1_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_R0_MINUS:I I1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_R0_MINUS:I I1_0_2_0_1_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_R0_MINUS:I I1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_R0_MINUS:I I1_0_2_1_1_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_R0_MINUS:I I1_0_2_2_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_R0_MINUS:I I1_0_2_2_1_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_R0_MINUS:I I1_1_0_0_1_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_R0_MINUS:I I1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_R0_MINUS:I I1_1_0_1_1_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_R0_MINUS:I I1_1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_R0_MINUS:I I1_1_0_2_1_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_R0_MINUS:I I1_1_1_0_1_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_R0_MINUS:I I1_1_1_1_1_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_R0_MINUS:I I1_1_1_2_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_R0_MINUS:I I1_1_1_2_1_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_R0_MINUS:I I1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_R0_MINUS:I I1_1_2_0_1_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_R0_MINUS:I I1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_R0_MINUS:I I1_1_2_1_1_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_R0_MINUS:I I1_1_2_2_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_R0_MINUS:I I1_1_2_2_1_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_R0_MINUS:I I1_2_0_0_1_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_R0_MINUS:I I1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_R0_MINUS:I I1_2_0_1_1_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_R0_MINUS:I I1_2_0_2_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_R0_MINUS:I I1_2_0_2_1_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_R0_MINUS:I I1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_R0_MINUS:I I1_2_1_0_1_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_R0_MINUS:I I1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_R0_MINUS:I I1_2_1_1_1_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_R0_MINUS:I I1_2_1_2_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_R0_MINUS:I I1_2_1_2_1_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_R0_MINUS:I I1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_R0_MINUS:I I1_2_2_0_1_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_R0_MINUS:I I1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_R0_MINUS:I I1_2_2_1_1_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_R0_MINUS:I I1_2_2_2_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_R0_MINUS:I I1_2_2_2_1_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_R0 I1_2_2_2_1_0_R0_PLUS I1_2_2_2_1_0_R0_MINUS gnd!
++ pplus_u m=8.0 l=50u w=50u r=187.206 par=8.0 s=1
+RI1_2_2_2_0_0_R0 I1_2_2_2_0_0_R0_PLUS I1_2_2_2_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=50u r=187.206 par=1.0 s=8
+RI1_2_2_1_1_0_R0 I1_2_2_1_1_0_R0_PLUS I1_2_2_1_1_0_R0_MINUS gnd!
++ pplus_u m=3.0 l=50u w=50u r=187.206 par=3.0 s=1
+RI1_2_2_1_0_0_R0 I1_2_2_1_0_0_R0_PLUS I1_2_2_1_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=50u r=187.206 par=1.0 s=3
+RI1_2_2_0_1_0_R0 I1_2_2_0_1_0_R0_PLUS I1_2_2_0_1_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=50u r=187.206 par=1.0 s=1
+RI1_2_2_0_0_0_R0 I1_2_2_0_0_0_R0_PLUS I1_2_2_0_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=50u r=187.206 par=1.0 s=1
+RI1_2_1_2_1_0_R0 I1_2_1_2_1_0_R0_PLUS I1_2_1_2_1_0_R0_MINUS gnd!
++ pplus_u m=8.0 l=7.6u w=50u r=30.1528 par=8.0 s=1
+RI1_2_1_2_0_0_R0 I1_2_1_2_0_0_R0_PLUS I1_2_1_2_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=50u r=30.1528 par=1.0 s=8
+RI1_2_1_1_1_0_R0 I1_2_1_1_1_0_R0_PLUS I1_2_1_1_1_0_R0_MINUS gnd!
++ pplus_u m=3.0 l=7.6u w=50u r=30.1528 par=3.0 s=1
+RI1_2_1_1_0_0_R0 I1_2_1_1_0_0_R0_PLUS I1_2_1_1_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=50u r=30.1528 par=1.0 s=3
+RI1_2_1_0_1_0_R0 I1_2_1_0_1_0_R0_PLUS I1_2_1_0_1_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=50u r=30.1528 par=1.0 s=1
+RI1_2_1_0_0_0_R0 I1_2_1_0_0_0_R0_PLUS I1_2_1_0_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=50u r=30.1528 par=1.0 s=1
+RI1_2_0_2_1_0_R0 I1_2_0_2_1_0_R0_PLUS I1_2_0_2_1_0_R0_MINUS gnd!
++ pplus_u m=8.0 l=1.6u w=50u r=7.92835 par=8.0 s=1
+RI1_2_0_2_0_0_R0 I1_2_0_2_0_0_R0_PLUS I1_2_0_2_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=50u r=7.92835 par=1.0 s=8
+RI1_2_0_1_1_0_R0 I1_2_0_1_1_0_R0_PLUS I1_2_0_1_1_0_R0_MINUS gnd!
++ pplus_u m=3.0 l=1.6u w=50u r=7.92835 par=3.0 s=1
+RI1_2_0_1_0_0_R0 I1_2_0_1_0_0_R0_PLUS I1_2_0_1_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=50u r=7.92835 par=1.0 s=3
+RI1_2_0_0_1_0_R0 I1_2_0_0_1_0_R0_PLUS I1_2_0_0_1_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=50u r=7.92835 par=1.0 s=1
+RI1_2_0_0_0_0_R0 I1_2_0_0_0_0_R0_PLUS I1_2_0_0_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=50u r=7.92835 par=1.0 s=1
+RI1_1_2_2_1_0_R0 I1_1_2_2_1_0_R0_PLUS I1_1_2_2_1_0_R0_MINUS gnd!
++ pplus_u m=8.0 l=50u w=3.62u r=2.62272K par=8.0 s=1
+RI1_1_2_2_0_0_R0 I1_1_2_2_0_0_R0_PLUS I1_1_2_2_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=3.62u r=2.62272K par=1.0 s=8
+RI1_1_2_1_1_0_R0 I1_1_2_1_1_0_R0_PLUS I1_1_2_1_1_0_R0_MINUS gnd!
++ pplus_u m=3.0 l=50u w=3.62u r=2.62272K par=3.0 s=1
+RI1_1_2_1_0_0_R0 I1_1_2_1_0_0_R0_PLUS I1_1_2_1_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=3.62u r=2.62272K par=1.0 s=3
+RI1_1_2_0_1_0_R0 I1_1_2_0_1_0_R0_PLUS I1_1_2_0_1_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=3.62u r=2.62272K par=1.0 s=1
+RI1_1_2_0_0_0_R0 I1_1_2_0_0_0_R0_PLUS I1_1_2_0_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=3.62u r=2.62272K par=1.0 s=1
+RI1_1_1_2_1_0_R0 I1_1_1_2_1_0_R0_PLUS I1_1_1_2_1_0_R0_MINUS gnd!
++ pplus_u m=8.0 l=7.6u w=3.62u r=422.435 par=8.0 s=1
+RI1_1_1_2_0_0_R0 I1_1_1_2_0_0_R0_PLUS I1_1_1_2_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=3.62u r=422.435 par=1.0 s=8
+RI1_1_1_1_1_0_R0 I1_1_1_1_1_0_R0_PLUS I1_1_1_1_1_0_R0_MINUS gnd!
++ pplus_u m=3.0 l=7.6u w=3.62u r=422.435 par=3.0 s=1
+RI1_1_1_1_0_0_R0 I1_1_1_1_0_0_R0_PLUS I1_1_1_1_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=3.62u r=422.435 par=1.0 s=3
+RI1_1_1_0_1_0_R0 I1_1_1_0_1_0_R0_PLUS I1_1_1_0_1_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=3.62u r=422.435 par=1.0 s=1
+RI1_1_1_0_0_0_R0 I1_1_1_0_0_0_R0_PLUS I1_1_1_0_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=3.62u r=422.435 par=1.0 s=1
+RI1_1_0_2_1_0_R0 I1_1_0_2_1_0_R0_PLUS I1_1_0_2_1_0_R0_MINUS gnd!
++ pplus_u m=8.0 l=1.6u w=3.62u r=111.075 par=8.0 s=1
+RI1_1_0_2_0_0_R0 I1_1_0_2_0_0_R0_PLUS I1_1_0_2_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=3.62u r=111.075 par=1.0 s=8
+RI1_1_0_1_1_0_R0 I1_1_0_1_1_0_R0_PLUS I1_1_0_1_1_0_R0_MINUS gnd!
++ pplus_u m=3.0 l=1.6u w=3.62u r=111.075 par=3.0 s=1
+RI1_1_0_1_0_0_R0 I1_1_0_1_0_0_R0_PLUS I1_1_0_1_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=3.62u r=111.075 par=1.0 s=3
+RI1_1_0_0_1_0_R0 I1_1_0_0_1_0_R0_PLUS I1_1_0_0_1_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=3.62u r=111.075 par=1.0 s=1
+RI1_1_0_0_0_0_R0 I1_1_0_0_0_0_R0_PLUS I1_1_0_0_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=3.62u r=111.075 par=1.0 s=1
+RI1_0_2_2_1_0_R0 I1_0_2_2_1_0_R0_PLUS I1_0_2_2_1_0_R0_MINUS gnd!
++ pplus_u m=8.0 l=50u w=800n r=12.5503K par=8.0 s=1
+RI1_0_2_2_0_0_R0 I1_0_2_2_0_0_R0_PLUS I1_0_2_2_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=800n r=12.5503K par=1.0 s=8
+RI1_0_2_1_1_0_R0 I1_0_2_1_1_0_R0_PLUS I1_0_2_1_1_0_R0_MINUS gnd!
++ pplus_u m=3.0 l=50u w=800n r=12.5503K par=3.0 s=1
+RI1_0_2_1_0_0_R0 I1_0_2_1_0_0_R0_PLUS I1_0_2_1_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=800n r=12.5503K par=1.0 s=3
+RI1_0_2_0_1_0_R0 I1_0_2_0_1_0_R0_PLUS I1_0_2_0_1_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=800n r=12.5503K par=1.0 s=1
+RI1_0_2_0_0_0_R0 I1_0_2_0_0_0_R0_PLUS I1_0_2_0_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=50u w=800n r=12.5503K par=1.0 s=1
+RI1_0_1_2_1_0_R0 I1_0_1_2_1_0_R0_PLUS I1_0_1_2_1_0_R0_MINUS gnd!
++ pplus_u m=8.0 l=7.6u w=800n r=2.02145K par=8.0 s=1
+RI1_0_1_2_0_0_R0 I1_0_1_2_0_0_R0_PLUS I1_0_1_2_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=800n r=2.02145K par=1.0 s=8
+RI1_0_1_1_1_0_R0 I1_0_1_1_1_0_R0_PLUS I1_0_1_1_1_0_R0_MINUS gnd!
++ pplus_u m=3.0 l=7.6u w=800n r=2.02145K par=3.0 s=1
+RI1_0_1_1_0_0_R0 I1_0_1_1_0_0_R0_PLUS I1_0_1_1_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=800n r=2.02145K par=1.0 s=3
+RI1_0_1_0_1_0_R0 I1_0_1_0_1_0_R0_PLUS I1_0_1_0_1_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=800n r=2.02145K par=1.0 s=1
+RI1_0_1_0_0_0_R0 I1_0_1_0_0_0_R0_PLUS I1_0_1_0_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=7.6u w=800n r=2.02145K par=1.0 s=1
+RI1_0_0_2_1_0_R0 I1_0_0_2_1_0_R0_PLUS I1_0_0_2_1_0_R0_MINUS gnd!
++ pplus_u m=8.0 l=1.6u w=800n r=531.519 par=8.0 s=1
+RI1_0_0_2_0_0_R0 I1_0_0_2_0_0_R0_PLUS I1_0_0_2_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=800n r=531.519 par=1.0 s=8
+RI1_0_0_1_1_0_R0 I1_0_0_1_1_0_R0_PLUS I1_0_0_1_1_0_R0_MINUS gnd!
++ pplus_u m=3.0 l=1.6u w=800n r=531.519 par=3.0 s=1
+RI1_0_0_1_0_0_R0 I1_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=800n r=531.519 par=1.0 s=3
+RI1_0_0_0_1_0_R0 I1_0_0_0_1_0_R0_PLUS I1_0_0_0_1_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=800n r=531.519 par=1.0 s=1
+RI1_0_0_0_0_0_R0 I1_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_R0_MINUS gnd!
++ pplus_u m=1.0 l=1.6u w=800n r=531.519 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! pplus_u m=1.0 l=2u
++ w=1u r=497.3349 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_u_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_u_dw.cdl
new file mode 100644
index 0000000..2fbec64
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pplus_u_dw.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pplus_u_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:54:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pplus_u_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pplus_u_dw I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=8.0 l=50u w=50u r=187.206 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=50u r=187.206 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=3.0 l=50u w=50u r=187.206 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=50u r=187.206 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=50u r=187.206 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=50u r=187.206 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=8.0 l=7.6u w=50u r=30.1528 par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=50u r=30.1528 par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=3.0 l=7.6u w=50u r=30.1528 par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=50u r=30.1528 par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=50u r=30.1528 par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=50u r=30.1528 par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=8.0 l=1.6u w=50u r=7.92835 par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=50u r=7.92835 par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=3.0 l=1.6u w=50u r=7.92835 par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=50u r=7.92835 par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=50u r=7.92835 par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=50u r=7.92835 par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=8.0 l=50u w=3.62u r=2.62272K par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=3.62u r=2.62272K par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=3.0 l=50u w=3.62u r=2.62272K par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=3.62u r=2.62272K par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=3.62u r=2.62272K par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=3.62u r=2.62272K par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=8.0 l=7.6u w=3.62u r=422.435 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=3.62u r=422.435 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=3.0 l=7.6u w=3.62u r=422.435 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=3.62u r=422.435 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=3.62u r=422.435 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=3.62u r=422.435 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=8.0 l=1.6u w=3.62u r=111.075 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=3.62u r=111.075 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=3.0 l=1.6u w=3.62u r=111.075 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=3.62u r=111.075 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=3.62u r=111.075 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=3.62u r=111.075 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=8.0 l=50u w=800n r=12.5503K par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=800n r=12.5503K par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=3.0 l=50u w=800n r=12.5503K par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=800n r=12.5503K par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=800n r=12.5503K par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=50u w=800n r=12.5503K par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=8.0 l=7.6u w=800n r=2.02145K par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=800n r=2.02145K par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=3.0 l=7.6u w=800n r=2.02145K par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=800n r=2.02145K par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=800n r=2.02145K par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=7.6u w=800n r=2.02145K par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=8.0 l=1.6u w=800n r=531.519 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=800n r=531.519 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=3.0 l=1.6u w=800n r=531.519 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=800n r=531.519 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=800n r=531.519 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ pplus_u_dw m=1.0 l=1.6u w=800n r=531.519 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! pplus_u_dw m=1.0
++ l=2u w=1u r=497.3349 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_s.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_s.cdl
new file mode 100644
index 0000000..94ea8c3
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_s.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: ppolyf_s
+* View Name: schematic
+* Netlisted on: Nov 24 09:58:06 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: ppolyf_s
+* View Name: schematic
+************************************************************************
+
+.SUBCKT ppolyf_s I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=8.0 l=50u w=50u r=7.50221 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=50u r=7.50221 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=3.0 l=50u w=50u r=7.50221 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=50u r=7.50221 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=50u r=7.50221 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=50u r=7.50221 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=8.0 l=7.6u w=50u r=1.30995 par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=50u r=1.30995 par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=3.0 l=7.6u w=50u r=1.30995 par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=50u r=1.30995 par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=50u r=1.30995 par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=50u r=1.30995 par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=8.0 l=1.6u w=50u r=433.686m par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=50u r=433.686m par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=3.0 l=1.6u w=50u r=433.686m par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=50u r=433.686m par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=50u r=433.686m par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=50u r=433.686m par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=8.0 l=50u w=3.62u r=104.022 par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=3.62u r=104.022 par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=3.0 l=50u w=3.62u r=104.022 par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=3.62u r=104.022 par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=3.62u r=104.022 par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=3.62u r=104.022 par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=8.0 l=7.6u w=3.62u r=18.1631 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=3.62u r=18.1631 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=3.0 l=7.6u w=3.62u r=18.1631 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=3.62u r=18.1631 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=3.62u r=18.1631 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=3.62u r=18.1631 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=8.0 l=1.6u w=3.62u r=6.01326 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=3.62u r=6.01326 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=3.0 l=1.6u w=3.62u r=6.01326 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=3.62u r=6.01326 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=3.62u r=6.01326 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=3.62u r=6.01326 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=8.0 l=50u w=800n r=477.704 par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=800n r=477.704 par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=3.0 l=50u w=800n r=477.704 par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=800n r=477.704 par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=800n r=477.704 par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=50u w=800n r=477.704 par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=8.0 l=7.6u w=800n r=83.4112 par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=800n r=83.4112 par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=3.0 l=7.6u w=800n r=83.4112 par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=800n r=83.4112 par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=800n r=83.4112 par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=7.6u w=800n r=83.4112 par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=8.0 l=1.6u w=800n r=27.615 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=800n r=27.615 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=3.0 l=1.6u w=800n r=27.615 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=800n r=27.615 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=800n r=27.615 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s m=1.0 l=1.6u w=800n r=27.615 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! ppolyf_s m=1.0
++ l=1.6u w=800.0n r=27.615 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_s_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_s_dw.cdl
new file mode 100644
index 0000000..abab827
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_s_dw.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: ppolyf_s_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:58:45 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: ppolyf_s_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT ppolyf_s_dw I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=8.0 l=50u w=50u r=7.50221 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=50u r=7.50221 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=3.0 l=50u w=50u r=7.50221 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=50u r=7.50221 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=50u r=7.50221 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=50u r=7.50221 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=8.0 l=7.6u w=50u r=1.30995 par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=50u r=1.30995 par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=3.0 l=7.6u w=50u r=1.30995 par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=50u r=1.30995 par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=50u r=1.30995 par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=50u r=1.30995 par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=8.0 l=1.6u w=50u r=433.686m par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=50u r=433.686m par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=3.0 l=1.6u w=50u r=433.686m par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=50u r=433.686m par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=50u r=433.686m par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=50u r=433.686m par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=8.0 l=50u w=3.62u r=104.022 par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=3.62u r=104.022 par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=3.0 l=50u w=3.62u r=104.022 par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=3.62u r=104.022 par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=3.62u r=104.022 par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=3.62u r=104.022 par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=8.0 l=7.6u w=3.62u r=18.1631 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=3.62u r=18.1631 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=3.0 l=7.6u w=3.62u r=18.1631 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=3.62u r=18.1631 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=3.62u r=18.1631 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=3.62u r=18.1631 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=8.0 l=1.6u w=3.62u r=6.01326 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=3.62u r=6.01326 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=3.0 l=1.6u w=3.62u r=6.01326 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=3.62u r=6.01326 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=3.62u r=6.01326 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=3.62u r=6.01326 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=8.0 l=50u w=800n r=477.704 par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=800n r=477.704 par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=3.0 l=50u w=800n r=477.704 par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=800n r=477.704 par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=800n r=477.704 par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=50u w=800n r=477.704 par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=8.0 l=7.6u w=800n r=83.4112 par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=800n r=83.4112 par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=3.0 l=7.6u w=800n r=83.4112 par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=800n r=83.4112 par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=800n r=83.4112 par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=7.6u w=800n r=83.4112 par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=8.0 l=1.6u w=800n r=27.615 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=800n r=27.615 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=3.0 l=1.6u w=800n r=27.615 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=800n r=27.615 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=800n r=27.615 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_s_dw m=1.0 l=1.6u w=800n r=27.615 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! ppolyf_s_dw m=1.0
++ l=1.6u w=800.0n r=27.615 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u.cdl
new file mode 100644
index 0000000..05fbcf8
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: ppolyf_u
+* View Name: schematic
+* Netlisted on: Nov 24 10:02:18 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: ppolyf_u
+* View Name: schematic
+************************************************************************
+
+.SUBCKT ppolyf_u I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=8.0 l=50u w=50u r=352.76 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=50u r=352.76 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=3.0 l=50u w=50u r=352.76 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=50u r=352.76 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=50u r=352.76 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=50u r=352.76 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=8.0 l=7.6u w=50u r=55.6565 par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=50u r=55.6565 par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=3.0 l=7.6u w=50u r=55.6565 par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=50u r=55.6565 par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=50u r=55.6565 par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=50u r=55.6565 par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=8.0 l=1.6u w=50u r=13.6136 par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=50u r=13.6136 par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=3.0 l=1.6u w=50u r=13.6136 par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=50u r=13.6136 par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=50u r=13.6136 par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=50u r=13.6136 par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=8.0 l=50u w=3.62u r=4.93695K par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=3.62u r=4.93695K par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=3.0 l=50u w=3.62u r=4.93695K par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=3.62u r=4.93695K par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=3.62u r=4.93695K par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=3.62u r=4.93695K par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=8.0 l=7.6u w=3.62u r=778.926 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=3.62u r=778.926 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=3.0 l=7.6u w=3.62u r=778.926 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=3.62u r=778.926 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=3.62u r=778.926 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=3.62u r=778.926 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=8.0 l=1.6u w=3.62u r=190.526 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=3.62u r=190.526 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=3.0 l=1.6u w=3.62u r=190.526 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=3.62u r=190.526 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=3.62u r=190.526 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=3.62u r=190.526 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=8.0 l=50u w=800n r=23.5247K par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=800n r=23.5247K par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=3.0 l=50u w=800n r=23.5247K par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=800n r=23.5247K par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=800n r=23.5247K par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=50u w=800n r=23.5247K par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=8.0 l=7.6u w=800n r=3.7116K par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=800n r=3.7116K par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=3.0 l=7.6u w=800n r=3.7116K par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=800n r=3.7116K par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=800n r=3.7116K par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=7.6u w=800n r=3.7116K par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=8.0 l=1.6u w=800n r=907.858 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=800n r=907.858 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=3.0 l=1.6u w=800n r=907.858 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=800n r=907.858 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=800n r=907.858 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u m=1.0 l=1.6u w=800n r=907.858 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! ppolyf_u m=1.0
++ l=1.6u w=800.0n r=907.8585 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_1k.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_1k.cdl
new file mode 100644
index 0000000..9ab2d9a
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_1k.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: ppolyf_u_1k
+* View Name: schematic
+* Netlisted on: Nov 24 10:10:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: ppolyf_u_1k
+* View Name: schematic
+************************************************************************
+
+.SUBCKT ppolyf_u_1k I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=8.0 l=100u w=50u r=2.0046K par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=3.0 l=100u w=50u r=2.0046K par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=8.0 l=100u w=50u r=2.0046K par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=3.0 l=100u w=50u r=2.0046K par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=8.0 l=100u w=50u r=2.0046K par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=3.0 l=100u w=50u r=2.0046K par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=8.0 l=50u w=3.62u r=13.9736K par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=50u w=3.62u r=13.9736K par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=3.0 l=50u w=3.62u r=13.9736K par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=50u w=3.62u r=13.9736K par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=50u w=3.62u r=13.9736K par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=50u w=3.62u r=13.9736K par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=8.0 l=7.6u w=3.62u r=2.16433K par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.6u w=3.62u r=2.16433K par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=3.0 l=7.6u w=3.62u r=2.16433K par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.6u w=3.62u r=2.16433K par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.6u w=3.62u r=2.16433K par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.6u w=3.62u r=2.16433K par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=8.0 l=7.24u w=3.62u r=2.06407K par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.24u w=3.62u r=2.06407K par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=3.0 l=7.24u w=3.62u r=2.06407K par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.24u w=3.62u r=2.06407K par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.24u w=3.62u r=2.06407K par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.24u w=3.62u r=2.06407K par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=8.0 l=50u w=1u r=51.7012K par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=50u w=1u r=51.7012K par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=3.0 l=50u w=1u r=51.7012K par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=50u w=1u r=51.7012K par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=50u w=1u r=51.7012K par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=50u w=1u r=51.7012K par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=8.0 l=7.6u w=1u r=8.00786K par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.6u w=1u r=8.00786K par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=3.0 l=7.6u w=1u r=8.00786K par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.6u w=1u r=8.00786K par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.6u w=1u r=8.00786K par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=7.6u w=1u r=8.00786K par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=8.0 l=2u w=1u r=2.23704K par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=2u w=1u r=2.23704K par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=3.0 l=2u w=1u r=2.23704K par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=2u w=1u r=2.23704K par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=2u w=1u r=2.23704K par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k m=1.0 l=2u w=1u r=2.23704K par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! ppolyf_u_1k m=1.0
++ l=2u w=1u r=2.2370394K par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_1k_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_1k_dw.cdl
new file mode 100644
index 0000000..3c33289
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_1k_dw.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: ppolyf_u_1k_dw
+* View Name: schematic
+* Netlisted on: Nov 24 12:27:24 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: ppolyf_u_1k_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT ppolyf_u_1k_dw I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=8.0 l=100u w=50u r=2.0046K par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=3.0 l=100u w=50u r=2.0046K par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=8.0 l=100u w=50u r=2.0046K par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=3.0 l=100u w=50u r=2.0046K par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=8.0 l=100u w=50u r=2.0046K par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=3.0 l=100u w=50u r=2.0046K par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=100u w=50u r=2.0046K par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=8.0 l=50u w=3.62u r=13.9736K par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=50u w=3.62u r=13.9736K par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=3.0 l=50u w=3.62u r=13.9736K par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=50u w=3.62u r=13.9736K par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=50u w=3.62u r=13.9736K par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=50u w=3.62u r=13.9736K par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=8.0 l=7.6u w=3.62u r=2.16433K par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.6u w=3.62u r=2.16433K par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=3.0 l=7.6u w=3.62u r=2.16433K par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.6u w=3.62u r=2.16433K par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.6u w=3.62u r=2.16433K par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.6u w=3.62u r=2.16433K par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=8.0 l=7.24u w=3.62u r=2.06407K par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.24u w=3.62u r=2.06407K par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=3.0 l=7.24u w=3.62u r=2.06407K par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.24u w=3.62u r=2.06407K par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.24u w=3.62u r=2.06407K par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.24u w=3.62u r=2.06407K par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=8.0 l=50u w=1u r=51.7012K par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=50u w=1u r=51.7012K par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=3.0 l=50u w=1u r=51.7012K par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=50u w=1u r=51.7012K par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=50u w=1u r=51.7012K par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=50u w=1u r=51.7012K par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=8.0 l=7.6u w=1u r=8.00786K par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.6u w=1u r=8.00786K par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=3.0 l=7.6u w=1u r=8.00786K par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.6u w=1u r=8.00786K par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.6u w=1u r=8.00786K par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=7.6u w=1u r=8.00786K par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=8.0 l=2u w=1u r=2.23704K par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=2u w=1u r=2.23704K par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=3.0 l=2u w=1u r=2.23704K par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=2u w=1u r=2.23704K par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=2u w=1u r=2.23704K par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_1k_dw m=1.0 l=2u w=1u r=2.23704K par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! ppolyf_u_1k_dw m=1.0
++ l=2u w=1u r=2.2370394K par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_2k.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_2k.cdl
new file mode 100644
index 0000000..1aca933
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_2k.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: ppolyf_u_2k
+* View Name: schematic
+* Netlisted on: Nov 24 11:44:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: ppolyf_u_2k
+* View Name: schematic
+************************************************************************
+
+.SUBCKT ppolyf_u_2k I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=8.0 l=100u w=50u r=4.0124K par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=3.0 l=100u w=50u r=4.0124K par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=8.0 l=100u w=50u r=4.0124K par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=3.0 l=100u w=50u r=4.0124K par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=8.0 l=100u w=50u r=4.0124K par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=3.0 l=100u w=50u r=4.0124K par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=8.0 l=50u w=3.62u r=28.0958K par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=50u w=3.62u r=28.0958K par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=3.0 l=50u w=3.62u r=28.0958K par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=50u w=3.62u r=28.0958K par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=50u w=3.62u r=28.0958K par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=50u w=3.62u r=28.0958K par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=8.0 l=7.6u w=3.62u r=4.37473K par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.6u w=3.62u r=4.37473K par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=3.0 l=7.6u w=3.62u r=4.37473K par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.6u w=3.62u r=4.37473K par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.6u w=3.62u r=4.37473K par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.6u w=3.62u r=4.37473K par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=8.0 l=7.24u w=3.62u r=4.17332K par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.24u w=3.62u r=4.17332K par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=3.0 l=7.24u w=3.62u r=4.17332K par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.24u w=3.62u r=4.17332K par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.24u w=3.62u r=4.17332K par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.24u w=3.62u r=4.17332K par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=8.0 l=50u w=1u r=105.185K par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=50u w=1u r=105.185K par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=3.0 l=50u w=1u r=105.185K par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=50u w=1u r=105.185K par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=50u w=1u r=105.185K par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=50u w=1u r=105.185K par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=8.0 l=7.6u w=1u r=16.3781K par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.6u w=1u r=16.3781K par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=3.0 l=7.6u w=1u r=16.3781K par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.6u w=1u r=16.3781K par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.6u w=1u r=16.3781K par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=7.6u w=1u r=16.3781K par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=8.0 l=2u w=1u r=4.64888K par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=2u w=1u r=4.64888K par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=3.0 l=2u w=1u r=4.64888K par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=2u w=1u r=4.64888K par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=2u w=1u r=4.64888K par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k m=1.0 l=2u w=1u r=4.64888K par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! ppolyf_u_2k m=1.0
++ l=2u w=1u r=4.6488773K par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_2k_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_2k_dw.cdl
new file mode 100644
index 0000000..e08fea5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_2k_dw.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: ppolyf_u_2k_dw
+* View Name: schematic
+* Netlisted on: Nov 24 11:48:25 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: ppolyf_u_2k_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT ppolyf_u_2k_dw I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=8.0 l=100u w=50u r=4.0124K par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=3.0 l=100u w=50u r=4.0124K par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=8.0 l=100u w=50u r=4.0124K par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=3.0 l=100u w=50u r=4.0124K par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=8.0 l=100u w=50u r=4.0124K par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=3.0 l=100u w=50u r=4.0124K par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=100u w=50u r=4.0124K par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=8.0 l=50u w=3.62u r=28.0958K par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=50u w=3.62u r=28.0958K par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=3.0 l=50u w=3.62u r=28.0958K par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=50u w=3.62u r=28.0958K par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=50u w=3.62u r=28.0958K par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=50u w=3.62u r=28.0958K par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=8.0 l=7.6u w=3.62u r=4.37473K par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.6u w=3.62u r=4.37473K par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=3.0 l=7.6u w=3.62u r=4.37473K par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.6u w=3.62u r=4.37473K par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.6u w=3.62u r=4.37473K par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.6u w=3.62u r=4.37473K par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=8.0 l=7.24u w=3.62u r=4.17332K par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.24u w=3.62u r=4.17332K par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=3.0 l=7.24u w=3.62u r=4.17332K par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.24u w=3.62u r=4.17332K par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.24u w=3.62u r=4.17332K par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.24u w=3.62u r=4.17332K par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=8.0 l=50u w=1u r=105.185K par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=50u w=1u r=105.185K par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=3.0 l=50u w=1u r=105.185K par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=50u w=1u r=105.185K par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=50u w=1u r=105.185K par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=50u w=1u r=105.185K par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=8.0 l=7.6u w=1u r=16.3781K par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.6u w=1u r=16.3781K par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=3.0 l=7.6u w=1u r=16.3781K par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.6u w=1u r=16.3781K par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.6u w=1u r=16.3781K par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=7.6u w=1u r=16.3781K par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=8.0 l=2u w=1u r=4.64888K par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=2u w=1u r=4.64888K par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=3.0 l=2u w=1u r=4.64888K par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=2u w=1u r=4.64888K par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=2u w=1u r=4.64888K par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_2k_dw m=1.0 l=2u w=1u r=4.64888K par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! ppolyf_u_2k_dw m=1.0
++ l=2u w=1u r=4.6488773K par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_dw.cdl
new file mode 100644
index 0000000..3b10565
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_dw.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: ppolyf_u_dw
+* View Name: schematic
+* Netlisted on: Nov 24 10:15:15 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: ppolyf_u_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT ppolyf_u_dw I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=8.0 l=50u w=50u r=352.76 par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=50u r=352.76 par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=3.0 l=50u w=50u r=352.76 par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=50u r=352.76 par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=50u r=352.76 par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=50u r=352.76 par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=8.0 l=7.6u w=50u r=55.6565 par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=50u r=55.6565 par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=3.0 l=7.6u w=50u r=55.6565 par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=50u r=55.6565 par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=50u r=55.6565 par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=50u r=55.6565 par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=8.0 l=1.6u w=50u r=13.6136 par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=50u r=13.6136 par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=3.0 l=1.6u w=50u r=13.6136 par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=50u r=13.6136 par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=50u r=13.6136 par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=50u r=13.6136 par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=8.0 l=50u w=3.62u r=4.93695K par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=3.62u r=4.93695K par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=3.0 l=50u w=3.62u r=4.93695K par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=3.62u r=4.93695K par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=3.62u r=4.93695K par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=3.62u r=4.93695K par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=8.0 l=7.6u w=3.62u r=778.926 par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=3.62u r=778.926 par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=3.0 l=7.6u w=3.62u r=778.926 par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=3.62u r=778.926 par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=3.62u r=778.926 par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=3.62u r=778.926 par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=8.0 l=1.6u w=3.62u r=190.526 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=3.62u r=190.526 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=3.0 l=1.6u w=3.62u r=190.526 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=3.62u r=190.526 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=3.62u r=190.526 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=3.62u r=190.526 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=8.0 l=50u w=800n r=23.5247K par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=800n r=23.5247K par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=3.0 l=50u w=800n r=23.5247K par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=800n r=23.5247K par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=800n r=23.5247K par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=50u w=800n r=23.5247K par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=8.0 l=7.6u w=800n r=3.7116K par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=800n r=3.7116K par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=3.0 l=7.6u w=800n r=3.7116K par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=800n r=3.7116K par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=800n r=3.7116K par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=7.6u w=800n r=3.7116K par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=8.0 l=1.6u w=800n r=907.858 par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=800n r=907.858 par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=3.0 l=1.6u w=800n r=907.858 par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=800n r=907.858 par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=800n r=907.858 par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_dw m=1.0 l=1.6u w=800n r=907.858 par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! ppolyf_u_dw m=1.0
++ l=1.6u w=800.0n r=907.8585 par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_fhr_16p0_lv.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_fhr_16p0_lv.cdl
new file mode 100644
index 0000000..b977cd1
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_fhr_16p0_lv.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: ppolyf_u_fhr_16p0_lv
+* View Name: schematic
+* Netlisted on: Nov 24 10:10:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: ppolyf_u_fhr_16p0_lv
+* View Name: schematic
+************************************************************************
+
+.SUBCKT ppolyf_u_fhr_16p0_lv I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=8.0 l=100u w=50u par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=3.0 l=100u w=50u par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=8.0 l=100u w=50u par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=3.0 l=100u w=50u par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=8.0 l=100u w=50u par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=3.0 l=100u w=50u par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=100u w=50u par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=8.0 l=50u w=3.62u par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=50u w=3.62u par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=3.0 l=50u w=3.62u par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=50u w=3.62u par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=50u w=3.62u par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=50u w=3.62u par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=8.0 l=7.6u w=3.62u par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.6u w=3.62u par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=3.0 l=7.6u w=3.62u par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.6u w=3.62u par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.6u w=3.62u par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.6u w=3.62u par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=8.0 l=7.24u w=3.62u par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.24u w=3.62u par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=3.0 l=7.24u w=3.62u par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.24u w=3.62u par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.24u w=3.62u par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.24u w=3.62u par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=8.0 l=50u w=1u par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=50u w=1u par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=3.0 l=50u w=1u par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=50u w=1u par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=50u w=1u par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=50u w=1u par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=8.0 l=7.6u w=1u par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.6u w=1u par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=3.0 l=7.6u w=1u par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.6u w=1u par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.6u w=1u par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=7.6u w=1u par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=8.0 l=2u w=1u par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=2u w=1u par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=3.0 l=2u w=1u par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=2u w=1u par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=2u w=1u par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv m=1.0 l=2u w=1u par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! ppolyf_u_fhr_16p0_lv m=1.0
++ l=2u w=1u par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_fhr_16p0_lv_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_fhr_16p0_lv_dw.cdl
new file mode 100644
index 0000000..efab9f4
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/ppolyf_u_fhr_16p0_lv_dw.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: ppolyf_u_fhr_16p0_lv_dw
+* View Name: schematic
+* Netlisted on: Nov 24 10:10:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: ppolyf_u_fhr_16p0_lv_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT ppolyf_u_fhr_16p0_lv_dw I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=8.0 l=100u w=50u par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=3.0 l=100u w=50u par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=8.0 l=100u w=50u par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=3.0 l=100u w=50u par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=8.0 l=100u w=50u par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=3.0 l=100u w=50u par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=100u w=50u par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=8.0 l=50u w=3.62u par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=50u w=3.62u par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=3.0 l=50u w=3.62u par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=50u w=3.62u par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=50u w=3.62u par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=50u w=3.62u par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=8.0 l=7.6u w=3.62u par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.6u w=3.62u par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=3.0 l=7.6u w=3.62u par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.6u w=3.62u par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.6u w=3.62u par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.6u w=3.62u par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=8.0 l=7.24u w=3.62u par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.24u w=3.62u par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=3.0 l=7.24u w=3.62u par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.24u w=3.62u par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.24u w=3.62u par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.24u w=3.62u par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=8.0 l=50u w=1u par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=50u w=1u par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=3.0 l=50u w=1u par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=50u w=1u par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=50u w=1u par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=50u w=1u par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=8.0 l=7.6u w=1u par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.6u w=1u par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=3.0 l=7.6u w=1u par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.6u w=1u par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.6u w=1u par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=7.6u w=1u par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=8.0 l=2u w=1u par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=2u w=1u par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=3.0 l=2u w=1u par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=2u w=1u par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=2u w=1u par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ ppolyf_u_fhr_16p0_lv_dw m=1.0 l=2u w=1u par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! ppolyf_u_fhr_16p0_lv_dw m=1.0
++ l=2u w=1u par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pwell.cdl b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pwell.cdl
new file mode 100644
index 0000000..5ecec85
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/res_devices/netlist/pwell.cdl
@@ -0,0 +1,234 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pwell
+* View Name: schematic
+* Netlisted on: Nov 24 09:41:48 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pwell
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pwell I1_0_0_0_0_0_0_R0_MINUS I1_0_0_0_0_0_0_R0_PLUS
++ I1_0_0_0_1_0_0_R0_MINUS I1_0_0_0_1_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS
++ I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS I1_0_0_1_1_0_0_R0_PLUS
++ I1_0_0_2_0_0_0_R0_MINUS I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS
++ I1_0_0_2_1_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS I1_0_1_0_0_0_0_R0_PLUS
++ I1_0_1_0_1_0_0_R0_MINUS I1_0_1_0_1_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS
++ I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS I1_0_1_1_1_0_0_R0_PLUS
++ I1_0_1_2_0_0_0_R0_MINUS I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS
++ I1_0_1_2_1_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS I1_0_2_0_0_0_0_R0_PLUS
++ I1_0_2_0_1_0_0_R0_MINUS I1_0_2_0_1_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS
++ I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS I1_0_2_1_1_0_0_R0_PLUS
++ I1_0_2_2_0_0_0_R0_MINUS I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS
++ I1_0_2_2_1_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS I1_1_0_0_0_0_0_R0_PLUS
++ I1_1_0_0_1_0_0_R0_MINUS I1_1_0_0_1_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS
++ I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS I1_1_0_1_1_0_0_R0_PLUS
++ I1_1_0_2_0_0_0_R0_MINUS I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS
++ I1_1_0_2_1_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS I1_1_1_0_0_0_0_R0_PLUS
++ I1_1_1_0_1_0_0_R0_MINUS I1_1_1_0_1_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS
++ I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS I1_1_1_1_1_0_0_R0_PLUS
++ I1_1_1_2_0_0_0_R0_MINUS I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS
++ I1_1_1_2_1_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS I1_1_2_0_0_0_0_R0_PLUS
++ I1_1_2_0_1_0_0_R0_MINUS I1_1_2_0_1_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS
++ I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS I1_1_2_1_1_0_0_R0_PLUS
++ I1_1_2_2_0_0_0_R0_MINUS I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS
++ I1_1_2_2_1_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS I1_2_0_0_0_0_0_R0_PLUS
++ I1_2_0_0_1_0_0_R0_MINUS I1_2_0_0_1_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS
++ I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS I1_2_0_1_1_0_0_R0_PLUS
++ I1_2_0_2_0_0_0_R0_MINUS I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS
++ I1_2_0_2_1_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS I1_2_1_0_0_0_0_R0_PLUS
++ I1_2_1_0_1_0_0_R0_MINUS I1_2_1_0_1_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS
++ I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS I1_2_1_1_1_0_0_R0_PLUS
++ I1_2_1_2_0_0_0_R0_MINUS I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS
++ I1_2_1_2_1_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS I1_2_2_0_0_0_0_R0_PLUS
++ I1_2_2_0_1_0_0_R0_MINUS I1_2_2_0_1_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS
++ I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS I1_2_2_1_1_0_0_R0_PLUS
++ I1_2_2_2_0_0_0_R0_MINUS I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS
++ I1_2_2_2_1_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS gnd!
+*.PININFO I1_0_0_0_0_0_0_R0_MINUS:I I1_0_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_0_1_0_0_R0_MINUS:I I1_0_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_0_0_0_R0_MINUS:I I1_0_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_1_1_0_0_R0_MINUS:I I1_0_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_0_0_0_R0_MINUS:I I1_0_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_0_2_1_0_0_R0_MINUS:I I1_0_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_0_1_0_0_R0_MINUS:I I1_0_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_0_0_0_R0_MINUS:I I1_0_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_1_1_0_0_R0_MINUS:I I1_0_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_0_0_0_R0_MINUS:I I1_0_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_1_2_1_0_0_R0_MINUS:I I1_0_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_0_0_0_R0_MINUS:I I1_0_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_0_1_0_0_R0_MINUS:I I1_0_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_0_0_0_R0_MINUS:I I1_0_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_1_1_0_0_R0_MINUS:I I1_0_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_0_0_0_R0_MINUS:I I1_0_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_0_2_2_1_0_0_R0_MINUS:I I1_0_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_0_0_0_R0_MINUS:I I1_1_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_0_1_0_0_R0_MINUS:I I1_1_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_0_0_0_R0_MINUS:I I1_1_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_1_1_0_0_R0_MINUS:I I1_1_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_0_0_0_R0_MINUS:I I1_1_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_0_2_1_0_0_R0_MINUS:I I1_1_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_0_0_0_R0_MINUS:I I1_1_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_0_1_0_0_R0_MINUS:I I1_1_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_0_0_0_R0_MINUS:I I1_1_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_1_1_0_0_R0_MINUS:I I1_1_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_0_0_0_R0_MINUS:I I1_1_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_1_2_1_0_0_R0_MINUS:I I1_1_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_0_0_R0_MINUS:I I1_1_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_1_0_0_R0_MINUS:I I1_1_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_0_0_0_R0_MINUS:I I1_1_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_1_1_0_0_R0_MINUS:I I1_1_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_0_0_0_R0_MINUS:I I1_1_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_1_2_2_1_0_0_R0_MINUS:I I1_1_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_0_0_0_R0_MINUS:I I1_2_0_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_0_1_0_0_R0_MINUS:I I1_2_0_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_0_0_0_R0_MINUS:I I1_2_0_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_1_1_0_0_R0_MINUS:I I1_2_0_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_0_0_0_R0_MINUS:I I1_2_0_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_0_2_1_0_0_R0_MINUS:I I1_2_0_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_0_0_R0_MINUS:I I1_2_1_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_1_0_0_R0_MINUS:I I1_2_1_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_0_0_0_R0_MINUS:I I1_2_1_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_1_1_0_0_R0_MINUS:I I1_2_1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_0_0_0_R0_MINUS:I I1_2_1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_2_1_0_0_R0_MINUS:I I1_2_1_2_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_0_0_0_R0_MINUS:I I1_2_2_0_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_0_1_0_0_R0_MINUS:I I1_2_2_0_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_0_0_0_R0_MINUS:I I1_2_2_1_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_1_1_0_0_R0_MINUS:I I1_2_2_1_1_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_0_0_0_R0_MINUS:I I1_2_2_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_2_2_1_0_0_R0_MINUS:I I1_2_2_2_1_0_0_R0_PLUS:I
+*.PININFO I1_default_MINUS:I I1_default_PLUS:I gnd!:I
+RI1_2_2_2_1_0_0_R0 I1_2_2_2_1_0_0_R0_PLUS I1_2_2_2_1_0_0_R0_MINUS gnd!
++ pwell m=8.0 l=50u w=50u r=1.01864K par=8.0 s=1
+RI1_2_2_2_0_0_0_R0 I1_2_2_2_0_0_0_R0_PLUS I1_2_2_2_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=50u r=1.01864K par=1.0 s=8
+RI1_2_2_1_1_0_0_R0 I1_2_2_1_1_0_0_R0_PLUS I1_2_2_1_1_0_0_R0_MINUS gnd!
++ pwell m=3.0 l=50u w=50u r=1.01864K par=3.0 s=1
+RI1_2_2_1_0_0_0_R0 I1_2_2_1_0_0_0_R0_PLUS I1_2_2_1_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=50u r=1.01864K par=1.0 s=3
+RI1_2_2_0_1_0_0_R0 I1_2_2_0_1_0_0_R0_PLUS I1_2_2_0_1_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=50u r=1.01864K par=1.0 s=1
+RI1_2_2_0_0_0_0_R0 I1_2_2_0_0_0_0_R0_PLUS I1_2_2_0_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=50u r=1.01864K par=1.0 s=1
+RI1_2_1_2_1_0_0_R0 I1_2_1_2_1_0_0_R0_PLUS I1_2_1_2_1_0_0_R0_MINUS gnd!
++ pwell m=8.0 l=11.61u w=50u r=243.958 par=8.0 s=1
+RI1_2_1_2_0_0_0_R0 I1_2_1_2_0_0_0_R0_PLUS I1_2_1_2_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=50u r=243.958 par=1.0 s=8
+RI1_2_1_1_1_0_0_R0 I1_2_1_1_1_0_0_R0_PLUS I1_2_1_1_1_0_0_R0_MINUS gnd!
++ pwell m=3.0 l=11.61u w=50u r=243.958 par=3.0 s=1
+RI1_2_1_1_0_0_0_R0 I1_2_1_1_0_0_0_R0_PLUS I1_2_1_1_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=50u r=243.958 par=1.0 s=3
+RI1_2_1_0_1_0_0_R0 I1_2_1_0_1_0_0_R0_PLUS I1_2_1_0_1_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=50u r=243.958 par=1.0 s=1
+RI1_2_1_0_0_0_0_R0 I1_2_1_0_0_0_0_R0_PLUS I1_2_1_0_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=50u r=243.958 par=1.0 s=1
+RI1_2_0_2_1_0_0_R0 I1_2_0_2_1_0_0_R0_PLUS I1_2_0_2_1_0_0_R0_MINUS gnd!
++ pwell m=8.0 l=4u w=50u r=90.3947 par=8.0 s=1
+RI1_2_0_2_0_0_0_R0 I1_2_0_2_0_0_0_R0_PLUS I1_2_0_2_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=50u r=90.3947 par=1.0 s=8
+RI1_2_0_1_1_0_0_R0 I1_2_0_1_1_0_0_R0_PLUS I1_2_0_1_1_0_0_R0_MINUS gnd!
++ pwell m=3.0 l=4u w=50u r=90.3947 par=3.0 s=1
+RI1_2_0_1_0_0_0_R0 I1_2_0_1_0_0_0_R0_PLUS I1_2_0_1_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=50u r=90.3947 par=1.0 s=3
+RI1_2_0_0_1_0_0_R0 I1_2_0_0_1_0_0_R0_PLUS I1_2_0_0_1_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=50u r=90.3947 par=1.0 s=1
+RI1_2_0_0_0_0_0_R0 I1_2_0_0_0_0_0_R0_PLUS I1_2_0_0_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=50u r=90.3947 par=1.0 s=1
+RI1_1_2_2_1_0_0_R0 I1_1_2_2_1_0_0_R0_PLUS I1_1_2_2_1_0_0_R0_MINUS gnd!
++ pwell m=8.0 l=50u w=5.71u r=9.58595K par=8.0 s=1
+RI1_1_2_2_0_0_0_R0 I1_1_2_2_0_0_0_R0_PLUS I1_1_2_2_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=5.71u r=9.58595K par=1.0 s=8
+RI1_1_2_1_1_0_0_R0 I1_1_2_1_1_0_0_R0_PLUS I1_1_2_1_1_0_0_R0_MINUS gnd!
++ pwell m=3.0 l=50u w=5.71u r=9.58595K par=3.0 s=1
+RI1_1_2_1_0_0_0_R0 I1_1_2_1_0_0_0_R0_PLUS I1_1_2_1_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=5.71u r=9.58595K par=1.0 s=3
+RI1_1_2_0_1_0_0_R0 I1_1_2_0_1_0_0_R0_PLUS I1_1_2_0_1_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=5.71u r=9.58595K par=1.0 s=1
+RI1_1_2_0_0_0_0_R0 I1_1_2_0_0_0_0_R0_PLUS I1_1_2_0_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=5.71u r=9.58595K par=1.0 s=1
+RI1_1_1_2_1_0_0_R0 I1_1_1_2_1_0_0_R0_PLUS I1_1_1_2_1_0_0_R0_MINUS gnd!
++ pwell m=8.0 l=11.61u w=5.71u r=2.29578K par=8.0 s=1
+RI1_1_1_2_0_0_0_R0 I1_1_1_2_0_0_0_R0_PLUS I1_1_1_2_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=5.71u r=2.29578K par=1.0 s=8
+RI1_1_1_1_1_0_0_R0 I1_1_1_1_1_0_0_R0_PLUS I1_1_1_1_1_0_0_R0_MINUS gnd!
++ pwell m=3.0 l=11.61u w=5.71u r=2.29578K par=3.0 s=1
+RI1_1_1_1_0_0_0_R0 I1_1_1_1_0_0_0_R0_PLUS I1_1_1_1_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=5.71u r=2.29578K par=1.0 s=3
+RI1_1_1_0_1_0_0_R0 I1_1_1_0_1_0_0_R0_PLUS I1_1_1_0_1_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=5.71u r=2.29578K par=1.0 s=1
+RI1_1_1_0_0_0_0_R0 I1_1_1_0_0_0_0_R0_PLUS I1_1_1_0_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=5.71u r=2.29578K par=1.0 s=1
+RI1_1_0_2_1_0_0_R0 I1_1_0_2_1_0_0_R0_PLUS I1_1_0_2_1_0_0_R0_MINUS gnd!
++ pwell m=8.0 l=4u w=5.71u r=850.665 par=8.0 s=1
+RI1_1_0_2_0_0_0_R0 I1_1_0_2_0_0_0_R0_PLUS I1_1_0_2_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=5.71u r=850.665 par=1.0 s=8
+RI1_1_0_1_1_0_0_R0 I1_1_0_1_1_0_0_R0_PLUS I1_1_0_1_1_0_0_R0_MINUS gnd!
++ pwell m=3.0 l=4u w=5.71u r=850.665 par=3.0 s=1
+RI1_1_0_1_0_0_0_R0 I1_1_0_1_0_0_0_R0_PLUS I1_1_0_1_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=5.71u r=850.665 par=1.0 s=3
+RI1_1_0_0_1_0_0_R0 I1_1_0_0_1_0_0_R0_PLUS I1_1_0_0_1_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=5.71u r=850.665 par=1.0 s=1
+RI1_1_0_0_0_0_0_R0 I1_1_0_0_0_0_0_R0_PLUS I1_1_0_0_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=5.71u r=850.665 par=1.0 s=1
+RI1_0_2_2_1_0_0_R0 I1_0_2_2_1_0_0_R0_PLUS I1_0_2_2_1_0_0_R0_MINUS gnd!
++ pwell m=8.0 l=50u w=2u r=32.4419K par=8.0 s=1
+RI1_0_2_2_0_0_0_R0 I1_0_2_2_0_0_0_R0_PLUS I1_0_2_2_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=2u r=32.4419K par=1.0 s=8
+RI1_0_2_1_1_0_0_R0 I1_0_2_1_1_0_0_R0_PLUS I1_0_2_1_1_0_0_R0_MINUS gnd!
++ pwell m=3.0 l=50u w=2u r=32.4419K par=3.0 s=1
+RI1_0_2_1_0_0_0_R0 I1_0_2_1_0_0_0_R0_PLUS I1_0_2_1_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=2u r=32.4419K par=1.0 s=3
+RI1_0_2_0_1_0_0_R0 I1_0_2_0_1_0_0_R0_PLUS I1_0_2_0_1_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=2u r=32.4419K par=1.0 s=1
+RI1_0_2_0_0_0_0_R0 I1_0_2_0_0_0_0_R0_PLUS I1_0_2_0_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=50u w=2u r=32.4419K par=1.0 s=1
+RI1_0_1_2_1_0_0_R0 I1_0_1_2_1_0_0_R0_PLUS I1_0_1_2_1_0_0_R0_MINUS gnd!
++ pwell m=8.0 l=11.61u w=2u r=7.76967K par=8.0 s=1
+RI1_0_1_2_0_0_0_R0 I1_0_1_2_0_0_0_R0_PLUS I1_0_1_2_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=2u r=7.76967K par=1.0 s=8
+RI1_0_1_1_1_0_0_R0 I1_0_1_1_1_0_0_R0_PLUS I1_0_1_1_1_0_0_R0_MINUS gnd!
++ pwell m=3.0 l=11.61u w=2u r=7.76967K par=3.0 s=1
+RI1_0_1_1_0_0_0_R0 I1_0_1_1_0_0_0_R0_PLUS I1_0_1_1_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=2u r=7.76967K par=1.0 s=3
+RI1_0_1_0_1_0_0_R0 I1_0_1_0_1_0_0_R0_PLUS I1_0_1_0_1_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=2u r=7.76967K par=1.0 s=1
+RI1_0_1_0_0_0_0_R0 I1_0_1_0_0_0_0_R0_PLUS I1_0_1_0_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=11.61u w=2u r=7.76967K par=1.0 s=1
+RI1_0_0_2_1_0_0_R0 I1_0_0_2_1_0_0_R0_PLUS I1_0_0_2_1_0_0_R0_MINUS gnd!
++ pwell m=8.0 l=4u w=2u r=2.87892K par=8.0 s=1
+RI1_0_0_2_0_0_0_R0 I1_0_0_2_0_0_0_R0_PLUS I1_0_0_2_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=2u r=2.87892K par=1.0 s=8
+RI1_0_0_1_1_0_0_R0 I1_0_0_1_1_0_0_R0_PLUS I1_0_0_1_1_0_0_R0_MINUS gnd!
++ pwell m=3.0 l=4u w=2u r=2.87892K par=3.0 s=1
+RI1_0_0_1_0_0_0_R0 I1_0_0_1_0_0_0_R0_PLUS I1_0_0_1_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=2u r=2.87892K par=1.0 s=3
+RI1_0_0_0_1_0_0_R0 I1_0_0_0_1_0_0_R0_PLUS I1_0_0_0_1_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=2u r=2.87892K par=1.0 s=1
+RI1_0_0_0_0_0_0_R0 I1_0_0_0_0_0_0_R0_PLUS I1_0_0_0_0_0_0_R0_MINUS gnd!
++ pwell m=1.0 l=4u w=2u r=2.87892K par=1.0 s=1
+RI1_default I1_default_PLUS I1_default_MINUS gnd! pwell m=1.0 l=4u
++ w=2u r=2.8789203K par=1.0 s=1
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds
new file mode 100644
index 0000000..7efb14d
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds
new file mode 100644
index 0000000..6893fe8
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds
new file mode 100644
index 0000000..7a85d9f
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds
new file mode 100644
index 0000000..280f16e
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/mos_varactor_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds
new file mode 100644
index 0000000..0bcb398
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds
new file mode 100644
index 0000000..576a490
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_1p8_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds
new file mode 100644
index 0000000..a91f22d
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds
new file mode 100644
index 0000000..ddbf511
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/layout/pn_varactor_6p0_dw.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl
new file mode 100644
index 0000000..80daea9
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mos_varactor_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mos_varactor_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mos_varactor_1p8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_1p8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_1p8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_1p8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_1p8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_1p8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_1p8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_1p8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_1p8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_1p8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_1p8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl
new file mode 100644
index 0000000..918db43
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_1p8_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mos_varactor_1p8_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:12:27 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mos_varactor_1p8_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mos_varactor_1p8_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_1p8_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_1p8_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_1p8_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_1p8_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl
new file mode 100644
index 0000000..47c6313
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mos_varactor_6p0
+* View Name: schematic
+* Netlisted on: Nov 24 09:13:17 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mos_varactor_6p0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mos_varactor_6p0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_6p0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_6p0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_6p0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_6p0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_6p0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_6p0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_6p0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_6p0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_6p0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_6p0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl
new file mode 100644
index 0000000..05f01ad
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/mos_varactor_6p0_dw.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: mos_varactor_6p0_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:15:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: mos_varactor_6p0_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT mos_varactor_6p0_dw I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D mos_varactor_6p0_dw m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D mos_varactor_6p0_dw m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D mos_varactor_6p0_dw m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D mos_varactor_6p0_dw m=1 l=5u w=5u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl
new file mode 100644
index 0000000..5395cc5
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pn_varactor_1p8
+* View Name: schematic
+* Netlisted on: Nov 24 09:49:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pn_varactor_1p8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pn_varactor_1p8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_default_MINUS I1_default_PLUS
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS pn_varactor_1p8 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_1p8 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_1p8 m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl
new file mode 100644
index 0000000..adc3e1b
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_1p8_dw.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pn_varactor_1p8_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:00 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pn_varactor_1p8_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pn_varactor_1p8_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS
++ I1_default_PLUS I1_default_MINUS
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_1p8_dw m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_1p8_dw m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl
new file mode 100644
index 0000000..7a8a560
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0.cdl
@@ -0,0 +1,44 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pn_varactor_6p0
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pn_varactor_6p0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pn_varactor_6p0 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_default_MINUS I1_default_PLUS
+
+
+CI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS pn_varactor_6p0 m=1 L=1.1u W=1.1u
+CI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=1.1u
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_6p0 m=1 L=0.36u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_6p0 m=1 L=1u W=1u
+.ENDS
+
diff --git a/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl
new file mode 100644
index 0000000..e7361a4
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/varactor_devices/netlist/pn_varactor_6p0_dw.cdl
@@ -0,0 +1,40 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: pn_varactor_6p0_dw
+* View Name: schematic
+* Netlisted on: Nov 24 09:51:10 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: pn_varactor_6p0_dw
+* View Name: schematic
+************************************************************************
+
+.SUBCKT pn_varactor_6p0_dw I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS
++ I1_default_PLUS I1_default_MINUS
+
+CI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=100u
+CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=13.2u
+CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=1.1u
+CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pn_varactor_6p0_dw m=1 L=0.565u W=0.565u
+CI1_default I1_default_PLUS I1_default_MINUS pn_varactor_6p0_dw m=1 L=1u W=1u
+.ENDS
+
