Merge pull request #125 from mabrains/bcd_docs
diff --git a/BCDLite/klayout/lvs/gf180BCDLite.lvs b/BCDLite/klayout/lvs/gf180BCDLite.lvs
index e489b67..42151c1 100644
--- a/BCDLite/klayout/lvs/gf180BCDLite.lvs
+++ b/BCDLite/klayout/lvs/gf180BCDLite.lvs
@@ -265,6 +265,12 @@
# %include rule_decks/mimcap_derivations.lvs
+#==================================
+# ------ MOSCAP DERIVATIONS -------
+#==================================
+
+# %include rule_decks/moscap_derivations.lvs
+
#====================================
# ------ VARACTOR DERIVATIONS -------
#====================================
@@ -307,6 +313,12 @@
# %include rule_decks/mimcap_extraction.lvs
+#==================================
+# ------- MOSCAP EXTRACTION -------
+#==================================
+
+# %include rule_decks/moscap_extraction.lvs
+
#====================================
# ------- VARACTOR EXTRACTION -------
#====================================
diff --git a/BCDLite/klayout/lvs/rule_decks/diode_connections.lvs b/BCDLite/klayout/lvs/rule_decks/diode_connections.lvs
index c0be24e..167c4fc 100644
--- a/BCDLite/klayout/lvs/rule_decks/diode_connections.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/diode_connections.lvs
@@ -75,43 +75,12 @@
# diode_pw2dw: Model for LVPWELL/DNWELL diode (applicable for both 1.8V/6V) [dnwpw]
connect(diode_pw2dw_terminal_p, contact)
-#======================
-# --- DNWPWHV DIODE ---
-#======================
-
-# diode_pw2dw_hv: Model for NW/PWHV diode (10V diode) [dnwpwhv]
-connect(diode_pw2dw_hv_terminal_n, contact)
-connect(diode_pw2dw_hv_terminal_p, contact)
-
-#=======================
-# --- DPWHVDNW DIODE ---
-#=======================
-
-# diode_pw2dnw_hv: Model for PWHV/DNW diode [dpwhvdnw]
-connect(diode_pw2dnw_hv_terminal_n, contact)
-connect(diode_pw2dnw_hv_terminal_p, contact)
-
-#======================
-# --- NP 30P0 DIODE ---
-#======================
-
-# diode_nd2ps_30v0: Model for HVNDDD/Psub diode [np_30p0]
-connect(diode_nd2ps_30v0_terminal_n, contact)
-connect(diode_nd2ps_30v0_terminal_p, contact)
-
-#======================
-# --- PN 30P0 DIODE ---
-#======================
-
-# diode_pd2nw_30v0: Model for HVPDDD/DNWELL diode [np_30p0]
-connect(diode_pd2nw_30v0_terminal_n, contact)
-
#====================
# --- DNWPS DIODE ---
#====================
# diode_dw2ps: Model for DNWELL/Psub diode(1.8V/6V) [dnwps]
-connect(diode_dw2ps_terminal_p, contact)
+connect(diode_dw2ps_terminal_p, ptap)
#=================
# --- SC DIODE ---
@@ -120,23 +89,3 @@
# diode_sc: Model for schottky diode [sc_diode]
connect(diode_sc_terminal_n, contact)
connect(diode_sc_terminal_p, schottky_diode)
-
-#====================
-# --- ZENER DIODE ---
-#====================
-
-# diode_zener: Model for zener diode outside DNWELL [zener_diode]
-connect(diode_zener_terminal_n, contact)
-connect(diode_zener_terminal_p, zener)
-
-# diode_zener_dn: Model for zener diode inside DNWELL [zener_diode_dw]
-connect(diode_zener_dn_terminal_n, contact)
-connect(diode_zener_dn_terminal_p, zener)
-
-#===================
-# --- POLY DIODE ---
-#===================
-
-# diode_poly: Model for poly diode [poly_diode]
-connect(diode_poly_terminal_n, contact)
-connect(diode_poly_terminal_p, contact)
diff --git a/BCDLite/klayout/lvs/rule_decks/diode_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/diode_derivations.lvs
index be7cc47..fb71277 100644
--- a/BCDLite/klayout/lvs/rule_decks/diode_derivations.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/diode_derivations.lvs
@@ -45,7 +45,7 @@
#=====================
diode_nd2ps_01v8_exclude = diode_nd2ps_pd2nw_exclude.join(nwell).join(pplus).join(dualgate2_d)
-diode_nd2ps_01v8 = ncomp.and(diode_mk).not(diode_nd2ps_01v8_exclude)
+diode_nd2ps_01v8 = ncomp.and(diode_mk).not_interacting(diode_nd2ps_01v8_exclude)
# diode_nd2ps_01v8: Model for 1.8V N+/Psub diode (outside DNWELL) [np_1p8]
diode_nd2ps_01v8_terminal_n = diode_nd2ps_01v8.not(dnwell)
@@ -58,7 +58,7 @@
#=====================
diode_pd2nw_01v8_exclude = diode_nd2ps_pd2nw_exclude.join(lvpwell).join(nplus).join(dualgate2_d)
-diode_pd2nw_01v8 = pcomp.and(diode_mk).not(diode_pd2nw_01v8_exclude)
+diode_pd2nw_01v8 = pcomp.and(diode_mk).not_interacting(diode_pd2nw_01v8_exclude)
# diode_pd2nw_01v8: Model for 1.8V P+/Nwell diode (outside DNWELL) [pn_1p8]
diode_pd2nw_01v8_terminal_p = diode_pd2nw_01v8.not(dnwell)
@@ -71,7 +71,7 @@
#=====================
diode_nd2ps_06v0_exclude = diode_nd2ps_pd2nw_exclude.join(nwell).join(pplus)
-diode_nd2ps_06v0 = ncomp.and(diode_mk).and(dualgate2_d).not(diode_nd2ps_06v0_exclude)
+diode_nd2ps_06v0 = ncomp.and(diode_mk).and(dualgate2_d).not_interacting(diode_nd2ps_06v0_exclude)
# diode_nd2ps_06v0: Model for 6V N+/Pwell diode (outside DNWELL) [np_6p0]
diode_nd2ps_06v0_terminal_n = diode_nd2ps_06v0.not(dnwell)
@@ -84,7 +84,7 @@
#=====================
diode_pd2nw_06v0_exclude = diode_nd2ps_pd2nw_exclude.join(lvpwell).join(nplus)
-diode_pd2nw_06v0 = pcomp.and(diode_mk).and(dualgate2_d).not(diode_pd2nw_06v0_exclude)
+diode_pd2nw_06v0 = pcomp.and(diode_mk).and(dualgate2_d).not_interacting(diode_pd2nw_06v0_exclude)
# diode_pd2nw_06v0: Model for 6V P+/Nwell diode (outside DNWELL) [pn_6p0]
diode_pd2nw_06v0_terminal_p = diode_pd2nw_06v0.not(dnwell)
@@ -100,7 +100,7 @@
# diode_nw2ps_06v0: Model for Nwell/Psub diode (applicable for both 1.8V/6V) [nwp_6p0]
diode_nw2ps_06v0_terminal_p = pcomp.and(diode_mk).not(diode_nw2ps_06v0_exclude)
-diode_nw2ps_06v0_terminal_n = diode_mk.covering(nwell.covering(ncomp)).not(diode_nw2ps_06v0_exclude)
+diode_nw2ps_06v0_terminal_n = diode_mk.covering(nwell.covering(ncomp)).not_interacting(diode_nw2ps_06v0_exclude)
#====================
# --- DNWPW DIODE ---
@@ -109,69 +109,21 @@
diode_pw2dw_exclude = diode_nd2ps_pd2nw_exclude.join(nwell).join(nplus)
# diode_pw2dw: Model for LVPWELL/DNWELL diode (applicable for both 1.8V/6V) [dnwpw]
-diode_pw2dw_terminal_p = lvpwell.interacting(pcomp).and(well_diode_mk).not(diode_pw2dw_exclude)
-
-#======================
-# --- DNWPWHV DIODE ---
-#======================
-
-diode_pw2dw_hv_exclude = diode_exclude.join(lvpwell).join(poly2)
- .join(pplus).join(schottky_diode).join(zener)
- .join(res_mk).join(hvnddd).join(hvpddd)
- .join(nwell)
-
-# diode_pw2dw_hv: Model for NW/PWHV diode (10V diode) [dnwpwhv]
-dnwell_hv = dnwell.and(dualgate2_d)
-diode_pw2dw_hv_terminal_p = pwhv.and(well_diode_mk).and(ldmos_xtor).not(diode_pw2dw_hv_exclude)
-diode_pw2dw_hv_terminal_n = well_diode_mk.covering(dnwell_hv.covering(ncomp)).and(ldmos_xtor)
- .interacting(mvsd).not(diode_pw2dw_hv_exclude)
-
-#=======================
-# --- DPWHVDNW DIODE ---
-#=======================
-
-diode_pw2dnw_hv_exclude = diode_exclude.join(lvpwell).join(poly2)
- .join(nplus).join(schottky_diode).join(zener)
- .join(res_mk).join(hvnddd).join(hvpddd)
- .join(nwell)
-
-# diode_pw2dnw_hv: Model for PWHV/DNW diode [dpwhvdnw]
-diode_pw2dnw_hv_terminal_p = pwhv.and(well_diode_mk).and(ldmos_xtor).not(diode_pw2dnw_hv_exclude)
-diode_pw2dnw_hv_terminal_n = well_diode_mk.covering(dnwell_hv.covering(pcomp)).and(ldmos_xtor)
- .interacting(mvsd).not(diode_pw2dnw_hv_exclude)
-
-#======================
-# --- NP 30P0 DIODE ---
-#======================
-
-diode_nd2ps_30v0_exclude = diode_exclude.join(dnwell).join(nwell)
- .join(lvpwell).join(poly2)
-
-# diode_nd2ps_30v0: Model for HVNDDD/Psub diode [np_30p0]
-diode_nd2ps_30v0_terminal_n = dualgate2_d.covering(hvnddd.and(diode_mk)).not(diode_nd2ps_30v0_exclude)
-diode_nd2ps_30v0_terminal_p = pcomp.and(diode_mk).not(diode_nd2ps_30v0_exclude)
-
-#======================
-# --- PN 30P0 DIODE ---
-#======================
-
-diode_pd2nw_30v0_exclude = diode_exclude.join(nwell).join(lvpwell).join(poly2)
-
-# diode_pd2nw_30v0: Model for HVPDDD/DNWELL diode [np_30p0]
-diode_pd2nw_30v0_terminal_n = hvpddd.and(diode_mk).and(dualgate2_d).not(diode_pd2nw_30v0_exclude)
+diode_pw2dw_terminal_p = lvpwell.interacting(pcomp).and(well_diode_mk).not_interacting(diode_pw2dw_exclude)
#====================
# --- DNWPS DIODE ---
#====================
# diode_dw2ps: Model for DNWELL/Psub diode(1.8V/6V) [dnwps]
+diode_dw2ps_terminal_p_ = ptap.extents.covering(ncomp)
diode_dw2ps_exclude = diode_exclude.join(nwell).join(lvpwell)
.join(poly2).join(pwhv).join(schottky_diode)
.join(zener).join(mvsd).join(hvnddd)
.join(hvpddd).join(ldmos_xtor)
-diode_dw2ps_terminal_p = pcomp.and(dualgate2_d).and(dnwell).and(well_diode_mk)
- .not(diode_dw2ps_exclude)
+diode_dw2ps_terminal_p = diode_dw2ps_terminal_p_.interacting(dnwell).interacting(well_diode_mk)
+ .not_interacting(diode_dw2ps_exclude)
#=================
# --- SC DIODE ---
@@ -182,44 +134,5 @@
.join(hvnddd).join(hvpddd).join(ldmos_xtor)
# diode_sc: Model for schottky diode [sc_diode]
-diode_sc_terminal_n = ncomp.and(dnwell).and(schottky_diode).not(diode_sc_exclude)
-diode_sc_terminal_p = metal1.and(dnwell).not_interacting(diode_sc_terminal_n).not(diode_sc_exclude)
-
-#====================
-# --- ZENER DIODE ---
-#====================
-
-diode_zener_exclude = diode_exclude.join(lvpwell).join(poly2)
- .join(pplus).join(zener).join(res_mk)
- .join(hvnddd).join(hvpddd).join(ldmos_xtor)
-
-# diode_zener: Model for zener diode outside DNWELL [zener_diode]
-zener_mv = zener.and(dualgate2_d)
-diode_zener_terminal_n = ncomp.and(zener_mv).not(dnwell).not(diode_zener_exclude)
-diode_zener_terminal_p = nwell.and(zener_mv).not(dnwell).covering(pcomp).and(diode_mk).not(diode_zener_exclude)
-
-# diode_zener_dn: Model for zener diode inside DNWELL [zener_diode_dw]
-diode_zener_dn_terminal_n = ncomp.and(zener_mv).and(dnwell).and(diode_mk).not(diode_zener_exclude)
-diode_zener_dn_terminal_p = nwell.and(zener_mv).and(dnwell).covering(pcomp).and(diode_mk).not(diode_zener_exclude)
-
-
-#===================
-# --- POLY DIODE ---
-#===================
-
-# diode_poly: Model for poly diode [poly_diode]
-diode_poly_exclude = comp.join(resistor).join(esd)
- .join(pwhv).join(polyfuse).join(fusewindow_d)
- .join(schottky_diode).join(piscap).join(zener)
- .join(res_mk).join(v5_xtor).join(nat)
- .join(fhres).join(mvsd).join(mvpsd)
- .join(elmd_mk).join(elmd2_mk).join(lvs_rf)
- .join(lvs_source).join(lvs_35v).join(mk_35v)
- .join(well_diode_mk).join(esd_hbm_mk).join(mos_mk_type1)
- .join(hvnddd).join(hvpddd).join(hvpolyrs)
- .join(ldmos_xtor)
-
-diode_poly_terminal_p = poly2.and(sab).interacting(nplus).interacting(pplus)
- .and(diode_mk).not(diode_poly_exclude)
-diode_poly_terminal_n = diode_mk.covering(diode_poly_terminal_p)
-
+diode_sc_terminal_n = ncomp.and(dnwell).and(schottky_diode).not_interacting(diode_sc_exclude)
+diode_sc_terminal_p = metal1.and(dnwell).not_interacting(diode_sc_terminal_n).not_interacting(diode_sc_exclude)
diff --git a/BCDLite/klayout/lvs/rule_decks/diode_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/diode_extraction.lvs
index c598159..67adef9 100644
--- a/BCDLite/klayout/lvs/rule_decks/diode_extraction.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/diode_extraction.lvs
@@ -84,38 +84,6 @@
logger.info('Extracting diode_pw2dw diode')
extract_devices(diode('diode_pw2dw'), { 'N' => dnwell, 'P' => diode_pw2dw_terminal_p })
-#======================
-# --- DNWPWHV DIODE ---
-#======================
-
-# diode_pw2dw_hv: Model for NW/PWHV diode (10V diode) [dnwpwhv]
-logger.info('Extracting diode_pw2dw_hv diode')
-extract_devices(diode('diode_pw2dw_hv'), { 'N' => diode_pw2dw_hv_terminal_n, 'P' => diode_pw2dw_hv_terminal_p })
-
-#=======================
-# --- DPWHVDNW DIODE ---
-#=======================
-
-# diode_pw2dnw_hv: Model for PWHV/DNW diode [dpwhvdnw]
-logger.info('Extracting diode_pw2dnw_hv diode')
-extract_devices(diode('diode_pw2dnw_hv'), { 'N' => diode_pw2dnw_hv_terminal_n, 'P' => diode_pw2dnw_hv_terminal_p })
-
-#======================
-# --- NP 30P0 DIODE ---
-#======================
-
-# diode_nd2ps_30v0: Model for HVNDDD/Psub diode [np_30p0]
-logger.info('Extracting diode_nd2ps_30v0 diode')
-extract_devices(diode('diode_nd2ps_30v0'), { 'N' => diode_nd2ps_30v0_terminal_n, 'P' => diode_nd2ps_30v0_terminal_p })
-
-#======================
-# --- PN 30P0 DIODE ---
-#======================
-
-# diode_pd2nw_30v0: Model for HVPDDD/DNWELL diode [np_30p0]
-logger.info('Extracting diode_pd2nw_30v0 diode')
-extract_devices(diode('diode_pd2nw_30v0'), { 'N' => diode_pd2nw_30v0_terminal_n, 'P' => dnwell })
-
#====================
# --- DNWPS DIODE ---
#====================
@@ -131,24 +99,3 @@
# diode_sc: Model for schottky diode [sc_diode]
logger.info('Extracting diode_sc diode')
extract_devices(diode('diode_sc'), { 'N' => diode_sc_terminal_n, 'P' => schottky_diode })
-
-#====================
-# --- ZENER DIODE ---
-#====================
-
-# diode_zener: Model for zener diode outside DNWELL [zener_diode]
-logger.info('Extracting diode_zener diode')
-extract_devices(diode('diode_zener'), { 'N' => diode_zener_terminal_n, 'P' => zener })
-
-# diode_zener_dn: Model for zener diode inside DNWELL [zener_diode_dw]
-logger.info('Extracting diode_zener_dn diode')
-extract_devices(diode('diode_zener_dn'), { 'N' => diode_zener_dn_terminal_n, 'P' => zener })
-
-#===================
-# --- POLY DIODE ---
-#===================
-
-# diode_poly: Model for poly diode [poly_diode]
-logger.info('Extracting diode_poly diode')
-extract_devices(diode('diode_poly'), { 'N' => diode_poly_terminal_n, 'P' => diode_poly_terminal_p })
-
diff --git a/BCDLite/klayout/lvs/rule_decks/moscap_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/moscap_derivations.lvs
new file mode 100644
index 0000000..163c04c
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/moscap_derivations.lvs
@@ -0,0 +1,117 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------ MOSCAP DERIVATIONS -------
+#==================================
+
+logger.info('Starting MOSCAP DERIVATIONS')
+
+#=======================
+# --- MOSCAP EXCLUDE ---
+#=======================
+
+moscap_exclude = resistor.join(esd).join(sab)
+ .join(dni).join(pwhv).join(fusewindow_d)
+ .join(polyfuse).join(schottky_diode).join(piscap)
+ .join(zener).join(res_mk).join(diode_mk)
+ .join(v5_xtor).join(drc_bjt).join(nat)
+ .join(fhres).join(mvsd).join(mvpsd)
+ .join(elmd_mk).join(elmd2_mk).join(lvs_rf)
+ .join(lvs_source).join(mk_35v).join(lvs_35v)
+ .join(well_diode_mk).join(esd_hbm_mk).join(mos_mk_type1)
+ .join(swfet_mk).join(hvnddd).join(hvpddd)
+ .join(hvpolyrs).join(ldmos_xtor)
+
+ngate_lv = ngate.not(dualgate2_d).and(mos_cap_mk)
+ngate_mv = ngate.and(dualgate2_d).and(mos_cap_mk)
+
+ngate_lv_nw = ngate_lv.and(nwell)
+ngate_lv_n_nw = ngate_lv.not(nwell)
+
+ngate_mv_nw = ngate_mv.and(nwell)
+ngate_mv_n_nw = ngate_mv.not(nwell)
+
+pgate_lv = pgate.not(dualgate2_d).and(mos_cap_mk)
+pgate_mv = pgate.and(dualgate2_d).and(mos_cap_mk)
+
+#=====================
+# --- NMOS 1P8 CAP ---
+#=====================
+
+# cap_nmos_01v8 capacitor: 1.8V inversion-mode NMOS capacitor (outside DNWELL) [nmoscap_1p8]
+cap_nmos_01v8_g = ngate_lv_n_nw.not(dnwell)
+
+# cap_nmos_01v8_dn capacitor: 1.8V inversion-mode NMOS capacitor (inside DNWELL) [nmoscap_1p8_dw]
+cap_nmos_01v8_dn_g = ngate_lv_n_nw.and(dnwell)
+
+#=====================
+# --- PMOS 1P8 CAP ---
+#=====================
+
+# cap_pmos_01v8 capacitor: 1.8V inversion-mode PMOS capacitor (outside DNWELL) [pmoscap_1p8]
+cap_pmos_01v8_g = pgate_lv.and(nwell).not(dnwell)
+
+# cap_pmos_01v8_dn capacitor: 1.8V inversion-mode PMOS capacitor (inside DNWELL) [pmoscap_1p8_dw]
+cap_pmos_01v8_dn_g = pgate_lv.and(dnwell)
+
+#=====================
+# --- NMOS 6P0 CAP ---
+#=====================
+
+# cap_nmos_06v0 capacitor: 6.0V inversion-mode NMOS capacitor (outside DNWELL) [nmoscap_6p0]
+cap_nmos_06v0_g = ngate_mv_n_nw.not(dnwell)
+
+# cap_nmos_06v0_dn capacitor: 6.0V inversion-mode NMOS capacitor (inside DNWELL) [nmoscap_6p0_dw]
+cap_nmos_06v0_dn_g = ngate_mv_n_nw.and(dnwell)
+
+#=====================
+# --- PMOS 6P0 CAP ---
+#=====================
+
+# cap_pmos_06v0 capacitor: 6.0V inversion-mode PMOS capacitor (outside DNWELL) [pmoscap_6p0]
+cap_pmos_06v0_g = pgate_mv.and(nwell).not(dnwell)
+
+# cap_pmos_06v0_dn capacitor: 6.0V inversion-mode PMOS capacitor (inside DNWELL) [pmoscap_6p0_dw]
+cap_pmos_06v0_dn_g = pgate_mv.and(dnwell)
+
+#===========================
+# --- NMOS-NWELL 1P8 CAP ---
+#===========================
+
+# cap_nmos_01v8_nwell capacitor: 1.8V NMOS in Nwell capacitor (outside DNWELL) [nmoscap_1p8_nwell]
+cap_nmos_01v8_nwell_g = ngate_lv_nw.not(dnwell)
+
+#============================
+# --- NMOS-DNWELL 1P8 CAP ---
+#============================
+
+# cap_nmos_01v8_dnwell capacitor: 1.8V NMOS in Nwell capacitor (inside DNWELL) [nmoscap_1p8_dnwell]
+cap_nmos_01v8_dnwell_g = ngate_lv_nw.and(dnwell)
+
+#===========================
+# --- NMOS-NWELL 6P0 CAP ---
+#===========================
+
+# cap_nmos_06v0_nwell capacitor: 6V NMOS in Nwell capacitor (outside DNWELL) [nmoscap_6p0_nwell]
+cap_nmos_06v0_nwell_g = ngate_mv_nw.not(dnwell)
+
+#============================
+# --- NMOS-DNWELL 6P0 CAP ---
+#============================
+
+# cap_nmos_06v0_dnwell capacitor: 6V NMOS in Nwell capacitor (inside DNWELL) [nmoscap_6p0_dnwell]
+cap_nmos_06v0_dnwell_g = ngate_mv_nw.and(dnwell)
diff --git a/BCDLite/klayout/lvs/rule_decks/moscap_extraction.lvs b/BCDLite/klayout/lvs/rule_decks/moscap_extraction.lvs
new file mode 100644
index 0000000..4656e4e
--- /dev/null
+++ b/BCDLite/klayout/lvs/rule_decks/moscap_extraction.lvs
@@ -0,0 +1,115 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#==================================
+# ------- MOSCAP EXTRACTION -------
+#==================================
+
+logger.info('Starting MOSCAP EXTRACTION')
+
+#=====================
+# --- NMOS 1P8 CAP ---
+#=====================
+
+# cap_nmos_01v8 capacitor: 1.8V inversion-mode NMOS capacitor (outside DNWELL) [nmoscap_1p8]
+logger.info('Extracting cap_nmos_01v8 device')
+extract_devices(capacitor('cap_nmos_01v8', 4.4e-15, MosCap),
+ { 'P1' => cap_nmos_01v8_g, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+# cap_nmos_01v8_dn capacitor: 1.8V inversion-mode NMOS capacitor (inside DNWELL) [nmoscap_1p8_dw]
+logger.info('Extracting cap_nmos_01v8_dn device')
+extract_devices(capacitor('cap_nmos_01v8_dn', 4.4e-15, MosCap),
+ { 'P1' => cap_nmos_01v8_dn_g, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+#=====================
+# --- PMOS 1P8 CAP ---
+#=====================
+
+# cap_pmos_01v8 capacitor: 1.8V inversion-mode PMOS capacitor (outside DNWELL) [pmoscap_1p8]
+logger.info('Extracting cap_pmos_01v8 device')
+extract_devices(capacitor('cap_pmos_01v8', 4.4e-15, MosCap),
+ { 'P1' => cap_pmos_01v8_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => psd })
+
+# cap_pmos_01v8_dn capacitor: 1.8V inversion-mode PMOS capacitor (inside DNWELL) [pmoscap_1p8_dw]
+logger.info('Extracting cap_pmos_01v8_dn device')
+extract_devices(capacitor('cap_pmos_01v8_dn', 4.4e-15, MosCap),
+ { 'P1' => cap_pmos_01v8_dn_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => psd_dw })
+
+#=====================
+# --- NMOS 6P0 CAP ---
+#=====================
+
+# cap_nmos_06v0 capacitor: 6.0V inversion-mode NMOS capacitor (outside DNWELL) [nmoscap_6p0]
+logger.info('Extracting cap_nmos_06v0 device')
+extract_devices(capacitor('cap_nmos_06v0', 2.3e-15, MosCap),
+ { 'P1' => cap_nmos_06v0_g, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+# cap_nmos_06v0_dn capacitor: 6.0V inversion-mode NMOS capacitor (inside DNWELL) [nmoscap_6p0_dw]
+logger.info('Extracting cap_nmos_06v0_dn device')
+extract_devices(capacitor('cap_nmos_06v0_dn', 2.3e-15, MosCap),
+ { 'P1' => cap_nmos_06v0_dn_g, 'P2' => lvpwell_con, 'tA' => poly2_con, 'tB' => nsd })
+
+#=====================
+# --- PMOS 6P0 CAP ---
+#=====================
+
+# cap_pmos_06v0 capacitor: 6.0V inversion-mode PMOS capacitor (outside DNWELL) [pmoscap_6p0]
+logger.info('Extracting cap_pmos_06v0 device')
+extract_devices(capacitor('cap_pmos_06v0', 2.3e-15, MosCap),
+ { 'P1' => cap_pmos_06v0_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => psd })
+
+# cap_pmos_06v0_dn capacitor: 6.0V inversion-mode PMOS capacitor (inside DNWELL) [pmoscap_6p0_dw]
+logger.info('Extracting cap_pmos_06v0_dn device')
+extract_devices(capacitor('cap_pmos_06v0_dn', 2.3e-15, MosCap),
+ { 'P1' => cap_pmos_06v0_dn_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => psd_dw })
+
+#===========================
+# --- NMOS-NWELL 1P8 CAP ---
+#===========================
+
+# cap_nmos_01v8_nwell capacitor: 1.8V NMOS in Nwell capacitor (outside DNWELL) [nmoscap_1p8_nwell]
+logger.info('Extracting cap_nmos_01v8_nwell device')
+extract_devices(capacitor('cap_nmos_01v8_nwell', 4.4e-15, MosCap),
+ { 'P1' => cap_nmos_01v8_nwell_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+#============================
+# --- NMOS-DNWELL 1P8 CAP ---
+#============================
+
+# cap_nmos_01v8_dnwell capacitor: 1.8V NMOS in Nwell capacitor (inside DNWELL) [nmoscap_1p8_dnwell]
+logger.info('Extracting cap_nmos_01v8_dnwell device')
+extract_devices(capacitor('cap_nmos_01v8_dnwell', 4.4e-15, MosCap),
+ { 'P1' => cap_nmos_01v8_dnwell_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
+
+#===========================
+# --- NMOS-NWELL 6P0 CAP ---
+#===========================
+
+# cap_nmos_06v0_nwell capacitor: 6V NMOS in Nwell capacitor (outside DNWELL) [nmoscap_6p0_nwell]
+logger.info('Extracting cap_nmos_06v0_nwell device')
+extract_devices(capacitor('cap_nmos_06v0_nwell', 2.3e-15, MosCap),
+ { 'P1' => cap_nmos_06v0_nwell_g, 'P2' => nwell_con, 'tA' => poly2_con, 'tB' => ntap })
+
+#============================
+# --- NMOS-DNWELL 6P0 CAP ---
+#============================
+
+# cap_nmos_06v0_dnwell capacitor: 6V NMOS in Nwell capacitor (inside DNWELL) [nmoscap_6p0_dnwell]
+logger.info('Extracting cap_nmos_06v0_dnwell device')
+extract_devices(capacitor('cap_nmos_06v0_dnwell', 2.3e-15, MosCap),
+ { 'P1' => cap_nmos_06v0_dnwell_g, 'P2' => dnwell, 'tA' => poly2_con, 'tB' => ntap })
+
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dw2ps.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dw2ps.gds
new file mode 100644
index 0000000..563ebe2
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dw2ps.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pw2dw.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pw2dw.gds
new file mode 100644
index 0000000..9c6b060
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pw2dw.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_sc.gds b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_sc.gds
new file mode 100644
index 0000000..a7db85c
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_sc.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dw2ps.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dw2ps.cdl
new file mode 100644
index 0000000..ebdf256
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dw2ps.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_dw2ps
+* View Name: schematic
+* Netlisted on: Nov 24 09:04:18 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_dw2ps
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_dw2ps I1_0_0_0_0_R0_NEG I1_0_1_0_0_R0_NEG I1_0_2_0_0_R0_NEG
++ I1_1_0_0_0_R0_NEG I1_1_1_0_0_R0_NEG I1_1_2_0_0_R0_NEG I1_2_0_0_0_R0_NEG
++ I1_2_1_0_0_R0_NEG I1_2_2_0_0_R0_NEG I1_default_NEG gnd!
+*.PININFO I1_0_0_0_0_R0_NEG:I I1_0_1_0_0_R0_NEG:I I1_0_2_0_0_R0_NEG:I
+*.PININFO I1_1_0_0_0_R0_NEG:I I1_1_1_0_0_R0_NEG:I I1_1_2_0_0_R0_NEG:I
+*.PININFO I1_2_0_0_0_R0_NEG:I I1_2_1_0_0_R0_NEG:I I1_2_2_0_0_R0_NEG:I
+*.PININFO I1_default_NEG:I gnd!:I
+DI1_2_2_0_0_R0 gnd! I1_2_2_0_0_R0_NEG diode_dw2ps AREA=10n PJ=400e-6 m=1
+DI1_2_1_0_0_R0 gnd! I1_2_1_0_0_R0_NEG diode_dw2ps AREA=1.034n PJ=220.68e-6 m=1
+DI1_2_0_0_0_R0 gnd! I1_2_0_0_0_R0_NEG diode_dw2ps AREA=170p PJ=203.4e-6 m=1
+DI1_1_2_0_0_R0 gnd! I1_1_2_0_0_R0_NEG diode_dw2ps AREA=1.034n PJ=220.68e-6 m=1
+DI1_1_1_0_0_R0 gnd! I1_1_1_0_0_R0_NEG diode_dw2ps AREA=106.916p PJ=41.36e-6 m=1
+DI1_1_0_0_0_R0 gnd! I1_1_0_0_0_R0_NEG diode_dw2ps AREA=17.578p PJ=24.08e-6 m=1
+DI1_0_2_0_0_R0 gnd! I1_0_2_0_0_R0_NEG diode_dw2ps AREA=170p PJ=203.4e-6 m=1
+DI1_0_1_0_0_R0 gnd! I1_0_1_0_0_R0_NEG diode_dw2ps AREA=17.578p PJ=24.08e-6 m=1
+DI1_0_0_0_0_R0 gnd! I1_0_0_0_0_R0_NEG diode_dw2ps AREA=3.1535p PJ=7.11e-6 m=1
+DI1_default gnd! I1_default_NEG diode_dw2ps AREA=100e-12 PJ=40e-6 m=1
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwpw.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pw2dw.cdl
similarity index 61%
rename from IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwpw.cdl
rename to BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pw2dw.cdl
index 4f085b6..3b58e57 100644
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwpw.cdl
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pw2dw.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: diode_dnwpw
+* Top Cell Name: diode_pw2dw
* View Name: schematic
* Netlisted on: Nov 24 09:06:01 2021
************************************************************************
@@ -24,11 +24,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: diode_dnwpw
+* Cell Name: diode_pw2dw
* View Name: schematic
************************************************************************
-.SUBCKT diode_dnwpw I1_0_0_0_0_0_R0_POS I1_0_1_0_0_0_R0_POS I1_0_2_0_0_0_R0_POS
+.SUBCKT diode_pw2dw I1_0_0_0_0_0_R0_POS I1_0_1_0_0_0_R0_POS I1_0_2_0_0_0_R0_POS
+ I1_1_0_0_0_0_R0_POS I1_1_1_0_0_0_R0_POS I1_1_2_0_0_0_R0_POS
+ I1_2_0_0_0_0_R0_POS I1_2_1_0_0_0_R0_POS I1_2_2_0_0_0_R0_POS I1_default_POS
+ vdd!
@@ -36,15 +36,15 @@
*.PININFO I1_1_0_0_0_0_R0_POS:I I1_1_1_0_0_0_R0_POS:I I1_1_2_0_0_0_R0_POS:I
*.PININFO I1_2_0_0_0_0_R0_POS:I I1_2_1_0_0_0_R0_POS:I I1_2_2_0_0_0_R0_POS:I
*.PININFO I1_default_POS:I vdd!:I
-DI1_2_2_0_0_0_R0 I1_2_2_0_0_0_R0_POS vdd! diode_dnwpw AREA=10n PJ=400e-6 m=1
-DI1_2_1_0_0_0_R0 I1_2_1_0_0_0_R0_POS vdd! diode_dnwpw AREA=1.023n PJ=220.46e-6 m=1
-DI1_2_0_0_0_0_R0 I1_2_0_0_0_0_R0_POS vdd! diode_dnwpw AREA=60p PJ=201.2e-6 m=1
-DI1_1_2_0_0_0_R0 I1_1_2_0_0_0_R0_POS vdd! diode_dnwpw AREA=1.023n PJ=220.46e-6 m=1
-DI1_1_1_0_0_0_R0 I1_1_1_0_0_0_R0_POS vdd! diode_dnwpw AREA=104.653p PJ=40.92e-6 m=1
-DI1_1_0_0_0_0_R0 I1_1_0_0_0_0_R0_POS vdd! diode_dnwpw AREA=6.138p PJ=21.66e-6 m=1
-DI1_0_2_0_0_0_R0 I1_0_2_0_0_0_R0_POS vdd! diode_dnwpw AREA=60p PJ=201.2e-6 m=1
-DI1_0_1_0_0_0_R0 I1_0_1_0_0_0_R0_POS vdd! diode_dnwpw AREA=6.138p PJ=21.66e-6 m=1
-DI1_0_0_0_0_0_R0 I1_0_0_0_0_0_R0_POS vdd! diode_dnwpw AREA=627f PJ=3.29e-6 m=1
-DI1_default I1_default_POS vdd! diode_dnwpw AREA=100e-12 PJ=40e-6 m=1
+DI1_2_2_0_0_0_R0 I1_2_2_0_0_0_R0_POS vdd! diode_pw2dw AREA=10n PJ=400e-6 m=1
+DI1_2_1_0_0_0_R0 I1_2_1_0_0_0_R0_POS vdd! diode_pw2dw AREA=1.023n PJ=220.46e-6 m=1
+DI1_2_0_0_0_0_R0 I1_2_0_0_0_0_R0_POS vdd! diode_pw2dw AREA=60p PJ=201.2e-6 m=1
+DI1_1_2_0_0_0_R0 I1_1_2_0_0_0_R0_POS vdd! diode_pw2dw AREA=1.023n PJ=220.46e-6 m=1
+DI1_1_1_0_0_0_R0 I1_1_1_0_0_0_R0_POS vdd! diode_pw2dw AREA=104.653p PJ=40.92e-6 m=1
+DI1_1_0_0_0_0_R0 I1_1_0_0_0_0_R0_POS vdd! diode_pw2dw AREA=6.138p PJ=21.66e-6 m=1
+DI1_0_2_0_0_0_R0 I1_0_2_0_0_0_R0_POS vdd! diode_pw2dw AREA=60p PJ=201.2e-6 m=1
+DI1_0_1_0_0_0_R0 I1_0_1_0_0_0_R0_POS vdd! diode_pw2dw AREA=6.138p PJ=21.66e-6 m=1
+DI1_0_0_0_0_0_R0 I1_0_0_0_0_0_R0_POS vdd! diode_pw2dw AREA=627f PJ=3.29e-6 m=1
+DI1_default I1_default_POS vdd! diode_pw2dw AREA=100e-12 PJ=40e-6 m=1
.ENDS
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_sc.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_sc.cdl
new file mode 100644
index 0000000..f077c9f
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_sc.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_sc
+* View Name: schematic
+* Netlisted on: Nov 24 10:18:05 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_sc
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_sc I1_0_0_R0_n I1_0_0_R0_p I1_0_1_R0_n I1_0_1_R0_p I1_0_2_R0_n
++ I1_0_2_R0_p I1_1_0_R0_n I1_1_0_R0_p I1_1_1_R0_n I1_1_1_R0_p I1_1_2_R0_n
++ I1_1_2_R0_p I1_2_0_R0_n I1_2_0_R0_p I1_2_1_R0_n I1_2_1_R0_p I1_2_2_R0_n
++ I1_2_2_R0_p I1_default_n I1_default_p
+*.PININFO I1_0_0_R0_n:I I1_0_0_R0_p:I I1_0_1_R0_n:I I1_0_1_R0_p:I
+*.PININFO I1_0_2_R0_n:I I1_0_2_R0_p:I I1_1_0_R0_n:I I1_1_0_R0_p:I
+*.PININFO I1_1_1_R0_n:I I1_1_1_R0_p:I I1_1_2_R0_n:I I1_1_2_R0_p:I
+*.PININFO I1_2_0_R0_n:I I1_2_0_R0_p:I I1_2_1_R0_n:I I1_2_1_R0_p:I
+*.PININFO I1_2_2_R0_n:I I1_2_2_R0_p:I I1_default_n:I I1_default_p:I
+DI1_2_2_R0 I1_2_2_R0_p I1_2_2_R0_n diode_sc m=9.0 l=100u w=620.00n
+DI1_2_1_R0 I1_2_1_R0_p I1_2_1_R0_n diode_sc m=6.0 l=100u w=620.00n
+DI1_2_0_R0 I1_2_0_R0_p I1_2_0_R0_n diode_sc m=1.0 l=100u w=620.00n
+DI1_1_2_R0 I1_1_2_R0_p I1_1_2_R0_n diode_sc m=9.0 l=12.3u w=620.00n
+DI1_1_1_R0 I1_1_1_R0_p I1_1_1_R0_n diode_sc m=6.0 l=12.3u w=620.00n
+DI1_1_0_R0 I1_1_0_R0_p I1_1_0_R0_n diode_sc m=1.0 l=12.3u w=620.00n
+DI1_0_2_R0 I1_0_2_R0_p I1_0_2_R0_n diode_sc m=9.0 l=1u w=620.00n
+DI1_0_1_R0 I1_0_1_R0_p I1_0_1_R0_n diode_sc m=6.0 l=1u w=620.00n
+DI1_0_0_R0 I1_0_0_R0_p I1_0_0_R0_n diode_sc m=1.0 l=1u w=620.00n
+DI1_default I1_default_p I1_default_n diode_sc m=4.0 l=20u w=620.00n
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8.gds
new file mode 100644
index 0000000..7d17eea
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dn.gds
new file mode 100644
index 0000000..8cf9f2f
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dnwell.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dnwell.gds
new file mode 100644
index 0000000..55048e9
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_dnwell.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_nwell.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_nwell.gds
new file mode 100644
index 0000000..d0ae546
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_01v8_nwell.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0.gds
new file mode 100644
index 0000000..76009a0
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dn.gds
new file mode 100644
index 0000000..929e0b3
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dnwell.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dnwell.gds
new file mode 100644
index 0000000..4c9b13b
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_dnwell.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_nwell.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_nwell.gds
new file mode 100644
index 0000000..ee28fa4
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_nmos_06v0_nwell.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8.gds
new file mode 100644
index 0000000..834c552
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8_dn.gds
new file mode 100644
index 0000000..96caa4e
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_01v8_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0.gds
new file mode 100644
index 0000000..1d1ca6c
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0_dn.gds b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0_dn.gds
new file mode 100644
index 0000000..1a302b1
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/layout/cap_pmos_06v0_dn.gds
Binary files differ
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8.cdl
new file mode 100644
index 0000000..72b5531
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_nmos_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:07:52 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_nmos_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_nmos_01v8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_01v8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_01v8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_01v8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_01v8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_01v8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_01v8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_01v8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_01v8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_01v8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_01v8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dn.cdl
new file mode 100644
index 0000000..dfc0b41
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_nmos_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:12:27 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_nmos_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_nmos_01v8_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_01v8_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_01v8_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_01v8_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_01v8_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_01v8_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_01v8_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_01v8_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_01v8_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_01v8_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_01v8_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dnwell.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dnwell.cdl
new file mode 100644
index 0000000..b199a3e
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_dnwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_nmos_01v8_dnwell
+* View Name: schematic
+* Netlisted on: Nov 24 09:11:11 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_nmos_01v8_dnwell
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_nmos_01v8_dnwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_01v8_dnwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_01v8_dnwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_01v8_dnwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_01v8_dnwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_01v8_dnwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_01v8_dnwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_01v8_dnwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_01v8_dnwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_01v8_dnwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_01v8_dnwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_nwell.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_nwell.cdl
new file mode 100644
index 0000000..2671210
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_01v8_nwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_nmos_01v8_nwell
+* View Name: schematic
+* Netlisted on: Nov 24 09:11:11 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_nmos_01v8_nwell
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_nmos_01v8_nwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_01v8_nwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_01v8_nwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_01v8_nwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_01v8_nwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_01v8_nwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_01v8_nwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_01v8_nwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_01v8_nwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_01v8_nwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_01v8_nwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0.cdl
new file mode 100644
index 0000000..bf895e5
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_nmos_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:13:17 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_nmos_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_nmos_06v0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_06v0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_06v0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_06v0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_06v0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_06v0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_06v0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_06v0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_06v0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_06v0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_06v0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dn.cdl
new file mode 100644
index 0000000..a810f36
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_nmos_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:15:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_nmos_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_nmos_06v0_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_06v0_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_06v0_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_06v0_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_06v0_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_06v0_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_06v0_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_06v0_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_06v0_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_06v0_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_06v0_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dnwell.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dnwell.cdl
new file mode 100644
index 0000000..b74909f
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_dnwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_nmos_06v0_dnwell
+* View Name: schematic
+* Netlisted on: Nov 24 09:14:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_nmos_06v0_dnwell
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_nmos_06v0_dnwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_06v0_dnwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_06v0_dnwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_06v0_dnwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_06v0_dnwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_06v0_dnwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_06v0_dnwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_06v0_dnwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_06v0_dnwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_06v0_dnwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_06v0_dnwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_nwell.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_nwell.cdl
new file mode 100644
index 0000000..56954d0
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_nmos_06v0_nwell.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_nmos_06v0_nwell
+* View Name: schematic
+* Netlisted on: Nov 24 09:14:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_nmos_06v0_nwell
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_nmos_06v0_nwell I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_nmos_06v0_nwell m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_nmos_06v0_nwell m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_nmos_06v0_nwell m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_nmos_06v0_nwell m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_nmos_06v0_nwell m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_nmos_06v0_nwell m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_nmos_06v0_nwell m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_nmos_06v0_nwell m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_nmos_06v0_nwell m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_nmos_06v0_nwell m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8.cdl
new file mode 100644
index 0000000..fb8e48f
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pmos_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:44:20 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pmos_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pmos_01v8 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_pmos_01v8 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_pmos_01v8 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_pmos_01v8 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_pmos_01v8 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_pmos_01v8 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_pmos_01v8 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_pmos_01v8 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_pmos_01v8 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_pmos_01v8 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_pmos_01v8 m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8_dn.cdl
new file mode 100644
index 0000000..ca920ad
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_01v8_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pmos_01v8_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:45:53 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pmos_01v8_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pmos_01v8_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_pmos_01v8_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_pmos_01v8_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_pmos_01v8_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_pmos_01v8_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_pmos_01v8_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_pmos_01v8_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_pmos_01v8_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_pmos_01v8_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_pmos_01v8_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_pmos_01v8_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0.cdl
new file mode 100644
index 0000000..24a54a3
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pmos_06v0
+* View Name: schematic
+* Netlisted on: Nov 24 09:47:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pmos_06v0
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pmos_06v0 I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_pmos_06v0 m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_pmos_06v0 m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_pmos_06v0 m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_pmos_06v0 m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_pmos_06v0 m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_pmos_06v0 m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_pmos_06v0 m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_pmos_06v0 m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_pmos_06v0 m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_pmos_06v0 m=1 l=5u w=5u
+.ENDS
+
diff --git a/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0_dn.cdl b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0_dn.cdl
new file mode 100644
index 0000000..8435c90
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/unit/moscap_devices/netlist/cap_pmos_06v0_dn.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_pmos_06v0_dn
+* View Name: schematic
+* Netlisted on: Nov 24 09:48:31 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_pmos_06v0_dn
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_pmos_06v0_dn I1_0_0_R0_D I1_0_0_R0_G I1_0_1_R0_D I1_0_1_R0_G
++ I1_0_2_R0_D I1_0_2_R0_G I1_1_0_R0_D I1_1_0_R0_G I1_1_1_R0_D I1_1_1_R0_G
++ I1_1_2_R0_D I1_1_2_R0_G I1_2_0_R0_D I1_2_0_R0_G I1_2_1_R0_D I1_2_1_R0_G
++ I1_2_2_R0_D I1_2_2_R0_G I1_default_D I1_default_G
+*.PININFO I1_0_0_R0_D:I I1_0_0_R0_G:I I1_0_1_R0_D:I I1_0_1_R0_G:I
+*.PININFO I1_0_2_R0_D:I I1_0_2_R0_G:I I1_1_0_R0_D:I I1_1_0_R0_G:I
+*.PININFO I1_1_1_R0_D:I I1_1_1_R0_G:I I1_1_2_R0_D:I I1_1_2_R0_G:I
+*.PININFO I1_2_0_R0_D:I I1_2_0_R0_G:I I1_2_1_R0_D:I I1_2_1_R0_G:I
+*.PININFO I1_2_2_R0_D:I I1_2_2_R0_G:I I1_default_D:I I1_default_G:I
+CI1_2_2_R0 I1_2_2_R0_G I1_2_2_R0_D cap_pmos_06v0_dn m=1 l=50.000u w=50.000u
+CI1_2_1_R0 I1_2_1_R0_G I1_2_1_R0_D cap_pmos_06v0_dn m=1 l=50.000u w=12.350u
+CI1_2_0_R0 I1_2_0_R0_G I1_2_0_R0_D cap_pmos_06v0_dn m=1 l=50.000u w=1.000u
+CI1_1_2_R0 I1_1_2_R0_G I1_1_2_R0_D cap_pmos_06v0_dn m=1 l=12.350u w=50.000u
+CI1_1_1_R0 I1_1_1_R0_G I1_1_1_R0_D cap_pmos_06v0_dn m=1 l=12.350u w=12.350u
+CI1_1_0_R0 I1_1_0_R0_G I1_1_0_R0_D cap_pmos_06v0_dn m=1 l=12.350u w=1.000u
+CI1_0_2_R0 I1_0_2_R0_G I1_0_2_R0_D cap_pmos_06v0_dn m=1 l=1.000u w=50.000u
+CI1_0_1_R0 I1_0_1_R0_G I1_0_1_R0_D cap_pmos_06v0_dn m=1 l=1.000u w=12.350u
+CI1_0_0_R0 I1_0_0_R0_G I1_0_0_R0_D cap_pmos_06v0_dn m=1 l=1.000u w=1.000u
+CI1_default I1_default_G I1_default_D cap_pmos_06v0_dn m=1 l=5u w=5u
+.ENDS
+
diff --git a/IC/klayout/lvs/gf180ic.lvs b/IC/klayout/lvs/gf180IC.lvs
similarity index 84%
rename from IC/klayout/lvs/gf180ic.lvs
rename to IC/klayout/lvs/gf180IC.lvs
index c15c0b8..b543779 100644
--- a/IC/klayout/lvs/gf180ic.lvs
+++ b/IC/klayout/lvs/gf180IC.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -30,7 +30,6 @@
"
end
-
#================================================
#----------------- FILE SETUP -------------------
#================================================
@@ -78,7 +77,7 @@
end
#=== GET SUBSTRATE NAME ===
-substrate_name = $lvs_sub || 'gf180ic_gnd'
+substrate_name = $lvs_sub || 'gf180IC_gnd'
logger.info("Substrate name used: #{$lvs_sub}")
@@ -139,7 +138,7 @@
logger.info("Selected PURGE_NETS option: #{PURGE_NETS}")
# SIMPLIFY
-SIMPLIFY = if $net_only || $top_lvl_pins || $combine || $purge || $purge_nets
+SIMPLIFY = if NET_ONLY || TOP_LVL_PINS || COMBINE || PURGE || PURGE_NETS
false
else
true
@@ -188,47 +187,10 @@
logger.info("MIM Option selected: #{MIM_OPTION}")
# MIM
-MIM_CAP = $mim_cap || '0'
+MIM_CAP = $mim_cap || '2'
logger.info("MIM CAP selected: #{MIM_CAP}")
-MIM_CAP_STACK = $mim_cap_stack || '0'
-
-logger.info("STACKED MIM CAP selected: #{MIM_CAP_STACK}")
-
-#================================================
-#------------- METAL LEVEL SWITCHES -------------
-#================================================
-
-case MIM_OPTION
-when 'A'
- cap_mim1f0 = 'cap_mim_1f0_m2m3_noshield'
- cap_mim1f5 = 'cap_mim_1f5_m2m3_noshield'
- cap_mim_single_2f0 = 'cap_mim_single_2f0_m2m3_noshield'
-
-when 'B'
- case METAL_LEVEL
- when '6LM'
- cap_mim1f0 = 'cap_mim_1f0_m5m6_noshield'
- cap_mim1f5 = 'cap_mim_1f5_m5m6_noshield'
- cap_mim_single_2f0 = 'cap_mim_single_2f0_m5m6_noshield'
- cap_mim2f0 = 'cap_mim_2f0_m4m6_noshield'
- cap_mim3f0 = 'cap_mim_3f0_m4m6_noshield'
- when '5LM'
- cap_mim1f0 = 'cap_mim_1f0_m4m5_noshield'
- cap_mim1f5 = 'cap_mim_1f5_m4m5_noshield'
- cap_mim_single_2f0 = 'cap_mim_single_2f0_m4m5_noshield'
- cap_mim2f0 = 'cap_mim_2f0_m3m5_noshield'
- cap_mim3f0 = 'cap_mim_3f0_m3m5_noshield'
- when '4LM'
- cap_mim1f0 = 'cap_mim_1f0_m3m4_noshield'
- cap_mim1f5 = 'cap_mim_1f5_m3m4_noshield'
- cap_mim_single_2f0 = 'cap_mim_single_2f0_m3m4_noshield'
- cap_mim2f0 = 'cap_mim_2f0_m2m4_noshield'
- cap_mim3f0 = 'cap_mim_3f0_m2m4_noshield'
- end
-end
-
#================================================
# --------------- CUSTOM CLASSES ----------------
#================================================
@@ -278,7 +240,6 @@
# %include rule_decks/general_derivations.lvs
-
#==================================
# ------ MOSFET DERIVATIONS -------
#==================================
@@ -309,14 +270,6 @@
# %include rule_decks/mimcap_derivations.lvs
-#==================================
-# ------ Varactors DERIVATIONS -------
-#==================================
-
-# %include rule_decks/mos_varactor_derivations.lvs
-# %include rule_decks/pn_varactor_derivations.lvs
-
-
#================================================
#------------ DEVICES CONNECTIVITY --------------
#================================================
@@ -359,14 +312,6 @@
# %include rule_decks/mimcap_extraction.lvs
-#==================================
-# ------ Varactors EXTRACTION -------
-#==================================
-
-# %include rule_decks/mos_varactor_extraction.lvs
-# %include rule_decks/pn_varactor_extraction.lvs
-
-
#================================================
#------------- COMPARISON OPTIONS ---------------
#================================================
diff --git a/IC/klayout/lvs/rule_decks/bjt_connection.lvs b/IC/klayout/lvs/rule_decks/bjt_connections.lvs
similarity index 97%
rename from IC/klayout/lvs/rule_decks/bjt_connection.lvs
rename to IC/klayout/lvs/rule_decks/bjt_connections.lvs
index 5e21220..bf3f2c2 100644
--- a/IC/klayout/lvs/rule_decks/bjt_connection.lvs
+++ b/IC/klayout/lvs/rule_decks/bjt_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/IC/klayout/lvs/rule_decks/bjt_derivations.lvs b/IC/klayout/lvs/rule_decks/bjt_derivations.lvs
index ea43ee5..00df7ba 100644
--- a/IC/klayout/lvs/rule_decks/bjt_derivations.lvs
+++ b/IC/klayout/lvs/rule_decks/bjt_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/IC/klayout/lvs/rule_decks/bjt_extraction.lvs b/IC/klayout/lvs/rule_decks/bjt_extraction.lvs
index 45ffb86..6bdd5e7 100644
--- a/IC/klayout/lvs/rule_decks/bjt_extraction.lvs
+++ b/IC/klayout/lvs/rule_decks/bjt_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/IC/klayout/lvs/rule_decks/custom_classes.lvs b/IC/klayout/lvs/rule_decks/custom_classes.lvs
index d0e84fd..e9df15f 100644
--- a/IC/klayout/lvs/rule_decks/custom_classes.lvs
+++ b/IC/klayout/lvs/rule_decks/custom_classes.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/IC/klayout/lvs/rule_decks/devices_connections.lvs b/IC/klayout/lvs/rule_decks/devices_connections.lvs
index 4917c52..25e7eba 100644
--- a/IC/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/IC/klayout/lvs/rule_decks/devices_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -24,103 +24,28 @@
# ----- GENERAL CONNECTIONS -----
#================================
-logger.info('Starting GF180 LVS connectivity setup (Inter-layer)')
-
-# Inter-layer
-connect(sub, ptap)
-connect(dnwell, ntap_dw)
-connect(nwell_con, ntap)
-connect(ptap, contact)
-connect(ptap_dw, contact)
-connect(ntap, contact)
-connect(ntap_dw, contact)
-connect(psd, contact)
-connect(psd_dw, contact)
-connect(nsd, contact)
-connect(poly2_con, contact)
-connect(contact, metal1)
-connect(metal1, via1)
-connect(via1, metal2)
-if METAL_LEVEL != '2LM'
- connect(metal2, via2_ncap)
- connect(via2_ncap, metal3)
- connect(via2_cap, fusetop)
- connect(via2_cap, fusetop2)
- if METAL_LEVEL != '3LM'
- connect(metal3, via3_ncap)
- connect(via3_ncap, metal4)
- connect(via3_cap, fusetop)
- connect(via3_cap, fusetop2)
- if METAL_LEVEL != '4LM'
- connect(metal4, via4_ncap)
- connect(via4_ncap, metal5)
- connect(via4_cap, fusetop)
- connect(via4_cap, fusetop2)
- if METAL_LEVEL != '5LM'
- connect(metal5, via5_ncap)
- connect(via5_ncap, metaltop)
- connect(via5_cap, fusetop)
- connect(via5_cap, fusetop2)
- end
- end
- end
-end
-
-logger.info('Starting GF180 LVS connectivity setup (Attaching labels)')
-
-# Attaching labels
-connect(comp, comp_label)
-connect(poly2_con, poly2_label)
-connect(metal1, metal1_label)
-connect(metal2, metal2_label)
-if METAL_LEVEL != '2LM'
- connect(metal3, metal3_label)
- if METAL_LEVEL != '3LM'
- connect(metal4, metal4_label)
- if METAL_LEVEL != '4LM'
- connect(metal5, metal5_label)
- connect(metaltop, metaltop_label) if METAL_LEVEL != '5LM'
- end
- end
-end
-
-logger.info('Starting GF180 LVS connectivity setup (Global)')
-
-# Global
-connect_global(sub, substrate_name)
-
-logger.info('Starting GF180 LVS connectivity setup (Multifinger Devices)')
-
-# Multifinger Devices
-connect_implicit('*')
-
+# %include general_connections.lvs
#================================
# ------ BJT CONNECTIONS --------
#================================
-# %include bjt_connection.lvs
+# %include bjt_connections.lvs
#================================
# ----- DIODE CONNECTIONS -------
#================================
-# %include diode_connection.lvs
+# %include diode_connections.lvs
#==================================
# ------ MIMCAP CONNECTIONS -------
#==================================
-# %include mimcap_connection.lvs
-
-#========================================
-# ------ PN Varactors CONNECTIONS -------
-#========================================
-
-# %include pn_varactor_connection.lvs
+# %include mimcap_connections.lvs
#================================
# ---- RESISTOR DERIVATIONS -----
#================================
-# %include res_connection.lvs
+# %include res_connections.lvs
diff --git a/IC/klayout/lvs/rule_decks/diode_connection.lvs b/IC/klayout/lvs/rule_decks/diode_connection.lvs
deleted file mode 100644
index 2bd1560..0000000
--- a/IC/klayout/lvs/rule_decks/diode_connection.lvs
+++ /dev/null
@@ -1,55 +0,0 @@
-################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-################################################################################################
-
-#================================
-# ----- DIODE CONNECTIONS -------
-#================================
-
-logger.info('Starting LVS DIODE CONNECTIONS')
-
-# diode_np_1p8
-connect(diode_np_1p8_terminal_n, contact)
-connect(diode_np_1p8_terminal_p, contact)
-
-# diode_pn_1p8
-connect(diode_pn_1p8_terminal_n, contact)
-connect(diode_pn_1p8_terminal_p, contact)
-
-# diode_np_3p3
-connect(diode_np_3p3_terminal_n, contact)
-connect(diode_np_3p3_terminal_p, contact)
-
-# diode_pn_3p3
-connect(diode_pn_3p3_terminal_n, contact)
-connect(diode_pn_3p3_terminal_p, contact)
-
-# diode_nwp
-connect(diode_nwp_terminal_n, contact)
-connect(diode_nwp_terminal_p, contact)
-
-# diode_np_1p8_nat
-connect(diode_np_1p8_nat_terminal_n, contact)
-connect(diode_np_1p8_nat_terminal_p, contact)
-
-# diode_np_3p3_nat
-connect(diode_np_3p3_nat_terminal_n, contact)
-connect(diode_np_3p3_nat_terminal_p, contact)
-
-# diode_dnwpw
-connect(diode_dnwps_terminal_p, contact)
-
-# diode_dnwps
-connect(diode_dnwps_terminal_p, contact)
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/diode_connections.lvs b/IC/klayout/lvs/rule_decks/diode_connections.lvs
new file mode 100644
index 0000000..dcf1bfa
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/diode_connections.lvs
@@ -0,0 +1,82 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- DIODE CONNECTIONS -------
+#================================
+
+logger.info('Starting LVS DIODE CONNECTIONS')
+
+#=====================
+# --- NP 1P8 DIODE ---
+#=====================
+
+# diode_nd2ps_01v8: Model for 1.8V thin gate N+/Psub diode [diode_np_1p8]
+connect(diode_np_1p8_terminal_n, contact)
+connect(diode_np_1p8_terminal_p, ptap)
+
+# diode_nd2ps_01v8_nvt: Model for 1.8V thin gate N+/Psub native diode [diode_np_1p8_nat]
+connect(diode_np_1p8_nat_terminal_n, contact)
+connect(diode_np_1p8_nat_terminal_p, ptap)
+
+#=====================
+# --- PN 1P8 DIODE ---
+#=====================
+
+# diode_pd2nw_01v8: Model for 1.8V thin gate P+/Nwell diode: [diode_pn_1p8]
+connect(diode_pn_1p8_terminal_p, contact)
+
+#=====================
+# --- NP 3P0 DIODE ---
+#=====================
+
+# diode_nd2ps_03v3: Model for 3.3V thick gate N+/Psub diode: [diode_np_3p3]
+connect(diode_np_3p3_terminal_n, contact)
+connect(diode_np_3p3_terminal_p, ptap)
+
+# diode_nd2ps_03v3_nvt: Model for 3.3V thick gate N+/Psub native diode [diode_np_3p3_nat]
+connect(diode_np_3p3_nat_terminal_n, contact)
+connect(diode_np_3p3_nat_terminal_p, ptap)
+
+#=====================
+# --- PN 3P0 DIODE ---
+#=====================
+
+# diode_pd2nw_03v3: Model for 3.3V thick gate P+/Nwell diode: [diode_pn_3p3]
+connect(diode_pn_3p3_terminal_p, contact)
+
+#==================
+# --- NWP DIODE ---
+#==================
+
+# diode_nw2ps: Model Nwell/psub diode: [diode_nwp]
+connect(diode_nwp_terminal_p, contact)
+connect(diode_nwp_terminal_n, nwell)
+
+#====================
+# --- DNWPW DIODE ---
+#====================
+
+# diode_pw2dw: Model for Pwell/Deep Nwell junction [diode_dnwpw]
+connect(diode_dnwpw_terminal_p, contact)
+
+#====================
+# --- DNWPS DIODE ---
+#====================
+
+# diode_dw2ps: Model for Deep Nwell/Psub junction [diode_dnwps]
+connect(diode_dnwps_terminal_p, ptap)
+connect(diode_dnwps_terminal_n, dnwell)
diff --git a/IC/klayout/lvs/rule_decks/diode_derivations.lvs b/IC/klayout/lvs/rule_decks/diode_derivations.lvs
index c279dfd..407855f 100644
--- a/IC/klayout/lvs/rule_decks/diode_derivations.lvs
+++ b/IC/klayout/lvs/rule_decks/diode_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -20,42 +20,71 @@
logger.info('Starting DIODE DERIVATIONS')
-# diode_np_1p8
-diode_np_1p8_terminal_n = ncomp.not(poly2).not(dualgate).outside(dnwell)
- .not(res_mk).not(sab).not(lvs_bjt).interacting(diode_mk)
+diode_exclude = poly2.join(dnwell).join(res_mk)
+ .join(sab).join(lvs_bjt)
-# diode_pn_1p8
-diode_pn_1p8_terminal_p = pcomp.inside(nwell).not(poly2).not(dualgate).outside(dnwell)
- .not(res_mk).not(sab).not(lvs_bjt).interacting(diode_mk)
+#=====================
+# --- NP 1P8 DIODE ---
+#=====================
-# diode_np_3p3
-diode_np_3p3_terminal_n = ncomp.not(poly2).and(dualgate).outside(dnwell)
- .not(res_mk).not(sab).not(lvs_bjt).interacting(diode_mk)
+# diode_nd2ps_01v8: Model for 1.8V thin gate N+/Psub diode [diode_np_1p8]
+diode_np_1p8_terminal_n = ncomp.and(diode_mk).not(nwell).not(dualgate).not(nat).not(diode_exclude)
-# diode_pn_3p3
-diode_pn_3p3_terminal_p = pcomp.inside(nwell).not(poly2).and(dualgate)
- .outside(dnwell).not(res_mk).not(sab).not(lvs_bjt).interacting(diode_mk)
+diode_np_1p8_terminal_p = diode_mk.interacting(pcomp).not(nwell).not(dualgate).not(nat).not(diode_exclude)
-# diode_nwp
-diode_nwp_terminal_p = pcomp.interacting(well_diode_mk).not(lvs_bjt).inside(diode_mk)
- .not(nat).not(res_mk).not(res_mk_type1)
+# diode_nd2ps_01v8_nvt: Model for 1.8V thin gate N+/Psub native diode [diode_np_1p8_nat]
+diode_np_1p8_nat_terminal_n = ncomp.and(diode_mk).and(nat).not(nwell).not(dualgate).not(diode_exclude)
-diode_nwp_terminal_n = well_diode_mk.covering(nwell).and(diode_mk)
+diode_np_1p8_nat_terminal_p = diode_mk.interacting(pcomp).not(nwell).not(dualgate).and(nat).not(diode_exclude)
+
+#=====================
+# --- PN 1P8 DIODE ---
+#=====================
-# diode_np_1p8_nat
-diode_np_1p8_nat_terminal_n = ncomp.not(poly2).and(nat).not(dualgate).outside(dnwell)
- .not(res_mk).not(sab).not(lvs_bjt).interacting(diode_mk)
+# diode_pd2nw_01v8: Model for 1.8V thin gate P+/Nwell diode: [diode_pn_1p8]
+diode_pn_1p8_terminal_p = pcomp.and(diode_mk).and(nwell).not(dualgate).not(diode_exclude)
-# diode_np_3p3_nat
-diode_np_3p3_nat_terminal_n = ncomp.not(poly2).and(nat).and(dualgate).outside(dnwell)
- .not(res_mk).not(sab).not(lvs_bjt).interacting(diode_mk)
+#=====================
+# --- NP 3P0 DIODE ---
+#=====================
-# diode_dnwpw
-diode_dnwpw_terminal_p = sub.and(well_diode_mk).and(diode_mk).inside(dnwell).and(pplus)
- .not(lvs_bjt).not(nat).not(res_mk_type1).not_covering(nwell)
+# diode_nd2ps_03v3: Model for 3.3V thick gate N+/Psub diode: [diode_np_3p3]
+diode_np_3p3_terminal_n = ncomp.and(diode_mk).and(dualgate).not(nwell).not(nat).not(diode_exclude)
-# diode_dnwps
-diode_dnwps_terminal_p = ptap.extents.not_covering(nat).interacting(diode_mk).interacting(well_diode_mk)
- .not_covering(dualgate).not_interacting(res_mk_type1)
+diode_np_3p3_terminal_p = diode_mk.interacting(pcomp).and(dualgate).not(nwell).not(nat).not(diode_exclude)
+# diode_nd2ps_03v3_nvt: Model for 3.3V thick gate N+/Psub native diode [diode_np_3p3_nat]
+diode_np_3p3_nat_terminal_n = ncomp.and(diode_mk).and(dualgate).and(nat).not(nwell).not(diode_exclude)
+diode_np_3p3_nat_terminal_p = diode_mk.interacting(pcomp).and(dualgate).and(nat).not(nwell).not(diode_exclude)
+
+#=====================
+# --- PN 3P0 DIODE ---
+#=====================
+
+# diode_pd2nw_03v3: Model for 3.3V thick gate P+/Nwell diode: [diode_pn_3p3]
+diode_pn_3p3_terminal_p = pcomp.and(diode_mk).and(nwell).and(dualgate).not(diode_exclude)
+
+#==================
+# --- NWP DIODE ---
+#==================
+
+# diode_nw2ps: Model Nwell/psub diode: [diode_nwp]
+diode_nwp_terminal_p = pcomp.and(well_diode_mk).not(lvs_bjt).not(nat).not(res_mk).not(res_mk_type1)
+diode_nwp_terminal_n = well_diode_mk.covering(nwell.covering(ncomp))
+
+#====================
+# --- DNWPW DIODE ---
+#====================
+
+# diode_pw2dw: Model for Pwell/Deep Nwell junction [diode_dnwpw]
+diode_dnwpw_terminal_p = pcomp.and(dnwell).and(well_diode_mk).and(diode_mk).not(lvs_bjt).not(nat).not(res_mk_type1)
+
+#====================
+# --- DNWPS DIODE ---
+#====================
+
+# diode_dw2ps: Model for Deep Nwell/Psub junction [diode_dnwps]
+diode_dnwps_terminal_p = ptap.extents.interacting(well_diode_mk).interacting(diode_mk)
+ .covering(ncomp.and(dnwell)).not(nat).not(res_mk_type1)
+diode_dnwps_terminal_n = dnwell.and(ptap.holes).not_covering(pcomp)
diff --git a/IC/klayout/lvs/rule_decks/diode_extraction.lvs b/IC/klayout/lvs/rule_decks/diode_extraction.lvs
index 066f06a..a9940d1 100644
--- a/IC/klayout/lvs/rule_decks/diode_extraction.lvs
+++ b/IC/klayout/lvs/rule_decks/diode_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -20,40 +20,68 @@
logger.info('Starting DIODE EXTRACTION')
-# diode_np_1p8
-logger.info('Extracting diode_np_1p8')
-extract_devices(diode('diode_np_1p8'), { 'N' => diode_np_1p8_terminal_n, 'P' => sub })
+#=====================
+# --- NP 1P8 DIODE ---
+#=====================
-# diode_pn_1p8
-logger.info('Extracting diode_pn_1p8')
-extract_devices(diode('diode_pn_1p8'), { 'N' => nwell_con, 'P' => diode_pn_1p8_terminal_p })
+# diode_nd2ps_01v8: Model for 1.8V thin gate N+/Psub diode [diode_np_1p8]
+logger.info('Extracting diode_nd2ps_01v8')
+extract_devices(diode('diode_nd2ps_01v8'), { 'N' => diode_np_1p8_terminal_n, 'P' => diode_np_1p8_terminal_p })
-# diode_np_3p3
-logger.info('Extracting diode_np_3p3')
-extract_devices(diode('diode_np_3p3'), { 'N' => diode_np_3p3_terminal_n, 'P' => sub })
+# diode_nd2ps_01v8_nvt: Model for 1.8V thin gate N+/Psub native diode [diode_np_1p8_nat]
+logger.info('Extracting diode_nd2ps_01v8_nvt')
+extract_devices(diode('diode_nd2ps_01v8_nvt'), { 'N' => diode_np_1p8_nat_terminal_n,
+ 'P' => diode_np_1p8_nat_terminal_p })
-# diode_pn_3p3
-logger.info('Extracting diode_pn_3p3')
-extract_devices(diode('diode_pn_3p3'), { 'N' => nwell_con, 'P' => diode_pn_3p3_terminal_p })
+#=====================
+# --- PN 1P8 DIODE ---
+#=====================
-# diode_nwp
-logger.info('Extracting diode_nwp')
-extract_devices(diode('diode_nwp'), { 'N' => diode_nwp_terminal_n, 'P' => diode_nwp_terminal_p })
+# diode_pd2nw_01v8: Model for 1.8V thin gate P+/Nwell diode: [diode_pn_1p8]
+logger.info('Extracting diode_pd2nw_01v8')
+extract_devices(diode('diode_pd2nw_01v8'), { 'N' => nwell_con, 'P' => diode_pn_1p8_terminal_p })
-# diode_np_1p8_nat
-logger.info('Extracting diode_np_1p8_nat')
-extract_devices(diode('diode_np_1p8_nat'), { 'N' => diode_np_1p8_nat_terminal_n,
- 'P' => sub, })
+#=====================
+# --- NP 3P0 DIODE ---
+#=====================
-# diode_np_3p3_nat
-logger.info('Extracting diode_np_3p3_nat')
-extract_devices(diode('diode_np_3p3_nat'), { 'N' => diode_np_3p3_nat_terminal_n,
- 'P' => sub, })
+# diode_nd2ps_03v3: Model for 3.3V thick gate N+/Psub diode: [diode_np_3p3]
+logger.info('Extracting diode_nd2ps_03v3')
+extract_devices(diode('diode_nd2ps_03v3'), { 'N' => diode_np_3p3_terminal_n, 'P' => diode_np_3p3_terminal_p })
-# diode_dnwpw
-logger.info('Extracting diode_dnwpw')
-extract_devices(diode('diode_dnwpw'), { 'N' => dnwell, 'P' => diode_dnwpw_terminal_p })
+# diode_nd2ps_03v3_nvt: Model for 3.3V thick gate N+/Psub native diode [diode_np_3p3_nat]
+logger.info('Extracting diode_nd2ps_03v3_nvt')
+extract_devices(diode('diode_nd2ps_03v3_nvt'), { 'N' => diode_np_3p3_nat_terminal_n,
+ 'P' => diode_np_3p3_nat_terminal_p })
-# diode_dnwps
-logger.info('Extracting diode_dnwps')
-extract_devices(diode('diode_dnwps'), { 'N' => dnwell, 'P' => diode_dnwps_terminal_p })
\ No newline at end of file
+#=====================
+# --- PN 3P0 DIODE ---
+#=====================
+
+# diode_pd2nw_03v3: Model for 3.3V thick gate P+/Nwell diode: [diode_pn_3p3]
+logger.info('Extracting diode_pd2nw_03v3')
+extract_devices(diode('diode_pd2nw_03v3'), { 'N' => nwell_con, 'P' => diode_pn_3p3_terminal_p })
+
+#==================
+# --- NWP DIODE ---
+#==================
+
+# diode_nw2ps: Model Nwell/psub diode: [diode_nwp]
+logger.info('Extracting diode_nw2ps')
+extract_devices(diode('diode_nw2ps'), { 'N' => diode_nwp_terminal_n, 'P' => diode_nwp_terminal_p })
+
+#====================
+# --- DNWPW DIODE ---
+#====================
+
+# diode_pw2dw: Model for Pwell/Deep Nwell junction [diode_dnwpw]
+logger.info('Extracting diode_pw2dw')
+extract_devices(diode('diode_pw2dw'), { 'N' => dnwell, 'P' => diode_dnwpw_terminal_p })
+
+#====================
+# --- DNWPS DIODE ---
+#====================
+
+# diode_dw2ps: Model for Deep Nwell/Psub junction [diode_dnwps]
+logger.info('Extracting diode_dw2ps')
+extract_devices(diode('diode_dw2ps'), { 'N' => diode_dnwps_terminal_n , 'P' => diode_dnwps_terminal_p})
diff --git a/IC/klayout/lvs/rule_decks/general_connections.lvs b/IC/klayout/lvs/rule_decks/general_connections.lvs
new file mode 100644
index 0000000..f1ace83
--- /dev/null
+++ b/IC/klayout/lvs/rule_decks/general_connections.lvs
@@ -0,0 +1,77 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- GENERAL CONNECTIONS -----
+#================================
+
+logger.info('Starting GF180 LVS connectivity setup (Inter-layer)')
+
+# Inter-layer
+connect(sub, ptap)
+connect(dnwell, ntap)
+connect(nwell_con, ntap)
+connect(ptap, contact)
+connect(ntap, contact)
+connect(psd, contact)
+connect(nsd, contact)
+connect(poly2_con, contact)
+connect(contact, metal1)
+connect(metal1, via1)
+connect(via1, metal2)
+
+case METAL_LEVEL
+when '3LM', '4LM', '5LM', '6LM'
+ connect(metal2, via2_n_cap)
+ connect(via2_n_cap, metal3)
+ connect(metal3, metal3_label)
+end
+case METAL_LEVEL
+when '4LM', '5LM', '6LM'
+ connect(metal3, via3_n_cap)
+ connect(via3_n_cap, metal4)
+ connect(metal4, metal4_label)
+end
+case METAL_LEVEL
+when '5LM', '6LM'
+ connect(metal4, via4_n_cap)
+ connect(via4_n_cap, metal5)
+ connect(metal5, metal5_label)
+end
+case METAL_LEVEL
+when '6LM'
+ connect(metal5, via5_n_cap)
+ connect(via5_n_cap, metaltop)
+ connect(metaltop, metaltop_label)
+end
+connect(top_via, top_metal)
+connect(top_metal, top_metal_label)
+
+# Attaching labels
+connect(comp, comp_label)
+connect(poly2_con, poly2_label)
+connect(metal1, metal1_label)
+connect(metal2_ncap, metal2_label)
+
+logger.info('Starting GF180IC LVS connectivity setup (Global)')
+
+# Global
+connect_global(sub, substrate_name)
+
+logger.info('Starting GF180IC LVS connectivity setup (Multifinger Devices)')
+
+# Multifinger Devices
+connect_implicit('*')
diff --git a/IC/klayout/lvs/rule_decks/general_derivations.lvs b/IC/klayout/lvs/rule_decks/general_derivations.lvs
index efd371d..1039df8 100644
--- a/IC/klayout/lvs/rule_decks/general_derivations.lvs
+++ b/IC/klayout/lvs/rule_decks/general_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -18,45 +18,80 @@
# ------ GENERAL DERIVATIONS ------
#==================================
+all_nwell = dnwell.join(nwell)
+
ncomp = comp.and(nplus)
pcomp = comp.and(pplus)
tgate = poly2.and(comp).not(res_mk)
-ngate = nplus.and(tgate)
-nsd = ncomp.outside(nwell).interacting(ngate).not(ngate).not(res_mk)
-ptap = pcomp.outside(nwell).outside(dnwell).not(res_mk)
+nactive = ncomp.not(all_nwell)
+ngate = nactive.and(tgate)
+nsd = nactive.interacting(ngate).not(ngate).not(res_mk)
+ptap = pcomp.not(all_nwell).not(res_mk)
-pgate = pplus.and(tgate)
-psd = pcomp.inside(nwell).interacting(pgate).not(pgate).not(res_mk)
-ntap = ncomp.inside(nwell).not(res_mk)
+pactive = pcomp.and(all_nwell)
+pgate = pactive.and(tgate)
+psd = pactive.interacting(pgate).not(pgate).not(res_mk)
+ntap = ncomp.and(all_nwell).not(res_mk)
-ngate_dw = ngate.and(dnwell)
-ptap_dw = pcomp.inside(dnwell).outside(well_diode_mk).not(res_mk)
+ngate_dn = ngate.and(dnwell)
+ptap_dn = ptap.and(dnwell).outside(well_diode_mk)
-pgate_dw = pgate.inside(dnwell)
-ntap_dw = ncomp.inside(dnwell).not(res_mk)
+pgate_dn = pgate.and(dnwell)
+ntap_dn = ntap.and(dnwell)
-psd_dw = pcomp.and(dnwell).interacting(pgate).not(pgate).not(res_mk)
+psd_dn = pcomp.and(dnwell).interacting(pgate_dn).not(pgate_dn).not(res_mk)
+nsd_dn = ncomp.and(dnwell).interacting(ngate_dn).not(ngate_dn).not(res_mk)
+
+natcomp = nat.and(comp)
+
+# Gate
+nom_gate = tgate.not(dualgate)
+thick_gate = tgate.and(dualgate)
+
nwell_con = nwell.not(res_mk)
poly2_con = poly2.not(res_mk).not(plfuse)
+fusetop_all = fusetop.join(fusetop2)
-# Splitting vias into cap-vias, ncap-vias
-
-if METAL_LEVEL != '2LM'
- via2_ncap = via2.not(fusetop.or(fusetop2))
- via2_cap = via2.and(fusetop.or(fusetop2))
- if METAL_LEVEL != '3LM'
- via3_ncap = via3.not(fusetop.or(fusetop2))
- via3_cap = via3.and(fusetop.or(fusetop2))
- if METAL_LEVEL != '4LM'
- via4_ncap = via4.not(fusetop.or(fusetop2))
- via4_cap = via4.and(fusetop.or(fusetop2))
- if METAL_LEVEL != '5LM'
- via5_ncap = via5.not(fusetop.or(fusetop2))
- via5_cap = via5.and(fusetop.or(fusetop2))
- end
- end
- end
+case METAL_LEVEL
+when '3LM', '4LM', '5LM', '6LM'
+ via2_n_cap = via2.not(fusetop_all)
+ via2_cap = via2.and(fusetop_all)
+end
+case METAL_LEVEL
+when '4LM', '5LM', '6LM'
+ via3_n_cap = via3.not(fusetop_all)
+ via3_cap = via3.and(fusetop_all)
+end
+case METAL_LEVEL
+when '5LM', '6LM'
+ via4_n_cap = via4.not(fusetop_all)
+ via4_cap = via4.and(fusetop_all)
+end
+case METAL_LEVEL
+when '6LM'
+ via5_n_cap = via5.not(fusetop_all)
+ via5_cap = via5.and(fusetop_all)
end
+case METAL_LEVEL
+when '2LM'
+ top_via_n_cap = via1.not(fusetop_all)
+ top_via_cap = via1.and(fusetop_all)
+when '3LM'
+ top_via_n_cap = via2.not(fusetop_all)
+ top_via_cap = via2.and(fusetop_all)
+when '4LM'
+ top_via_n_cap = via3.not(fusetop_all)
+ top_via_cap = via3.and(fusetop_all)
+when '5LM'
+ top_via_n_cap = via4.not(fusetop_all)
+ top_via_cap = via4.and(fusetop_all)
+when '6LM'
+ top_via_n_cap = via5.not(fusetop_all)
+ top_via_cap = via5.and(fusetop_all)
+else
+ logger.error("Unknown metal stack #{METAL_LEVEL}")
+ raise
+end
diff --git a/IC/klayout/lvs/rule_decks/lateral_bjt_derivations.lvs b/IC/klayout/lvs/rule_decks/lateral_bjt_derivations.lvs
deleted file mode 100644
index 1d8878c..0000000
--- a/IC/klayout/lvs/rule_decks/lateral_bjt_derivations.lvs
+++ /dev/null
@@ -1,58 +0,0 @@
-################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-################################################################################################
-
-#================================
-# ------ BJT DERIVATIONS --------
-#================================
-
-logger.info('Starting BJT DERIVATIONS')
-
-#===============
-# ---- lpnp ----
-# ==============
-logger.info('Starting lpnp layers DERIVATIONS')
-
-# lpnp general nodes DERIVATIONS
-e_c_layer = pcomp.inside(nwell).outside(dnwell).inside(lvs_bjt).not(dualgate)
- .not(res_mk).not(nat).not(sab).not(poly2).not(res_mk_type1).not(resistor)
-
-lpnp_b = ncomp.and(nwell).outside(dnwell).interacting(lvs_bjt).covering(e_c_layer)
- .not(dualgate).not(res_mk).not(nat).not(sab).not(poly2).not(res_mk_type1).not(resistor)
-
-lpnp_c = e_c_layer.inside(lpnp_b)
-
-lpnp_e = e_c_layer.inside(lpnp_b).outside(lpnp_c)
-
-
-# lpnp_1p8_0p54x0p54 nodes DERIVATIONS
-lpnp_1p8_0p54x0p54_e = lpnp_e.with_area(0.2.um, 0.4.um).interacting(vpnp_e.edges.with_length(0.5.um, 0.6.um))
-lpnp_1p8_0p54x0p54_b = lpnp_b.interacting(vpnp_b.extents.interacting(lpnp_1p8_0p54x0p54_e))
-lpnp_1p8_0p54x0p54_c = lpnp_c.interacting(vpnp_c.extents.interacting(lpnp_1p8_0p54x0p54_e))
-
-# lpnp_1p8_0p54x1p2 nodes DERIVATIONS
-lpnp_1p8_0p54x1p2_e = lpnp_e.with_area(0.5.um, 0.8.um).interacting(vpnp_e.edges.with_length(1.um, 1.4.um))
-lpnp_1p8_0p54x1p2_b = lpnp_b.interacting(vpnp_b.extents.interacting(lpnp_1p8_0p54x1p2_e))
-lpnp_1p8_0p54x1p2_c = lpnp_c.interacting(vpnp_c.extents.interacting(lpnp_1p8_0p54x1p2_e))
-
-# lpnp_1p8_1p2x2p5 nodes DERIVATIONS
-lpnp_1p8_1p2x2p5_e = lpnp_e.with_area(2.5.um, 3.5.um).interacting(vpnp_e.edges.with_length(2.3.um, 2.7.um))
-lpnp_1p8_1p2x2p5_b = lpnp_b.interacting(vpnp_b.extents.interacting(lpnp_1p8_1p2x2p5_e))
-lpnp_1p8_1p2x2p5_c = lpnp_c.interacting(vpnp_c.extents.interacting(lpnp_1p8_1p2x2p5_e))
-
-# lpnp_1p8_05p00x05p00 nodes DERIVATIONS
-lpnp_1p8_05p00x05p00_e = lpnp_e.with_area(24.5.um, 25.5.um).interacting(vpnp_e.edges.with_length(4.8.um, 5.2.um))
-lpnp_1p8_05p00x05p00_b = lpnp_b.interacting(vpnp_b.extents.interacting(lpnp_1p8_1p2x2p5_e))
-lpnp_1p8_05p00x05p00_c = lpnp_c.interacting(vpnp_c.extents.interacting(lpnp_1p8_1p2x2p5_e))
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/lateral_bjt_extraction.lvs b/IC/klayout/lvs/rule_decks/lateral_bjt_extraction.lvs
deleted file mode 100644
index 591275a..0000000
--- a/IC/klayout/lvs/rule_decks/lateral_bjt_extraction.lvs
+++ /dev/null
@@ -1,75 +0,0 @@
-################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-################################################################################################
-
-#================================
-# ------- BJT EXTRACTION --------
-#================================
-
-
-# ====================
-# ------- lpnp--------
-# ====================
-logger.info('Starting lpnp BJT EXTRACTION')
-
-# lpnp_1p8_0p54x0p54 BJT
-ignore_parameter('lpnp_1p8_0p54x0p54', 'AE')
-logger.info('Extracting lpnp_1p8_0p54x0p54 BJT')
-extract_devices(bjt4('lpnp_1p8_0p54x0p54'), { 'C' => lpnp_1p8_0p54x0p54_c.extents,
- 'B' => lpnp_1p8_0p54x0p54_b.extents,
- 'E' => lpnp_1p8_0p54x0p54_e,
- 'S' => sub.extents,
- 'tC' => lpnp_1p8_0p54x0p54_c,
- 'tB' => lpnp_1p8_0p54x0p54_b,
- 'tE' => lpnp_1p8_0p54x0p54_e
- 'tS' => sub })
-
-# lpnp_1p8_0p54x1p2 BJT
-ignore_parameter('lpnp_1p8_0p54x1p2', 'AE')
-logger.info('Extracting lpnp_1p8_0p54x1p2 BJT')
-extract_devices(bjt4('lpnp_1p8_0p54x1p2'), { 'C' => lpnp_1p8_0p54x1p2_c.extents,
- 'B' => lpnp_1p8_0p54x1p2_b.extents,
- 'E' => lpnp_1p8_0p54x1p2_e,
- 'S' => sub.extents,
- 'tC' => lpnp_1p8_0p54x1p2_c,
- 'tB' => lpnp_1p8_0p54x1p2_b,
- 'tE' => lpnp_1p8_0p54x1p2_e
- 'tS' => sub })
-
-# lpnp_1p8_1p2x2p5 BJT
-ignore_parameter('lpnp_1p8_1p2x2p5', 'AE')
-logger.info('Extracting lpnp_1p8_1p2x2p5 BJT')
-extract_devices(bjt4('lpnp_1p8_1p2x2p5'), { 'C' => lpnp_1p8_1p2x2p5_c.extents,
- 'B' => lpnp_1p8_1p2x2p5_b.extents,
- 'E' => lpnp_1p8_1p2x2p5_e,
- 'S' => sub.extents,
- 'tC' => lpnp_1p8_1p2x2p5_c,
- 'tB' => lpnp_1p8_1p2x2p5_b,
- 'tE' => lpnp_1p8_1p2x2p5_e
- 'tS' => sub})
-
-
-# lpnp_1p8_05p00x05p00 BJT
-ignore_parameter('lpnp_1p8_05p00x05p00', 'AE')
-logger.info('Extracting lpnp_1p8_05p00x05p00 BJT')
-extract_devices(bjt4('lpnp_1p8_05p00x05p00'), { 'C' => lpnp_1p8_05p00x05p00_c.extents,
- 'B' => lpnp_1p8_05p00x05p00_b.extents,
- 'E' => lpnp_1p8_05p00x05p00_e,
- 'S' => sub.extents,
- 'tC' => lpnp_1p8_05p00x05p00_c,
- 'tB' => lpnp_1p8_05p00x05p00_b,
- 'tE' => lpnp_1p8_05p00x05p00_e
- 'tS' => sub})
-
diff --git a/IC/klayout/lvs/rule_decks/layers_definitions.lvs b/IC/klayout/lvs/rule_decks/layers_definitions.lvs
index 7295fc4..d2b6f9b 100644
--- a/IC/klayout/lvs/rule_decks/layers_definitions.lvs
+++ b/IC/klayout/lvs/rule_decks/layers_definitions.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -15,526 +15,506 @@
################################################################################################
#================================================
-#------------- LAYERS DEFINITIONS ---------------
+#------------- LAYERS DERIVATIONS ---------------
#================================================
-polygons_count = 0
-logger.info("Read in polygons from layers.")
-comp = polygons(22 , 0 ).merged
-count = comp.count()
-logger.info("comp has %d polygons" % [count])
+polygons_count = 0
+logger.info('Read in polygons from layers.')
+
+def get_polygons(layer, data_type)
+ ps = polygons(layer, data_type)
+ $run_mode == 'deep' ? ps : ps.merged
+end
+
+comp = get_polygons(22, 0)
+count = comp.count
+logger.info("comp has #{count} polygons")
polygons_count += count
-dnwell = polygons(12 , 0 ).merged
-count = dnwell.count()
-logger.info("dnwell has %d polygons" % [count])
-polygons_count += count
+dnwell = get_polygons(12, 0)
+count = dnwell.count
+logger.info("dnwell has #{count} polygons")
+polygons_count += count
-nwell = polygons(21 , 0 ).merged
-count = nwell.count()
-logger.info("nwell has %d polygons" % [count])
-polygons_count += count
+nwell = get_polygons(21, 0)
+count = nwell.count
+logger.info("nwell has #{count} polygons")
+polygons_count += count
-dualgate = polygons(55 , 0 ).merged
-count = dualgate.count()
-logger.info("dualgate has %d polygons" % [count])
-polygons_count += count
+dualgate = get_polygons(55, 0)
+count = dualgate.count
+logger.info("dualgate has #{count} polygons")
+polygons_count += count
-otpgate = polygons(225 , 0 ).merged
-count = otpgate.count()
-logger.info("otpgate has %d polygons" % [count])
-polygons_count += count
+poly2 = get_polygons(30, 0)
+count = poly2.count
+logger.info("poly2 has #{count} polygons")
+polygons_count += count
-poly2 = polygons(30 , 0 ).merged
-count = poly2.count()
-logger.info("poly2 has %d polygons" % [count])
-polygons_count += count
+nplus = get_polygons(32, 0)
+count = nplus.count
+logger.info("nplus has #{count} polygons")
+polygons_count += count
-nplus = polygons(32 , 0 ).merged
-count = nplus.count()
-logger.info("nplus has %d polygons" % [count])
-polygons_count += count
+pplus = get_polygons(31, 0)
+count = pplus.count
+logger.info("pplus has #{count} polygons")
+polygons_count += count
-pplus = polygons(31 , 0 ).merged
-count = pplus.count()
-logger.info("pplus has %d polygons" % [count])
-polygons_count += count
+otpgate = get_polygons(225, 0)
+count = otpgate.count
+logger.info("otpgate has #{count} polygons")
+polygons_count += count
-sab = polygons(49 , 0 ).merged
-count = sab.count()
-logger.info("sab has %d polygons" % [count])
-polygons_count += count
+sab = get_polygons(49, 0)
+count = sab.count
+logger.info("sab has #{count} polygons")
+polygons_count += count
-esd = polygons(24 , 0 ).merged
-count = esd.count()
-logger.info("esd has %d polygons" % [count])
-polygons_count += count
+esd = get_polygons(24, 0)
+count = esd.count
+logger.info("esd has #{count} polygons")
+polygons_count += count
-resistor = polygons(62 , 0 ).merged
-count = resistor.count()
-logger.info("resistor has %d polygons" % [count])
-polygons_count += count
+resistor = get_polygons(62, 0)
+count = resistor.count
+logger.info("resistor has #{count} polygons")
+polygons_count += count
-fusetop = polygons(75 , 0 ).merged
-count = fusetop.count()
-logger.info("fusetop has %d polygons" % [count])
-polygons_count += count
+fusetop = get_polygons(75, 0)
+count = fusetop.count
+logger.info("fusetop has #{count} polygons")
+polygons_count += count
-fusetop2 = polygons(215 , 0 ).merged
-count = fusetop2.count()
-logger.info("fusetop2 has %d polygons" % [count])
-polygons_count += count
+fusetop2 = get_polygons(215, 0)
+count = fusetop2.count
+logger.info("fusetop2 has #{count} polygons")
+polygons_count += count
-nat = polygons(5 , 0 ).merged
-count = nat.count()
-logger.info("nat has %d polygons" % [count])
-polygons_count += count
+nat = get_polygons(5, 0)
+count = nat.count
+logger.info("nat has #{count} polygons")
+polygons_count += count
-lvt = polygons(87 , 0 ).merged
-count = lvt.count()
-logger.info("lvt has %d polygons" % [count])
-polygons_count += count
+lvt = get_polygons(87, 0)
+count = lvt.count
+logger.info("lvt has #{count} polygons")
+polygons_count += count
-comp_dummy = polygons(22 , 4 ).merged
-count = comp_dummy.count()
-logger.info("comp_dummy has %d polygons" % [count])
-polygons_count += count
+comp_dummy = get_polygons(22, 4)
+count = comp_dummy.count
+logger.info("comp_dummy has #{count} polygons")
+polygons_count += count
-poly2_dummy = polygons(30 , 4 ).merged
-count = poly2_dummy.count()
-logger.info("poly2_dummy has %d polygons" % [count])
-polygons_count += count
+poly2_dummy = get_polygons(30, 4)
+count = poly2_dummy.count
+logger.info("poly2_dummy has #{count} polygons")
+polygons_count += count
-res_mk = polygons(110, 5 ).merged
-count = res_mk.count()
-logger.info("res_mk has %d polygons" % [count])
-polygons_count += count
+res_mk = get_polygons(110, 5)
+count = res_mk.count
+logger.info("res_mk has #{count} polygons")
+polygons_count += count
-res_mk_type1 = polygons(26, 17 ).merged
-count = res_mk_type1.count()
-logger.info("res_mk_type1 has %d polygons" % [count])
-polygons_count += count
+res_mk_type1 = get_polygons(26, 17)
+count = res_mk_type1.count
+logger.info("res_mk_type1 has #{count} polygons")
+polygons_count += count
-ndmy = polygons(111, 5 ).merged
-count = ndmy.count()
-logger.info("ndmy has %d polygons" % [count])
-polygons_count += count
+ndmy = get_polygons(111, 5)
+count = ndmy.count
+logger.info("ndmy has #{count} polygons")
+polygons_count += count
-ind_mk = polygons(151, 5 ).merged
-count = ind_mk.count()
-logger.info("ind_mk has %d polygons" % [count])
-polygons_count += count
+ind_mk = get_polygons(151, 5)
+count = ind_mk.count
+logger.info("ind_mk has #{count} polygons")
+polygons_count += count
-diode_mk = polygons(115, 5 ).merged
-count = diode_mk.count()
-logger.info("diode_mk has %d polygons" % [count])
-polygons_count += count
+diode_mk = get_polygons(115, 5)
+count = diode_mk.count
+logger.info("diode_mk has #{count} polygons")
+polygons_count += count
-lvs_bjt = polygons(118, 5 ).merged
-count = lvs_bjt.count()
-logger.info("lvs_bjt has %d polygons" % [count])
-polygons_count += count
+lvs_bjt = get_polygons(118, 5)
+count = lvs_bjt.count
+logger.info("lvs_bjt has #{count} polygons")
+polygons_count += count
-guard_ring_mk = polygons(167, 5 ).merged
-count = guard_ring_mk.count()
-logger.info("guard_ring_mk has %d polygons" % [count])
-polygons_count += count
+guard_ring_mk = get_polygons(167, 5)
+count = guard_ring_mk.count
+logger.info("guard_ring_mk has #{count} polygons")
+polygons_count += count
-sramcore_1 = polygons(101, 5 ).merged
-sramcore_2 = polygons(102, 5 ).merged
-sramcore_3 = polygons(103, 5 ).merged
-sramcore_4 = polygons(105, 5 ).merged
-sramcore_5 = polygons(108, 5 ).merged
-sramcore = sramcore_1.or(sramcore_2).or(sramcore_3).or(sramcore_4).or(sramcore_5)
-count = sramcore.count()
-logger.info("sramcore has %d polygons" % [count])
-polygons_count += count
+sramcore_1 = get_polygons(101, 5)
+sramcore_2 = get_polygons(102, 5)
+sramcore_3 = get_polygons(103, 5)
+sramcore_4 = get_polygons(105, 5)
+sramcore_5 = get_polygons(108, 5)
+sramcore = sramcore_1.join(sramcore_2).join(sramcore_3)
+ .join(sramcore_4).join(sramcore_5)
+count = sramcore.count
+logger.info("sramcore has #{count} polygons")
+polygons_count += count
-lvs_rf = polygons(100, 5 ).merged
-count = lvs_rf.count()
-logger.info("lvs_rf has %d polygons" % [count])
-polygons_count += count
+lvs_rf = get_polygons(100, 5)
+count = lvs_rf.count
+logger.info("lvs_rf has #{count} polygons")
+polygons_count += count
-lvs_drain = polygons(100, 7 ).merged
-count = lvs_drain.count()
-logger.info("lvs_drain has %d polygons" % [count])
-polygons_count += count
+lvs_drain = get_polygons(100, 7)
+count = lvs_drain.count
+logger.info("lvs_drain has #{count} polygons")
+polygons_count += count
-lvs_io = polygons(119, 5 ).merged
-count = lvs_io.count()
-logger.info("lvs_io has %d polygons" % [count])
-polygons_count += count
+lvs_io = get_polygons(119, 5)
+count = lvs_io.count
+logger.info("lvs_io has #{count} polygons")
+polygons_count += count
-probe_mk = polygons(13 , 17).merged
-count = probe_mk.count()
-logger.info("probe_mk has %d polygons" % [count])
-polygons_count += count
+probe_mk = get_polygons(13, 17)
+count = probe_mk.count
+logger.info("probe_mk has #{count} polygons")
+polygons_count += count
-lvs_source = polygons(100, 8 ).merged
-count = lvs_source.count()
-logger.info("lvs_source has %d polygons" % [count])
-polygons_count += count
+lvs_source = get_polygons(100, 8)
+count = lvs_source.count
+logger.info("lvs_source has #{count} polygons")
+polygons_count += count
-well_diode_mk = polygons(153, 51).merged
-count = well_diode_mk.count()
-logger.info("well_diode_mk has %d polygons" % [count])
-polygons_count += count
+well_diode_mk = get_polygons(153, 51)
+count = well_diode_mk.count
+logger.info("well_diode_mk has #{count} polygons")
+polygons_count += count
-plfuse = polygons(125, 5 ).merged
-count = plfuse.count()
-logger.info("plfuse has %d polygons" % [count])
-polygons_count += count
+plfuse = get_polygons(125, 5)
+count = plfuse.count
+logger.info("plfuse has #{count} polygons")
+polygons_count += count
-efuse_mk = polygons(80 , 5 ).merged
-count = efuse_mk.count()
-logger.info("efuse_mk has %d polygons" % [count])
-polygons_count += count
+efuse_mk = get_polygons(80, 5)
+count = efuse_mk.count
+logger.info("efuse_mk has #{count} polygons")
+polygons_count += count
-mcell_feol_mk = polygons(11 , 17).merged
-count = mcell_feol_mk.count()
-logger.info("mcell_feol_mk has %d polygons" % [count])
-polygons_count += count
+mcell_feol_mk = get_polygons(11, 17)
+count = mcell_feol_mk.count
+logger.info("mcell_feol_mk has #{count} polygons")
+polygons_count += count
-comp_label = polygons(22 , 10).merged
-count = comp_label.count()
-logger.info("comp_label has %d polygons" % [count])
-polygons_count += count
+comp_label = labels(22, 10)
+count = comp_label.count
+logger.info("comp_label has #{count} polygons")
+polygons_count += count
-poly2_label = polygons(30 , 10).merged
-count = poly2_label.count()
-logger.info("poly2_label has %d polygons" % [count])
-polygons_count += count
+poly2_label = labels(30, 10)
+count = poly2_label.count
+logger.info("poly2_label has #{count} polygons")
+polygons_count += count
-mdiode = polygons(116, 5 ).merged
-count = mdiode.count()
-logger.info("mdiode has %d polygons" % [count])
-polygons_count += count
+mdiode = get_polygons(116, 5)
+count = mdiode.count
+logger.info("mdiode has #{count} polygons")
+polygons_count += count
-contact = polygons(33 , 0 ).merged
-count = contact.count()
-logger.info("contact has %d polygons" % [count])
-polygons_count += count
+contact = get_polygons(33, 0)
+count = contact.count
+logger.info("contact has #{count} polygons")
+polygons_count += count
-metal1_drawn = polygons(34, 0).merged
+metal1_drawn = get_polygons(34, 0)
count = metal1_drawn.count
logger.info("metal1_drawn has #{count} polygons")
polygons_count += count
-metal1_dummy = polygons(34, 4).merged
+metal1_dummy = get_polygons(34, 4)
count = metal1_dummy.count
logger.info("metal1_dummy has #{count} polygons")
polygons_count += count
metal1 = metal1_drawn + metal1_dummy
-metal1_label = polygons(34, 10).merged
+metal1_label = labels(34, 10)
count = metal1_label.count
logger.info("metal1_label has #{count} polygons")
polygons_count += count
-metal1_slot = polygons(34, 3).merged
+metal1_slot = get_polygons(34, 3)
count = metal1_slot.count
logger.info("metal1_slot has #{count} polygons")
polygons_count += count
-metal1_blk = polygons(34, 5).merged
+metal1_blk = get_polygons(34, 5)
count = metal1_blk.count
logger.info("metal1_blk has #{count} polygons")
polygons_count += count
-via1 = polygons(35, 0).merged
+via1 = get_polygons(35, 0)
count = via1.count
logger.info("via1 has #{count} polygons")
polygons_count += count
-metal2_drawn = polygons(36, 0).merged
+metal2_drawn = get_polygons(36, 0)
count = metal2_drawn.count
logger.info("metal2_drawn has #{count} polygons")
polygons_count += count
-metal2_dummy = polygons(36, 4).merged
+metal2_dummy = get_polygons(36, 4)
count = metal2_dummy.count
logger.info("metal2_dummy has #{count} polygons")
polygons_count += count
metal2 = metal2_drawn + metal2_dummy
-metal2_label = polygons(36, 10).merged
+metal2_label = labels(36, 10)
count = metal2_label.count
logger.info("metal2_label has #{count} polygons")
polygons_count += count
-metal2_slot = polygons(36, 3).merged
+metal2_slot = get_polygons(36, 3)
count = metal2_slot.count
logger.info("metal2_slot has #{count} polygons")
polygons_count += count
-metal2_blk = polygons(36, 5).merged
+metal2_blk = get_polygons(36, 5)
count = metal2_blk.count
logger.info("metal2_blk has #{count} polygons")
polygons_count += count
-if METAL_LEVEL == '2LM'
-
- top_via = via1
- topmin1_via = contact
- top_metal = metal2
- topmin1_metal = metal1
-
-else
-
- via2 = polygons(38, 0).merged
+case METAL_LEVEL
+when '3LM', '4LM', '5LM', '6LM'
+ via2 = get_polygons(38, 0)
count = via2.count
logger.info("via2 has #{count} polygons")
polygons_count += count
- metal3_drawn = polygons(42, 0).merged
+ metal3_drawn = get_polygons(42, 0)
count = metal3_drawn.count
logger.info("metal3_drawn has #{count} polygons")
polygons_count += count
- metal3_dummy = polygons(42, 4).merged
+ metal3_dummy = get_polygons(42, 4)
count = metal3_dummy.count
logger.info("metal3_dummy has #{count} polygons")
polygons_count += count
metal3 = metal3_drawn + metal3_dummy
- metal3_label = polygons(42, 10).merged
+ metal3_label = get_polygons(42, 10)
count = metal3_label.count
logger.info("metal3_label has #{count} polygons")
polygons_count += count
- metal3_slot = polygons(42, 3).merged
+ metal3_slot = get_polygons(42, 3)
count = metal3_slot.count
logger.info("metal3_slot has #{count} polygons")
polygons_count += count
- metal3_blk = polygons(42, 5).merged
+ metal3_blk = get_polygons(42, 5)
count = metal3_blk.count
logger.info("metal3_blk has #{count} polygons")
polygons_count += count
-
- if METAL_LEVEL == '3LM'
-
- top_via = via2
- topmin1_via = via1
- top_metal = metal3
- topmin1_metal = metal2
- topmin2_metal = metal1
- else
-
- via3 = polygons(40, 0).merged
- count = via3.count
- logger.info("via3 has #{count} polygons")
- polygons_count += count
-
- metal4_drawn = polygons(46, 0).merged
- count = metal4_drawn.count
- logger.info("metal4_drawn has #{count} polygons")
- polygons_count += count
-
- metal4_dummy = polygons(46, 4).merged
- count = metal4_dummy.count
- logger.info("metal4_dummy has #{count} polygons")
- polygons_count += count
-
- metal4 = metal4_drawn + metal4_dummy
-
- metal4_label = polygons(46, 10).merged
- count = metal4_label.count
- logger.info("metal4_label has #{count} polygons")
- polygons_count += count
-
- metal4_slot = polygons(46, 3).merged
- count = metal4_slot.count
- logger.info("metal4_slot has #{count} polygons")
- polygons_count += count
-
- metal4_blk = polygons(46, 5).merged
- count = metal4_blk.count
- logger.info("metal4_blk has #{count} polygons")
- polygons_count += count
-
- if METAL_LEVEL == '4LM'
-
- top_via = via3
- topmin1_via = via2
- top_metal = metal4
- topmin1_metal = metal3
- topmin2_metal = metal2
- else
-
- via4 = polygons(41, 0).merged
- count = via4.count
- logger.info("via4 has #{count} polygons")
- polygons_count += count
-
- case METAL_LEVEL
- when '5LM'
- metal5_drawn = polygons(81, 0).merged
- count = metal5_drawn.count
- logger.info("metal5_drawn has #{count} polygons")
- polygons_count += count
-
- metal5_dummy = polygons(81, 4).merged
- count = metal5_dummy.count
- logger.info("metal5_dummy has #{count} polygons")
- polygons_count += count
-
- metal5 = metal5_drawn + metal5_dummy
-
- metal5_label = polygons(81, 10).merged
- count = metal5_label.count
- logger.info("metal5_label has #{count} polygons")
- polygons_count += count
-
- metal5_slot = polygons(81, 3).merged
- count = metal5_slot.count
- logger.info("metal5_slot has #{count} polygons")
- polygons_count += count
-
- metal5_blk = polygons(81, 5).merged
- count = metal5_blk.count
- logger.info("metal5_blk has #{count} polygons")
- polygons_count += count
-
- top_via = via4
- topmin1_via = via3
- top_metal = metal5
- topmin1_metal = metal4
- topmin2_metal = metal3
- when '6LM'
- metal5_drawn = polygons(81, 0).merged
- count = metal5_drawn.count
- logger.info("metal5_drawn has #{count} polygons")
- polygons_count += count
-
- metal5_dummy = polygons(81, 4).merged
- count = metal5_dummy.count
- logger.info("metal5_dummy has #{count} polygons")
- polygons_count += count
-
- metal5 = metal5_drawn + metal5_dummy
-
- metal5_label = polygons(81, 10).merged
- count = metal5_label.count
- logger.info("metal5_label has #{count} polygons")
- polygons_count += count
-
- metal5_slot = polygons(81, 3).merged
- count = metal5_slot.count
- logger.info("metal5_slot has #{count} polygons")
- polygons_count += count
-
- metal5_blk = polygons(81, 5).merged
- count = metal5_blk.count
- logger.info("metal5_blk has #{count} polygons")
- polygons_count += count
-
- via5 = polygons(82, 0).merged
- count = via5.count
- logger.info("via5 has #{count} polygons")
- polygons_count += count
-
- metaltop_drawn = polygons(53, 0).merged
- count = metaltop_drawn.count
- logger.info("metaltop_drawn has #{count} polygons")
- polygons_count += count
-
- metaltop_dummy = polygons(53, 4).merged
- count = metaltop_dummy.count
- logger.info("metaltop_dummy has #{count} polygons")
- polygons_count += count
-
- metaltop = metaltop_drawn + metaltop_dummy
-
- metaltop_label = polygons(53, 10).merged
- count = metaltop_label.count
- logger.info("metaltop_label has #{count} polygons")
- polygons_count += count
-
- metaltop_slot = polygons(53, 3).merged
- count = metaltop_slot.count
- logger.info("metaltop_slot has #{count} polygons")
- polygons_count += count
-
- metalt_blk = polygons(53, 5).merged
- count = metalt_blk.count
- logger.info("metalt_blk has #{count} polygons")
- polygons_count += count
-
- top_via = via5
- topmin1_via = via4
- top_metal = metaltop
- topmin1_metal = metal5
- topmin2_metal = metal4
- else
- logger.error("Unknown metal stack #{METAL_LEVEL}")
- raise
- end
- end
- end
end
-metalrdl = polygons(171 , 0 ).merged
-count = metalrdl.count()
-logger.info("metalrdl has %d polygons" % [count])
-polygons_count += count
+case METAL_LEVEL
+when '4LM', '5LM', '6LM'
+ via3 = get_polygons(40, 0)
+ count = via3.count
+ logger.info("via3 has #{count} polygons")
+ polygons_count += count
-metalrdl_label = polygons(171 , 10 ).merged
-count = metalrdl_label.count()
-logger.info("metalrdl_label has %d polygons" % [count])
-polygons_count += count
+ metal4_drawn = get_polygons(46, 0)
+ count = metal4_drawn.count
+ logger.info("metal4_drawn has #{count} polygons")
+ polygons_count += count
-viardl = polygons(170 , 0 ).merged
-count = viardl.count()
-logger.info("viardl has %d polygons" % [count])
-polygons_count += count
+ metal4_dummy = get_polygons(46, 4)
+ count = metal4_dummy.count
+ logger.info("metal4_dummy has #{count} polygons")
+ polygons_count += count
-piscap = polygons(120 , 0 ).merged
-count = piscap.count()
-logger.info("piscap has %d polygons" % [count])
-polygons_count += count
+ metal4 = metal4_drawn + metal4_dummy
-lvs_cap = polygons(117 , 5 ).merged
-count = lvs_cap.count()
-logger.info("lvs_cap has %d polygons" % [count])
-polygons_count += count
+ metal4_label = get_polygons(46, 10)
+ count = metal4_label.count
+ logger.info("metal4_label has #{count} polygons")
+ polygons_count += count
-pad = polygons(37 , 0 ).merged
-count = pad.count()
-logger.info("pad has %d polygons" % [count])
-polygons_count += count
+ metal4_slot = get_polygons(46, 3)
+ count = metal4_slot.count
+ logger.info("metal4_slot has #{count} polygons")
+ polygons_count += count
-pad_label = polygons(37 , 10 ).merged
-count = pad_label.count()
-logger.info("pad_label has %d polygons" % [count])
-polygons_count += count
+ metal4_blk = get_polygons(46, 5)
+ count = metal4_blk.count
+ logger.info("metal4_blk has #{count} polygons")
+ polygons_count += count
+end
-ubmpperi = polygons(183, 0 ).merged
-count = ubmpperi.count()
-logger.info("ubmpperi has %d polygons" % [count])
-polygons_count += count
+case METAL_LEVEL
+when '5LM', '6LM'
+ via4 = get_polygons(41, 0)
+ count = via4.count
+ logger.info("via4 has #{count} polygons")
+ polygons_count += count
-ubmparray = polygons(184, 0 ).merged
-count = ubmparray.count()
-logger.info("ubmparray has %d polygons" % [count])
-polygons_count += count
+ metal5_drawn = get_polygons(81, 0)
+ count = metal5_drawn.count
+ logger.info("metal5_drawn has #{count} polygons")
+ polygons_count += count
-ubmeplate = polygons(185, 0 ).merged
-count = ubmeplate.count()
-logger.info("ubmeplate has %d polygons" % [count])
-polygons_count += count
+ metal5_dummy = get_polygons(81, 4)
+ count = metal5_dummy.count
+ logger.info("metal5_dummy has #{count} polygons")
+ polygons_count += count
-pr_bndry = polygons(0 , 0 ).merged
-count = pr_bndry.count()
-logger.info("pr_bndry has %d polygons" % [count])
-polygons_count += count
+ metal5 = metal5_drawn + metal5_dummy
+
+ metal5_label = get_polygons(81, 10)
+ count = metal5_label.count
+ logger.info("metal5_label has #{count} polygons")
+ polygons_count += count
+
+ metal5_slot = get_polygons(81, 3)
+ count = metal5_slot.count
+ logger.info("metal5_slot has #{count} polygons")
+ polygons_count += count
+
+ metal5_blk = get_polygons(81, 5)
+ count = metal5_blk.count
+ logger.info("metal5_blk has #{count} polygons")
+ polygons_count += count
+end
+
+case METAL_LEVEL
+when '6LM'
+ via5 = get_polygons(82, 0)
+ count = via5.count
+ logger.info("via5 has #{count} polygons")
+ polygons_count += count
+
+ metaltop_drawn = get_polygons(53, 0)
+ count = metaltop_drawn.count
+ logger.info("metaltop_drawn has #{count} polygons")
+ polygons_count += count
+
+ metaltop_dummy = get_polygons(53, 4)
+ count = metaltop_dummy.count
+ logger.info("metaltop_dummy has #{count} polygons")
+ polygons_count += count
+
+ metaltop = metaltop_drawn + metaltop_dummy
+
+ metaltop_label = get_polygons(53, 10)
+ count = metaltop_label.count
+ logger.info("metaltop_label has #{count} polygons")
+ polygons_count += count
+
+ metaltop_slot = get_polygons(53, 3)
+ count = metaltop_slot.count
+ logger.info("metaltop_slot has #{count} polygons")
+ polygons_count += count
+
+ metaltop_blk = get_polygons(53, 5)
+ count = metaltop_blk.count
+ logger.info("metaltop_blk has #{count} polygons")
+ polygons_count += count
+end
+
+case METAL_LEVEL
+when '2LM'
+ top_via = via1
+ topmin1_via = contact
+ top_metal = metal2
+ topmin1_metal = metal1
+ top_metal_label = metal2_label
+when '3LM'
+ top_via = via2
+ topmin1_via = via1
+ top_metal = metal3
+ topmin1_metal = metal2
+ top_metal_label = metal3_label
+when '4LM'
+ top_via = via3
+ topmin1_via = via2
+ top_metal = metal4
+ topmin1_metal = metal3
+ top_metal_label = metal4_label
+when '5LM'
+ top_via = via4
+ topmin1_via = via3
+ top_metal = metal5
+ topmin1_metal = metal4
+ top_metal_label = metal5_label
+when '6LM'
+ top_via = via5
+ topmin1_via = via4
+ top_metal = metaltop
+ topmin1_metal = metal5
+ top_metal_label = metaltop_label
+else
+ logger.error("Unknown metal stack #{METAL_LEVEL}")
+ raise
+end
+
+metalrdl = get_polygons(171, 0)
+count = metalrdl.count
+logger.info("metalrdl has #{count} polygons")
+polygons_count += count
+
+metalrdl_label = labels(171, 10)
+count = metalrdl_label.count
+logger.info("metalrdl_label has #{count} polygons")
+polygons_count += count
+
+viardl = get_polygons(170, 0)
+count = viardl.count
+logger.info("viardl has #{count} polygons")
+polygons_count += count
+
+piscap = get_polygons(120, 0)
+count = piscap.count
+logger.info("piscap has #{count} polygons")
+polygons_count += count
+
+lvs_cap = get_polygons(117, 5)
+count = lvs_cap.count
+logger.info("lvs_cap has #{count} polygons")
+polygons_count += count
+
+pad = get_polygons(37, 0)
+count = pad.count
+logger.info("pad has #{count} polygons")
+polygons_count += count
+
+pad_label = labels(37, 10)
+count = pad_label.count
+logger.info("pad_label has #{count} polygons")
+polygons_count += count
+
+ubmpperi = get_polygons(183, 0)
+count = ubmpperi.count
+logger.info("ubmpperi has #{count} polygons")
+polygons_count += count
+
+ubmparray = get_polygons(184, 0)
+count = ubmparray.count
+logger.info("ubmparray has #{count} polygons")
+polygons_count += count
+
+ubmeplate = get_polygons(185, 0)
+count = ubmeplate.count
+logger.info("ubmeplate has #{count} polygons")
+polygons_count += count
+
+pr_bndry = get_polygons(0, 0)
+count = pr_bndry.count
+logger.info("pr_bndry has #{count} polygons")
+polygons_count += count
logger.info("Total no. of polygons in the design is #{polygons_count}")
logger.info("Starting deriving base layers.")
#=== BULK LAYER ===
-sub = polygon_layer
\ No newline at end of file
+sub = polygon_layer
diff --git a/IC/klayout/lvs/rule_decks/mimcap_connection.lvs b/IC/klayout/lvs/rule_decks/mimcap_connection.lvs
deleted file mode 100644
index c2e6646..0000000
--- a/IC/klayout/lvs/rule_decks/mimcap_connection.lvs
+++ /dev/null
@@ -1,34 +0,0 @@
-################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-################################################################################################
-
-#==================================
-# ------ MIMCAP CONNECTIONS -------
-#==================================
-
-logger.info('Starting LVS MIMCAP CONNECTIONS')
-
-case MIM_OPTION
-when 'A'
- connect(metal2, mim_virtual)
- connect(fuse_cap, via2)
-
-when 'B'
- connect(topmin1_metal, mimtm_virtual)
- connect(fuse_cap, top_via)
- connect(topmin1_metal, mimtm_stack1_virtual)
- connect(topmin2_metal, mimtm_stack2_virtual)
- connect(fuse2_cap, topmin1_via)
-end
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/mimcap_connection.lvs b/IC/klayout/lvs/rule_decks/mimcap_connections.lvs
similarity index 92%
copy from ULL/klayout/lvs/rule_decks/mimcap_connection.lvs
copy to IC/klayout/lvs/rule_decks/mimcap_connections.lvs
index 886bdc9..7731736 100644
--- a/ULL/klayout/lvs/rule_decks/mimcap_connection.lvs
+++ b/IC/klayout/lvs/rule_decks/mimcap_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -28,4 +28,5 @@
when 'B'
connect(topmin1_metal, mimtm_virtual)
connect(fuse_cap, top_via)
-end
\ No newline at end of file
+ connect(fuse2_cap, topmin1_via)
+end
diff --git a/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs b/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
index de22dc7..9d94ed2 100644
--- a/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
+++ b/IC/klayout/lvs/rule_decks/mimcap_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -25,9 +25,7 @@
mim_virtual = fusetop.sized(1.06.um).and(metal2.interacting(fusetop)).not(fusetop2)
fuse_cap = fusetop.interacting(lvs_cap)
fuse2_cap = fusetop2.interacting(lvs_cap)
+metal2_ncap = metal2.not(mim_virtual)
# mim_option B
mimtm_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop)).not(fusetop2)
-mimtm_stack1_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop))
-mimtm_stack2_virtual = fusetop2.sized(1.06.um).and(topmin2_metal.interacting(fusetop2))
-
diff --git a/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs b/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs
index 0f0a15b..6ec0dea 100644
--- a/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs
+++ b/IC/klayout/lvs/rule_decks/mimcap_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -25,78 +25,100 @@
case MIM_CAP
when '1'
-
- # cap_mim1f0 capacitor
- logger.info('Extracting cap_mim1f0 device')
- extract_devices(capacitor(cap_mim1f0, 1.0e-15, MIMCap), { 'P1' => mim_virtual, 'P2' => fuse_cap })
- tolerance(cap_mim1f0, 'C', relative: 0.25)
+ # cap_mim_1f0 capacitor
+ logger.info('Extracting cap_mim_1f0_m2m3_noshield device')
+ extract_devices(capacitor('cap_mim_1f0_m2m3_noshield', 1.0e-15, MIMCap), { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m2m3_noshield', 'C', relative: 0.25)
when '1.5'
-
- # cap_mim1f5 capacitor
- logger.info('Extracting cap_mim1f5 device')
- extract_devices(capacitor(cap_mim1f5, 1.5e-15, MIMCap), { 'P1' => mim_virtual, 'P2' => fuse_cap })
- tolerance(cap_mim1f5, 'C', relative: 0.25)
+ # cap_mim_1f5 capacitor
+ logger.info('Extracting cap_mim_1f5_m2m3_noshield device')
+ extract_devices(capacitor('cap_mim_1f5_m2m3_noshield', 1.5e-15, MIMCap), { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m2m3_noshield', 'C', relative: 0.25)
when '2'
-
- # cap_mim_single_2f0 capacitor
- logger.info('Extracting cap_mim_single_2f0 device')
- extract_devices(capacitor(cap_mim_single_2f0, 2.0e-15, MIMCap), { 'P1' => mim_virtual, 'P2' => fuse_cap })
- tolerance(cap_mim_single_2f0, 'C', relative: 0.25)
-
+ # cap_mim_2f0 capacitor
+ logger.info('Extracting cap_mim_2f0_m2m3_noshield device')
+ extract_devices(capacitor('cap_mim_2f0_m2m3_noshield', 2.0e-15, MIMCap), { 'P1' => mim_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_2f0_m2m3_noshield', 'C', relative: 0.25)
end
when 'B'
- case MIM_CAP
- when '1'
+ case METAL_LEVEL
+ when '6LM'
- # cap_mim1f0 capacitor
- logger.info('Extracting cap_mim1f0 device')
- extract_devices(capacitor(cap_mim1f0, 1.0e-15, MIMCap), { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
- tolerance(cap_mim1f0, 'C', relative: 0.25)
+ case MIM_CAP
+ when '1'
+ # cap_mim1f0 capacitor
+ logger.info('Extracting cap_mim_1f0_m5m6_noshield device')
+ extract_devices(capacitor('cap_mim_1f0_m5m6_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m5m6_noshield', 'C', relative: 0.25)
- when '1.5'
+ when '1.5'
+ # cap_mim1f5 capacitor
+ logger.info('Extracting cap_mim_1f5_m5m6_noshield device')
+ extract_devices(capacitor('cap_mim_1f5_m5m6_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m5m6_noshield', 'C', relative: 0.25)
- # cap_mim1f5 capacitor
- logger.info('Extracting cap_mim1f5 device')
- extract_devices(capacitor(cap_mim1f5, 1.5e-15, MIMCap), { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
- tolerance(cap_mim1f5, 'C', relative: 0.25)
-
- when '2'
-
- # cap_mim_single_2f0 capacitor
- logger.info('Extracting cap_mim_single_2f0 device')
- extract_devices(capacitor(cap_mim_single_2f0, 2.0e-15, MIMCap), { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
- tolerance(cap_mim_single_2f0, 'C', relative: 0.25)
-
- end
-
- case MIM_CAP_STACK
-
- when '2'
-
+ when '2'
# cap_mim2f0 capacitor
- logger.info('Extracting cap_mim2f0 device')
+ logger.info('Extracting cap_mim_2f0_m5m6_noshield device')
+ extract_devices(capacitor('cap_mim_2f0_m5m6_noshield', 2.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_2f0_m5m6_noshield', 'C', relative: 0.25)
+ end
- extract_devices(capacitor(cap_mim2f0, 2.0e-15, MIMCap), { 'P1' => mimtm_stack1_virtual,
- 'P2' => fuse_cap, })
- extract_devices(capacitor(cap_mim2f0, 2.0e-15, MIMCap), { 'P1' => mimtm_stack2_virtual,
- 'P2' => fuse2_cap, })
- tolerance(cap_mim2f0, 'C', relative: 0.25)
-
- when '3'
-
- # cap_mim3f0 capacitor
- logger.info('Extracting cap_mim3f0 device')
-
- extract_devices(capacitor(cap_mim3f0, 3.0e-15, MIMCap), { 'P1' => mimtm_stack1_virtual,
- 'P2' => fuse_cap, })
- extract_devices(capacitor(cap_mim3f0, 3.0e-15, MIMCap), { 'P1' => mimtm_stack2_virtual,
- 'P2' => fuse2_cap, })
- tolerance(cap_mim3f0, 'C', relative: 0.25)
-
+ when '5LM'
+
+ case MIM_CAP
+ when '1'
+ # cap_mim1f0 capacitor
+ logger.info('Extracting cap_mim_1f0_m4m5_noshield device')
+ extract_devices(capacitor('cap_mim_1f0_m4m5_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m4m5_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # cap_mim1f5 capacitor
+ logger.info('Extracting cap_mim_1f5_m4m5_noshield device')
+ extract_devices(capacitor('cap_mim_1f5_m4m5_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m4m5_noshield', 'C', relative: 0.25)
+
+ when '2'
+ # cap_mim2f0 capacitor
+ logger.info('Extracting cap_mim_2f0_m4m5_noshield device')
+ extract_devices(capacitor('cap_mim_2f0_m4m5_noshield', 2.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_2f0_m4m5_noshield', 'C', relative: 0.25)
+ end
+
+ when '4LM'
+
+ case MIM_CAP
+ when '1'
+ # cap_mim1f0 capacitor
+ logger.info('Extracting cap_mim_1f0_m3m4_noshield device')
+ extract_devices(capacitor('cap_mim_1f0_m3m4_noshield', 1.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f0_m3m4_noshield', 'C', relative: 0.25)
+
+ when '1.5'
+ # cap_mim1f5 capacitor
+ logger.info('Extracting cap_mim_1f5_m3m4_noshield device')
+ extract_devices(capacitor('cap_mim_1f5_m3m4_noshield', 1.5e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_1f5_m3m4_noshield', 'C', relative: 0.25)
+
+ when '2'
+ # cap_mim2f0 capacitor
+ logger.info('Extracting cap_mim_2f0_m3m4_noshield device')
+ extract_devices(capacitor('cap_mim_2f0_m3m4_noshield', 2.0e-15, MIMCap),
+ { 'P1' => mimtm_virtual, 'P2' => fuse_cap })
+ tolerance('cap_mim_2f0_m3m4_noshield', 'C', relative: 0.25)
+ end
end
-
-end
\ No newline at end of file
+end
diff --git a/IC/klayout/lvs/rule_decks/mos_derivations.lvs b/IC/klayout/lvs/rule_decks/mos_derivations.lvs
index 400e3cd..55fceeb 100644
--- a/IC/klayout/lvs/rule_decks/mos_derivations.lvs
+++ b/IC/klayout/lvs/rule_decks/mos_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -20,31 +20,42 @@
logger.info('Starting MOSFET DERIVATIONS')
+# ===================
+# --- MOS EXCLUDE ---
+# ===================
+
+mos_exclude = resistor.join(sab).join(res_mk)
+ .join(diode_mk).join(lvs_bjt).join(lvs_rf)
+ .join(res_mk_type1)
+
+ngate_lv = ngate.not(dualgate)
+ngate_mv = ngate.and(dualgate)
+
+# ==============
+# ---- NMOS ----
+# ==============
+
+logger.info('Starting NMOS layers DERIVATIONS')
+
+# nfet_01v8: Thin gate NMOS (1.8v) [nmos_1p8]
+ngate_01v8 = ngate_lv.not(mos_exclude).not(nat)
+
+# nfet_03v3: Thick gate NMOS (3.3v) [nmos_3p3]
+ngate_03v3 = ngate_mv.not(mos_exclude).not(nat)
+
+# nfet_01v8_nvt: Thin gate native NMOS (1.8v) [nmos_1p8_nat]
+ngate_nvt_01v8 = ngate_lv.and(nat).not(mos_exclude)
+
+# nfet_03v3_nvt: Thick gate native NMOS (3.3v) [nmos_3p3_nat]
+ngate_nvt_03v3 = ngate_mv.and(nat).not(mos_exclude)
+
# ==============
# ---- PMOS ----
# ==============
logger.info('Starting PMOS layers DERIVATIONS')
-# 1.8V PMOS transistor
-pgate_1p8 = pgate.not(dualgate).not(res_mk_type1).not(sab).not(nat).not(diode_mk).not(lvs_bjt)
+# pfet_01v8: Thin gate PMOS (1.8v) [pmos_1p8]
+pgate_01v8 = pgate.not(dualgate).not(mos_exclude).not(nat)
-# 3.3V PMOS transistor
-pgate_3p3 = pgate.and(dualgate).not(res_mk_type1).not(sab).not(nat).not(diode_mk).not(lvs_bjt)
-
-
-# ==============
-# ---- NMOS ----
-# ==============
-logger.info('Starting NMOS layers DERIVATIONS')
-
-# 1.8V NMOS transistor
-ngate_1p8 = ngate.not(dualgate).not(res_mk_type1).not(sab).not(nat).not(diode_mk).not(lvs_bjt)
-
-# 3.3V NMOS transistor
-ngate_3p3 = ngate.and(dualgate).not(res_mk_type1).not(sab).not(nat).not(diode_mk).not(lvs_bjt)
-
-# Nat 1.8V NMOS transistor
-ngate_nat_1p8 = ngate.not(dualgate).not(res_mk_type1).not(sab).and(nat).not(diode_mk).not(lvs_bjt)
-
-# Nat 3.3V NMOS transistor
-ngate_nat_3p3 = ngate.and(dualgate).not(res_mk_type1).not(sab).and(nat).not(diode_mk).not(lvs_bjt)
\ No newline at end of file
+# pfet_03v3: 3.3V PMOS transistor [pmos_3p3]
+pgate_03v3 = pgate.and(dualgate).not(mos_exclude).not(nat)
diff --git a/IC/klayout/lvs/rule_decks/mos_extraction.lvs b/IC/klayout/lvs/rule_decks/mos_extraction.lvs
index 7a9afe4..9f3c0e4 100644
--- a/IC/klayout/lvs/rule_decks/mos_extraction.lvs
+++ b/IC/klayout/lvs/rule_decks/mos_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -14,7 +14,6 @@
# limitations under the License.
################################################################################################
-
#================================
# ----- MOSFET EXTRACTION -------
#================================
@@ -22,43 +21,42 @@
logger.info('Starting MOSFET EXTRACTION')
# ==============
-# ---- PMOS ----
-# ==============
-logger.info('Starting PMOS EXTRACTION')
-
-# 1.8V PMOS transistor
-logger.info('Extracting 1.8V PMOS transistor')
-extract_devices(mos4('pmos_1p8'),
- { 'SD' => psd, 'G' => pgate_1p8, 'tS' => psd, 'tD' => psd, 'tG' => poly2_con, 'W' => nwell_con })
-
-# 3.3V PMOS transistor
-logger.info('Extracting 3.3V PMOS transistor')
-extract_devices(mos4('pmos_3p3'),
- { 'SD' => psd, 'G' => pgate_3p3, 'tS' => psd, 'tD' => psd, 'tG' => poly2_con, 'W' => nwell_con })
-
-
-# ==============
# ---- NMOS ----
# ==============
logger.info('Starting NMOS EXTRACTION')
-# 1.8V NMOS transistor
-logger.info('1.8V NMOS transistor')
-extract_devices(mos4('nmos_1p8'),
- { 'SD' => nsd, 'G' => ngate_1p8, 'tS' => nsd, 'tD' => nsd, 'tG' => poly2_con, 'W' => sub })
+# nfet_01v8: Thin gate NMOS (1.8v) [nmos_1p8]
+logger.info('Extracting nfet_01v8 transistor')
+extract_devices(mos4('nfet_01v8'),
+ { 'SD' => nsd, 'G' => ngate_01v8, 'tS' => nsd, 'tD' => nsd, 'tG' => poly2_con, 'W' => sub })
-# 3.3V NMOS transistor
-logger.info('3.3V NMOS transistor')
-extract_devices(mos4('nmos_3p3'),
- { 'SD' => nsd, 'G' => ngate_3p3, 'tS' => nsd, 'tD' => nsd, 'tG' => poly2_con, 'W' => sub })
+# nfet_03v3: Thick gate NMOS (3.3v) [nmos_3p3]
+logger.info('Extracting nfet_03v3 transistor')
+extract_devices(mos4('nfet_03v3'),
+ { 'SD' => nsd, 'G' => ngate_03v3, 'tS' => nsd, 'tD' => nsd, 'tG' => poly2_con, 'W' => sub })
-# Nat 1.8V NMOS transistor
-logger.info('Nat 1.8V NMOS transistor')
-extract_devices(mos4('nmos_1p8_nat'),
- { 'SD' => nsd, 'G' => ngate_nat_1p8, 'tS' => nsd, 'tD' => nsd, 'tG' => poly2_con, 'W' => sub })
+# nfet_01v8_nvt: Thin gate native NMOS (1.8v) [nmos_1p8_nat]
+logger.info('Extracting nfet_01v8_nvt transistor')
+extract_devices(mos4('nfet_01v8_nvt'),
+ { 'SD' => nsd, 'G' => ngate_nvt_01v8, 'tS' => nsd, 'tD' => nsd, 'tG' => poly2_con, 'W' => sub })
-# Nat 3.3V NMOS transistor
-logger.info('Nat 3.3V NMOS transistor')
-extract_devices(mos4('nmos_3p3_nat'),
- { 'SD' => nsd, 'G' => ngate_nat_3p3, 'tS' => nsd, 'tD' => nsd, 'tG' => poly2_con, 'W' => sub })
\ No newline at end of file
+# nfet_03v3_nvt: Thick gate native NMOS (3.3v) [nmos_3p3_nat]
+logger.info('Extracting nfet_03v3_nvt transistor')
+extract_devices(mos4('nfet_03v3_nvt'),
+ { 'SD' => nsd, 'G' => ngate_nvt_03v3, 'tS' => nsd, 'tD' => nsd, 'tG' => poly2_con, 'W' => sub })
+
+# ==============
+# ---- PMOS ----
+# ==============
+logger.info('Starting PMOS EXTRACTION')
+
+# pfet_01v8: Thin gate PMOS (1.8v) [pmos_1p8]
+logger.info('Extracting pfet_01v8 transistor')
+extract_devices(mos4('pfet_01v8'),
+ { 'SD' => psd, 'G' => pgate_01v8, 'tS' => psd, 'tD' => psd, 'tG' => poly2_con, 'W' => nwell_con })
+
+# pfet_03v3: 3.3V PMOS transistor [pmos_3p3]
+logger.info('Extracting pfet_03v3 transistor')
+extract_devices(mos4('pfet_03v3'),
+ { 'SD' => psd, 'G' => pgate_03v3, 'tS' => psd, 'tD' => psd, 'tG' => poly2_con, 'W' => nwell_con })
diff --git a/IC/klayout/lvs/rule_decks/mos_varactor_derivations.lvs b/IC/klayout/lvs/rule_decks/mos_varactor_derivations.lvs
deleted file mode 100644
index e32e1f9..0000000
--- a/IC/klayout/lvs/rule_decks/mos_varactor_derivations.lvs
+++ /dev/null
@@ -1,31 +0,0 @@
-################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-################################################################################################
-
-#==================================
-# --- MOS Varactor DERIVATIONS ---
-#==================================
-
-logger.info('Starting MOS Varactor layers DERIVATIONS')
-
-# nmosvar_1p8 varactor
-ngate_1p8 = ngate.interacting(nwell).not(dnwell).not(dualgate).not(pplus).not(sab).not(res_mk)
- .not(diode_mk).not(lvs_bjt).not(nat).not(resistor).not(res_mk_type1)
-
-
-
-# nmosvar_3p3 varactor
-ngate_3p3 = ngate.interacting(nwell).not(dnwell).and(dualgate).not(pplus).not(sab).not(res_mk)
- .not(diode_mk).not(lvs_bjt).not(nat).not(resistor).not(res_mk_type1)
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/mos_varactor_extraction.lvs b/IC/klayout/lvs/rule_decks/mos_varactor_extraction.lvs
deleted file mode 100644
index 2f9b8ea..0000000
--- a/IC/klayout/lvs/rule_decks/mos_varactor_extraction.lvs
+++ /dev/null
@@ -1,32 +0,0 @@
-################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-################################################################################################
-
-#==================================
-# --- MOS Varactor Extraction ---
-#==================================
-
-logger.info('Starting MOS Varactor EXTRACTION')
-
-area_cap_1p8 = ngate_1p8.area
-area_cap_3p3 = ngate_3p3.area
-
-# nmosvar_1p8 varactor
-logger.info('nmosvar_1p8 varactor')
-extract_devices(capacitor('nmosvar_1p8', area_cap_1p8), { "P1" => ngate_1p8, "P2" => nsd })
-
-# nmosvar_3p3 varactor
-logger.info('nmosvar_3p3 varactor')
-extract_devices(capacitor('nmosvar_3p3', area_cap_3p3), { "P1" => ngate_3p3, "P2" => nsd })
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/pn_varactor_connection.lvs b/IC/klayout/lvs/rule_decks/pn_varactor_connection.lvs
deleted file mode 100644
index 8f4c111..0000000
--- a/IC/klayout/lvs/rule_decks/pn_varactor_connection.lvs
+++ /dev/null
@@ -1,23 +0,0 @@
-################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-################################################################################################
-
-#========================================
-# ------ PN Varactors CONNECTIONS -------
-#========================================
-
-# pnvar_1p8 varactor nodes connections
-connect(pnvar_1p8_terminal_n, contact)
-connect(pnvar_1p8_terminal_p, contact)
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/pn_varactor_derivations.lvs b/IC/klayout/lvs/rule_decks/pn_varactor_derivations.lvs
deleted file mode 100644
index f456046..0000000
--- a/IC/klayout/lvs/rule_decks/pn_varactor_derivations.lvs
+++ /dev/null
@@ -1,28 +0,0 @@
-################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-################################################################################################
-
-#==================================
-# --- PN Varactor DERIVATIONS ---
-#==================================
-
-logger.info('Starting PN Varactor layers DERIVATIONS')
-
-# pnvar_1p8 varactor
-pnvar_1p8_terminal_n = ncomp.outside(nwell).outside(dnwell).not(dualgate).not(sab).not(res_mk)
- .not(diode_mk).not(lvs_bjt).not(nat).not(resistor).not(res_mk_type1)
-
-pnvar_1p8_terminal_p = pcomp.outside(nwell).outside(dnwell).not(dualgate).not(sab).not(res_mk)
- .not(diode_mk).not(lvs_bjt).not(nat).not(resistor).not(res_mk_type1)
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/pn_varactor_extraction.lvs b/IC/klayout/lvs/rule_decks/pn_varactor_extraction.lvs
deleted file mode 100644
index 634fad1..0000000
--- a/IC/klayout/lvs/rule_decks/pn_varactor_extraction.lvs
+++ /dev/null
@@ -1,26 +0,0 @@
-################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-################################################################################################
-
-#=======================================
-# ------ PN Varactor EXTRACTION -------
-#=======================================
-
-# pnvar_1p8 varactor
-logger.info('Extracting pnvar_1p8')
-
-extract_devices(capacitor_with_bulk("pnvar_1p8", 4.4e-15, VarCap),
- { "P1" => pnvar_1p8_terminal_p, "P2" => pnvar_1p8_terminal_n,
- "W" => sub})
\ No newline at end of file
diff --git a/IC/klayout/lvs/rule_decks/res_connection.lvs b/IC/klayout/lvs/rule_decks/res_connections.lvs
similarity index 95%
rename from IC/klayout/lvs/rule_decks/res_connection.lvs
rename to IC/klayout/lvs/rule_decks/res_connections.lvs
index 813bd1b..d5f77d6 100644
--- a/IC/klayout/lvs/rule_decks/res_connection.lvs
+++ b/IC/klayout/lvs/rule_decks/res_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/IC/klayout/lvs/rule_decks/res_derivations.lvs b/IC/klayout/lvs/rule_decks/res_derivations.lvs
index 6a3efed..93b8da1 100644
--- a/IC/klayout/lvs/rule_decks/res_derivations.lvs
+++ b/IC/klayout/lvs/rule_decks/res_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/IC/klayout/lvs/rule_decks/res_extraction.lvs b/IC/klayout/lvs/rule_decks/res_extraction.lvs
index af17e49..e17eaad 100644
--- a/IC/klayout/lvs/rule_decks/res_extraction.lvs
+++ b/IC/klayout/lvs/rule_decks/res_extraction.lvs
@@ -1,6 +1,6 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/IC/klayout/lvs/run_lvs.py b/IC/klayout/lvs/run_lvs.py
index e6d0bf3..c0179f0 100644
--- a/IC/klayout/lvs/run_lvs.py
+++ b/IC/klayout/lvs/run_lvs.py
@@ -1,194 +1,426 @@
-# Copyright 2022 GlobalFoundries PDK Authors
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
-# http://www.apache.org/licenses/LICENSE-2.0
+# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
+################################################################################################
"""Run GlobalFoundries 180nm IC LVS.
Usage:
run_lvs.py (--help| -h)
- run_lvs.py (--design=<layout_path>) (--net=<netlist_path>) (--gf180ic=<combined_options>) [--thr=<thr>] [--run_mode=<run_mode>] [--lvs_sub=<sub_name>] [--no_net_names] [--set_spice_comments] [--set_scale] [--set_verbose] [--set_schematic_simplify] [--set_net_only] [--set_top_lvl_pins] [--set_combine] [--set_purge] [--set_purge_nets]
+ run_lvs.py (--layout=<layout_path>) (--netlist=<netlist_path>) (--variant=<combined_options>) [--thr=<thr>] [--run_dir=<run_dir_path>] [--topcell=<topcell_name>] [--run_mode=<run_mode>] [--verbose] [--lvs_sub=<sub_name>] [--no_net_names] [--spice_comments] [--scale] [--schematic_simplify] [--net_only] [--top_lvl_pins] [--combine] [--purge] [--purge_nets]
Options:
--help -h Print this help message.
- --design=<layout_path> The input GDS file path.
- --net=<netlist_path> The input netlist file path.
- --gf180ic=<combined_options> Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C).
- gf180ic=A: Select metal_top=30K mim_option=A metal_level=3LM poly_res=1K, and mim_cap=2
- gf180ic=B: Select metal_top=11K mim_option=B metal_level=4LM poly_res=1K, and mim_cap=2
- gf180ic=C: Select metal_top=9K mim_option=B metal_level=5LM poly_res=1K, and mim_cap=2
- --thr=<thr> Number of cores to be used by LVS checker
+ --layout=<layout_path> The input GDS file path.
+ --netlist=<netlist_path> The input netlist file path.
+ --variant=<combined_options> Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C).
+ gf180IC=A: Select metal_top=30K mim_option=A metal_level=3LM poly_res=1K, and mim_cap=2
+ gf180IC=B: Select metal_top=11K mim_option=B metal_level=4LM poly_res=1K, and mim_cap=2
+ gf180IC=C: Select metal_top=9K mim_option=B metal_level=5LM poly_res=1K, and mim_cap=2
+ --thr=<thr> The number of threads used in run.
+ --run_dir=<run_dir_path> Run directory to save all the results [default: pwd]
+ --topcell=<topcell_name> Topcell name to use.
--run_mode=<run_mode> Select klayout mode Allowed modes (flat , deep, tiling). [default: deep]
- --lvs_sub=<sub_name> Assign the substrate name used in design.
+ --lvs_sub=<sub_name> Substrate name used in your design.
+ --verbose Detailed rule execution log for debugging.
--no_net_names Discard net names in extracted netlist.
- --set_spice_comments Set netlist comments in extracted netlist.
- --set_scale Set scale of 1e6 in extracted netlist.
- --set_verbose Set verbose mode.
- --set_schematic_simplify Set schematic simplification in input netlist.
- --set_net_only Set netlist object creation only in extracted netlist.
- --set_top_lvl_pins Set top level pins only in extracted netlist.
- --set_combine Set netlist combine only in extracted netlist.
- --set_purge Set netlist purge all only in extracted netlist.
- --set_purge_nets Set netlist purge nets only in extracted netlist.
+ --spice_comments Enable netlist comments in extracted netlist.
+ --scale Enable scale of 1e6 in extracted netlist.
+ --schematic_simplify Enable schematic simplification in input netlist.
+ --net_only Enable netlist object creation only in extracted netlist.
+ --top_lvl_pins Enable top level pins only in extracted netlist.
+ --combine Enable netlist combine only in extracted netlist.
+ --purge Enable netlist purge all only in extracted netlist.
+ --purge_nets Enable netlist purge nets only in extracted netlist.
"""
from docopt import docopt
import os
import logging
-
+import klayout.db
+from datetime import datetime
from subprocess import check_call
-def main():
+def check_klayout_version():
+ """
+ check_klayout_version checks klayout version and makes sure it would work with the LVS.
+ """
+ # ======= Checking Klayout version =======
+ klayout_v_ = os.popen("klayout -b -v").read()
+ klayout_v_ = klayout_v_.split("\n")[0]
+ klayout_v_list = []
- # Switches used in run
- switches = ""
+ if klayout_v_ == "":
+ logging.error("Klayout is not found. Please make sure klayout is installed.")
+ exit(1)
+ else:
+ klayout_v_list = [int(v) for v in klayout_v_.split(" ")[-1].split(".")]
- if args["--run_mode"] in ["flat", "deep", "tiling"]:
- switches = switches + f'-rd run_mode={args["--run_mode"]} '
+ if len(klayout_v_list) < 1 or len(klayout_v_list) > 3:
+ logging.error("Was not able to get klayout version properly.")
+ exit(1)
+ elif len(klayout_v_list) >= 2 or len(klayout_v_list) <= 3:
+ if klayout_v_list[1] < 28:
+ logging.error("Prerequisites at a minimum: KLayout 0.28.0")
+ logging.error(
+ "Using this klayout version has not been assesed in this development. Limits are unknown"
+ )
+ exit(1)
+
+ logging.info(f"Your Klayout version is: {klayout_v_}")
+
+
+def check_layout_type(layout_path):
+ """
+ check_layout_type checks if the layout provided is GDS or OAS. Otherwise, kill the process. We only support GDS or OAS now.
+
+ Parameters
+ ----------
+ layout_path : string
+ string that represent the path of the layout.
+
+ Returns
+ -------
+ string
+ string that represent full absolute layout path.
+ """
+
+ if not os.path.isfile(layout_path):
+ logging.error(
+ f"## GDS file path {layout_path} provided doesn't exist or not a file."
+ )
+ exit(1)
+
+ if ".gds" not in layout_path and ".oas" not in layout_path:
+ logging.error(
+ f"## Layout {layout_path} is not in GDSII or OASIS format. Please use gds format."
+ )
+ exit(1)
+
+ return os.path.abspath(layout_path)
+
+
+def get_top_cell_names(gds_path):
+ """
+ get_top_cell_names get the top cell names from the GDS file.
+
+ Parameters
+ ----------
+ gds_path : string
+ Path to the target GDS file.
+
+ Returns
+ -------
+ List of string
+ Names of the top cell in the layout.
+ """
+ layout = klayout.db.Layout()
+ layout.read(gds_path)
+ top_cells = [t.name for t in layout.top_cells()]
+
+ return top_cells
+
+
+def get_run_top_cell_name(arguments, layout_path):
+ """
+ get_run_top_cell_name Get the top cell name to use for running. If it's provided by the user, we use the user input.
+ If not, we get it from the GDS file.
+
+ Parameters
+ ----------
+ arguments : dict
+ Dictionary that holds the user inputs for the script generated by docopt.
+ layout_path : string
+ Path to the target layout.
+
+ Returns
+ -------
+ string
+ Name of the topcell to use in run.
+
+ """
+
+ if arguments["--topcell"]:
+ topcell = arguments["--topcell"]
+ else:
+ layout_topcells = get_top_cell_names(layout_path)
+ if len(layout_topcells) > 1:
+ logging.error(
+ "## Layout has multiple topcells. Please use --topcell to determine which topcell you want to run on."
+ )
+ exit(1)
+ else:
+ topcell = layout_topcells[0]
+
+ return topcell
+
+
+def generate_klayout_switches(arguments, layout_path, netlist_path):
+ """
+ parse_switches Function that parse all the args from input to prepare switches for LVS run.
+
+ Parameters
+ ----------
+ arguments : dict
+ Dictionary that holds the arguments used by user in the run command. This is generated by docopt library.
+ layout_path : string
+ Path to the layout file that we will run LVS on.
+ netlist_path : string
+ Path to the netlist file that we will run LVS on.
+
+ Returns
+ -------
+ dict
+ Dictionary that represent all run switches passed to klayout.
+ """
+ switches = dict()
+
+ # No. of threads
+ thrCount = 2 if arguments["--thr"] is None else int(arguments["--thr"])
+ switches["thr"] = str(int(thrCount))
+
+ if arguments["--run_mode"] in ["flat", "deep", "tiling"]:
+ switches["run_mode"] = arguments["--run_mode"]
else:
logging.error("Allowed klayout modes are (flat , deep , tiling) only")
exit()
- if args["--gf180ic"] == "A":
- switches = (
- switches
- + "-rd metal_top=30K -rd mim_option=A -rd metal_level=3LM -rd poly_res=1K -rd mim_cap=2 "
- )
- elif args["--gf180ic"] == "B":
- switches = (
- switches
- + "-rd metal_top=11K -rd mim_option=B -rd metal_level=4LM -rd poly_res=1K -rd mim_cap=2 "
- )
- elif args["--gf180ic"] == "C":
- switches = (
- switches
- + "-rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd poly_res=1K -rd mim_cap=2 "
- )
+ if arguments["--variant"] == "A":
+ switches["metal_top"] = "30K"
+ switches["mim_option"] = "A"
+ switches["metal_level"] = "3LM"
+ switches["poly_res"] = "1K"
+ switches["mim_cap"] = "2"
+ elif arguments["--variant"] == "B":
+ switches["metal_top"] = "11K"
+ switches["mim_option"] = "B"
+ switches["metal_level"] = "4LM"
+ switches["poly_res"] = "1K"
+ switches["mim_cap"] = "2"
+ elif arguments["--variant"] == "C":
+ switches["metal_top"] = "9K"
+ switches["mim_option"] = "B"
+ switches["metal_level"] = "5LM"
+ switches["poly_res"] = "1K"
+ switches["mim_cap"] = "2"
else:
- print("gf180ic switch allowed values are (A , B, C) only")
- exit()
+ logging.error("variant switch allowed values are (A , B, C) only")
+ exit(1)
- switches = (
- switches + "-rd spice_net_names=false "
- if args["--no_net_names"]
- else switches + "-rd spice_net_names=true "
- )
-
- switches = (
- switches + "-rd spice_comments=true "
- if args["--set_spice_comments"]
- else switches + "-rd spice_comments=false "
- )
-
- switches = (
- switches + "-rd scale=true "
- if args["--set_scale"]
- else switches + "-rd scale=false "
- )
-
- switches = (
- switches + "-rd verbose=true "
- if args["--set_verbose"]
- else switches + "-rd verbose=false "
- )
-
- switches = (
- switches + "-rd schematic_simplify=true "
- if args["--set_schematic_simplify"]
- else switches + "-rd schematic_simplify=false "
- )
-
- switches = (
- switches + "-rd net_only=true "
- if args["--set_net_only"]
- else switches + "-rd net_only=false "
- )
-
- switches = (
- switches + "-rd top_lvl_pins=true "
- if args["--set_top_lvl_pins"]
- else switches + "-rd top_lvl_pins=false "
- )
-
- switches = (
- switches + "-rd combine=true "
- if args["--set_combine"]
- else switches + "-rd combine=false "
- )
-
- switches = (
- switches + "-rd purge=true "
- if args["--set_purge"]
- else switches + "-rd purge=false "
- )
-
- switches = (
- switches + "-rd purge_nets=true "
- if args["--set_purge_nets"]
- else switches + "-rd purge_nets=false "
- )
-
- switches = (
- switches + f'-rd lvs_sub={args["--lvs_sub"]} '
- if args["--lvs_sub"]
- else switches
- )
-
- # Generate databases
- if args["--design"]:
- path = args["--design"]
- if args["--design"]:
- file_name = args["--net"].split(".")
- else:
- print(
- "The script must be given a netlist file or a path to be able to run LVS"
- )
- exit()
- check_call(
- f"klayout -b -r {run_lvs_full_path}/gf180ic.lvs -rd input={path} -rd report={file_name[0]}.lyrdb -rd schematic={args['--net']} -rd target_netlist=extracted_netlist_{file_name[0]}.cir -rd thr={workers_count} {switches}",
- shell=True,
- )
-
+ if arguments["--lvs_sub"]:
+ switches["lvs_sub"] = arguments["--lvs_sub"]
else:
- print("The script must be given a layout file or a path to be able to run LVS")
- exit()
+ switches["lvs_sub"] = "gf180IC_gnd"
+
+ if arguments["--verbose"]:
+ switches["verbose"] = "true"
+ else:
+ switches["verbose"] = "false"
+
+ if arguments["--no_net_names"]:
+ switches["spice_net_names"] = "false"
+ else:
+ switches["spice_net_names"] = "true"
+
+ if arguments["--spice_comments"]:
+ switches["spice_comments"] = "true"
+ else:
+ switches["spice_comments"] = "false"
+
+ if arguments["--scale"]:
+ switches["scale"] = "true"
+ else:
+ switches["scale"] = "false"
+
+ if arguments["--schematic_simplify"]:
+ switches["schematic_simplify"] = "true"
+ else:
+ switches["schematic_simplify"] = "false"
+
+ if arguments["--net_only"]:
+ switches["net_only"] = "true"
+ else:
+ switches["net_only"] = "false"
+
+ if arguments["--top_lvl_pins"]:
+ switches["top_lvl_pins"] = "true"
+ else:
+ switches["top_lvl_pins"] = "false"
+
+ if arguments["--combine"]:
+ switches["combine"] = "true"
+ else:
+ switches["combine"] = "false"
+
+ if arguments["--purge"]:
+ switches["purge"] = "true"
+ else:
+ switches["purge"] = "false"
+
+ if arguments["--purge_nets"]:
+ switches["purge_nets"] = "true"
+ else:
+ switches["purge_nets"] = "false"
+
+ switches["topcell"] = get_run_top_cell_name(arguments, layout_path)
+ switches["input"] = os.path.abspath(layout_path)
+ switches["schematic"] = os.path.abspath(netlist_path)
+
+ return switches
+
+
+def build_switches_string(sws: dict):
+ """
+ build_switches_string Build swtiches string from dictionary.
+
+ Parameters
+ ----------
+ sws : dict
+ Dictionary that holds the Antenna swithces.
+ """
+ return " ".join(f"-rd {k}={v}" for k, v in sws.items())
+
+
+def check_lvs_results(results_db_files: list):
+ """
+ check_lvs_results Checks the results db generated from run and report at the end if the LVS run failed or passed.
+
+ Parameters
+ ----------
+ results_db_files : list
+ A list of strings that represent paths to results databases of all the LVS runs.
+ """
+
+ if len(results_db_files) < 1:
+ logging.error("Klayout did not generate any db results. Please check run logs")
+ exit(1)
+
+
+def run_check(lvs_file: str, path: str, run_dir: str, sws: dict):
+ """
+ run_check run LVS check.
+
+ Parameters
+ ----------
+ lvs_file : str
+ String that has the file full path to run.
+ path : str
+ String that holds the full path of the layout.
+ run_dir : str
+ String that holds the full path of the run location.
+ sws : dict
+ Dictionary that holds all switches that needs to be passed to the antenna checks.
+
+ Returns
+ -------
+ string
+ string that represent the path to the results output database for this run.
+
+ """
+
+ logging.info(f'Running Global Foundries 180nm IC {lvs_file} checks on design {path} on cell {sws["topcell"]}')
+
+ layout_base_name = os.path.basename(path).split(".")[0]
+ new_sws = sws.copy()
+ report_path = os.path.join(run_dir, f"{layout_base_name}.lvsdb")
+ ext_net_path = os.path.join(run_dir, f"{layout_base_name}.cir")
+ new_sws["report"] = report_path
+ new_sws["target_netlist"] = ext_net_path
+
+ sws_str = build_switches_string(new_sws)
+
+ run_str = f"klayout -b -r {lvs_file} {sws_str}"
+ check_call(run_str, shell=True)
+
+ return report_path
+
+
+def main(lvs_run_dir: str, arguments: dict):
+ """
+ main function to run the LVS.
+
+ Parameters
+ ----------
+ lvs_run_dir : str
+ String with absolute path of the full run dir.
+ arguments : dict
+ Dictionary that holds the arguments used by user in the run command. This is generated by docopt library.
+ """
+
+ ## Check Klayout version
+ check_klayout_version()
+
+ ## Check layout file existance
+ layout_path = arguments["--layout"]
+ if not os.path.exists(arguments["--layout"]):
+ logging.error(
+ f"The input GDS file path {layout_path} doesn't exist, please recheck."
+ )
+ exit(1)
+
+ ## Check layout type
+ layout_path = check_layout_type(layout_path)
+
+ # Check netlist file existance
+ netlist_path = arguments["--netlist"]
+ if not os.path.exists(arguments["--netlist"]):
+ logging.error(
+ f"The input netlist file path {netlist_path} doesn't exist, please recheck."
+ )
+ exit(1)
+
+ lvs_rule_deck = os.path.join(os.path.dirname(os.path.abspath(__file__)), "gf180IC.lvs")
+
+ ## Get run switches
+ switches = generate_klayout_switches(arguments, layout_path, netlist_path)
+
+ ## Run LVS check
+ res_db_files = run_check(lvs_rule_deck, layout_path, lvs_run_dir, switches)
+
+ ## Check run
+ check_lvs_results(res_db_files)
if __name__ == "__main__":
+ # arguments
+ arguments = docopt(__doc__, version="RUN LVS: 1.0")
+
+ # logs format
+ now_str = datetime.utcnow().strftime("lvs_run_%Y_%m_%d_%H_%M_%S")
+
+ if (
+ arguments["--run_dir"] == "pwd"
+ or arguments["--run_dir"] == ""
+ or arguments["--run_dir"] is None
+ ):
+ lvs_run_dir = os.path.join(os.path.abspath(os.getcwd()), now_str)
+ else:
+ lvs_run_dir = os.path.abspath(arguments["--run_dir"])
+
+ os.makedirs(lvs_run_dir, exist_ok=True)
+
logging.basicConfig(
level=logging.DEBUG,
+ handlers=[
+ logging.FileHandler(os.path.join(lvs_run_dir, "{}.log".format(now_str))),
+ logging.StreamHandler(),
+ ],
format="%(asctime)s | %(levelname)-7s | %(message)s",
datefmt="%d-%b-%Y %H:%M:%S",
)
- # Args
- args = docopt(__doc__, version="LVS Checker: 0.1")
- workers_count = os.cpu_count() * 2 if args["--thr"] is None else int(args["--thr"])
-
- run_lvs_full_path = os.path.dirname(os.path.abspath(__file__))
-
- # ========= Checking Klayout version =========
- klayout_v_ = os.popen("klayout -v").read()
- klayout_v_ = klayout_v_.split("\n")[0]
- klayout_v = int(klayout_v_.split(".")[-1])
-
- if klayout_v < 8:
- logging.warning(
- "Using this klayout version has not been assesed in this development. Limits are unknown"
- )
- logging.info(f"Your version is: {klayout_v_}")
- logging.info("Prerequisites at a minimum: KLayout 0.27.8")
-
# Calling main function
- main()
+ main(lvs_run_dir, arguments)
diff --git a/IC/klayout/lvs/testing/Makefile b/IC/klayout/lvs/testing/Makefile
index 198c2a7..048d8cb 100644
--- a/IC/klayout/lvs/testing/Makefile
+++ b/IC/klayout/lvs/testing/Makefile
@@ -1,5 +1,5 @@
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -18,33 +18,21 @@
#=========================================================================
SHELL := /bin/bash
-Testing_DIR ?= $(shell pwd)
+
.DEFAULT_GOAL := all
all: test-LVS
-test-LVS: test-LVS-main
-
+test-LVS: test-LVS-switch test-LVS-main
+
#=================================
# ----- test-LVS_regression ------
#=================================
.ONESHELL:
-test-LVS-main: test-LVS-MOS test-LVS-BJT test-LVS-DIODE test-LVS-RES test-LVS-MIMCAP test-LVS-PN_VARACTOR test-LVS-MOS_VARACTOR
+test-LVS-main: test-LVS-MOS test-LVS-BJT test-LVS-DIODE test-LVS-RES test-LVS-MIMCAP test-LVS-MOSCAP test-LVS-MOS_SAB
.ONESHELL:
test-LVS-%:
+ @echo "========== LVS-$* testing =========="
@ python3 run_regression.py --device_name=$*
-
-#=================================
-# -------- test-LVS-switch -------
-#=================================
-
-.ONESHELL:
-test-LVS-switch:
- @cd $(Testing_DIR)
- @cd ..
- @echo "========== LVS-Switch testing =========="
- @python3 run_lvs.py --design=testing/extraction_checking/sample_nfet_03v3.gds --net=sample_nfet_03v3.cir --gf180ic=A
- @python3 run_lvs.py --design=testing/extraction_checking/sample_nfet_03v3.gds --net=sample_nfet_03v3.cir --gf180ic=B
- @python3 run_lvs.py --design=testing/extraction_checking/sample_nfet_03v3.gds --net=sample_nfet_03v3.cir --gf180ic=C
\ No newline at end of file
diff --git a/IC/klayout/lvs/testing/run_regression.py b/IC/klayout/lvs/testing/run_regression.py
index 9b81be9..ec7f3d3 100644
--- a/IC/klayout/lvs/testing/run_regression.py
+++ b/IC/klayout/lvs/testing/run_regression.py
@@ -20,7 +20,7 @@
Options:
--help -h Print this help message.
- --device_name=<device_name> Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, PN_VARACTOR, MOS_VARACTOR).
+ --device_name=<device_name> Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, PISCAP, ESD, EFUSE).
--mp=<num> The number of threads used in run.
--run_name=<run_name> Select your run name.
"""
@@ -70,9 +70,7 @@
logging.error("Was not able to get klayout version properly.")
exit(1)
elif len(klayout_v_list) >= 2 or len(klayout_v_list) <= 3:
- if klayout_v_list[1] < 28 or (
- klayout_v_list[1] == 28 and klayout_v_list[2] <= 3
- ):
+ if klayout_v_list[1] < 28 or (klayout_v_list[1] == 28 and klayout_v_list[2] <= 3):
logging.error("Prerequisites at a minimum: KLayout 0.28.4")
logging.error(
"Using this klayout version is not supported in this development."
@@ -85,6 +83,7 @@
def parse_existing_devices(rule_deck_path, output_path, target_device_group=None):
"""
This function collects the rule names from the existing drc rule decks.
+
Parameters
----------
rule_deck_path : string or Path object
@@ -93,6 +92,7 @@
Path of the run location to store the output analysis file.
target_device_group : string Optional
Name of the device group to be in testing
+
Returns
-------
pd.DataFrame
@@ -100,14 +100,10 @@
"""
if target_device_group is None:
- lvs_files = glob.glob(
- os.path.join(rule_deck_path, "rule_decks", "*_extraction.lvs")
- )
+ lvs_files = glob.glob(os.path.join(rule_deck_path, "rule_decks", "*_extraction.lvs"))
else:
table_device_file = os.path.join(
- rule_deck_path,
- "rule_decks",
- f"{str(target_device_group).lower()}_extraction.lvs",
+ rule_deck_path, "rule_decks", f"{str(target_device_group).lower()}_extraction.lvs"
)
if not os.path.isfile(table_device_file):
raise FileNotFoundError(
@@ -124,9 +120,9 @@
if "extract_devices" in line:
line_list = line.split("'")
rule_info = dict()
- rule_info["device_group"] = (
- os.path.basename(runset).replace("_extraction.lvs", "").upper()
- )
+ rule_info["device_group"] = os.path.basename(runset).replace(
+ "_extraction.lvs", ""
+ ).upper()
rule_info["device_name"] = line_list[1]
rule_info["in_rule_deck"] = 1
rules_data.append(rule_info)
@@ -140,12 +136,14 @@
def build_tests_dataframe(unit_test_cases_dir, target_device_group):
"""
This function is used for getting all test cases available in a formated dataframe before running.
+
Parameters
----------
unit_test_cases_dir : str
Path string to the location of unit test cases path.
target_device_group : str or None
Name of device group that we want to run regression for. If None, run all found.
+
Returns
-------
pd.DataFrame
@@ -155,37 +153,26 @@
Path(unit_test_cases_dir).rglob("*.{}".format(SUPPORTED_TC_EXT))
)
logging.info(
- "## Total number of gds files test cases found: {}".format(
- len(all_unit_test_cases_layout)
- )
+ "## Total number of gds files test cases found: {}".format(len(all_unit_test_cases_layout))
)
all_unit_test_cases_netlist = sorted(
Path(unit_test_cases_dir).rglob("*.{}".format(SUPPORTED_SPICE_EXT))
)
logging.info(
- "## Total number of spice files test cases found: {}".format(
- len(all_unit_test_cases_netlist)
- )
+ "## Total number of spice files test cases found: {}".format(len(all_unit_test_cases_netlist))
)
if len(all_unit_test_cases_netlist) != len(all_unit_test_cases_layout):
- logging.error("## Each testcase should have Layout and Netlist file")
+ logging.error(
+ "## Each testcase should have Layout and Netlist file"
+ )
exit(1)
# Get test cases df from test cases
- tc_df = pd.DataFrame(
- {
- "test_layout_path": all_unit_test_cases_layout,
- "test_netlist_path": all_unit_test_cases_netlist,
- }
- )
- tc_df["device_name"] = tc_df["test_layout_path"].apply(
- lambda x: x.name.replace(".gds", "")
- )
- tc_df["device_group"] = tc_df["test_layout_path"].apply(
- lambda x: x.parent.parent.name.replace("_devices", "").upper()
- )
+ tc_df = pd.DataFrame({"test_layout_path": all_unit_test_cases_layout , "test_netlist_path": all_unit_test_cases_netlist})
+ tc_df["device_name"] = tc_df["test_layout_path"].apply(lambda x: x.name.replace(".gds", ""))
+ tc_df["device_group"] = tc_df["test_layout_path"].apply(lambda x: x.parent.parent.name.replace("_devices", "").upper())
if target_device_group is not None:
tc_df = tc_df[tc_df["device_group"] == target_device_group]
@@ -228,6 +215,7 @@
):
"""
This function run a single test case using the correct DRC file.
+
Parameters
----------
lvs_dir : string or Path
@@ -240,6 +228,7 @@
Path to the location where is the regression run is done.
device_name : string
Device name that we are running on.
+
Returns
-------
dict
@@ -255,16 +244,12 @@
switches = " ".join(get_switches(sw_file, device_name))
else:
# Get switches
- switches = (
- " -rd lvs_sub=sub!"
- if device_name == "sample_ggnfet_06v0_dss"
- else " -rd lvs_sub=vdd!"
- ) # default switch
+ switches = " -rd lvs_sub=sub!" if device_name == "sample_ggnfet_06v0_dss" else " -rd lvs_sub=vdd!" # default switch
# Creating run folder structure and copy testcases in it
pattern_clean = ".".join(os.path.basename(layout_path).split(".")[:-1])
- output_loc = f"{run_dir}/{device_name}"
- pattern_log = f"{output_loc}/{pattern_clean}_lvs.log"
+ output_loc = os.path.join(run_dir, device_name)
+ pattern_log = os.path.join(output_loc, f"{pattern_clean}_lvs.log")
os.makedirs(output_loc, exist_ok=True)
layout_path_run = os.path.join(run_dir, device_name, f"{device_name}.gds")
netlist_path_run = os.path.join(run_dir, device_name, f"{device_name}.cdl")
@@ -272,7 +257,7 @@
shutil.copyfile(netlist_path, netlist_path_run)
# command to run drc
- call_str = f"klayout -b -r {lvs_dir}/gf180ic.lvs -rd input={layout_path_run} -rd schematic={device_name}.cdl -rd report={device_name}.lvsdb -rd target_netlist={device_name}_extracted.cir {switches} > {pattern_log} 2>&1"
+ call_str = f"klayout -b -r {lvs_dir}/gf180IC.lvs -rd input={layout_path_run} -rd schematic={device_name}.cdl -rd report={device_name}.lvsdb -rd target_netlist={device_name}_extracted.cir {switches} > {pattern_log} 2>&1"
# Starting klayout run
try:
@@ -292,11 +277,11 @@
line = line.strip()
logging.info(f"{line}")
- # checking device status
- device_status = "Failed"
+ # checking device status
+ device_status = 'Failed'
if "Congratulations! Netlists match" in result:
logging.info(f"{device_name} testcase passed")
- device_status = "Passed"
+ device_status = 'Passed'
else:
logging.error(f"{device_name} testcase failed.")
logging.error(f"Please recheck {layout_path} file.")
@@ -310,6 +295,7 @@
def run_all_test_cases(tc_df, lvs_dir, run_dir, num_workers):
"""
This function run all test cases from the input dataframe.
+
Parameters
----------
tc_df : pd.DataFrame
@@ -320,6 +306,7 @@
Path string to the location of the testing code and output.
num_workers : int
Number of workers to use for running the regression.
+
Returns
-------
pd.DataFrame
@@ -354,15 +341,19 @@
return tc_df
-def aggregate_results(results_df: pd.DataFrame, devices_df: pd.DataFrame):
+def aggregate_results(
+ results_df: pd.DataFrame, devices_df: pd.DataFrame
+):
"""
aggregate_results Aggregate the results for all runs.
+
Parameters
----------
results_df : pd.DataFrame
Dataframe that holds the information about the unit test rules.
devices_df : pd.DataFrame
Dataframe that holds the information about all the devices implemented in the rule deck.
+
Returns
-------
pd.DataFrame
@@ -376,11 +367,9 @@
elif len(devices_df) > 0 and len(results_df) < 1:
df = devices_df
else:
- df = results_df.merge(
- devices_df, how="outer", on=["device_group", "device_name"]
- )
+ df = results_df.merge(devices_df, how="outer", on=["device_group", "device_name"])
- df.loc[(df["device_status"] != "Passed"), "device_status"] = "Failed"
+ df.loc[(df["device_status"] != 'Passed'), "device_status"] = "Failed"
return df
@@ -388,7 +377,9 @@
def run_regression(lvs_dir, output_path, target_device_group, cpu_count):
"""
Running Regression Procedure.
+
This function runs the full regression on all test cases.
+
Parameters
----------
lvs_dir : string
@@ -426,7 +417,7 @@
## Aggregate all dataframes into one
df = aggregate_results(results_df, devices_df)
df.drop_duplicates(inplace=True)
- df.drop("run_id", inplace=True, axis=1)
+ df.drop('run_id', inplace=True, axis=1)
logging.info("## Final analysis table: \n" + str(df))
## Generate error if there are any missing info or fails.
@@ -447,7 +438,9 @@
def main(lvs_dir, output_path, target_device_group):
"""
Main Procedure.
+
This function is the main execution procedure
+
Parameters
----------
lvs_dir : str
@@ -526,21 +519,11 @@
)
## selected device
- allowed_devices = [
- "MOS",
- "BJT",
- "DIODE",
- "RES",
- "MIMCAP",
- "PN_VARACTOR",
- "MOS_VARACTOR",
- ]
+ allowed_devices = ["MOS", "BJT", "DIODE", "RES", "MIMCAP", "MOSCAP", "PISCAP", "APMOMCAP", "VARACTOR" , "EFUSE", "ESD"]
target_device_group = args["--device_name"]
if target_device_group and target_device_group not in allowed_devices:
- logging.error(
- "Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, PN_VARACTOR, MOS_VARACTOR) only"
- )
+ logging.error("Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, APMOMCAP, VARACTOR, MOSCAP, PISCAP, ESD, EFUSE) only")
exit(1)
# Calling main function
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwps.gds b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dw2ps.gds
similarity index 99%
rename from IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwps.gds
rename to IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dw2ps.gds
index 3e2cd60..fc4276b 100644
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwps.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dw2ps.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8.gds b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8.gds
similarity index 99%
copy from IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8.gds
copy to IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8.gds
index 00e0788..92783e9 100644
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8.gds b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8_nvt.gds
similarity index 99%
rename from IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8.gds
rename to IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8_nvt.gds
index 00e0788..2234302 100644
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_01v8_nvt.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_03v3.gds b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_03v3.gds
new file mode 100644
index 0000000..d81cb44
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_03v3.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3_nat.gds b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_03v3_nvt.gds
similarity index 99%
rename from IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3_nat.gds
rename to IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_03v3_nvt.gds
index 7a7cad2..709a5d3 100644
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3_nat.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nd2ps_03v3_nvt.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8_nat.gds b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8_nat.gds
deleted file mode 100644
index 5ea84d3..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_1p8_nat.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3.gds b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3.gds
deleted file mode 100644
index 888e4a5..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_np_3p3.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nwp.gds b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nw2ps.gds
similarity index 99%
rename from IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nwp.gds
rename to IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nw2ps.gds
index 7b82ed3..f17eeaf 100644
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nwp.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_nw2ps.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_1p8.gds b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8.gds
similarity index 99%
rename from IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_1p8.gds
rename to IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8.gds
index f32b27a..d91e0d5 100644
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_1p8.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_01v8.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_3p3.gds b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_03v3.gds
similarity index 99%
rename from IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_3p3.gds
rename to IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_03v3.gds
index 68d16b3..ad17a1c 100644
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pn_3p3.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pd2nw_03v3.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwpw.gds b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pw2dw.gds
similarity index 99%
rename from IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwpw.gds
rename to IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pw2dw.gds
index 91baff7..7d62020 100644
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_dnwpw.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/layout/diode_pw2dw.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwps.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwps.cdl
deleted file mode 100644
index 4654fe7..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwps.cdl
+++ /dev/null
@@ -1,49 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: diode_dnwps
-* View Name: schematic
-* Netlisted on: Nov 24 09:04:18 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-*.GLOBAL gnd!
-
-*.PIN gnd!
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: diode_dnwps
-* View Name: schematic
-************************************************************************
-
-.SUBCKT diode_dnwps I1_0_0_0_0_R0_NEG I1_0_1_0_0_R0_NEG I1_0_2_0_0_R0_NEG
-+ I1_1_0_0_0_R0_NEG I1_1_1_0_0_R0_NEG I1_1_2_0_0_R0_NEG I1_2_0_0_0_R0_NEG
-+ I1_2_1_0_0_R0_NEG I1_2_2_0_0_R0_NEG I1_default_NEG gnd!
-*.PININFO I1_0_0_0_0_R0_NEG:I I1_0_1_0_0_R0_NEG:I I1_0_2_0_0_R0_NEG:I
-*.PININFO I1_1_0_0_0_R0_NEG:I I1_1_1_0_0_R0_NEG:I I1_1_2_0_0_R0_NEG:I
-*.PININFO I1_2_0_0_0_R0_NEG:I I1_2_1_0_0_R0_NEG:I I1_2_2_0_0_R0_NEG:I
-*.PININFO I1_default_NEG:I gnd!:I
-DI1_2_2_0_0_R0 gnd! I1_2_2_0_0_R0_NEG diode_dnwps AREA=10n PJ=400e-6 m=1
-DI1_2_1_0_0_R0 gnd! I1_2_1_0_0_R0_NEG diode_dnwps AREA=1.034n PJ=220.68e-6 m=1
-DI1_2_0_0_0_R0 gnd! I1_2_0_0_0_R0_NEG diode_dnwps AREA=170p PJ=203.4e-6 m=1
-DI1_1_2_0_0_R0 gnd! I1_1_2_0_0_R0_NEG diode_dnwps AREA=1.034n PJ=220.68e-6 m=1
-DI1_1_1_0_0_R0 gnd! I1_1_1_0_0_R0_NEG diode_dnwps AREA=106.916p PJ=41.36e-6 m=1
-DI1_1_0_0_0_R0 gnd! I1_1_0_0_0_R0_NEG diode_dnwps AREA=17.578p PJ=24.08e-6 m=1
-DI1_0_2_0_0_R0 gnd! I1_0_2_0_0_R0_NEG diode_dnwps AREA=170p PJ=203.4e-6 m=1
-DI1_0_1_0_0_R0 gnd! I1_0_1_0_0_R0_NEG diode_dnwps AREA=17.578p PJ=24.08e-6 m=1
-DI1_0_0_0_0_R0 gnd! I1_0_0_0_0_R0_NEG diode_dnwps AREA=3.1535p PJ=7.11e-6 m=1
-DI1_default gnd! I1_default_NEG diode_dnwps AREA=100e-12 PJ=40e-6 m=1
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dw2ps.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dw2ps.cdl
new file mode 100644
index 0000000..ebdf256
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dw2ps.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_dw2ps
+* View Name: schematic
+* Netlisted on: Nov 24 09:04:18 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL gnd!
+
+*.PIN gnd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_dw2ps
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_dw2ps I1_0_0_0_0_R0_NEG I1_0_1_0_0_R0_NEG I1_0_2_0_0_R0_NEG
++ I1_1_0_0_0_R0_NEG I1_1_1_0_0_R0_NEG I1_1_2_0_0_R0_NEG I1_2_0_0_0_R0_NEG
++ I1_2_1_0_0_R0_NEG I1_2_2_0_0_R0_NEG I1_default_NEG gnd!
+*.PININFO I1_0_0_0_0_R0_NEG:I I1_0_1_0_0_R0_NEG:I I1_0_2_0_0_R0_NEG:I
+*.PININFO I1_1_0_0_0_R0_NEG:I I1_1_1_0_0_R0_NEG:I I1_1_2_0_0_R0_NEG:I
+*.PININFO I1_2_0_0_0_R0_NEG:I I1_2_1_0_0_R0_NEG:I I1_2_2_0_0_R0_NEG:I
+*.PININFO I1_default_NEG:I gnd!:I
+DI1_2_2_0_0_R0 gnd! I1_2_2_0_0_R0_NEG diode_dw2ps AREA=10n PJ=400e-6 m=1
+DI1_2_1_0_0_R0 gnd! I1_2_1_0_0_R0_NEG diode_dw2ps AREA=1.034n PJ=220.68e-6 m=1
+DI1_2_0_0_0_R0 gnd! I1_2_0_0_0_R0_NEG diode_dw2ps AREA=170p PJ=203.4e-6 m=1
+DI1_1_2_0_0_R0 gnd! I1_1_2_0_0_R0_NEG diode_dw2ps AREA=1.034n PJ=220.68e-6 m=1
+DI1_1_1_0_0_R0 gnd! I1_1_1_0_0_R0_NEG diode_dw2ps AREA=106.916p PJ=41.36e-6 m=1
+DI1_1_0_0_0_R0 gnd! I1_1_0_0_0_R0_NEG diode_dw2ps AREA=17.578p PJ=24.08e-6 m=1
+DI1_0_2_0_0_R0 gnd! I1_0_2_0_0_R0_NEG diode_dw2ps AREA=170p PJ=203.4e-6 m=1
+DI1_0_1_0_0_R0 gnd! I1_0_1_0_0_R0_NEG diode_dw2ps AREA=17.578p PJ=24.08e-6 m=1
+DI1_0_0_0_0_R0 gnd! I1_0_0_0_0_R0_NEG diode_dw2ps AREA=3.1535p PJ=7.11e-6 m=1
+DI1_default gnd! I1_default_NEG diode_dw2ps AREA=100e-12 PJ=40e-6 m=1
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8.cdl
new file mode 100644
index 0000000..0f81e63
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:16:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_01v8 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=1.32n PJ=226.4u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=110p PJ=202.2u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=36p PJ=200.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=1.32n PJ=226.4u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=4.752p PJ=27.12u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=110p PJ=202.2u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=1.21p PJ=4.4u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=396f PJ=2.92u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=36p PJ=200.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=4.752p PJ=27.12u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=396f PJ=2.92u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nd2ps_01v8 m=1 AREA=203.4f PJ=1.85u
+DI1_default vdd! I1_default_MINUS diode_nd2ps_01v8 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8_nvt.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8_nvt.cdl
new file mode 100644
index 0000000..ecaef2a
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_01v8_nvt.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_01v8_nvt
+* View Name: schematic
+* Netlisted on: Nov 24 09:16:13 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_01v8_nvt
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_01v8_nvt I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=1.32n PJ=226.4u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=110p PJ=202.2u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=36p PJ=200.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=1.32n PJ=226.4u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=4.752p PJ=27.12u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=110p PJ=202.2u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=1.21p PJ=4.4u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=396f PJ=2.92u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=36p PJ=200.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=4.752p PJ=27.12u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=396f PJ=2.92u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nd2ps_01v8_nvt m=1 AREA=203.4f PJ=1.85u
+DI1_default vdd! I1_default_MINUS diode_nd2ps_01v8_nvt m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_03v3.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_03v3.cdl
new file mode 100644
index 0000000..3a2721f
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_03v3.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_03v3
+* View Name: schematic
+* Netlisted on: Nov 24 09:18:14 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_03v3
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_03v3 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=1.32n PJ=226.4u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=110p PJ=202.2u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=36p PJ=200.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=1.32n PJ=226.4u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=4.752p PJ=27.12u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=110p PJ=202.2u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=1.21p PJ=4.4u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=396f PJ=2.92u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=36p PJ=200.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=4.752p PJ=27.12u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=396f PJ=2.92u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nd2ps_03v3 m=1 AREA=203.4f PJ=1.85u
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_03v3_nvt.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_03v3_nvt.cdl
new file mode 100644
index 0000000..49c3130
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nd2ps_03v3_nvt.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nd2ps_03v3_nvt
+* View Name: schematic
+* Netlisted on: Nov 24 09:18:14 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nd2ps_03v3_nvt
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nd2ps_03v3_nvt I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=1.32n PJ=226.4u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=110p PJ=202.2u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=36p PJ=200.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=1.32n PJ=226.4u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=174.24p PJ=52.8u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=14.52p PJ=28.6u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=4.752p PJ=27.12u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=110p PJ=202.2u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=14.52p PJ=28.6u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=1.21p PJ=4.4u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=396f PJ=2.92u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=36p PJ=200.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=4.752p PJ=27.12u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=396f PJ=2.92u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nd2ps_03v3_nvt m=1 AREA=203.4f PJ=1.85u
+DI1_default vdd! I1_default_MINUS diode_nd2ps_03v3_nvt m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8.cdl
deleted file mode 100644
index 4d94bbb..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8.cdl
+++ /dev/null
@@ -1,61 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: diode_np_1p8
-* View Name: schematic
-* Netlisted on: Nov 24 09:16:13 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-*.GLOBAL vdd!
-
-*.PIN vdd!
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: diode_np_1p8
-* View Name: schematic
-************************************************************************
-
-.SUBCKT diode_np_1p8 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
-+ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
-+ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
-+ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
-+ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
-+ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
-*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
-*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
-*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
-*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
-*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
-*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
-DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_np_1p8 m=1 AREA=10n PJ=400u
-DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_np_1p8 m=1 AREA=1.32n PJ=226.4u
-DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_np_1p8 m=1 AREA=110p PJ=202.2u
-DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_np_1p8 m=1 AREA=36p PJ=200.72u
-DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_np_1p8 m=1 AREA=1.32n PJ=226.4u
-DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_np_1p8 m=1 AREA=174.24p PJ=52.8u
-DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_np_1p8 m=1 AREA=14.52p PJ=28.6u
-DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_np_1p8 m=1 AREA=4.752p PJ=27.12u
-DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_np_1p8 m=1 AREA=110p PJ=202.2u
-DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_np_1p8 m=1 AREA=14.52p PJ=28.6u
-DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_np_1p8 m=1 AREA=1.21p PJ=4.4u
-DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_np_1p8 m=1 AREA=396f PJ=2.92u
-DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_np_1p8 m=1 AREA=36p PJ=200.72u
-DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_np_1p8 m=1 AREA=4.752p PJ=27.12u
-DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_np_1p8 m=1 AREA=396f PJ=2.92u
-DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_np_1p8 m=1 AREA=203.4f PJ=1.85u
-DI1_default vdd! I1_default_MINUS diode_np_1p8 m=1 AREA=1p PJ=4u
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8_nat.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8_nat.cdl
deleted file mode 100644
index 07c0cab..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_1p8_nat.cdl
+++ /dev/null
@@ -1,61 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: diode_np_1p8_nat
-* View Name: schematic
-* Netlisted on: Nov 24 09:16:13 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-*.GLOBAL vdd!
-
-*.PIN vdd!
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: diode_np_1p8_nat
-* View Name: schematic
-************************************************************************
-
-.SUBCKT diode_np_1p8_nat I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
-+ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
-+ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
-+ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
-+ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
-+ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
-*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
-*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
-*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
-*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
-*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
-*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
-DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=10n PJ=400u
-DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=1.32n PJ=226.4u
-DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=110p PJ=202.2u
-DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=36p PJ=200.72u
-DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=1.32n PJ=226.4u
-DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=174.24p PJ=52.8u
-DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=14.52p PJ=28.6u
-DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=4.752p PJ=27.12u
-DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=110p PJ=202.2u
-DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=14.52p PJ=28.6u
-DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=1.21p PJ=4.4u
-DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=396f PJ=2.92u
-DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=36p PJ=200.72u
-DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=4.752p PJ=27.12u
-DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=396f PJ=2.92u
-DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_np_1p8_nat m=1 AREA=203.4f PJ=1.85u
-DI1_default vdd! I1_default_MINUS diode_np_1p8_nat m=1 AREA=1p PJ=4u
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3.cdl
deleted file mode 100644
index 5714936..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3.cdl
+++ /dev/null
@@ -1,61 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: diode_np_3p3
-* View Name: schematic
-* Netlisted on: Nov 24 09:18:14 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-*.GLOBAL vdd!
-
-*.PIN vdd!
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: diode_np_3p3
-* View Name: schematic
-************************************************************************
-
-.SUBCKT diode_np_3p3 I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
-+ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
-+ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
-+ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
-+ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
-+ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
-*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
-*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
-*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
-*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
-*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
-*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
-DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_np_3p3 m=1 AREA=10n PJ=400u
-DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_np_3p3 m=1 AREA=1.32n PJ=226.4u
-DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_np_3p3 m=1 AREA=110p PJ=202.2u
-DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_np_3p3 m=1 AREA=36p PJ=200.72u
-DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_np_3p3 m=1 AREA=1.32n PJ=226.4u
-DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_np_3p3 m=1 AREA=174.24p PJ=52.8u
-DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_np_3p3 m=1 AREA=14.52p PJ=28.6u
-DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_np_3p3 m=1 AREA=4.752p PJ=27.12u
-DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_np_3p3 m=1 AREA=110p PJ=202.2u
-DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_np_3p3 m=1 AREA=14.52p PJ=28.6u
-DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_np_3p3 m=1 AREA=1.21p PJ=4.4u
-DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_np_3p3 m=1 AREA=396f PJ=2.92u
-DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_np_3p3 m=1 AREA=36p PJ=200.72u
-DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_np_3p3 m=1 AREA=4.752p PJ=27.12u
-DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_np_3p3 m=1 AREA=396f PJ=2.92u
-DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_np_3p3 m=1 AREA=203.4f PJ=1.85u
-DI1_default vdd! I1_default_MINUS diode_np_3p3 m=1 AREA=1p PJ=4u
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3_nat.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3_nat.cdl
deleted file mode 100644
index 568c3bb..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_np_3p3_nat.cdl
+++ /dev/null
@@ -1,61 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: diode_np_3p3_nat
-* View Name: schematic
-* Netlisted on: Nov 24 09:18:14 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-*.GLOBAL vdd!
-
-*.PIN vdd!
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: diode_np_3p3_nat
-* View Name: schematic
-************************************************************************
-
-.SUBCKT diode_np_3p3_nat I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
-+ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
-+ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
-+ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
-+ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
-+ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
-*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
-*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
-*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
-*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
-*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
-*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
-DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=10n PJ=400u
-DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=1.32n PJ=226.4u
-DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=110p PJ=202.2u
-DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=36p PJ=200.72u
-DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=1.32n PJ=226.4u
-DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=174.24p PJ=52.8u
-DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=14.52p PJ=28.6u
-DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=4.752p PJ=27.12u
-DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=110p PJ=202.2u
-DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=14.52p PJ=28.6u
-DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=1.21p PJ=4.4u
-DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=396f PJ=2.92u
-DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=36p PJ=200.72u
-DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=4.752p PJ=27.12u
-DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=396f PJ=2.92u
-DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_np_3p3_nat m=1 AREA=203.4f PJ=1.85u
-DI1_default vdd! I1_default_MINUS diode_np_3p3_nat m=1 AREA=1p PJ=4u
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nw2ps.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nw2ps.cdl
new file mode 100644
index 0000000..31f80ce
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nw2ps.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_nw2ps
+* View Name: schematic
+* Netlisted on: Nov 24 09:42:29 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+*.GLOBAL vdd!
+
+*.PIN vdd!
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_nw2ps
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_nw2ps I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
++ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
++ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
++ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
++ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
++ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
+DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nw2ps m=1 AREA=10n PJ=400u
+DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nw2ps m=1 AREA=1.21n PJ=224.2u
+DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nw2ps m=1 AREA=123p PJ=202.46u
+DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nw2ps m=1 AREA=86p PJ=201.72u
+DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nw2ps m=1 AREA=1.21n PJ=224.2u
+DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nw2ps m=1 AREA=146.41p PJ=48.4u
+DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nw2ps m=1 AREA=14.883p PJ=26.66u
+DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nw2ps m=1 AREA=10.406p PJ=25.92u
+DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nw2ps m=1 AREA=123p PJ=202.46u
+DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nw2ps m=1 AREA=14.883p PJ=26.66u
+DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nw2ps m=1 AREA=1.5129p PJ=4.92u
+DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nw2ps m=1 AREA=1.0578p PJ=4.18u
+DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nw2ps m=1 AREA=86p PJ=201.72u
+DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nw2ps m=1 AREA=10.406p PJ=25.92u
+DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nw2ps m=1 AREA=1.0578p PJ=4.18u
+DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nw2ps m=1 AREA=739.6f PJ=3.44u
+DI1_default vdd! I1_default_MINUS diode_nw2ps m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nwp.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nwp.cdl
deleted file mode 100644
index e68eada..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_nwp.cdl
+++ /dev/null
@@ -1,61 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: diode_nwp
-* View Name: schematic
-* Netlisted on: Nov 24 09:42:29 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-*.GLOBAL vdd!
-
-*.PIN vdd!
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: diode_nwp
-* View Name: schematic
-************************************************************************
-
-.SUBCKT diode_nwp I1_0_0_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS I1_0_2_0_0_R0_MINUS
-+ I1_0_3_0_0_R0_MINUS I1_1_0_0_0_R0_MINUS I1_1_1_0_0_R0_MINUS
-+ I1_1_2_0_0_R0_MINUS I1_1_3_0_0_R0_MINUS I1_2_0_0_0_R0_MINUS
-+ I1_2_1_0_0_R0_MINUS I1_2_2_0_0_R0_MINUS I1_2_3_0_0_R0_MINUS
-+ I1_3_0_0_0_R0_MINUS I1_3_1_0_0_R0_MINUS I1_3_2_0_0_R0_MINUS
-+ I1_3_3_0_0_R0_MINUS I1_default_MINUS vdd!
-*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_1_0_0_R0_MINUS:I I1_0_2_0_0_R0_MINUS:I
-*.PININFO I1_0_3_0_0_R0_MINUS:I I1_1_0_0_0_R0_MINUS:I I1_1_1_0_0_R0_MINUS:I
-*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_3_0_0_R0_MINUS:I I1_2_0_0_0_R0_MINUS:I
-*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_2_0_0_R0_MINUS:I I1_2_3_0_0_R0_MINUS:I
-*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_1_0_0_R0_MINUS:I I1_3_2_0_0_R0_MINUS:I
-*.PININFO I1_3_3_0_0_R0_MINUS:I I1_default_MINUS:I vdd!:I
-DI1_3_3_0_0_R0 vdd! I1_3_3_0_0_R0_MINUS diode_nwp m=1 AREA=10n PJ=400u
-DI1_3_2_0_0_R0 vdd! I1_3_2_0_0_R0_MINUS diode_nwp m=1 AREA=1.21n PJ=224.2u
-DI1_3_1_0_0_R0 vdd! I1_3_1_0_0_R0_MINUS diode_nwp m=1 AREA=123p PJ=202.46u
-DI1_3_0_0_0_R0 vdd! I1_3_0_0_0_R0_MINUS diode_nwp m=1 AREA=86p PJ=201.72u
-DI1_2_3_0_0_R0 vdd! I1_2_3_0_0_R0_MINUS diode_nwp m=1 AREA=1.21n PJ=224.2u
-DI1_2_2_0_0_R0 vdd! I1_2_2_0_0_R0_MINUS diode_nwp m=1 AREA=146.41p PJ=48.4u
-DI1_2_1_0_0_R0 vdd! I1_2_1_0_0_R0_MINUS diode_nwp m=1 AREA=14.883p PJ=26.66u
-DI1_2_0_0_0_R0 vdd! I1_2_0_0_0_R0_MINUS diode_nwp m=1 AREA=10.406p PJ=25.92u
-DI1_1_3_0_0_R0 vdd! I1_1_3_0_0_R0_MINUS diode_nwp m=1 AREA=123p PJ=202.46u
-DI1_1_2_0_0_R0 vdd! I1_1_2_0_0_R0_MINUS diode_nwp m=1 AREA=14.883p PJ=26.66u
-DI1_1_1_0_0_R0 vdd! I1_1_1_0_0_R0_MINUS diode_nwp m=1 AREA=1.5129p PJ=4.92u
-DI1_1_0_0_0_R0 vdd! I1_1_0_0_0_R0_MINUS diode_nwp m=1 AREA=1.0578p PJ=4.18u
-DI1_0_3_0_0_R0 vdd! I1_0_3_0_0_R0_MINUS diode_nwp m=1 AREA=86p PJ=201.72u
-DI1_0_2_0_0_R0 vdd! I1_0_2_0_0_R0_MINUS diode_nwp m=1 AREA=10.406p PJ=25.92u
-DI1_0_1_0_0_R0 vdd! I1_0_1_0_0_R0_MINUS diode_nwp m=1 AREA=1.0578p PJ=4.18u
-DI1_0_0_0_0_R0 vdd! I1_0_0_0_0_R0_MINUS diode_nwp m=1 AREA=739.6f PJ=3.44u
-DI1_default vdd! I1_default_MINUS diode_nwp m=1 AREA=1p PJ=4u
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8.cdl
new file mode 100644
index 0000000..8f87022
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_01v8.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pd2nw_01v8
+* View Name: schematic
+* Netlisted on: Nov 24 09:49:28 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pd2nw_01v8
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pd2nw_01v8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=36p
++ PJ=200.72u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=174.24p
++ PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=36p
++ PJ=200.72u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pd2nw_01v8 m=1 AREA=203.4f
++ PJ=1.85u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pd2nw_01v8 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_03v3.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_03v3.cdl
new file mode 100644
index 0000000..7a283fb
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pd2nw_03v3.cdl
@@ -0,0 +1,86 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: diode_pd2nw_03v3
+* View Name: schematic
+* Netlisted on: Nov 24 09:50:38 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: diode_pd2nw_03v3
+* View Name: schematic
+************************************************************************
+
+.SUBCKT diode_pd2nw_03v3 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
++ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
++ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
++ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
++ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
++ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
++ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
++ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
++ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
++ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
++ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
+*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
+*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
+*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
+*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
+*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
+*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
+*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
+*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
+*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
+*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
+*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
+*.PININFO I1_default_PLUS:I
+DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=10n
++ PJ=400u
+DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=110p
++ PJ=202.2u
+DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=36p
++ PJ=200.72u
+DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=1.32n
++ PJ=226.4u
+DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=174.24p
++ PJ=52.8u
+DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=110p
++ PJ=202.2u
+DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=14.52p
++ PJ=28.6u
+DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=1.21p
++ PJ=4.4u
+DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=36p
++ PJ=200.72u
+DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=4.752p
++ PJ=27.12u
+DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=396f
++ PJ=2.92u
+DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pd2nw_03v3 m=1 AREA=203.4f
++ PJ=1.85u
+DI1_default I1_default_PLUS I1_default_MINUS diode_pd2nw_03v3 m=1 AREA=1p PJ=4u
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_1p8.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_1p8.cdl
deleted file mode 100644
index f5087d7..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_1p8.cdl
+++ /dev/null
@@ -1,86 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: diode_pn_1p8
-* View Name: schematic
-* Netlisted on: Nov 24 09:49:28 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: diode_pn_1p8
-* View Name: schematic
-************************************************************************
-
-.SUBCKT diode_pn_1p8 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
-+ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
-+ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
-+ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
-+ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
-+ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
-+ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
-+ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
-+ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
-+ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
-+ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
-*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
-*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
-*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
-*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
-*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
-*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
-*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
-*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
-*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
-*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
-*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
-*.PININFO I1_default_PLUS:I
-DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=10n
-+ PJ=400u
-DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=1.32n
-+ PJ=226.4u
-DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=110p
-+ PJ=202.2u
-DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=36p
-+ PJ=200.72u
-DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=1.32n
-+ PJ=226.4u
-DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=174.24p
-+ PJ=52.8u
-DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=14.52p
-+ PJ=28.6u
-DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=4.752p
-+ PJ=27.12u
-DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=110p
-+ PJ=202.2u
-DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=14.52p
-+ PJ=28.6u
-DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=1.21p
-+ PJ=4.4u
-DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=396f
-+ PJ=2.92u
-DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=36p
-+ PJ=200.72u
-DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=4.752p
-+ PJ=27.12u
-DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=396f
-+ PJ=2.92u
-DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pn_1p8 m=1 AREA=203.4f
-+ PJ=1.85u
-DI1_default I1_default_PLUS I1_default_MINUS diode_pn_1p8 m=1 AREA=1p PJ=4u
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_3p3.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_3p3.cdl
deleted file mode 100644
index 2c9deae..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pn_3p3.cdl
+++ /dev/null
@@ -1,86 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: diode_pn_3p3
-* View Name: schematic
-* Netlisted on: Nov 24 09:50:38 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: diode_pn_3p3
-* View Name: schematic
-************************************************************************
-
-.SUBCKT diode_pn_3p3 I1_0_0_0_0_R0_MINUS I1_0_0_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS
-+ I1_0_1_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS I1_0_2_0_0_R0_PLUS
-+ I1_0_3_0_0_R0_MINUS I1_0_3_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS
-+ I1_1_0_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS I1_1_1_0_0_R0_PLUS
-+ I1_1_2_0_0_R0_MINUS I1_1_2_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS
-+ I1_1_3_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS I1_2_0_0_0_R0_PLUS
-+ I1_2_1_0_0_R0_MINUS I1_2_1_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS
-+ I1_2_2_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS I1_2_3_0_0_R0_PLUS
-+ I1_3_0_0_0_R0_MINUS I1_3_0_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS
-+ I1_3_1_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS I1_3_2_0_0_R0_PLUS
-+ I1_3_3_0_0_R0_MINUS I1_3_3_0_0_R0_PLUS I1_default_MINUS I1_default_PLUS
-*.PININFO I1_0_0_0_0_R0_MINUS:I I1_0_0_0_0_R0_PLUS:I I1_0_1_0_0_R0_MINUS:I
-*.PININFO I1_0_1_0_0_R0_PLUS:I I1_0_2_0_0_R0_MINUS:I I1_0_2_0_0_R0_PLUS:I
-*.PININFO I1_0_3_0_0_R0_MINUS:I I1_0_3_0_0_R0_PLUS:I I1_1_0_0_0_R0_MINUS:I
-*.PININFO I1_1_0_0_0_R0_PLUS:I I1_1_1_0_0_R0_MINUS:I I1_1_1_0_0_R0_PLUS:I
-*.PININFO I1_1_2_0_0_R0_MINUS:I I1_1_2_0_0_R0_PLUS:I I1_1_3_0_0_R0_MINUS:I
-*.PININFO I1_1_3_0_0_R0_PLUS:I I1_2_0_0_0_R0_MINUS:I I1_2_0_0_0_R0_PLUS:I
-*.PININFO I1_2_1_0_0_R0_MINUS:I I1_2_1_0_0_R0_PLUS:I I1_2_2_0_0_R0_MINUS:I
-*.PININFO I1_2_2_0_0_R0_PLUS:I I1_2_3_0_0_R0_MINUS:I I1_2_3_0_0_R0_PLUS:I
-*.PININFO I1_3_0_0_0_R0_MINUS:I I1_3_0_0_0_R0_PLUS:I I1_3_1_0_0_R0_MINUS:I
-*.PININFO I1_3_1_0_0_R0_PLUS:I I1_3_2_0_0_R0_MINUS:I I1_3_2_0_0_R0_PLUS:I
-*.PININFO I1_3_3_0_0_R0_MINUS:I I1_3_3_0_0_R0_PLUS:I I1_default_MINUS:I
-*.PININFO I1_default_PLUS:I
-DI1_3_3_0_0_R0 I1_3_3_0_0_R0_PLUS I1_3_3_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=10n
-+ PJ=400u
-DI1_3_2_0_0_R0 I1_3_2_0_0_R0_PLUS I1_3_2_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=1.32n
-+ PJ=226.4u
-DI1_3_1_0_0_R0 I1_3_1_0_0_R0_PLUS I1_3_1_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=110p
-+ PJ=202.2u
-DI1_3_0_0_0_R0 I1_3_0_0_0_R0_PLUS I1_3_0_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=36p
-+ PJ=200.72u
-DI1_2_3_0_0_R0 I1_2_3_0_0_R0_PLUS I1_2_3_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=1.32n
-+ PJ=226.4u
-DI1_2_2_0_0_R0 I1_2_2_0_0_R0_PLUS I1_2_2_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=174.24p
-+ PJ=52.8u
-DI1_2_1_0_0_R0 I1_2_1_0_0_R0_PLUS I1_2_1_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=14.52p
-+ PJ=28.6u
-DI1_2_0_0_0_R0 I1_2_0_0_0_R0_PLUS I1_2_0_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=4.752p
-+ PJ=27.12u
-DI1_1_3_0_0_R0 I1_1_3_0_0_R0_PLUS I1_1_3_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=110p
-+ PJ=202.2u
-DI1_1_2_0_0_R0 I1_1_2_0_0_R0_PLUS I1_1_2_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=14.52p
-+ PJ=28.6u
-DI1_1_1_0_0_R0 I1_1_1_0_0_R0_PLUS I1_1_1_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=1.21p
-+ PJ=4.4u
-DI1_1_0_0_0_R0 I1_1_0_0_0_R0_PLUS I1_1_0_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=396f
-+ PJ=2.92u
-DI1_0_3_0_0_R0 I1_0_3_0_0_R0_PLUS I1_0_3_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=36p
-+ PJ=200.72u
-DI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=4.752p
-+ PJ=27.12u
-DI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=396f
-+ PJ=2.92u
-DI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS diode_pn_3p3 m=1 AREA=203.4f
-+ PJ=1.85u
-DI1_default I1_default_PLUS I1_default_MINUS diode_pn_3p3 m=1 AREA=1p PJ=4u
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwpw.cdl b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pw2dw.cdl
similarity index 61%
copy from IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwpw.cdl
copy to IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pw2dw.cdl
index 4f085b6..3b58e57 100644
--- a/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_dnwpw.cdl
+++ b/IC/klayout/lvs/testing/testcases/unit/diode_devices/netlist/diode_pw2dw.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: diode_dnwpw
+* Top Cell Name: diode_pw2dw
* View Name: schematic
* Netlisted on: Nov 24 09:06:01 2021
************************************************************************
@@ -24,11 +24,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: diode_dnwpw
+* Cell Name: diode_pw2dw
* View Name: schematic
************************************************************************
-.SUBCKT diode_dnwpw I1_0_0_0_0_0_R0_POS I1_0_1_0_0_0_R0_POS I1_0_2_0_0_0_R0_POS
+.SUBCKT diode_pw2dw I1_0_0_0_0_0_R0_POS I1_0_1_0_0_0_R0_POS I1_0_2_0_0_0_R0_POS
+ I1_1_0_0_0_0_R0_POS I1_1_1_0_0_0_R0_POS I1_1_2_0_0_0_R0_POS
+ I1_2_0_0_0_0_R0_POS I1_2_1_0_0_0_R0_POS I1_2_2_0_0_0_R0_POS I1_default_POS
+ vdd!
@@ -36,15 +36,15 @@
*.PININFO I1_1_0_0_0_0_R0_POS:I I1_1_1_0_0_0_R0_POS:I I1_1_2_0_0_0_R0_POS:I
*.PININFO I1_2_0_0_0_0_R0_POS:I I1_2_1_0_0_0_R0_POS:I I1_2_2_0_0_0_R0_POS:I
*.PININFO I1_default_POS:I vdd!:I
-DI1_2_2_0_0_0_R0 I1_2_2_0_0_0_R0_POS vdd! diode_dnwpw AREA=10n PJ=400e-6 m=1
-DI1_2_1_0_0_0_R0 I1_2_1_0_0_0_R0_POS vdd! diode_dnwpw AREA=1.023n PJ=220.46e-6 m=1
-DI1_2_0_0_0_0_R0 I1_2_0_0_0_0_R0_POS vdd! diode_dnwpw AREA=60p PJ=201.2e-6 m=1
-DI1_1_2_0_0_0_R0 I1_1_2_0_0_0_R0_POS vdd! diode_dnwpw AREA=1.023n PJ=220.46e-6 m=1
-DI1_1_1_0_0_0_R0 I1_1_1_0_0_0_R0_POS vdd! diode_dnwpw AREA=104.653p PJ=40.92e-6 m=1
-DI1_1_0_0_0_0_R0 I1_1_0_0_0_0_R0_POS vdd! diode_dnwpw AREA=6.138p PJ=21.66e-6 m=1
-DI1_0_2_0_0_0_R0 I1_0_2_0_0_0_R0_POS vdd! diode_dnwpw AREA=60p PJ=201.2e-6 m=1
-DI1_0_1_0_0_0_R0 I1_0_1_0_0_0_R0_POS vdd! diode_dnwpw AREA=6.138p PJ=21.66e-6 m=1
-DI1_0_0_0_0_0_R0 I1_0_0_0_0_0_R0_POS vdd! diode_dnwpw AREA=627f PJ=3.29e-6 m=1
-DI1_default I1_default_POS vdd! diode_dnwpw AREA=100e-12 PJ=40e-6 m=1
+DI1_2_2_0_0_0_R0 I1_2_2_0_0_0_R0_POS vdd! diode_pw2dw AREA=10n PJ=400e-6 m=1
+DI1_2_1_0_0_0_R0 I1_2_1_0_0_0_R0_POS vdd! diode_pw2dw AREA=1.023n PJ=220.46e-6 m=1
+DI1_2_0_0_0_0_R0 I1_2_0_0_0_0_R0_POS vdd! diode_pw2dw AREA=60p PJ=201.2e-6 m=1
+DI1_1_2_0_0_0_R0 I1_1_2_0_0_0_R0_POS vdd! diode_pw2dw AREA=1.023n PJ=220.46e-6 m=1
+DI1_1_1_0_0_0_R0 I1_1_1_0_0_0_R0_POS vdd! diode_pw2dw AREA=104.653p PJ=40.92e-6 m=1
+DI1_1_0_0_0_0_R0 I1_1_0_0_0_0_R0_POS vdd! diode_pw2dw AREA=6.138p PJ=21.66e-6 m=1
+DI1_0_2_0_0_0_R0 I1_0_2_0_0_0_R0_POS vdd! diode_pw2dw AREA=60p PJ=201.2e-6 m=1
+DI1_0_1_0_0_0_R0 I1_0_1_0_0_0_R0_POS vdd! diode_pw2dw AREA=6.138p PJ=21.66e-6 m=1
+DI1_0_0_0_0_0_R0 I1_0_0_0_0_0_R0_POS vdd! diode_pw2dw AREA=627f PJ=3.29e-6 m=1
+DI1_default I1_default_POS vdd! diode_pw2dw AREA=100e-12 PJ=40e-6 m=1
.ENDS
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m3_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m3_noshield.gds
new file mode 100644
index 0000000..5b74d6e
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m3_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m3_noshield.yaml
similarity index 66%
rename from IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.yaml
rename to IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m3_noshield.yaml
index 8447ef4..da07c0f 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.yaml
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m3_noshield.yaml
@@ -1,4 +1,4 @@
-cap_mim_single_2f0_m2m3_noshield:
+cap_mim_2f0_m2m3_noshield:
-rd mim_option: "A"
-rd metal_level: "3LM"
-rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.gds
deleted file mode 100644
index 0b9ce22..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.yaml
deleted file mode 100644
index d6d92ba..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m2m4_noshield.yaml
+++ /dev/null
@@ -1,4 +0,0 @@
-cap_mim_2f0_m2m4_noshield:
- -rd mim_option: "B"
- -rd metal_level: "4LM"
- -rd mim_cap_stack: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m4_noshield.gds
similarity index 99%
rename from IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.gds
rename to IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m4_noshield.gds
index 0efcff6..db96077 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m4_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m4_noshield.yaml
similarity index 66%
rename from IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.yaml
rename to IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m4_noshield.yaml
index f98ba7a..d85e7a1 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m3m4_noshield.yaml
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m4_noshield.yaml
@@ -1,4 +1,4 @@
-cap_mim_single_2f0_m3m4_noshield:
+cap_mim_2f0_m3m4_noshield:
-rd mim_option: "B"
-rd metal_level: "4LM"
-rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.gds
deleted file mode 100644
index 183a4f5..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.yaml
deleted file mode 100644
index b16f754..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m3m5_noshield.yaml
+++ /dev/null
@@ -1,4 +0,0 @@
-cap_mim_2f0_m3m5_noshield:
- -rd mim_option: "B"
- -rd metal_level: "5LM"
- -rd mim_cap_stack: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m5_noshield.gds
similarity index 99%
rename from IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.gds
rename to IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m5_noshield.gds
index 1cde1f1..7246781 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m5_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m5_noshield.yaml
similarity index 66%
rename from IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.yaml
rename to IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m5_noshield.yaml
index 8f4830f..cb6ac9c 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m4m5_noshield.yaml
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m5_noshield.yaml
@@ -1,4 +1,4 @@
-cap_mim_single_2f0_m4m5_noshield:
+cap_mim_2f0_m4m5_noshield:
-rd mim_option: "B"
-rd metal_level: "5LM"
-rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.gds
deleted file mode 100644
index 94fb19d..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.yaml
deleted file mode 100644
index 7e1db3f..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m4m6_noshield.yaml
+++ /dev/null
@@ -1,4 +0,0 @@
-cap_mim_2f0_m4m6_noshield:
- -rd mim_option: "B"
- -rd metal_level: "6LM"
- -rd mim_cap_stack: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m5m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m5m6_noshield.gds
new file mode 100644
index 0000000..f4330c1
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m5m6_noshield.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m5m6_noshield.yaml
similarity index 66%
rename from IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.yaml
rename to IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m5m6_noshield.yaml
index a816f4a..0f3ab89 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.yaml
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_2f0_m5m6_noshield.yaml
@@ -1,4 +1,4 @@
-cap_mim_single_2f0_m5m6_noshield:
+cap_mim_2f0_m5m6_noshield:
-rd mim_option: "B"
-rd metal_level: "6LM"
-rd mim_cap: "2"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.gds
deleted file mode 100644
index 3e95cd6..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.yaml
deleted file mode 100644
index a347fd3..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m2m4_noshield.yaml
+++ /dev/null
@@ -1,4 +0,0 @@
-cap_mim_3f0_m2m4_noshield:
- -rd mim_option: "B"
- -rd metal_level: "4LM"
- -rd mim_cap_stack: "3"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.gds
deleted file mode 100644
index 913993f..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.yaml
deleted file mode 100644
index 9cd5c50..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m3m5_noshield.yaml
+++ /dev/null
@@ -1,4 +0,0 @@
-cap_mim_3f0_m3m5_noshield:
- -rd mim_option: "B"
- -rd metal_level: "5LM"
- -rd mim_cap_stack: "3"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.gds
deleted file mode 100644
index 6b8701a..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.yaml b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.yaml
deleted file mode 100644
index 1798498..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_3f0_m4m6_noshield.yaml
+++ /dev/null
@@ -1,4 +0,0 @@
-cap_mim_3f0_m4m6_noshield:
- -rd mim_option: "B"
- -rd metal_level: "6LM"
- -rd mim_cap_stack: "3"
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.gds
deleted file mode 100644
index 2499b86..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m2m3_noshield.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.gds b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.gds
deleted file mode 100644
index 1c81603..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/layout/cap_mim_single_2f0_m5m6_noshield.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m3_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m3_noshield.cdl
new file mode 100644
index 0000000..61880d4
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m3_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_2f0_m2m3_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 10:53:54 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_2f0_m2m3_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_2f0_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m2m3_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_2f0_m2m3_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_2f0_m2m3_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_2f0_m2m3_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m2m3_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_2f0_m2m3_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_2f0_m2m3_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_2f0_m2m3_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_2f0_m2m3_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_2f0_m2m3_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m4_noshield.cdl
deleted file mode 100644
index 888a326..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m2m4_noshield.cdl
+++ /dev/null
@@ -1,36 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: cap_mim_2f0_m2m4_noshield
-* View Name: schematic
-* Netlisted on: Nov 24 11:32:36 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: cap_mim_2f0_m2m4_noshield
-* View Name: schematic
-************************************************************************
-.SUBCKT cap_mim_2f0_m2m4_noshield
-
-CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m2m4_noshield M=1 l=100.000u
-+ w=100.000u c=2e-11
-
-CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m2m4_noshield M=1 l=100.000u
-+ w=100.000u c=2e-11
-
-.ENDS cap_mim_2f0_m2m4_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m4_noshield.cdl
new file mode 100644
index 0000000..02d889e
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m4_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_2f0_m3m4_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_2f0_m3m4_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_2f0_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m3m4_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_2f0_m3m4_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_2f0_m3m4_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_2f0_m3m4_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m3m4_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_2f0_m3m4_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_2f0_m3m4_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_2f0_m3m4_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_2f0_m3m4_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_2f0_m3m4_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m5_noshield.cdl
deleted file mode 100644
index 1350b61..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m3m5_noshield.cdl
+++ /dev/null
@@ -1,36 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: cap_mim_2f0_m3m5_noshield
-* View Name: schematic
-* Netlisted on: Nov 24 11:32:36 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: cap_mim_2f0_m3m5_noshield
-* View Name: schematic
-************************************************************************
-.SUBCKT cap_mim_2f0_m3m5_noshield
-
-CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m3m5_noshield M=1 l=100.000u
-+ w=100.000u c=2e-11
-
-CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m3m5_noshield M=1 l=100.000u
-+ w=100.000u c=2e-11
-
-.ENDS cap_mim_2f0_m3m5_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m5_noshield.cdl
new file mode 100644
index 0000000..ab3ffbf
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m5_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_2f0_m4m5_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_2f0_m4m5_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_2f0_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m4m5_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_2f0_m4m5_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_2f0_m4m5_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_2f0_m4m5_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m4m5_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_2f0_m4m5_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_2f0_m4m5_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_2f0_m4m5_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_2f0_m4m5_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_2f0_m4m5_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m6_noshield.cdl
deleted file mode 100644
index a19b204..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m4m6_noshield.cdl
+++ /dev/null
@@ -1,36 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: cap_mim_2f0_m4m6_noshield
-* View Name: schematic
-* Netlisted on: Nov 24 11:32:36 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: cap_mim_2f0_m4m6_noshield
-* View Name: schematic
-************************************************************************
-.SUBCKT cap_mim_2f0_m4m6_noshield
-
-CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m4m6_noshield M=1 l=100.000u
-+ w=100.000u c=2e-11
-
-CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m4m6_noshield M=1 l=100.000u
-+ w=100.000u c=2e-11
-
-.ENDS cap_mim_2f0_m4m6_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m5m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m5m6_noshield.cdl
new file mode 100644
index 0000000..7f4bc39
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_2f0_m5m6_noshield.cdl
@@ -0,0 +1,60 @@
+************************************************************************
+* auCdl Netlist:
+*
+* Library Name: TCG_Library
+* Top Cell Name: cap_mim_2f0_m5m6_noshield
+* View Name: schematic
+* Netlisted on: Nov 24 11:32:36 2021
+************************************************************************
+
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+
+
+
+************************************************************************
+* Library Name: TCG_Library
+* Cell Name: cap_mim_2f0_m5m6_noshield
+* View Name: schematic
+************************************************************************
+
+.SUBCKT cap_mim_2f0_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
++ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
++ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
++ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
++ I1_default_TOP
+*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
+*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
+*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
+*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
+*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
+CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_2f0_m5m6_noshield M=1 l=100.000u
++ w=100.000u c=19.99532p
+CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_2f0_m5m6_noshield M=1 l=100.000u
++ w=12.340u c=2.50920124p
+CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_2f0_m5m6_noshield M=1 l=100.000u
++ w=5.000u c=1.045043p
+CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_2f0_m5m6_noshield M=1 l=12.340u
++ w=100.000u c=2.50920124p
+CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_2f0_m5m6_noshield M=1 l=12.340u
++ w=12.340u c=0.31479093p
+CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_2f0_m5m6_noshield M=1 l=12.340u
++ w=5.000u c=0.13104724p
+CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_2f0_m5m6_noshield M=1 l=5.000u
++ w=100.000u c=1.045043p
+CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_2f0_m5m6_noshield M=1 l=5.000u
++ w=12.340u c=0.13104724p
+CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_2f0_m5m6_noshield M=1 l=5.000u
++ w=5.000u c=0.054516p
+CI1_default I1_default_TOP I1_default_BOT cap_mim_2f0_m5m6_noshield M=1 l=5u w=5u
++ c=0.054516p
+.ENDS
+
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m2m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m2m4_noshield.cdl
deleted file mode 100644
index 0ab1cdb..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m2m4_noshield.cdl
+++ /dev/null
@@ -1,36 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: cap_mim_3f0_m2m4_noshield
-* View Name: schematic
-* Netlisted on: Nov 24 11:32:36 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: cap_mim_3f0_m2m4_noshield
-* View Name: schematic
-************************************************************************
-.SUBCKT cap_mim_3f0_m2m4_noshield
-
-CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_3f0_m2m4_noshield M=1 l=100.000u
-+ w=100.000u c=3e-11
-
-CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_3f0_m2m4_noshield M=1 l=100.000u
-+ w=100.000u c=3e-11
-
-.ENDS cap_mim_3f0_m2m4_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m3m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m3m5_noshield.cdl
deleted file mode 100644
index 1a9f274..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m3m5_noshield.cdl
+++ /dev/null
@@ -1,36 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: cap_mim_3f0_m3m5_noshield
-* View Name: schematic
-* Netlisted on: Nov 24 11:32:36 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: cap_mim_3f0_m3m5_noshield
-* View Name: schematic
-************************************************************************
-.SUBCKT cap_mim_3f0_m3m5_noshield
-
-CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_3f0_m3m5_noshield M=1 l=100.000u
-+ w=100.000u c=3e-11
-
-CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_3f0_m3m5_noshield M=1 l=100.000u
-+ w=100.000u c=3e-11
-
-.ENDS cap_mim_3f0_m3m5_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m4m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m4m6_noshield.cdl
deleted file mode 100644
index aea33a7..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_3f0_m4m6_noshield.cdl
+++ /dev/null
@@ -1,36 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: cap_mim_3f0_m4m6_noshield
-* View Name: schematic
-* Netlisted on: Nov 24 11:32:36 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: cap_mim_3f0_m4m6_noshield
-* View Name: schematic
-************************************************************************
-.SUBCKT cap_mim_3f0_m4m6_noshield
-
-CI1_1 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_3f0_m4m6_noshield M=1 l=100.000u
-+ w=100.000u c=3e-11
-
-CI1_2 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_3f0_m4m6_noshield M=1 l=100.000u
-+ w=100.000u c=3e-11
-
-.ENDS cap_mim_3f0_m4m6_noshield
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m2m3_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m2m3_noshield.cdl
deleted file mode 100644
index 523b1ac..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m2m3_noshield.cdl
+++ /dev/null
@@ -1,60 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: cap_mim_single_2f0_m2m3_noshield
-* View Name: schematic
-* Netlisted on: Nov 24 10:53:54 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: cap_mim_single_2f0_m2m3_noshield
-* View Name: schematic
-************************************************************************
-
-.SUBCKT cap_mim_single_2f0_m2m3_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
-+ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
-+ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
-+ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
-+ I1_default_TOP
-*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
-*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
-*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
-*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
-*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
-CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=100.000u
-+ w=100.000u c=19.99532p
-CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=100.000u
-+ w=12.340u c=2.50920124p
-CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=100.000u
-+ w=5.000u c=1.045043p
-CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=12.340u
-+ w=100.000u c=2.50920124p
-CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=12.340u
-+ w=12.340u c=0.31479093p
-CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=12.340u
-+ w=5.000u c=0.13104724p
-CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5.000u
-+ w=100.000u c=1.045043p
-CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5.000u
-+ w=12.340u c=0.13104724p
-CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5.000u
-+ w=5.000u c=0.054516p
-CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m2m3_noshield M=1 l=5u w=5u
-+ c=0.054516p
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m3m4_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m3m4_noshield.cdl
deleted file mode 100644
index 4689f50..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m3m4_noshield.cdl
+++ /dev/null
@@ -1,60 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: cap_mim_single_2f0_m3m4_noshield
-* View Name: schematic
-* Netlisted on: Nov 24 11:32:36 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: cap_mim_single_2f0_m3m4_noshield
-* View Name: schematic
-************************************************************************
-
-.SUBCKT cap_mim_single_2f0_m3m4_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
-+ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
-+ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
-+ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
-+ I1_default_TOP
-*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
-*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
-*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
-*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
-*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
-CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=100.000u
-+ w=100.000u c=19.99532p
-CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=100.000u
-+ w=12.340u c=2.50920124p
-CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=100.000u
-+ w=5.000u c=1.045043p
-CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=12.340u
-+ w=100.000u c=2.50920124p
-CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=12.340u
-+ w=12.340u c=0.31479093p
-CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=12.340u
-+ w=5.000u c=0.13104724p
-CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5.000u
-+ w=100.000u c=1.045043p
-CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5.000u
-+ w=12.340u c=0.13104724p
-CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5.000u
-+ w=5.000u c=0.054516p
-CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m3m4_noshield M=1 l=5u w=5u
-+ c=0.054516p
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m4m5_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m4m5_noshield.cdl
deleted file mode 100644
index 30e708a..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m4m5_noshield.cdl
+++ /dev/null
@@ -1,60 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: cap_mim_single_2f0_m4m5_noshield
-* View Name: schematic
-* Netlisted on: Nov 24 11:32:36 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: cap_mim_single_2f0_m4m5_noshield
-* View Name: schematic
-************************************************************************
-
-.SUBCKT cap_mim_single_2f0_m4m5_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
-+ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
-+ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
-+ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
-+ I1_default_TOP
-*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
-*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
-*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
-*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
-*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
-CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=100.000u
-+ w=100.000u c=19.99532p
-CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=100.000u
-+ w=12.340u c=2.50920124p
-CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=100.000u
-+ w=5.000u c=1.045043p
-CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=12.340u
-+ w=100.000u c=2.50920124p
-CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=12.340u
-+ w=12.340u c=0.31479093p
-CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=12.340u
-+ w=5.000u c=0.13104724p
-CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5.000u
-+ w=100.000u c=1.045043p
-CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5.000u
-+ w=12.340u c=0.13104724p
-CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5.000u
-+ w=5.000u c=0.054516p
-CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m4m5_noshield M=1 l=5u w=5u
-+ c=0.054516p
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m5m6_noshield.cdl b/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m5m6_noshield.cdl
deleted file mode 100644
index a5d4e30..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mimcap_devices/netlist/cap_mim_single_2f0_m5m6_noshield.cdl
+++ /dev/null
@@ -1,60 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: cap_mim_single_2f0_m5m6_noshield
-* View Name: schematic
-* Netlisted on: Nov 24 11:32:36 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: cap_mim_single_2f0_m5m6_noshield
-* View Name: schematic
-************************************************************************
-
-.SUBCKT cap_mim_single_2f0_m5m6_noshield I1_0_0_R0_BOT I1_0_0_R0_TOP I1_0_1_R0_BOT I1_0_1_R0_TOP
-+ I1_0_2_R0_BOT I1_0_2_R0_TOP I1_1_0_R0_BOT I1_1_0_R0_TOP I1_1_1_R0_BOT
-+ I1_1_1_R0_TOP I1_1_2_R0_BOT I1_1_2_R0_TOP I1_2_0_R0_BOT I1_2_0_R0_TOP
-+ I1_2_1_R0_BOT I1_2_1_R0_TOP I1_2_2_R0_BOT I1_2_2_R0_TOP I1_default_BOT
-+ I1_default_TOP
-*.PININFO I1_0_0_R0_BOT:I I1_0_0_R0_TOP:I I1_0_1_R0_BOT:I I1_0_1_R0_TOP:I
-*.PININFO I1_0_2_R0_BOT:I I1_0_2_R0_TOP:I I1_1_0_R0_BOT:I I1_1_0_R0_TOP:I
-*.PININFO I1_1_1_R0_BOT:I I1_1_1_R0_TOP:I I1_1_2_R0_BOT:I I1_1_2_R0_TOP:I
-*.PININFO I1_2_0_R0_BOT:I I1_2_0_R0_TOP:I I1_2_1_R0_BOT:I I1_2_1_R0_TOP:I
-*.PININFO I1_2_2_R0_BOT:I I1_2_2_R0_TOP:I I1_default_BOT:I I1_default_TOP:I
-CI1_2_2_R0 I1_2_2_R0_TOP I1_2_2_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=100.000u
-+ w=100.000u c=19.99532p
-CI1_2_1_R0 I1_2_1_R0_TOP I1_2_1_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=100.000u
-+ w=12.340u c=2.50920124p
-CI1_2_0_R0 I1_2_0_R0_TOP I1_2_0_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=100.000u
-+ w=5.000u c=1.045043p
-CI1_1_2_R0 I1_1_2_R0_TOP I1_1_2_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=12.340u
-+ w=100.000u c=2.50920124p
-CI1_1_1_R0 I1_1_1_R0_TOP I1_1_1_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=12.340u
-+ w=12.340u c=0.31479093p
-CI1_1_0_R0 I1_1_0_R0_TOP I1_1_0_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=12.340u
-+ w=5.000u c=0.13104724p
-CI1_0_2_R0 I1_0_2_R0_TOP I1_0_2_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5.000u
-+ w=100.000u c=1.045043p
-CI1_0_1_R0 I1_0_1_R0_TOP I1_0_1_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5.000u
-+ w=12.340u c=0.13104724p
-CI1_0_0_R0 I1_0_0_R0_TOP I1_0_0_R0_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5.000u
-+ w=5.000u c=0.054516p
-CI1_default I1_default_TOP I1_default_BOT cap_mim_single_2f0_m5m6_noshield M=1 l=5u w=5u
-+ c=0.054516p
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_01v8.gds b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_01v8.gds
new file mode 100644
index 0000000..c38f9b5
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_01v8.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8_nat.gds b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_01v8_nvt.gds
similarity index 99%
copy from IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8_nat.gds
copy to IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_01v8_nvt.gds
index 615efc5..0bbe77c 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8_nat.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_01v8_nvt.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8_nat.gds b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_03v3.gds
similarity index 99%
copy from IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8_nat.gds
copy to IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_03v3.gds
index 615efc5..ab969d3 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8_nat.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_03v3.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8_nat.gds b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_03v3_nvt.gds
similarity index 99%
rename from IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8_nat.gds
rename to IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_03v3_nvt.gds
index 615efc5..df2ec63 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8_nat.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nfet_03v3_nvt.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8.gds b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8.gds
deleted file mode 100644
index dac9f90..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_1p8.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_3p3.gds b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_3p3.gds
deleted file mode 100644
index f187713..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_3p3.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_3p3_nat.gds b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_3p3_nat.gds
deleted file mode 100644
index 33f45cb..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/nmos_3p3_nat.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pmos_1p8.gds b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pfet_01v8.gds
similarity index 99%
rename from IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pmos_1p8.gds
rename to IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pfet_01v8.gds
index 7ae2fae..2e6e75f 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pmos_1p8.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pfet_01v8.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pmos_1p8.gds b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pfet_03v3.gds
similarity index 99%
copy from IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pmos_1p8.gds
copy to IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pfet_03v3.gds
index 7ae2fae..feb4167 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pmos_1p8.gds
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pfet_03v3.gds
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pmos_3p3.gds b/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pmos_3p3.gds
deleted file mode 100644
index 5595f54..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/layout/pmos_3p3.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_01v8.cdl
similarity index 91%
rename from IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl
rename to IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_01v8.cdl
index b444597..db340d2 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_01v8.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_library_2
-* Top Cell Name: nmos_1p8
+* Top Cell Name: nfet_01v8
* View Name: schematic
* Netlisted on: Sep 10 16:28:03 2021
************************************************************************
@@ -18,11 +18,11 @@
************************************************************************
* Library Name: TCG_library_2
-* Cell Name: nmos_1p8
+* Cell Name: nfet_01v8
* View Name: schematic
************************************************************************
-.SUBCKT nmos_1p8 I1_default_D I1_default_G I1_default_S
+.SUBCKT nfet_01v8 I1_default_D I1_default_G I1_default_S
+ I1_lin_default_bodytie_0_R0_D I1_lin_default_bodytie_0_R0_G
+ I1_lin_default_bodytie_0_R0_S I1_lin_default_bodytie_1_R0_D
+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S
@@ -326,422 +326,422 @@
*.PININFO I1_lin_default_tapCntRows_4_R0_S:I I1_lin_default_topTap_0_R0_D:I
*.PININFO I1_lin_default_topTap_0_R0_G:I I1_lin_default_topTap_0_R0_S:I vdd!:I
MI1_lin_default_fingerW_34_R0 I1_lin_default_fingerW_34_R0_D
-+ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S vdd! nfet_01v8
+ m=1 w=1e-3 l=280n nf=10 as=296e-12 ad=260e-12 ps=1.20592e-3 pd=1.0052e-3
+ nrd=0.000260 nrs=0.000296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_fingerW_33_R0 I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S vdd! nfet_01v8
+ m=1 w=90.24e-6 l=280n nf=1 as=39.7056e-12 ad=39.7056e-12 ps=181.36e-6
+ pd=181.36e-6 nrd=0.004876 nrs=0.004876 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_32_R0 I1_lin_default_fingerW_32_R0_D
-+ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S vdd! nfet_01v8
+ m=1 w=75.2e-6 l=280n nf=1 as=33.088e-12 ad=33.088e-12 ps=151.28e-6
+ pd=151.28e-6 nrd=0.005851 nrs=0.005851 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_31_R0 I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S vdd! nfet_01v8
+ m=1 w=62.665e-6 l=280n nf=1 as=27.5726e-12 ad=27.5726e-12 ps=126.21e-6
+ pd=126.21e-6 nrd=0.007021 nrs=0.007021 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_30_R0 I1_lin_default_fingerW_30_R0_D
-+ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S vdd! nfet_01v8
+ m=1 w=52.225e-6 l=280n nf=1 as=22.979e-12 ad=22.979e-12 ps=105.33e-6
+ pd=105.33e-6 nrd=0.008425 nrs=0.008425 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_29_R0 I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S vdd! nfet_01v8
+ m=1 w=43.52e-6 l=280n nf=1 as=19.1488e-12 ad=19.1488e-12 ps=87.92e-6
+ pd=87.92e-6 nrd=0.010110 nrs=0.010110 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_28_R0 I1_lin_default_fingerW_28_R0_D
-+ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S vdd! nfet_01v8
+ m=1 w=36.265e-6 l=280n nf=1 as=15.9566e-12 ad=15.9566e-12 ps=73.41e-6
+ pd=73.41e-6 nrd=0.012133 nrs=0.012133 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_27_R0 I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S vdd! nfet_01v8
+ m=1 w=30.22e-6 l=280n nf=1 as=13.2968e-12 ad=13.2968e-12 ps=61.32e-6
+ pd=61.32e-6 nrd=0.014560 nrs=0.014560 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_26_R0 I1_lin_default_fingerW_26_R0_D
-+ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S vdd! nfet_01v8
+ m=1 w=25.185e-6 l=280n nf=1 as=11.0814e-12 ad=11.0814e-12 ps=51.25e-6
+ pd=51.25e-6 nrd=0.017471 nrs=0.017471 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_25_R0 I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S vdd! nfet_01v8
+ m=1 w=20.985e-6 l=280n nf=1 as=9.2334e-12 ad=9.2334e-12 ps=42.85e-6
+ pd=42.85e-6 nrd=0.020967 nrs=0.020967 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_24_R0 I1_lin_default_fingerW_24_R0_D
-+ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S vdd! nfet_01v8
+ m=1 w=17.49e-6 l=280n nf=1 as=7.6956e-12 ad=7.6956e-12 ps=35.86e-6
+ pd=35.86e-6 nrd=0.025157 nrs=0.025157 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_23_R0 I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S vdd! nfet_01v8
+ m=1 w=14.575e-6 l=280n nf=1 as=6.413e-12 ad=6.413e-12 ps=30.03e-6
+ pd=30.03e-6 nrd=0.030189 nrs=0.030189 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_22_R0 I1_lin_default_fingerW_22_R0_D
-+ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S vdd! nfet_01v8
+ m=1 w=12.145e-6 l=280n nf=1 as=5.3438e-12 ad=5.3438e-12 ps=25.17e-6
+ pd=25.17e-6 nrd=0.036229 nrs=0.036229 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_21_R0 I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S vdd! nfet_01v8
+ m=1 w=10.12e-6 l=280n nf=1 as=4.4528e-12 ad=4.4528e-12 ps=21.12e-6
+ pd=21.12e-6 nrd=0.043478 nrs=0.043478 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_20_R0 I1_lin_default_fingerW_20_R0_D
-+ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S vdd! nfet_01v8
+ m=1 w=8.435e-6 l=280n nf=1 as=3.7114e-12 ad=3.7114e-12 ps=17.75e-6
+ pd=17.75e-6 nrd=0.052164 nrs=0.052164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_19_R0 I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S vdd! nfet_01v8
+ m=1 w=7.03e-6 l=280n nf=1 as=3.0932e-12 ad=3.0932e-12 ps=14.94e-6
+ pd=14.94e-6 nrd=0.062589 nrs=0.062589 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_18_R0 I1_lin_default_fingerW_18_R0_D
-+ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S vdd! nfet_01v8
+ m=1 w=5.855e-6 l=280n nf=1 as=2.5762e-12 ad=2.5762e-12 ps=12.59e-6
+ pd=12.59e-6 nrd=0.075149 nrs=0.075149 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_17_R0 I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S vdd! nfet_01v8
+ m=1 w=4.88e-6 l=280n nf=1 as=2.1472e-12 ad=2.1472e-12 ps=10.64e-6
+ pd=10.64e-6 nrd=0.090164 nrs=0.090164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_16_R0 I1_lin_default_fingerW_16_R0_D
-+ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S vdd! nfet_01v8
+ m=1 w=4.065e-6 l=280n nf=1 as=1.7886e-12 ad=1.7886e-12 ps=9.01e-6 pd=9.01e-6
+ nrd=0.108241 nrs=0.108241 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_15_R0 I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S vdd! nfet_01v8
+ m=1 w=3.39e-6 l=280n nf=1 as=1.4916e-12 ad=1.4916e-12 ps=7.66e-6 pd=7.66e-6
+ nrd=0.129794 nrs=0.129794 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_14_R0 I1_lin_default_fingerW_14_R0_D
-+ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S vdd! nfet_01v8
+ m=1 w=2.825e-6 l=280n nf=1 as=1.243e-12 ad=1.243e-12 ps=6.53e-6 pd=6.53e-6
+ nrd=0.155752 nrs=0.155752 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_13_R0 I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S vdd! nfet_01v8
+ m=1 w=2.355e-6 l=280n nf=1 as=1.0362e-12 ad=1.0362e-12 ps=5.59e-6 pd=5.59e-6
+ nrd=0.186837 nrs=0.186837 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_12_R0 I1_lin_default_fingerW_12_R0_D
-+ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S vdd! nfet_01v8
+ m=1 w=1.96e-6 l=280n nf=1 as=862.4e-15 ad=862.4e-15 ps=4.8e-6 pd=4.8e-6
+ nrd=0.224490 nrs=0.224490 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_11_R0 I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S vdd! nfet_01v8
+ m=1 w=1.635e-6 l=280n nf=1 as=719.4e-15 ad=719.4e-15 ps=4.15e-6 pd=4.15e-6
+ nrd=0.269113 nrs=0.269113 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_10_R0 I1_lin_default_fingerW_10_R0_D
-+ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S vdd! nfet_01v8
+ m=1 w=1.36e-6 l=280n nf=1 as=598.4e-15 ad=598.4e-15 ps=3.6e-6 pd=3.6e-6
+ nrd=0.323529 nrs=0.323529 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_9_R0 I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S vdd! nfet_01v8
+ m=1 w=1.135e-6 l=280n nf=1 as=499.4e-15 ad=499.4e-15 ps=3.15e-6 pd=3.15e-6
+ nrd=0.387665 nrs=0.387665 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_8_R0 I1_lin_default_fingerW_8_R0_D
-+ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S vdd! nfet_01v8
+ m=1 w=945e-9 l=280n nf=1 as=415.8e-15 ad=415.8e-15 ps=2.77e-6 pd=2.77e-6
+ nrd=0.465608 nrs=0.465608 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_7_R0 I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S vdd! nfet_01v8
+ m=1 w=790e-9 l=280n nf=1 as=347.6e-15 ad=347.6e-15 ps=2.46e-6 pd=2.46e-6
+ nrd=0.556962 nrs=0.556962 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_6_R0 I1_lin_default_fingerW_6_R0_D
-+ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S vdd! nfet_01v8
+ m=1 w=655e-9 l=280n nf=1 as=288.2e-15 ad=288.2e-15 ps=2.19e-6 pd=2.19e-6
+ nrd=0.671756 nrs=0.671756 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_5_R0 I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S vdd! nfet_01v8
+ m=1 w=545e-9 l=280n nf=1 as=239.8e-15 ad=239.8e-15 ps=1.97e-6 pd=1.97e-6
+ nrd=0.807339 nrs=0.807339 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_4_R0 I1_lin_default_fingerW_4_R0_D
-+ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S vdd! nfet_01v8
+ m=1 w=455e-9 l=280n nf=1 as=200.2e-15 ad=200.2e-15 ps=1.79e-6 pd=1.79e-6
+ nrd=0.967033 nrs=0.967033 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_3_R0 I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S vdd! nfet_01v8
+ m=1 w=380e-9 l=280n nf=1 as=167.2e-15 ad=167.2e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.157895 nrs=1.157895 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_2_R0 I1_lin_default_fingerW_2_R0_D
-+ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S vdd! nfet_01v8
+ m=1 w=315e-9 l=280n nf=1 as=161.1e-15 ad=161.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.623583 nrs=1.623583 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_1_R0 I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S vdd! nfet_01v8
+ m=1 w=265e-9 l=280n nf=1 as=156.1e-15 ad=156.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=2.222855 nrs=2.222855 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_0_R0 I1_lin_default_fingerW_0_R0_D
-+ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S vdd! nfet_01v8
+ m=1 w=220e-9 l=280n nf=1 as=151.6e-15 ad=151.6e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=3.132231 nrs=3.132231 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_l_29_R0 I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G
-+ I1_lin_default_l_29_R0_S vdd! nmos_1p8 m=1 w=1.8e-6 l=50.000u nf=5
++ I1_lin_default_l_29_R0_S vdd! nfet_01v8 m=1 w=1.8e-6 l=50.000u nf=5
+ as=532.8e-15 ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_l_28_R0 I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G
-+ I1_lin_default_l_28_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=46.155u nf=1
++ I1_lin_default_l_28_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=46.155u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_27_R0 I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G
-+ I1_lin_default_l_27_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=38.465u nf=1
++ I1_lin_default_l_27_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=38.465u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_26_R0 I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G
-+ I1_lin_default_l_26_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=32.055u nf=1
++ I1_lin_default_l_26_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=32.055u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_25_R0 I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G
-+ I1_lin_default_l_25_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=26.710u nf=1
++ I1_lin_default_l_25_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=26.710u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_24_R0 I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G
-+ I1_lin_default_l_24_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=22.260u nf=1
++ I1_lin_default_l_24_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=22.260u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_23_R0 I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G
-+ I1_lin_default_l_23_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=18.550u nf=1
++ I1_lin_default_l_23_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=18.550u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_22_R0 I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G
-+ I1_lin_default_l_22_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=15.460u nf=1
++ I1_lin_default_l_22_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=15.460u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_21_R0 I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G
-+ I1_lin_default_l_21_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=12.880u nf=1
++ I1_lin_default_l_21_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=12.880u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_20_R0 I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G
-+ I1_lin_default_l_20_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=10.735u nf=1
++ I1_lin_default_l_20_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=10.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_19_R0 I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G
-+ I1_lin_default_l_19_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=8.945u nf=1
++ I1_lin_default_l_19_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=8.945u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_18_R0 I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G
-+ I1_lin_default_l_18_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=7.455u nf=1
++ I1_lin_default_l_18_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=7.455u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_17_R0 I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G
-+ I1_lin_default_l_17_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=6.210u nf=1
++ I1_lin_default_l_17_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=6.210u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_16_R0 I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G
-+ I1_lin_default_l_16_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=5.175u nf=1
++ I1_lin_default_l_16_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=5.175u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_15_R0 I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G
-+ I1_lin_default_l_15_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=4.315u nf=1
++ I1_lin_default_l_15_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=4.315u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_14_R0 I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G
-+ I1_lin_default_l_14_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=3.595u nf=1
++ I1_lin_default_l_14_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=3.595u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_13_R0 I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G
-+ I1_lin_default_l_13_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.995u nf=1
++ I1_lin_default_l_13_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=2.995u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_12_R0 I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G
-+ I1_lin_default_l_12_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.495u nf=1
++ I1_lin_default_l_12_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=2.495u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_11_R0 I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G
-+ I1_lin_default_l_11_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.080u nf=1
++ I1_lin_default_l_11_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=2.080u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_10_R0 I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G
-+ I1_lin_default_l_10_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.735u nf=1
++ I1_lin_default_l_10_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=1.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_9_R0 I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G
-+ I1_lin_default_l_9_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.445u nf=1
++ I1_lin_default_l_9_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=1.445u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_8_R0 I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G
-+ I1_lin_default_l_8_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.205u nf=1
++ I1_lin_default_l_8_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=1.205u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_7_R0 I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G
-+ I1_lin_default_l_7_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.005u nf=1
++ I1_lin_default_l_7_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=1.005u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_6_R0 I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G
-+ I1_lin_default_l_6_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.835u nf=1
++ I1_lin_default_l_6_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=0.835u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_5_R0 I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G
-+ I1_lin_default_l_5_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.695u nf=1
++ I1_lin_default_l_5_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=0.695u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_4_R0 I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G
-+ I1_lin_default_l_4_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.580u nf=1
++ I1_lin_default_l_4_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=0.580u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_3_R0 I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G
-+ I1_lin_default_l_3_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.485u nf=1
++ I1_lin_default_l_3_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=0.485u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_2_R0 I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G
-+ I1_lin_default_l_2_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.405u nf=1
++ I1_lin_default_l_2_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=0.405u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_1_R0 I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G
-+ I1_lin_default_l_1_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.335u nf=1
++ I1_lin_default_l_1_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=0.335u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_0_R0 I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G
-+ I1_lin_default_l_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.280u nf=1
++ I1_lin_default_l_0_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=0.280u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_nf_2_R0 I1_lin_default_nf_2_R0_D I1_lin_default_nf_2_R0_G
-+ I1_lin_default_nf_2_R0_S vdd! nmos_1p8 m=1 w=36e-6 l=280n nf=100
++ I1_lin_default_nf_2_R0_S vdd! nfet_01v8 m=1 w=36e-6 l=280n nf=100
+ as=9.4896e-12 ad=9.36e-12 ps=89.44e-6 pd=88e-6 nrd=0.007222 nrs=0.007322
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_1_R0 I1_lin_default_nf_1_R0_D I1_lin_default_nf_1_R0_G
-+ I1_lin_default_nf_1_R0_S vdd! nmos_1p8 m=1 w=18.36e-6 l=280n nf=51
++ I1_lin_default_nf_1_R0_S vdd! nfet_01v8 m=1 w=18.36e-6 l=280n nf=51
+ as=4.8384e-12 ad=4.8384e-12 ps=45.6e-6 pd=45.6e-6 nrd=0.014353 nrs=0.014353
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_0_R0 I1_lin_default_nf_0_R0_D I1_lin_default_nf_0_R0_G
-+ I1_lin_default_nf_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_nf_0_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_m_2_R0 I1_lin_default_m_2_R0_D I1_lin_default_m_2_R0_G
-+ I1_lin_default_m_2_R0_S vdd! nmos_1p8 m=100 w=360e-9 l=280n nf=1
++ I1_lin_default_m_2_R0_S vdd! nfet_01v8 m=100 w=360e-9 l=280n nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=100
MI1_lin_default_m_1_R0 I1_lin_default_m_1_R0_D I1_lin_default_m_1_R0_G
-+ I1_lin_default_m_1_R0_S vdd! nmos_1p8 m=51 w=1.8e-6 l=280n nf=5 as=532.8e-15
++ I1_lin_default_m_1_R0_S vdd! nfet_01v8 m=51 w=1.8e-6 l=280n nf=5 as=532.8e-15
+ ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444 sa=0.440u
+ sb=0.440u sd=0.520u dtemp=0 par=51
MI1_lin_default_m_0_R0 I1_lin_default_m_0_R0_D I1_lin_default_m_0_R0_G
-+ I1_lin_default_m_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_m_0_R0_S vdd! nfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_2_R0 I1_lin_default_calculatedParam_2_R0_D
+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ vdd! nmos_1p8 m=1 w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6
++ vdd! nfet_01v8 m=1 w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6
+ pd=1.76e-6 nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_calculatedParam_1_R0 I1_lin_default_calculatedParam_1_R0_D
+ I1_lin_default_calculatedParam_1_R0_G I1_lin_default_calculatedParam_1_R0_S
-+ vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ vdd! nfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_0_R0 I1_lin_default_calculatedParam_0_R0_D
+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ vdd! nfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_2_R0 I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S vdd! nfet_01v8
+ m=1 w=16.08e-6 l=280n nf=3 as=5.1456e-12 ad=5.1456e-12 ps=23.36e-6
+ pd=23.36e-6 nrd=0.019900 nrs=0.019900 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_gateConn_1_R0 I1_lin_default_gateConn_1_R0_D
-+ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_0_R0 I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_9_R0 I1_lin_default_sdWidth_9_R0_D
-+ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S vdd! nfet_01v8
+ m=1 w=26.8e-6 l=280n nf=5 as=20.3144e-12 ad=20.3144e-12 ps=39.74e-6
+ pd=39.74e-6 nrd=0.028284 nrs=0.028284 sa=1.210u sb=1.210u sd=1.290u dtemp=0
+ par=1
MI1_lin_default_sdWidth_8_R0 I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=432e-15 ad=432e-15 ps=3.12e-6 pd=3.12e-6
+ nrd=3.333333 nrs=3.333333 sa=1.200u sb=1.200u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_7_R0 I1_lin_default_sdWidth_7_R0_D
-+ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=372.6e-15 ad=372.6e-15 ps=2.79e-6 pd=2.79e-6
+ nrd=2.875000 nrs=2.875000 sa=1.035u sb=1.035u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_6_R0 I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=322.2e-15 ad=322.2e-15 ps=2.51e-6 pd=2.51e-6
+ nrd=2.486111 nrs=2.486111 sa=0.895u sb=0.895u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_5_R0 I1_lin_default_sdWidth_5_R0_D
-+ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=280.8e-15 ad=280.8e-15 ps=2.28e-6 pd=2.28e-6
+ nrd=2.166667 nrs=2.166667 sa=0.780u sb=0.780u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_4_R0 I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=246.6e-15 ad=246.6e-15 ps=2.09e-6 pd=2.09e-6
+ nrd=1.902778 nrs=1.902778 sa=0.685u sb=0.685u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_3_R0 I1_lin_default_sdWidth_3_R0_D
-+ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=217.8e-15 ad=217.8e-15 ps=1.93e-6 pd=1.93e-6
+ nrd=1.680556 nrs=1.680556 sa=0.605u sb=0.605u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_2_R0 I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=194.4e-15 ad=194.4e-15 ps=1.8e-6 pd=1.8e-6
+ nrd=1.500000 nrs=1.500000 sa=0.540u sb=0.540u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_1_R0 I1_lin_default_sdWidth_1_R0_D
-+ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=174.6e-15 ad=174.6e-15 ps=1.69e-6 pd=1.69e-6
+ nrd=1.347222 nrs=1.347222 sa=0.485u sb=0.485u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_0_R0 I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sFirst_0_R0 I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S vdd! nfet_01v8 m=1
+ w=16.8e-6 l=280n nf=5 as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6
+ nrd=0.017619 nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_2_R0 I1_lin_default_sdConn_2_R0_D
-+ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S vdd! nfet_01v8 m=1
+ w=13.6e-6 l=280n nf=10 as=4.0256e-12 ad=3.536e-12 ps=22.24e-6 pd=18.8e-6
+ nrd=0.019118 nrs=0.021765 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_1_R0 I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S vdd! nfet_01v8 m=1
+ w=1.08e-6 l=280n nf=3 as=345.6e-15 ad=345.6e-15 ps=3.36e-6 pd=3.36e-6
+ nrd=0.296296 nrs=0.296296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_0_R0 I1_lin_default_sdConn_0_R0_D
-+ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S vdd! nfet_01v8 m=1
+ w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6 pd=1.76e-6
+ nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_bodytie_1_R0 I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S vdd! nmos_1p8
++ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bodytie_0_R0 I1_lin_default_bodytie_0_R0_D
-+ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S vdd! nmos_1p8
++ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_leftTap_0_R0 I1_lin_default_leftTap_0_R0_D
-+ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S vdd! nmos_1p8
++ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_rightTap_0_R0 I1_lin_default_rightTap_0_R0_D
-+ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S vdd! nmos_1p8
++ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S vdd! nfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_topTap_0_R0 I1_lin_default_topTap_0_R0_D
-+ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S vdd! nfet_01v8 m=1
+ w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bottomTap_0_R0 I1_lin_default_bottomTap_0_R0_D
+ I1_lin_default_bottomTap_0_R0_G I1_lin_default_bottomTap_0_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_4_R0 I1_lin_default_tapCntRows_4_R0_D
+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S vdd!
-+ nmos_1p8 m=1 w=25.08e-6 l=280n nf=3 as=8.0256e-12 ad=8.0256e-12 ps=35.36e-6
++ nfet_01v8 m=1 w=25.08e-6 l=280n nf=3 as=8.0256e-12 ad=8.0256e-12 ps=35.36e-6
+ pd=35.36e-6 nrd=0.012759 nrs=0.012759 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_tapCntRows_3_R0 I1_lin_default_tapCntRows_3_R0_D
+ I1_lin_default_tapCntRows_3_R0_G I1_lin_default_tapCntRows_3_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_2_R0 I1_lin_default_tapCntRows_2_R0_D
+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_1_R0 I1_lin_default_tapCntRows_1_R0_D
+ I1_lin_default_tapCntRows_1_R0_G I1_lin_default_tapCntRows_1_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_0_R0 I1_lin_default_tapCntRows_0_R0_D
+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_default I1_default_D I1_default_G I1_default_S vdd! nmos_1p8 m=1 w=360e-9
+MI1_default I1_default_D I1_default_G I1_default_S vdd! nfet_01v8 m=1 w=360e-9
+ l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222
+ nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
.ENDS
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_01v8_nvt.cdl
similarity index 90%
copy from IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl
copy to IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_01v8_nvt.cdl
index b444597..6cff9ce 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_01v8_nvt.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_library_2
-* Top Cell Name: nmos_1p8
+* Top Cell Name: nfet_01v8_nvt
* View Name: schematic
* Netlisted on: Sep 10 16:28:03 2021
************************************************************************
@@ -18,11 +18,11 @@
************************************************************************
* Library Name: TCG_library_2
-* Cell Name: nmos_1p8
+* Cell Name: nfet_01v8_nvt
* View Name: schematic
************************************************************************
-.SUBCKT nmos_1p8 I1_default_D I1_default_G I1_default_S
+.SUBCKT nfet_01v8_nvt I1_default_D I1_default_G I1_default_S
+ I1_lin_default_bodytie_0_R0_D I1_lin_default_bodytie_0_R0_G
+ I1_lin_default_bodytie_0_R0_S I1_lin_default_bodytie_1_R0_D
+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S
@@ -326,422 +326,422 @@
*.PININFO I1_lin_default_tapCntRows_4_R0_S:I I1_lin_default_topTap_0_R0_D:I
*.PININFO I1_lin_default_topTap_0_R0_G:I I1_lin_default_topTap_0_R0_S:I vdd!:I
MI1_lin_default_fingerW_34_R0 I1_lin_default_fingerW_34_R0_D
-+ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S vdd! nfet_01v8_nvt
+ m=1 w=1e-3 l=280n nf=10 as=296e-12 ad=260e-12 ps=1.20592e-3 pd=1.0052e-3
+ nrd=0.000260 nrs=0.000296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_fingerW_33_R0 I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S vdd! nfet_01v8_nvt
+ m=1 w=90.24e-6 l=280n nf=1 as=39.7056e-12 ad=39.7056e-12 ps=181.36e-6
+ pd=181.36e-6 nrd=0.004876 nrs=0.004876 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_32_R0 I1_lin_default_fingerW_32_R0_D
-+ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S vdd! nfet_01v8_nvt
+ m=1 w=75.2e-6 l=280n nf=1 as=33.088e-12 ad=33.088e-12 ps=151.28e-6
+ pd=151.28e-6 nrd=0.005851 nrs=0.005851 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_31_R0 I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S vdd! nfet_01v8_nvt
+ m=1 w=62.665e-6 l=280n nf=1 as=27.5726e-12 ad=27.5726e-12 ps=126.21e-6
+ pd=126.21e-6 nrd=0.007021 nrs=0.007021 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_30_R0 I1_lin_default_fingerW_30_R0_D
-+ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S vdd! nfet_01v8_nvt
+ m=1 w=52.225e-6 l=280n nf=1 as=22.979e-12 ad=22.979e-12 ps=105.33e-6
+ pd=105.33e-6 nrd=0.008425 nrs=0.008425 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_29_R0 I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S vdd! nfet_01v8_nvt
+ m=1 w=43.52e-6 l=280n nf=1 as=19.1488e-12 ad=19.1488e-12 ps=87.92e-6
+ pd=87.92e-6 nrd=0.010110 nrs=0.010110 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_28_R0 I1_lin_default_fingerW_28_R0_D
-+ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S vdd! nfet_01v8_nvt
+ m=1 w=36.265e-6 l=280n nf=1 as=15.9566e-12 ad=15.9566e-12 ps=73.41e-6
+ pd=73.41e-6 nrd=0.012133 nrs=0.012133 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_27_R0 I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S vdd! nfet_01v8_nvt
+ m=1 w=30.22e-6 l=280n nf=1 as=13.2968e-12 ad=13.2968e-12 ps=61.32e-6
+ pd=61.32e-6 nrd=0.014560 nrs=0.014560 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_26_R0 I1_lin_default_fingerW_26_R0_D
-+ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S vdd! nfet_01v8_nvt
+ m=1 w=25.185e-6 l=280n nf=1 as=11.0814e-12 ad=11.0814e-12 ps=51.25e-6
+ pd=51.25e-6 nrd=0.017471 nrs=0.017471 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_25_R0 I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S vdd! nfet_01v8_nvt
+ m=1 w=20.985e-6 l=280n nf=1 as=9.2334e-12 ad=9.2334e-12 ps=42.85e-6
+ pd=42.85e-6 nrd=0.020967 nrs=0.020967 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_24_R0 I1_lin_default_fingerW_24_R0_D
-+ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S vdd! nfet_01v8_nvt
+ m=1 w=17.49e-6 l=280n nf=1 as=7.6956e-12 ad=7.6956e-12 ps=35.86e-6
+ pd=35.86e-6 nrd=0.025157 nrs=0.025157 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_23_R0 I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S vdd! nfet_01v8_nvt
+ m=1 w=14.575e-6 l=280n nf=1 as=6.413e-12 ad=6.413e-12 ps=30.03e-6
+ pd=30.03e-6 nrd=0.030189 nrs=0.030189 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_22_R0 I1_lin_default_fingerW_22_R0_D
-+ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S vdd! nfet_01v8_nvt
+ m=1 w=12.145e-6 l=280n nf=1 as=5.3438e-12 ad=5.3438e-12 ps=25.17e-6
+ pd=25.17e-6 nrd=0.036229 nrs=0.036229 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_21_R0 I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S vdd! nfet_01v8_nvt
+ m=1 w=10.12e-6 l=280n nf=1 as=4.4528e-12 ad=4.4528e-12 ps=21.12e-6
+ pd=21.12e-6 nrd=0.043478 nrs=0.043478 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_20_R0 I1_lin_default_fingerW_20_R0_D
-+ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S vdd! nfet_01v8_nvt
+ m=1 w=8.435e-6 l=280n nf=1 as=3.7114e-12 ad=3.7114e-12 ps=17.75e-6
+ pd=17.75e-6 nrd=0.052164 nrs=0.052164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_19_R0 I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S vdd! nfet_01v8_nvt
+ m=1 w=7.03e-6 l=280n nf=1 as=3.0932e-12 ad=3.0932e-12 ps=14.94e-6
+ pd=14.94e-6 nrd=0.062589 nrs=0.062589 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_18_R0 I1_lin_default_fingerW_18_R0_D
-+ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S vdd! nfet_01v8_nvt
+ m=1 w=5.855e-6 l=280n nf=1 as=2.5762e-12 ad=2.5762e-12 ps=12.59e-6
+ pd=12.59e-6 nrd=0.075149 nrs=0.075149 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_17_R0 I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S vdd! nfet_01v8_nvt
+ m=1 w=4.88e-6 l=280n nf=1 as=2.1472e-12 ad=2.1472e-12 ps=10.64e-6
+ pd=10.64e-6 nrd=0.090164 nrs=0.090164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_16_R0 I1_lin_default_fingerW_16_R0_D
-+ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S vdd! nfet_01v8_nvt
+ m=1 w=4.065e-6 l=280n nf=1 as=1.7886e-12 ad=1.7886e-12 ps=9.01e-6 pd=9.01e-6
+ nrd=0.108241 nrs=0.108241 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_15_R0 I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S vdd! nfet_01v8_nvt
+ m=1 w=3.39e-6 l=280n nf=1 as=1.4916e-12 ad=1.4916e-12 ps=7.66e-6 pd=7.66e-6
+ nrd=0.129794 nrs=0.129794 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_14_R0 I1_lin_default_fingerW_14_R0_D
-+ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S vdd! nfet_01v8_nvt
+ m=1 w=2.825e-6 l=280n nf=1 as=1.243e-12 ad=1.243e-12 ps=6.53e-6 pd=6.53e-6
+ nrd=0.155752 nrs=0.155752 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_13_R0 I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S vdd! nfet_01v8_nvt
+ m=1 w=2.355e-6 l=280n nf=1 as=1.0362e-12 ad=1.0362e-12 ps=5.59e-6 pd=5.59e-6
+ nrd=0.186837 nrs=0.186837 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_12_R0 I1_lin_default_fingerW_12_R0_D
-+ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S vdd! nfet_01v8_nvt
+ m=1 w=1.96e-6 l=280n nf=1 as=862.4e-15 ad=862.4e-15 ps=4.8e-6 pd=4.8e-6
+ nrd=0.224490 nrs=0.224490 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_11_R0 I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S vdd! nfet_01v8_nvt
+ m=1 w=1.635e-6 l=280n nf=1 as=719.4e-15 ad=719.4e-15 ps=4.15e-6 pd=4.15e-6
+ nrd=0.269113 nrs=0.269113 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_10_R0 I1_lin_default_fingerW_10_R0_D
-+ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S vdd! nfet_01v8_nvt
+ m=1 w=1.36e-6 l=280n nf=1 as=598.4e-15 ad=598.4e-15 ps=3.6e-6 pd=3.6e-6
+ nrd=0.323529 nrs=0.323529 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_9_R0 I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S vdd! nfet_01v8_nvt
+ m=1 w=1.135e-6 l=280n nf=1 as=499.4e-15 ad=499.4e-15 ps=3.15e-6 pd=3.15e-6
+ nrd=0.387665 nrs=0.387665 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_8_R0 I1_lin_default_fingerW_8_R0_D
-+ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S vdd! nfet_01v8_nvt
+ m=1 w=945e-9 l=280n nf=1 as=415.8e-15 ad=415.8e-15 ps=2.77e-6 pd=2.77e-6
+ nrd=0.465608 nrs=0.465608 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_7_R0 I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S vdd! nfet_01v8_nvt
+ m=1 w=790e-9 l=280n nf=1 as=347.6e-15 ad=347.6e-15 ps=2.46e-6 pd=2.46e-6
+ nrd=0.556962 nrs=0.556962 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_6_R0 I1_lin_default_fingerW_6_R0_D
-+ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S vdd! nfet_01v8_nvt
+ m=1 w=655e-9 l=280n nf=1 as=288.2e-15 ad=288.2e-15 ps=2.19e-6 pd=2.19e-6
+ nrd=0.671756 nrs=0.671756 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_5_R0 I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S vdd! nfet_01v8_nvt
+ m=1 w=545e-9 l=280n nf=1 as=239.8e-15 ad=239.8e-15 ps=1.97e-6 pd=1.97e-6
+ nrd=0.807339 nrs=0.807339 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_4_R0 I1_lin_default_fingerW_4_R0_D
-+ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S vdd! nfet_01v8_nvt
+ m=1 w=455e-9 l=280n nf=1 as=200.2e-15 ad=200.2e-15 ps=1.79e-6 pd=1.79e-6
+ nrd=0.967033 nrs=0.967033 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_3_R0 I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S vdd! nfet_01v8_nvt
+ m=1 w=380e-9 l=280n nf=1 as=167.2e-15 ad=167.2e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.157895 nrs=1.157895 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_2_R0 I1_lin_default_fingerW_2_R0_D
-+ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S vdd! nfet_01v8_nvt
+ m=1 w=315e-9 l=280n nf=1 as=161.1e-15 ad=161.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.623583 nrs=1.623583 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_1_R0 I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S vdd! nfet_01v8_nvt
+ m=1 w=265e-9 l=280n nf=1 as=156.1e-15 ad=156.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=2.222855 nrs=2.222855 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_0_R0 I1_lin_default_fingerW_0_R0_D
-+ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S vdd! nfet_01v8_nvt
+ m=1 w=220e-9 l=280n nf=1 as=151.6e-15 ad=151.6e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=3.132231 nrs=3.132231 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_l_29_R0 I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G
-+ I1_lin_default_l_29_R0_S vdd! nmos_1p8 m=1 w=1.8e-6 l=50.000u nf=5
++ I1_lin_default_l_29_R0_S vdd! nfet_01v8_nvt m=1 w=1.8e-6 l=50.000u nf=5
+ as=532.8e-15 ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_l_28_R0 I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G
-+ I1_lin_default_l_28_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=46.155u nf=1
++ I1_lin_default_l_28_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=46.155u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_27_R0 I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G
-+ I1_lin_default_l_27_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=38.465u nf=1
++ I1_lin_default_l_27_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=38.465u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_26_R0 I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G
-+ I1_lin_default_l_26_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=32.055u nf=1
++ I1_lin_default_l_26_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=32.055u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_25_R0 I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G
-+ I1_lin_default_l_25_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=26.710u nf=1
++ I1_lin_default_l_25_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=26.710u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_24_R0 I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G
-+ I1_lin_default_l_24_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=22.260u nf=1
++ I1_lin_default_l_24_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=22.260u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_23_R0 I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G
-+ I1_lin_default_l_23_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=18.550u nf=1
++ I1_lin_default_l_23_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=18.550u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_22_R0 I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G
-+ I1_lin_default_l_22_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=15.460u nf=1
++ I1_lin_default_l_22_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=15.460u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_21_R0 I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G
-+ I1_lin_default_l_21_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=12.880u nf=1
++ I1_lin_default_l_21_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=12.880u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_20_R0 I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G
-+ I1_lin_default_l_20_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=10.735u nf=1
++ I1_lin_default_l_20_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=10.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_19_R0 I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G
-+ I1_lin_default_l_19_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=8.945u nf=1
++ I1_lin_default_l_19_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=8.945u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_18_R0 I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G
-+ I1_lin_default_l_18_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=7.455u nf=1
++ I1_lin_default_l_18_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=7.455u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_17_R0 I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G
-+ I1_lin_default_l_17_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=6.210u nf=1
++ I1_lin_default_l_17_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=6.210u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_16_R0 I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G
-+ I1_lin_default_l_16_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=5.175u nf=1
++ I1_lin_default_l_16_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=5.175u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_15_R0 I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G
-+ I1_lin_default_l_15_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=4.315u nf=1
++ I1_lin_default_l_15_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=4.315u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_14_R0 I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G
-+ I1_lin_default_l_14_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=3.595u nf=1
++ I1_lin_default_l_14_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=3.595u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_13_R0 I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G
-+ I1_lin_default_l_13_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.995u nf=1
++ I1_lin_default_l_13_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=2.995u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_12_R0 I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G
-+ I1_lin_default_l_12_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.495u nf=1
++ I1_lin_default_l_12_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=2.495u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_11_R0 I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G
-+ I1_lin_default_l_11_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.080u nf=1
++ I1_lin_default_l_11_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=2.080u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_10_R0 I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G
-+ I1_lin_default_l_10_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.735u nf=1
++ I1_lin_default_l_10_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=1.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_9_R0 I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G
-+ I1_lin_default_l_9_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.445u nf=1
++ I1_lin_default_l_9_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=1.445u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_8_R0 I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G
-+ I1_lin_default_l_8_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.205u nf=1
++ I1_lin_default_l_8_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=1.205u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_7_R0 I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G
-+ I1_lin_default_l_7_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.005u nf=1
++ I1_lin_default_l_7_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=1.005u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_6_R0 I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G
-+ I1_lin_default_l_6_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.835u nf=1
++ I1_lin_default_l_6_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=0.835u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_5_R0 I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G
-+ I1_lin_default_l_5_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.695u nf=1
++ I1_lin_default_l_5_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=0.695u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_4_R0 I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G
-+ I1_lin_default_l_4_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.580u nf=1
++ I1_lin_default_l_4_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=0.580u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_3_R0 I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G
-+ I1_lin_default_l_3_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.485u nf=1
++ I1_lin_default_l_3_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=0.485u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_2_R0 I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G
-+ I1_lin_default_l_2_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.405u nf=1
++ I1_lin_default_l_2_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=0.405u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_1_R0 I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G
-+ I1_lin_default_l_1_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.335u nf=1
++ I1_lin_default_l_1_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=0.335u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_0_R0 I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G
-+ I1_lin_default_l_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.280u nf=1
++ I1_lin_default_l_0_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=0.280u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_nf_2_R0 I1_lin_default_nf_2_R0_D I1_lin_default_nf_2_R0_G
-+ I1_lin_default_nf_2_R0_S vdd! nmos_1p8 m=1 w=36e-6 l=280n nf=100
++ I1_lin_default_nf_2_R0_S vdd! nfet_01v8_nvt m=1 w=36e-6 l=280n nf=100
+ as=9.4896e-12 ad=9.36e-12 ps=89.44e-6 pd=88e-6 nrd=0.007222 nrs=0.007322
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_1_R0 I1_lin_default_nf_1_R0_D I1_lin_default_nf_1_R0_G
-+ I1_lin_default_nf_1_R0_S vdd! nmos_1p8 m=1 w=18.36e-6 l=280n nf=51
++ I1_lin_default_nf_1_R0_S vdd! nfet_01v8_nvt m=1 w=18.36e-6 l=280n nf=51
+ as=4.8384e-12 ad=4.8384e-12 ps=45.6e-6 pd=45.6e-6 nrd=0.014353 nrs=0.014353
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_0_R0 I1_lin_default_nf_0_R0_D I1_lin_default_nf_0_R0_G
-+ I1_lin_default_nf_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_nf_0_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_m_2_R0 I1_lin_default_m_2_R0_D I1_lin_default_m_2_R0_G
-+ I1_lin_default_m_2_R0_S vdd! nmos_1p8 m=100 w=360e-9 l=280n nf=1
++ I1_lin_default_m_2_R0_S vdd! nfet_01v8_nvt m=100 w=360e-9 l=280n nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=100
MI1_lin_default_m_1_R0 I1_lin_default_m_1_R0_D I1_lin_default_m_1_R0_G
-+ I1_lin_default_m_1_R0_S vdd! nmos_1p8 m=51 w=1.8e-6 l=280n nf=5 as=532.8e-15
++ I1_lin_default_m_1_R0_S vdd! nfet_01v8_nvt m=51 w=1.8e-6 l=280n nf=5 as=532.8e-15
+ ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444 sa=0.440u
+ sb=0.440u sd=0.520u dtemp=0 par=51
MI1_lin_default_m_0_R0 I1_lin_default_m_0_R0_D I1_lin_default_m_0_R0_G
-+ I1_lin_default_m_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_m_0_R0_S vdd! nfet_01v8_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_2_R0 I1_lin_default_calculatedParam_2_R0_D
+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ vdd! nmos_1p8 m=1 w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6
++ vdd! nfet_01v8_nvt m=1 w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6
+ pd=1.76e-6 nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_calculatedParam_1_R0 I1_lin_default_calculatedParam_1_R0_D
+ I1_lin_default_calculatedParam_1_R0_G I1_lin_default_calculatedParam_1_R0_S
-+ vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ vdd! nfet_01v8_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_0_R0 I1_lin_default_calculatedParam_0_R0_D
+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ vdd! nfet_01v8_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_2_R0 I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S vdd! nfet_01v8_nvt
+ m=1 w=16.08e-6 l=280n nf=3 as=5.1456e-12 ad=5.1456e-12 ps=23.36e-6
+ pd=23.36e-6 nrd=0.019900 nrs=0.019900 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_gateConn_1_R0 I1_lin_default_gateConn_1_R0_D
-+ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_0_R0 I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_9_R0 I1_lin_default_sdWidth_9_R0_D
-+ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S vdd! nfet_01v8_nvt
+ m=1 w=26.8e-6 l=280n nf=5 as=20.3144e-12 ad=20.3144e-12 ps=39.74e-6
+ pd=39.74e-6 nrd=0.028284 nrs=0.028284 sa=1.210u sb=1.210u sd=1.290u dtemp=0
+ par=1
MI1_lin_default_sdWidth_8_R0 I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=432e-15 ad=432e-15 ps=3.12e-6 pd=3.12e-6
+ nrd=3.333333 nrs=3.333333 sa=1.200u sb=1.200u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_7_R0 I1_lin_default_sdWidth_7_R0_D
-+ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=372.6e-15 ad=372.6e-15 ps=2.79e-6 pd=2.79e-6
+ nrd=2.875000 nrs=2.875000 sa=1.035u sb=1.035u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_6_R0 I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=322.2e-15 ad=322.2e-15 ps=2.51e-6 pd=2.51e-6
+ nrd=2.486111 nrs=2.486111 sa=0.895u sb=0.895u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_5_R0 I1_lin_default_sdWidth_5_R0_D
-+ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=280.8e-15 ad=280.8e-15 ps=2.28e-6 pd=2.28e-6
+ nrd=2.166667 nrs=2.166667 sa=0.780u sb=0.780u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_4_R0 I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=246.6e-15 ad=246.6e-15 ps=2.09e-6 pd=2.09e-6
+ nrd=1.902778 nrs=1.902778 sa=0.685u sb=0.685u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_3_R0 I1_lin_default_sdWidth_3_R0_D
-+ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=217.8e-15 ad=217.8e-15 ps=1.93e-6 pd=1.93e-6
+ nrd=1.680556 nrs=1.680556 sa=0.605u sb=0.605u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_2_R0 I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=194.4e-15 ad=194.4e-15 ps=1.8e-6 pd=1.8e-6
+ nrd=1.500000 nrs=1.500000 sa=0.540u sb=0.540u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_1_R0 I1_lin_default_sdWidth_1_R0_D
-+ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=174.6e-15 ad=174.6e-15 ps=1.69e-6 pd=1.69e-6
+ nrd=1.347222 nrs=1.347222 sa=0.485u sb=0.485u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_0_R0 I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sFirst_0_R0 I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S vdd! nfet_01v8_nvt m=1
+ w=16.8e-6 l=280n nf=5 as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6
+ nrd=0.017619 nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_2_R0 I1_lin_default_sdConn_2_R0_D
-+ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S vdd! nfet_01v8_nvt m=1
+ w=13.6e-6 l=280n nf=10 as=4.0256e-12 ad=3.536e-12 ps=22.24e-6 pd=18.8e-6
+ nrd=0.019118 nrs=0.021765 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_1_R0 I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S vdd! nfet_01v8_nvt m=1
+ w=1.08e-6 l=280n nf=3 as=345.6e-15 ad=345.6e-15 ps=3.36e-6 pd=3.36e-6
+ nrd=0.296296 nrs=0.296296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_0_R0 I1_lin_default_sdConn_0_R0_D
-+ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S vdd! nfet_01v8_nvt m=1
+ w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6 pd=1.76e-6
+ nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_bodytie_1_R0 I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S vdd! nmos_1p8
++ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bodytie_0_R0 I1_lin_default_bodytie_0_R0_D
-+ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S vdd! nmos_1p8
++ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_leftTap_0_R0 I1_lin_default_leftTap_0_R0_D
-+ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S vdd! nmos_1p8
++ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_rightTap_0_R0 I1_lin_default_rightTap_0_R0_D
-+ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S vdd! nmos_1p8
++ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S vdd! nfet_01v8_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_topTap_0_R0 I1_lin_default_topTap_0_R0_D
-+ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S vdd! nfet_01v8_nvt m=1
+ w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bottomTap_0_R0 I1_lin_default_bottomTap_0_R0_D
+ I1_lin_default_bottomTap_0_R0_G I1_lin_default_bottomTap_0_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_01v8_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_4_R0 I1_lin_default_tapCntRows_4_R0_D
+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S vdd!
-+ nmos_1p8 m=1 w=25.08e-6 l=280n nf=3 as=8.0256e-12 ad=8.0256e-12 ps=35.36e-6
++ nfet_01v8_nvt m=1 w=25.08e-6 l=280n nf=3 as=8.0256e-12 ad=8.0256e-12 ps=35.36e-6
+ pd=35.36e-6 nrd=0.012759 nrs=0.012759 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_tapCntRows_3_R0 I1_lin_default_tapCntRows_3_R0_D
+ I1_lin_default_tapCntRows_3_R0_G I1_lin_default_tapCntRows_3_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_01v8_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_2_R0 I1_lin_default_tapCntRows_2_R0_D
+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_01v8_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_1_R0 I1_lin_default_tapCntRows_1_R0_D
+ I1_lin_default_tapCntRows_1_R0_G I1_lin_default_tapCntRows_1_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_01v8_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_0_R0 I1_lin_default_tapCntRows_0_R0_D
+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_01v8_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_default I1_default_D I1_default_G I1_default_S vdd! nmos_1p8 m=1 w=360e-9
+MI1_default I1_default_D I1_default_G I1_default_S vdd! nfet_01v8_nvt m=1 w=360e-9
+ l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222
+ nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
.ENDS
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_03v3.cdl
similarity index 91%
copy from IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl
copy to IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_03v3.cdl
index b444597..746a272 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_03v3.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_library_2
-* Top Cell Name: nmos_1p8
+* Top Cell Name: nfet_03v3
* View Name: schematic
* Netlisted on: Sep 10 16:28:03 2021
************************************************************************
@@ -18,11 +18,11 @@
************************************************************************
* Library Name: TCG_library_2
-* Cell Name: nmos_1p8
+* Cell Name: nfet_03v3
* View Name: schematic
************************************************************************
-.SUBCKT nmos_1p8 I1_default_D I1_default_G I1_default_S
+.SUBCKT nfet_03v3 I1_default_D I1_default_G I1_default_S
+ I1_lin_default_bodytie_0_R0_D I1_lin_default_bodytie_0_R0_G
+ I1_lin_default_bodytie_0_R0_S I1_lin_default_bodytie_1_R0_D
+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S
@@ -326,422 +326,422 @@
*.PININFO I1_lin_default_tapCntRows_4_R0_S:I I1_lin_default_topTap_0_R0_D:I
*.PININFO I1_lin_default_topTap_0_R0_G:I I1_lin_default_topTap_0_R0_S:I vdd!:I
MI1_lin_default_fingerW_34_R0 I1_lin_default_fingerW_34_R0_D
-+ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S vdd! nfet_03v3
+ m=1 w=1e-3 l=280n nf=10 as=296e-12 ad=260e-12 ps=1.20592e-3 pd=1.0052e-3
+ nrd=0.000260 nrs=0.000296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_fingerW_33_R0 I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S vdd! nfet_03v3
+ m=1 w=90.24e-6 l=280n nf=1 as=39.7056e-12 ad=39.7056e-12 ps=181.36e-6
+ pd=181.36e-6 nrd=0.004876 nrs=0.004876 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_32_R0 I1_lin_default_fingerW_32_R0_D
-+ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S vdd! nfet_03v3
+ m=1 w=75.2e-6 l=280n nf=1 as=33.088e-12 ad=33.088e-12 ps=151.28e-6
+ pd=151.28e-6 nrd=0.005851 nrs=0.005851 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_31_R0 I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S vdd! nfet_03v3
+ m=1 w=62.665e-6 l=280n nf=1 as=27.5726e-12 ad=27.5726e-12 ps=126.21e-6
+ pd=126.21e-6 nrd=0.007021 nrs=0.007021 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_30_R0 I1_lin_default_fingerW_30_R0_D
-+ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S vdd! nfet_03v3
+ m=1 w=52.225e-6 l=280n nf=1 as=22.979e-12 ad=22.979e-12 ps=105.33e-6
+ pd=105.33e-6 nrd=0.008425 nrs=0.008425 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_29_R0 I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S vdd! nfet_03v3
+ m=1 w=43.52e-6 l=280n nf=1 as=19.1488e-12 ad=19.1488e-12 ps=87.92e-6
+ pd=87.92e-6 nrd=0.010110 nrs=0.010110 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_28_R0 I1_lin_default_fingerW_28_R0_D
-+ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S vdd! nfet_03v3
+ m=1 w=36.265e-6 l=280n nf=1 as=15.9566e-12 ad=15.9566e-12 ps=73.41e-6
+ pd=73.41e-6 nrd=0.012133 nrs=0.012133 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_27_R0 I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S vdd! nfet_03v3
+ m=1 w=30.22e-6 l=280n nf=1 as=13.2968e-12 ad=13.2968e-12 ps=61.32e-6
+ pd=61.32e-6 nrd=0.014560 nrs=0.014560 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_26_R0 I1_lin_default_fingerW_26_R0_D
-+ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S vdd! nfet_03v3
+ m=1 w=25.185e-6 l=280n nf=1 as=11.0814e-12 ad=11.0814e-12 ps=51.25e-6
+ pd=51.25e-6 nrd=0.017471 nrs=0.017471 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_25_R0 I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S vdd! nfet_03v3
+ m=1 w=20.985e-6 l=280n nf=1 as=9.2334e-12 ad=9.2334e-12 ps=42.85e-6
+ pd=42.85e-6 nrd=0.020967 nrs=0.020967 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_24_R0 I1_lin_default_fingerW_24_R0_D
-+ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S vdd! nfet_03v3
+ m=1 w=17.49e-6 l=280n nf=1 as=7.6956e-12 ad=7.6956e-12 ps=35.86e-6
+ pd=35.86e-6 nrd=0.025157 nrs=0.025157 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_23_R0 I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S vdd! nfet_03v3
+ m=1 w=14.575e-6 l=280n nf=1 as=6.413e-12 ad=6.413e-12 ps=30.03e-6
+ pd=30.03e-6 nrd=0.030189 nrs=0.030189 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_22_R0 I1_lin_default_fingerW_22_R0_D
-+ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S vdd! nfet_03v3
+ m=1 w=12.145e-6 l=280n nf=1 as=5.3438e-12 ad=5.3438e-12 ps=25.17e-6
+ pd=25.17e-6 nrd=0.036229 nrs=0.036229 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_21_R0 I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S vdd! nfet_03v3
+ m=1 w=10.12e-6 l=280n nf=1 as=4.4528e-12 ad=4.4528e-12 ps=21.12e-6
+ pd=21.12e-6 nrd=0.043478 nrs=0.043478 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_20_R0 I1_lin_default_fingerW_20_R0_D
-+ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S vdd! nfet_03v3
+ m=1 w=8.435e-6 l=280n nf=1 as=3.7114e-12 ad=3.7114e-12 ps=17.75e-6
+ pd=17.75e-6 nrd=0.052164 nrs=0.052164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_19_R0 I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S vdd! nfet_03v3
+ m=1 w=7.03e-6 l=280n nf=1 as=3.0932e-12 ad=3.0932e-12 ps=14.94e-6
+ pd=14.94e-6 nrd=0.062589 nrs=0.062589 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_18_R0 I1_lin_default_fingerW_18_R0_D
-+ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S vdd! nfet_03v3
+ m=1 w=5.855e-6 l=280n nf=1 as=2.5762e-12 ad=2.5762e-12 ps=12.59e-6
+ pd=12.59e-6 nrd=0.075149 nrs=0.075149 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_17_R0 I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S vdd! nfet_03v3
+ m=1 w=4.88e-6 l=280n nf=1 as=2.1472e-12 ad=2.1472e-12 ps=10.64e-6
+ pd=10.64e-6 nrd=0.090164 nrs=0.090164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_16_R0 I1_lin_default_fingerW_16_R0_D
-+ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S vdd! nfet_03v3
+ m=1 w=4.065e-6 l=280n nf=1 as=1.7886e-12 ad=1.7886e-12 ps=9.01e-6 pd=9.01e-6
+ nrd=0.108241 nrs=0.108241 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_15_R0 I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S vdd! nfet_03v3
+ m=1 w=3.39e-6 l=280n nf=1 as=1.4916e-12 ad=1.4916e-12 ps=7.66e-6 pd=7.66e-6
+ nrd=0.129794 nrs=0.129794 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_14_R0 I1_lin_default_fingerW_14_R0_D
-+ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S vdd! nfet_03v3
+ m=1 w=2.825e-6 l=280n nf=1 as=1.243e-12 ad=1.243e-12 ps=6.53e-6 pd=6.53e-6
+ nrd=0.155752 nrs=0.155752 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_13_R0 I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S vdd! nfet_03v3
+ m=1 w=2.355e-6 l=280n nf=1 as=1.0362e-12 ad=1.0362e-12 ps=5.59e-6 pd=5.59e-6
+ nrd=0.186837 nrs=0.186837 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_12_R0 I1_lin_default_fingerW_12_R0_D
-+ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S vdd! nfet_03v3
+ m=1 w=1.96e-6 l=280n nf=1 as=862.4e-15 ad=862.4e-15 ps=4.8e-6 pd=4.8e-6
+ nrd=0.224490 nrs=0.224490 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_11_R0 I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S vdd! nfet_03v3
+ m=1 w=1.635e-6 l=280n nf=1 as=719.4e-15 ad=719.4e-15 ps=4.15e-6 pd=4.15e-6
+ nrd=0.269113 nrs=0.269113 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_10_R0 I1_lin_default_fingerW_10_R0_D
-+ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S vdd! nfet_03v3
+ m=1 w=1.36e-6 l=280n nf=1 as=598.4e-15 ad=598.4e-15 ps=3.6e-6 pd=3.6e-6
+ nrd=0.323529 nrs=0.323529 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_9_R0 I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S vdd! nfet_03v3
+ m=1 w=1.135e-6 l=280n nf=1 as=499.4e-15 ad=499.4e-15 ps=3.15e-6 pd=3.15e-6
+ nrd=0.387665 nrs=0.387665 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_8_R0 I1_lin_default_fingerW_8_R0_D
-+ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S vdd! nfet_03v3
+ m=1 w=945e-9 l=280n nf=1 as=415.8e-15 ad=415.8e-15 ps=2.77e-6 pd=2.77e-6
+ nrd=0.465608 nrs=0.465608 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_7_R0 I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S vdd! nfet_03v3
+ m=1 w=790e-9 l=280n nf=1 as=347.6e-15 ad=347.6e-15 ps=2.46e-6 pd=2.46e-6
+ nrd=0.556962 nrs=0.556962 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_6_R0 I1_lin_default_fingerW_6_R0_D
-+ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S vdd! nfet_03v3
+ m=1 w=655e-9 l=280n nf=1 as=288.2e-15 ad=288.2e-15 ps=2.19e-6 pd=2.19e-6
+ nrd=0.671756 nrs=0.671756 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_5_R0 I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S vdd! nfet_03v3
+ m=1 w=545e-9 l=280n nf=1 as=239.8e-15 ad=239.8e-15 ps=1.97e-6 pd=1.97e-6
+ nrd=0.807339 nrs=0.807339 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_4_R0 I1_lin_default_fingerW_4_R0_D
-+ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S vdd! nfet_03v3
+ m=1 w=455e-9 l=280n nf=1 as=200.2e-15 ad=200.2e-15 ps=1.79e-6 pd=1.79e-6
+ nrd=0.967033 nrs=0.967033 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_3_R0 I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S vdd! nfet_03v3
+ m=1 w=380e-9 l=280n nf=1 as=167.2e-15 ad=167.2e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.157895 nrs=1.157895 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_2_R0 I1_lin_default_fingerW_2_R0_D
-+ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S vdd! nfet_03v3
+ m=1 w=315e-9 l=280n nf=1 as=161.1e-15 ad=161.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.623583 nrs=1.623583 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_1_R0 I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S vdd! nfet_03v3
+ m=1 w=265e-9 l=280n nf=1 as=156.1e-15 ad=156.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=2.222855 nrs=2.222855 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_0_R0 I1_lin_default_fingerW_0_R0_D
-+ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S vdd! nfet_03v3
+ m=1 w=220e-9 l=280n nf=1 as=151.6e-15 ad=151.6e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=3.132231 nrs=3.132231 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_l_29_R0 I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G
-+ I1_lin_default_l_29_R0_S vdd! nmos_1p8 m=1 w=1.8e-6 l=50.000u nf=5
++ I1_lin_default_l_29_R0_S vdd! nfet_03v3 m=1 w=1.8e-6 l=50.000u nf=5
+ as=532.8e-15 ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_l_28_R0 I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G
-+ I1_lin_default_l_28_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=46.155u nf=1
++ I1_lin_default_l_28_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=46.155u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_27_R0 I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G
-+ I1_lin_default_l_27_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=38.465u nf=1
++ I1_lin_default_l_27_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=38.465u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_26_R0 I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G
-+ I1_lin_default_l_26_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=32.055u nf=1
++ I1_lin_default_l_26_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=32.055u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_25_R0 I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G
-+ I1_lin_default_l_25_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=26.710u nf=1
++ I1_lin_default_l_25_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=26.710u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_24_R0 I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G
-+ I1_lin_default_l_24_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=22.260u nf=1
++ I1_lin_default_l_24_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=22.260u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_23_R0 I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G
-+ I1_lin_default_l_23_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=18.550u nf=1
++ I1_lin_default_l_23_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=18.550u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_22_R0 I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G
-+ I1_lin_default_l_22_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=15.460u nf=1
++ I1_lin_default_l_22_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=15.460u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_21_R0 I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G
-+ I1_lin_default_l_21_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=12.880u nf=1
++ I1_lin_default_l_21_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=12.880u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_20_R0 I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G
-+ I1_lin_default_l_20_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=10.735u nf=1
++ I1_lin_default_l_20_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=10.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_19_R0 I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G
-+ I1_lin_default_l_19_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=8.945u nf=1
++ I1_lin_default_l_19_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=8.945u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_18_R0 I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G
-+ I1_lin_default_l_18_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=7.455u nf=1
++ I1_lin_default_l_18_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=7.455u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_17_R0 I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G
-+ I1_lin_default_l_17_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=6.210u nf=1
++ I1_lin_default_l_17_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=6.210u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_16_R0 I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G
-+ I1_lin_default_l_16_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=5.175u nf=1
++ I1_lin_default_l_16_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=5.175u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_15_R0 I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G
-+ I1_lin_default_l_15_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=4.315u nf=1
++ I1_lin_default_l_15_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=4.315u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_14_R0 I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G
-+ I1_lin_default_l_14_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=3.595u nf=1
++ I1_lin_default_l_14_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=3.595u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_13_R0 I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G
-+ I1_lin_default_l_13_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.995u nf=1
++ I1_lin_default_l_13_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=2.995u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_12_R0 I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G
-+ I1_lin_default_l_12_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.495u nf=1
++ I1_lin_default_l_12_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=2.495u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_11_R0 I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G
-+ I1_lin_default_l_11_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.080u nf=1
++ I1_lin_default_l_11_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=2.080u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_10_R0 I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G
-+ I1_lin_default_l_10_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.735u nf=1
++ I1_lin_default_l_10_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=1.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_9_R0 I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G
-+ I1_lin_default_l_9_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.445u nf=1
++ I1_lin_default_l_9_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=1.445u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_8_R0 I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G
-+ I1_lin_default_l_8_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.205u nf=1
++ I1_lin_default_l_8_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=1.205u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_7_R0 I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G
-+ I1_lin_default_l_7_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.005u nf=1
++ I1_lin_default_l_7_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=1.005u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_6_R0 I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G
-+ I1_lin_default_l_6_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.835u nf=1
++ I1_lin_default_l_6_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=0.835u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_5_R0 I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G
-+ I1_lin_default_l_5_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.695u nf=1
++ I1_lin_default_l_5_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=0.695u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_4_R0 I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G
-+ I1_lin_default_l_4_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.580u nf=1
++ I1_lin_default_l_4_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=0.580u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_3_R0 I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G
-+ I1_lin_default_l_3_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.485u nf=1
++ I1_lin_default_l_3_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=0.485u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_2_R0 I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G
-+ I1_lin_default_l_2_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.405u nf=1
++ I1_lin_default_l_2_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=0.405u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_1_R0 I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G
-+ I1_lin_default_l_1_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.335u nf=1
++ I1_lin_default_l_1_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=0.335u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_0_R0 I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G
-+ I1_lin_default_l_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.280u nf=1
++ I1_lin_default_l_0_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=0.280u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_nf_2_R0 I1_lin_default_nf_2_R0_D I1_lin_default_nf_2_R0_G
-+ I1_lin_default_nf_2_R0_S vdd! nmos_1p8 m=1 w=36e-6 l=280n nf=100
++ I1_lin_default_nf_2_R0_S vdd! nfet_03v3 m=1 w=36e-6 l=280n nf=100
+ as=9.4896e-12 ad=9.36e-12 ps=89.44e-6 pd=88e-6 nrd=0.007222 nrs=0.007322
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_1_R0 I1_lin_default_nf_1_R0_D I1_lin_default_nf_1_R0_G
-+ I1_lin_default_nf_1_R0_S vdd! nmos_1p8 m=1 w=18.36e-6 l=280n nf=51
++ I1_lin_default_nf_1_R0_S vdd! nfet_03v3 m=1 w=18.36e-6 l=280n nf=51
+ as=4.8384e-12 ad=4.8384e-12 ps=45.6e-6 pd=45.6e-6 nrd=0.014353 nrs=0.014353
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_0_R0 I1_lin_default_nf_0_R0_D I1_lin_default_nf_0_R0_G
-+ I1_lin_default_nf_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_nf_0_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_m_2_R0 I1_lin_default_m_2_R0_D I1_lin_default_m_2_R0_G
-+ I1_lin_default_m_2_R0_S vdd! nmos_1p8 m=100 w=360e-9 l=280n nf=1
++ I1_lin_default_m_2_R0_S vdd! nfet_03v3 m=100 w=360e-9 l=280n nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=100
MI1_lin_default_m_1_R0 I1_lin_default_m_1_R0_D I1_lin_default_m_1_R0_G
-+ I1_lin_default_m_1_R0_S vdd! nmos_1p8 m=51 w=1.8e-6 l=280n nf=5 as=532.8e-15
++ I1_lin_default_m_1_R0_S vdd! nfet_03v3 m=51 w=1.8e-6 l=280n nf=5 as=532.8e-15
+ ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444 sa=0.440u
+ sb=0.440u sd=0.520u dtemp=0 par=51
MI1_lin_default_m_0_R0 I1_lin_default_m_0_R0_D I1_lin_default_m_0_R0_G
-+ I1_lin_default_m_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_m_0_R0_S vdd! nfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_2_R0 I1_lin_default_calculatedParam_2_R0_D
+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ vdd! nmos_1p8 m=1 w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6
++ vdd! nfet_03v3 m=1 w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6
+ pd=1.76e-6 nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_calculatedParam_1_R0 I1_lin_default_calculatedParam_1_R0_D
+ I1_lin_default_calculatedParam_1_R0_G I1_lin_default_calculatedParam_1_R0_S
-+ vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ vdd! nfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_0_R0 I1_lin_default_calculatedParam_0_R0_D
+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ vdd! nfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_2_R0 I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S vdd! nfet_03v3
+ m=1 w=16.08e-6 l=280n nf=3 as=5.1456e-12 ad=5.1456e-12 ps=23.36e-6
+ pd=23.36e-6 nrd=0.019900 nrs=0.019900 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_gateConn_1_R0 I1_lin_default_gateConn_1_R0_D
-+ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_0_R0 I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_9_R0 I1_lin_default_sdWidth_9_R0_D
-+ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S vdd! nfet_03v3
+ m=1 w=26.8e-6 l=280n nf=5 as=20.3144e-12 ad=20.3144e-12 ps=39.74e-6
+ pd=39.74e-6 nrd=0.028284 nrs=0.028284 sa=1.210u sb=1.210u sd=1.290u dtemp=0
+ par=1
MI1_lin_default_sdWidth_8_R0 I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=432e-15 ad=432e-15 ps=3.12e-6 pd=3.12e-6
+ nrd=3.333333 nrs=3.333333 sa=1.200u sb=1.200u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_7_R0 I1_lin_default_sdWidth_7_R0_D
-+ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=372.6e-15 ad=372.6e-15 ps=2.79e-6 pd=2.79e-6
+ nrd=2.875000 nrs=2.875000 sa=1.035u sb=1.035u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_6_R0 I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=322.2e-15 ad=322.2e-15 ps=2.51e-6 pd=2.51e-6
+ nrd=2.486111 nrs=2.486111 sa=0.895u sb=0.895u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_5_R0 I1_lin_default_sdWidth_5_R0_D
-+ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=280.8e-15 ad=280.8e-15 ps=2.28e-6 pd=2.28e-6
+ nrd=2.166667 nrs=2.166667 sa=0.780u sb=0.780u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_4_R0 I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=246.6e-15 ad=246.6e-15 ps=2.09e-6 pd=2.09e-6
+ nrd=1.902778 nrs=1.902778 sa=0.685u sb=0.685u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_3_R0 I1_lin_default_sdWidth_3_R0_D
-+ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=217.8e-15 ad=217.8e-15 ps=1.93e-6 pd=1.93e-6
+ nrd=1.680556 nrs=1.680556 sa=0.605u sb=0.605u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_2_R0 I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=194.4e-15 ad=194.4e-15 ps=1.8e-6 pd=1.8e-6
+ nrd=1.500000 nrs=1.500000 sa=0.540u sb=0.540u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_1_R0 I1_lin_default_sdWidth_1_R0_D
-+ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=174.6e-15 ad=174.6e-15 ps=1.69e-6 pd=1.69e-6
+ nrd=1.347222 nrs=1.347222 sa=0.485u sb=0.485u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_0_R0 I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sFirst_0_R0 I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S vdd! nfet_03v3 m=1
+ w=16.8e-6 l=280n nf=5 as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6
+ nrd=0.017619 nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_2_R0 I1_lin_default_sdConn_2_R0_D
-+ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S vdd! nfet_03v3 m=1
+ w=13.6e-6 l=280n nf=10 as=4.0256e-12 ad=3.536e-12 ps=22.24e-6 pd=18.8e-6
+ nrd=0.019118 nrs=0.021765 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_1_R0 I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S vdd! nfet_03v3 m=1
+ w=1.08e-6 l=280n nf=3 as=345.6e-15 ad=345.6e-15 ps=3.36e-6 pd=3.36e-6
+ nrd=0.296296 nrs=0.296296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_0_R0 I1_lin_default_sdConn_0_R0_D
-+ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S vdd! nfet_03v3 m=1
+ w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6 pd=1.76e-6
+ nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_bodytie_1_R0 I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S vdd! nmos_1p8
++ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bodytie_0_R0 I1_lin_default_bodytie_0_R0_D
-+ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S vdd! nmos_1p8
++ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_leftTap_0_R0 I1_lin_default_leftTap_0_R0_D
-+ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S vdd! nmos_1p8
++ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_rightTap_0_R0 I1_lin_default_rightTap_0_R0_D
-+ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S vdd! nmos_1p8
++ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S vdd! nfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_topTap_0_R0 I1_lin_default_topTap_0_R0_D
-+ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S vdd! nfet_03v3 m=1
+ w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bottomTap_0_R0 I1_lin_default_bottomTap_0_R0_D
+ I1_lin_default_bottomTap_0_R0_G I1_lin_default_bottomTap_0_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_4_R0 I1_lin_default_tapCntRows_4_R0_D
+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S vdd!
-+ nmos_1p8 m=1 w=25.08e-6 l=280n nf=3 as=8.0256e-12 ad=8.0256e-12 ps=35.36e-6
++ nfet_03v3 m=1 w=25.08e-6 l=280n nf=3 as=8.0256e-12 ad=8.0256e-12 ps=35.36e-6
+ pd=35.36e-6 nrd=0.012759 nrs=0.012759 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_tapCntRows_3_R0 I1_lin_default_tapCntRows_3_R0_D
+ I1_lin_default_tapCntRows_3_R0_G I1_lin_default_tapCntRows_3_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_2_R0 I1_lin_default_tapCntRows_2_R0_D
+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_1_R0 I1_lin_default_tapCntRows_1_R0_D
+ I1_lin_default_tapCntRows_1_R0_G I1_lin_default_tapCntRows_1_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_0_R0 I1_lin_default_tapCntRows_0_R0_D
+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_default I1_default_D I1_default_G I1_default_S vdd! nmos_1p8 m=1 w=360e-9
+MI1_default I1_default_D I1_default_G I1_default_S vdd! nfet_03v3 m=1 w=360e-9
+ l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222
+ nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
.ENDS
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_03v3_nvt.cdl
similarity index 90%
copy from IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl
copy to IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_03v3_nvt.cdl
index b444597..fa2af4f 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8.cdl
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nfet_03v3_nvt.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_library_2
-* Top Cell Name: nmos_1p8
+* Top Cell Name: nfet_03v3_nvt
* View Name: schematic
* Netlisted on: Sep 10 16:28:03 2021
************************************************************************
@@ -18,11 +18,11 @@
************************************************************************
* Library Name: TCG_library_2
-* Cell Name: nmos_1p8
+* Cell Name: nfet_03v3_nvt
* View Name: schematic
************************************************************************
-.SUBCKT nmos_1p8 I1_default_D I1_default_G I1_default_S
+.SUBCKT nfet_03v3_nvt I1_default_D I1_default_G I1_default_S
+ I1_lin_default_bodytie_0_R0_D I1_lin_default_bodytie_0_R0_G
+ I1_lin_default_bodytie_0_R0_S I1_lin_default_bodytie_1_R0_D
+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S
@@ -326,422 +326,422 @@
*.PININFO I1_lin_default_tapCntRows_4_R0_S:I I1_lin_default_topTap_0_R0_D:I
*.PININFO I1_lin_default_topTap_0_R0_G:I I1_lin_default_topTap_0_R0_S:I vdd!:I
MI1_lin_default_fingerW_34_R0 I1_lin_default_fingerW_34_R0_D
-+ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S vdd! nfet_03v3_nvt
+ m=1 w=1e-3 l=280n nf=10 as=296e-12 ad=260e-12 ps=1.20592e-3 pd=1.0052e-3
+ nrd=0.000260 nrs=0.000296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_fingerW_33_R0 I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S vdd! nfet_03v3_nvt
+ m=1 w=90.24e-6 l=280n nf=1 as=39.7056e-12 ad=39.7056e-12 ps=181.36e-6
+ pd=181.36e-6 nrd=0.004876 nrs=0.004876 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_32_R0 I1_lin_default_fingerW_32_R0_D
-+ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S vdd! nfet_03v3_nvt
+ m=1 w=75.2e-6 l=280n nf=1 as=33.088e-12 ad=33.088e-12 ps=151.28e-6
+ pd=151.28e-6 nrd=0.005851 nrs=0.005851 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_31_R0 I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S vdd! nfet_03v3_nvt
+ m=1 w=62.665e-6 l=280n nf=1 as=27.5726e-12 ad=27.5726e-12 ps=126.21e-6
+ pd=126.21e-6 nrd=0.007021 nrs=0.007021 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_30_R0 I1_lin_default_fingerW_30_R0_D
-+ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S vdd! nfet_03v3_nvt
+ m=1 w=52.225e-6 l=280n nf=1 as=22.979e-12 ad=22.979e-12 ps=105.33e-6
+ pd=105.33e-6 nrd=0.008425 nrs=0.008425 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_29_R0 I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S vdd! nfet_03v3_nvt
+ m=1 w=43.52e-6 l=280n nf=1 as=19.1488e-12 ad=19.1488e-12 ps=87.92e-6
+ pd=87.92e-6 nrd=0.010110 nrs=0.010110 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_28_R0 I1_lin_default_fingerW_28_R0_D
-+ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S vdd! nfet_03v3_nvt
+ m=1 w=36.265e-6 l=280n nf=1 as=15.9566e-12 ad=15.9566e-12 ps=73.41e-6
+ pd=73.41e-6 nrd=0.012133 nrs=0.012133 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_27_R0 I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S vdd! nfet_03v3_nvt
+ m=1 w=30.22e-6 l=280n nf=1 as=13.2968e-12 ad=13.2968e-12 ps=61.32e-6
+ pd=61.32e-6 nrd=0.014560 nrs=0.014560 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_26_R0 I1_lin_default_fingerW_26_R0_D
-+ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S vdd! nfet_03v3_nvt
+ m=1 w=25.185e-6 l=280n nf=1 as=11.0814e-12 ad=11.0814e-12 ps=51.25e-6
+ pd=51.25e-6 nrd=0.017471 nrs=0.017471 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_25_R0 I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S vdd! nfet_03v3_nvt
+ m=1 w=20.985e-6 l=280n nf=1 as=9.2334e-12 ad=9.2334e-12 ps=42.85e-6
+ pd=42.85e-6 nrd=0.020967 nrs=0.020967 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_24_R0 I1_lin_default_fingerW_24_R0_D
-+ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S vdd! nfet_03v3_nvt
+ m=1 w=17.49e-6 l=280n nf=1 as=7.6956e-12 ad=7.6956e-12 ps=35.86e-6
+ pd=35.86e-6 nrd=0.025157 nrs=0.025157 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_23_R0 I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S vdd! nfet_03v3_nvt
+ m=1 w=14.575e-6 l=280n nf=1 as=6.413e-12 ad=6.413e-12 ps=30.03e-6
+ pd=30.03e-6 nrd=0.030189 nrs=0.030189 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_22_R0 I1_lin_default_fingerW_22_R0_D
-+ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S vdd! nfet_03v3_nvt
+ m=1 w=12.145e-6 l=280n nf=1 as=5.3438e-12 ad=5.3438e-12 ps=25.17e-6
+ pd=25.17e-6 nrd=0.036229 nrs=0.036229 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_21_R0 I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S vdd! nfet_03v3_nvt
+ m=1 w=10.12e-6 l=280n nf=1 as=4.4528e-12 ad=4.4528e-12 ps=21.12e-6
+ pd=21.12e-6 nrd=0.043478 nrs=0.043478 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_20_R0 I1_lin_default_fingerW_20_R0_D
-+ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S vdd! nfet_03v3_nvt
+ m=1 w=8.435e-6 l=280n nf=1 as=3.7114e-12 ad=3.7114e-12 ps=17.75e-6
+ pd=17.75e-6 nrd=0.052164 nrs=0.052164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_19_R0 I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S vdd! nfet_03v3_nvt
+ m=1 w=7.03e-6 l=280n nf=1 as=3.0932e-12 ad=3.0932e-12 ps=14.94e-6
+ pd=14.94e-6 nrd=0.062589 nrs=0.062589 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_18_R0 I1_lin_default_fingerW_18_R0_D
-+ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S vdd! nfet_03v3_nvt
+ m=1 w=5.855e-6 l=280n nf=1 as=2.5762e-12 ad=2.5762e-12 ps=12.59e-6
+ pd=12.59e-6 nrd=0.075149 nrs=0.075149 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_17_R0 I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S vdd! nfet_03v3_nvt
+ m=1 w=4.88e-6 l=280n nf=1 as=2.1472e-12 ad=2.1472e-12 ps=10.64e-6
+ pd=10.64e-6 nrd=0.090164 nrs=0.090164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_16_R0 I1_lin_default_fingerW_16_R0_D
-+ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S vdd! nfet_03v3_nvt
+ m=1 w=4.065e-6 l=280n nf=1 as=1.7886e-12 ad=1.7886e-12 ps=9.01e-6 pd=9.01e-6
+ nrd=0.108241 nrs=0.108241 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_15_R0 I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S vdd! nfet_03v3_nvt
+ m=1 w=3.39e-6 l=280n nf=1 as=1.4916e-12 ad=1.4916e-12 ps=7.66e-6 pd=7.66e-6
+ nrd=0.129794 nrs=0.129794 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_14_R0 I1_lin_default_fingerW_14_R0_D
-+ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S vdd! nfet_03v3_nvt
+ m=1 w=2.825e-6 l=280n nf=1 as=1.243e-12 ad=1.243e-12 ps=6.53e-6 pd=6.53e-6
+ nrd=0.155752 nrs=0.155752 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_13_R0 I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S vdd! nfet_03v3_nvt
+ m=1 w=2.355e-6 l=280n nf=1 as=1.0362e-12 ad=1.0362e-12 ps=5.59e-6 pd=5.59e-6
+ nrd=0.186837 nrs=0.186837 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_12_R0 I1_lin_default_fingerW_12_R0_D
-+ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S vdd! nfet_03v3_nvt
+ m=1 w=1.96e-6 l=280n nf=1 as=862.4e-15 ad=862.4e-15 ps=4.8e-6 pd=4.8e-6
+ nrd=0.224490 nrs=0.224490 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_11_R0 I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S vdd! nfet_03v3_nvt
+ m=1 w=1.635e-6 l=280n nf=1 as=719.4e-15 ad=719.4e-15 ps=4.15e-6 pd=4.15e-6
+ nrd=0.269113 nrs=0.269113 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_10_R0 I1_lin_default_fingerW_10_R0_D
-+ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S vdd! nfet_03v3_nvt
+ m=1 w=1.36e-6 l=280n nf=1 as=598.4e-15 ad=598.4e-15 ps=3.6e-6 pd=3.6e-6
+ nrd=0.323529 nrs=0.323529 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_9_R0 I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S vdd! nfet_03v3_nvt
+ m=1 w=1.135e-6 l=280n nf=1 as=499.4e-15 ad=499.4e-15 ps=3.15e-6 pd=3.15e-6
+ nrd=0.387665 nrs=0.387665 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_8_R0 I1_lin_default_fingerW_8_R0_D
-+ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S vdd! nfet_03v3_nvt
+ m=1 w=945e-9 l=280n nf=1 as=415.8e-15 ad=415.8e-15 ps=2.77e-6 pd=2.77e-6
+ nrd=0.465608 nrs=0.465608 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_7_R0 I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S vdd! nfet_03v3_nvt
+ m=1 w=790e-9 l=280n nf=1 as=347.6e-15 ad=347.6e-15 ps=2.46e-6 pd=2.46e-6
+ nrd=0.556962 nrs=0.556962 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_6_R0 I1_lin_default_fingerW_6_R0_D
-+ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S vdd! nfet_03v3_nvt
+ m=1 w=655e-9 l=280n nf=1 as=288.2e-15 ad=288.2e-15 ps=2.19e-6 pd=2.19e-6
+ nrd=0.671756 nrs=0.671756 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_5_R0 I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S vdd! nfet_03v3_nvt
+ m=1 w=545e-9 l=280n nf=1 as=239.8e-15 ad=239.8e-15 ps=1.97e-6 pd=1.97e-6
+ nrd=0.807339 nrs=0.807339 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_4_R0 I1_lin_default_fingerW_4_R0_D
-+ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S vdd! nfet_03v3_nvt
+ m=1 w=455e-9 l=280n nf=1 as=200.2e-15 ad=200.2e-15 ps=1.79e-6 pd=1.79e-6
+ nrd=0.967033 nrs=0.967033 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_3_R0 I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S vdd! nfet_03v3_nvt
+ m=1 w=380e-9 l=280n nf=1 as=167.2e-15 ad=167.2e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.157895 nrs=1.157895 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_2_R0 I1_lin_default_fingerW_2_R0_D
-+ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S vdd! nfet_03v3_nvt
+ m=1 w=315e-9 l=280n nf=1 as=161.1e-15 ad=161.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.623583 nrs=1.623583 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_1_R0 I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S vdd! nfet_03v3_nvt
+ m=1 w=265e-9 l=280n nf=1 as=156.1e-15 ad=156.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=2.222855 nrs=2.222855 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_0_R0 I1_lin_default_fingerW_0_R0_D
-+ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S vdd! nmos_1p8
++ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S vdd! nfet_03v3_nvt
+ m=1 w=220e-9 l=280n nf=1 as=151.6e-15 ad=151.6e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=3.132231 nrs=3.132231 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_l_29_R0 I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G
-+ I1_lin_default_l_29_R0_S vdd! nmos_1p8 m=1 w=1.8e-6 l=50.000u nf=5
++ I1_lin_default_l_29_R0_S vdd! nfet_03v3_nvt m=1 w=1.8e-6 l=50.000u nf=5
+ as=532.8e-15 ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_l_28_R0 I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G
-+ I1_lin_default_l_28_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=46.155u nf=1
++ I1_lin_default_l_28_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=46.155u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_27_R0 I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G
-+ I1_lin_default_l_27_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=38.465u nf=1
++ I1_lin_default_l_27_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=38.465u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_26_R0 I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G
-+ I1_lin_default_l_26_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=32.055u nf=1
++ I1_lin_default_l_26_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=32.055u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_25_R0 I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G
-+ I1_lin_default_l_25_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=26.710u nf=1
++ I1_lin_default_l_25_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=26.710u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_24_R0 I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G
-+ I1_lin_default_l_24_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=22.260u nf=1
++ I1_lin_default_l_24_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=22.260u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_23_R0 I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G
-+ I1_lin_default_l_23_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=18.550u nf=1
++ I1_lin_default_l_23_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=18.550u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_22_R0 I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G
-+ I1_lin_default_l_22_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=15.460u nf=1
++ I1_lin_default_l_22_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=15.460u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_21_R0 I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G
-+ I1_lin_default_l_21_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=12.880u nf=1
++ I1_lin_default_l_21_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=12.880u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_20_R0 I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G
-+ I1_lin_default_l_20_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=10.735u nf=1
++ I1_lin_default_l_20_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=10.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_19_R0 I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G
-+ I1_lin_default_l_19_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=8.945u nf=1
++ I1_lin_default_l_19_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=8.945u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_18_R0 I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G
-+ I1_lin_default_l_18_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=7.455u nf=1
++ I1_lin_default_l_18_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=7.455u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_17_R0 I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G
-+ I1_lin_default_l_17_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=6.210u nf=1
++ I1_lin_default_l_17_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=6.210u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_16_R0 I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G
-+ I1_lin_default_l_16_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=5.175u nf=1
++ I1_lin_default_l_16_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=5.175u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_15_R0 I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G
-+ I1_lin_default_l_15_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=4.315u nf=1
++ I1_lin_default_l_15_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=4.315u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_14_R0 I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G
-+ I1_lin_default_l_14_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=3.595u nf=1
++ I1_lin_default_l_14_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=3.595u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_13_R0 I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G
-+ I1_lin_default_l_13_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.995u nf=1
++ I1_lin_default_l_13_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=2.995u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_12_R0 I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G
-+ I1_lin_default_l_12_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.495u nf=1
++ I1_lin_default_l_12_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=2.495u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_11_R0 I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G
-+ I1_lin_default_l_11_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=2.080u nf=1
++ I1_lin_default_l_11_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=2.080u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_10_R0 I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G
-+ I1_lin_default_l_10_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.735u nf=1
++ I1_lin_default_l_10_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=1.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_9_R0 I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G
-+ I1_lin_default_l_9_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.445u nf=1
++ I1_lin_default_l_9_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=1.445u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_8_R0 I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G
-+ I1_lin_default_l_8_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.205u nf=1
++ I1_lin_default_l_8_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=1.205u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_7_R0 I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G
-+ I1_lin_default_l_7_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=1.005u nf=1
++ I1_lin_default_l_7_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=1.005u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_6_R0 I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G
-+ I1_lin_default_l_6_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.835u nf=1
++ I1_lin_default_l_6_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=0.835u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_5_R0 I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G
-+ I1_lin_default_l_5_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.695u nf=1
++ I1_lin_default_l_5_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=0.695u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_4_R0 I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G
-+ I1_lin_default_l_4_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.580u nf=1
++ I1_lin_default_l_4_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=0.580u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_3_R0 I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G
-+ I1_lin_default_l_3_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.485u nf=1
++ I1_lin_default_l_3_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=0.485u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_2_R0 I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G
-+ I1_lin_default_l_2_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.405u nf=1
++ I1_lin_default_l_2_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=0.405u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_1_R0 I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G
-+ I1_lin_default_l_1_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.335u nf=1
++ I1_lin_default_l_1_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=0.335u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_0_R0 I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G
-+ I1_lin_default_l_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=0.280u nf=1
++ I1_lin_default_l_0_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=0.280u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_nf_2_R0 I1_lin_default_nf_2_R0_D I1_lin_default_nf_2_R0_G
-+ I1_lin_default_nf_2_R0_S vdd! nmos_1p8 m=1 w=36e-6 l=280n nf=100
++ I1_lin_default_nf_2_R0_S vdd! nfet_03v3_nvt m=1 w=36e-6 l=280n nf=100
+ as=9.4896e-12 ad=9.36e-12 ps=89.44e-6 pd=88e-6 nrd=0.007222 nrs=0.007322
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_1_R0 I1_lin_default_nf_1_R0_D I1_lin_default_nf_1_R0_G
-+ I1_lin_default_nf_1_R0_S vdd! nmos_1p8 m=1 w=18.36e-6 l=280n nf=51
++ I1_lin_default_nf_1_R0_S vdd! nfet_03v3_nvt m=1 w=18.36e-6 l=280n nf=51
+ as=4.8384e-12 ad=4.8384e-12 ps=45.6e-6 pd=45.6e-6 nrd=0.014353 nrs=0.014353
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_0_R0 I1_lin_default_nf_0_R0_D I1_lin_default_nf_0_R0_G
-+ I1_lin_default_nf_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_nf_0_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_m_2_R0 I1_lin_default_m_2_R0_D I1_lin_default_m_2_R0_G
-+ I1_lin_default_m_2_R0_S vdd! nmos_1p8 m=100 w=360e-9 l=280n nf=1
++ I1_lin_default_m_2_R0_S vdd! nfet_03v3_nvt m=100 w=360e-9 l=280n nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=100
MI1_lin_default_m_1_R0 I1_lin_default_m_1_R0_D I1_lin_default_m_1_R0_G
-+ I1_lin_default_m_1_R0_S vdd! nmos_1p8 m=51 w=1.8e-6 l=280n nf=5 as=532.8e-15
++ I1_lin_default_m_1_R0_S vdd! nfet_03v3_nvt m=51 w=1.8e-6 l=280n nf=5 as=532.8e-15
+ ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444 sa=0.440u
+ sb=0.440u sd=0.520u dtemp=0 par=51
MI1_lin_default_m_0_R0 I1_lin_default_m_0_R0_D I1_lin_default_m_0_R0_G
-+ I1_lin_default_m_0_R0_S vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_m_0_R0_S vdd! nfet_03v3_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_2_R0 I1_lin_default_calculatedParam_2_R0_D
+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ vdd! nmos_1p8 m=1 w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6
++ vdd! nfet_03v3_nvt m=1 w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6
+ pd=1.76e-6 nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_calculatedParam_1_R0 I1_lin_default_calculatedParam_1_R0_D
+ I1_lin_default_calculatedParam_1_R0_G I1_lin_default_calculatedParam_1_R0_S
-+ vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ vdd! nfet_03v3_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_0_R0 I1_lin_default_calculatedParam_0_R0_D
+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ vdd! nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ vdd! nfet_03v3_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_2_R0 I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S vdd! nfet_03v3_nvt
+ m=1 w=16.08e-6 l=280n nf=3 as=5.1456e-12 ad=5.1456e-12 ps=23.36e-6
+ pd=23.36e-6 nrd=0.019900 nrs=0.019900 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_gateConn_1_R0 I1_lin_default_gateConn_1_R0_D
-+ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_0_R0 I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S vdd! nmos_1p8
++ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_9_R0 I1_lin_default_sdWidth_9_R0_D
-+ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S vdd! nfet_03v3_nvt
+ m=1 w=26.8e-6 l=280n nf=5 as=20.3144e-12 ad=20.3144e-12 ps=39.74e-6
+ pd=39.74e-6 nrd=0.028284 nrs=0.028284 sa=1.210u sb=1.210u sd=1.290u dtemp=0
+ par=1
MI1_lin_default_sdWidth_8_R0 I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=432e-15 ad=432e-15 ps=3.12e-6 pd=3.12e-6
+ nrd=3.333333 nrs=3.333333 sa=1.200u sb=1.200u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_7_R0 I1_lin_default_sdWidth_7_R0_D
-+ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=372.6e-15 ad=372.6e-15 ps=2.79e-6 pd=2.79e-6
+ nrd=2.875000 nrs=2.875000 sa=1.035u sb=1.035u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_6_R0 I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=322.2e-15 ad=322.2e-15 ps=2.51e-6 pd=2.51e-6
+ nrd=2.486111 nrs=2.486111 sa=0.895u sb=0.895u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_5_R0 I1_lin_default_sdWidth_5_R0_D
-+ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=280.8e-15 ad=280.8e-15 ps=2.28e-6 pd=2.28e-6
+ nrd=2.166667 nrs=2.166667 sa=0.780u sb=0.780u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_4_R0 I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=246.6e-15 ad=246.6e-15 ps=2.09e-6 pd=2.09e-6
+ nrd=1.902778 nrs=1.902778 sa=0.685u sb=0.685u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_3_R0 I1_lin_default_sdWidth_3_R0_D
-+ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=217.8e-15 ad=217.8e-15 ps=1.93e-6 pd=1.93e-6
+ nrd=1.680556 nrs=1.680556 sa=0.605u sb=0.605u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_2_R0 I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=194.4e-15 ad=194.4e-15 ps=1.8e-6 pd=1.8e-6
+ nrd=1.500000 nrs=1.500000 sa=0.540u sb=0.540u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_1_R0 I1_lin_default_sdWidth_1_R0_D
-+ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=174.6e-15 ad=174.6e-15 ps=1.69e-6 pd=1.69e-6
+ nrd=1.347222 nrs=1.347222 sa=0.485u sb=0.485u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_0_R0 I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S vdd! nmos_1p8
++ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sFirst_0_R0 I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S vdd! nfet_03v3_nvt m=1
+ w=16.8e-6 l=280n nf=5 as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6
+ nrd=0.017619 nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_2_R0 I1_lin_default_sdConn_2_R0_D
-+ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S vdd! nfet_03v3_nvt m=1
+ w=13.6e-6 l=280n nf=10 as=4.0256e-12 ad=3.536e-12 ps=22.24e-6 pd=18.8e-6
+ nrd=0.019118 nrs=0.021765 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_1_R0 I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S vdd! nfet_03v3_nvt m=1
+ w=1.08e-6 l=280n nf=3 as=345.6e-15 ad=345.6e-15 ps=3.36e-6 pd=3.36e-6
+ nrd=0.296296 nrs=0.296296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_0_R0 I1_lin_default_sdConn_0_R0_D
-+ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S vdd! nfet_03v3_nvt m=1
+ w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6 pd=1.76e-6
+ nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_bodytie_1_R0 I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S vdd! nmos_1p8
++ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bodytie_0_R0 I1_lin_default_bodytie_0_R0_D
-+ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S vdd! nmos_1p8
++ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_leftTap_0_R0 I1_lin_default_leftTap_0_R0_D
-+ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S vdd! nmos_1p8
++ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_rightTap_0_R0 I1_lin_default_rightTap_0_R0_D
-+ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S vdd! nmos_1p8
++ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S vdd! nfet_03v3_nvt
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_topTap_0_R0 I1_lin_default_topTap_0_R0_D
-+ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S vdd! nmos_1p8 m=1
++ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S vdd! nfet_03v3_nvt m=1
+ w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bottomTap_0_R0 I1_lin_default_bottomTap_0_R0_D
+ I1_lin_default_bottomTap_0_R0_G I1_lin_default_bottomTap_0_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_03v3_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_4_R0 I1_lin_default_tapCntRows_4_R0_D
+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S vdd!
-+ nmos_1p8 m=1 w=25.08e-6 l=280n nf=3 as=8.0256e-12 ad=8.0256e-12 ps=35.36e-6
++ nfet_03v3_nvt m=1 w=25.08e-6 l=280n nf=3 as=8.0256e-12 ad=8.0256e-12 ps=35.36e-6
+ pd=35.36e-6 nrd=0.012759 nrs=0.012759 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_tapCntRows_3_R0 I1_lin_default_tapCntRows_3_R0_D
+ I1_lin_default_tapCntRows_3_R0_G I1_lin_default_tapCntRows_3_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_03v3_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_2_R0 I1_lin_default_tapCntRows_2_R0_D
+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_03v3_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_1_R0 I1_lin_default_tapCntRows_1_R0_D
+ I1_lin_default_tapCntRows_1_R0_G I1_lin_default_tapCntRows_1_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_03v3_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_0_R0 I1_lin_default_tapCntRows_0_R0_D
+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S vdd!
-+ nmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ nfet_03v3_nvt m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_default I1_default_D I1_default_G I1_default_S vdd! nmos_1p8 m=1 w=360e-9
+MI1_default I1_default_D I1_default_G I1_default_S vdd! nfet_03v3_nvt m=1 w=360e-9
+ l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222
+ nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
.ENDS
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8_nat.cdl b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8_nat.cdl
deleted file mode 100644
index 5749db3..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_1p8_nat.cdl
+++ /dev/null
@@ -1,748 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_library_2
-* Top Cell Name: nmos_1p8_nat
-* View Name: schematic
-* Netlisted on: Sep 10 16:28:03 2021
-************************************************************************
-
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-*.GLOBAL vdd!
-
-*.PIN vdd!
-
-************************************************************************
-* Library Name: TCG_library_2
-* Cell Name: nmos_1p8_nat
-* View Name: schematic
-************************************************************************
-
-.SUBCKT nmos_1p8_nat I1_default_D I1_default_G I1_default_S
-+ I1_lin_default_bodytie_0_R0_D I1_lin_default_bodytie_0_R0_G
-+ I1_lin_default_bodytie_0_R0_S I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S
-+ I1_lin_default_bottomTap_0_R0_D I1_lin_default_bottomTap_0_R0_G
-+ I1_lin_default_bottomTap_0_R0_S I1_lin_default_calculatedParam_0_R0_D
-+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ I1_lin_default_calculatedParam_1_R0_D I1_lin_default_calculatedParam_1_R0_G
-+ I1_lin_default_calculatedParam_1_R0_S I1_lin_default_calculatedParam_2_R0_D
-+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ I1_lin_default_fingerW_0_R0_D I1_lin_default_fingerW_0_R0_G
-+ I1_lin_default_fingerW_0_R0_S I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S
-+ I1_lin_default_fingerW_2_R0_D I1_lin_default_fingerW_2_R0_G
-+ I1_lin_default_fingerW_2_R0_S I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S
-+ I1_lin_default_fingerW_4_R0_D I1_lin_default_fingerW_4_R0_G
-+ I1_lin_default_fingerW_4_R0_S I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S
-+ I1_lin_default_fingerW_6_R0_D I1_lin_default_fingerW_6_R0_G
-+ I1_lin_default_fingerW_6_R0_S I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S
-+ I1_lin_default_fingerW_8_R0_D I1_lin_default_fingerW_8_R0_G
-+ I1_lin_default_fingerW_8_R0_S I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S
-+ I1_lin_default_fingerW_10_R0_D I1_lin_default_fingerW_10_R0_G
-+ I1_lin_default_fingerW_10_R0_S I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S
-+ I1_lin_default_fingerW_12_R0_D I1_lin_default_fingerW_12_R0_G
-+ I1_lin_default_fingerW_12_R0_S I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S
-+ I1_lin_default_fingerW_14_R0_D I1_lin_default_fingerW_14_R0_G
-+ I1_lin_default_fingerW_14_R0_S I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S
-+ I1_lin_default_fingerW_16_R0_D I1_lin_default_fingerW_16_R0_G
-+ I1_lin_default_fingerW_16_R0_S I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S
-+ I1_lin_default_fingerW_18_R0_D I1_lin_default_fingerW_18_R0_G
-+ I1_lin_default_fingerW_18_R0_S I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S
-+ I1_lin_default_fingerW_20_R0_D I1_lin_default_fingerW_20_R0_G
-+ I1_lin_default_fingerW_20_R0_S I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S
-+ I1_lin_default_fingerW_22_R0_D I1_lin_default_fingerW_22_R0_G
-+ I1_lin_default_fingerW_22_R0_S I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S
-+ I1_lin_default_fingerW_24_R0_D I1_lin_default_fingerW_24_R0_G
-+ I1_lin_default_fingerW_24_R0_S I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S
-+ I1_lin_default_fingerW_26_R0_D I1_lin_default_fingerW_26_R0_G
-+ I1_lin_default_fingerW_26_R0_S I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S
-+ I1_lin_default_fingerW_28_R0_D I1_lin_default_fingerW_28_R0_G
-+ I1_lin_default_fingerW_28_R0_S I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S
-+ I1_lin_default_fingerW_30_R0_D I1_lin_default_fingerW_30_R0_G
-+ I1_lin_default_fingerW_30_R0_S I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S
-+ I1_lin_default_fingerW_32_R0_D I1_lin_default_fingerW_32_R0_G
-+ I1_lin_default_fingerW_32_R0_S I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S
-+ I1_lin_default_fingerW_34_R0_D I1_lin_default_fingerW_34_R0_G
-+ I1_lin_default_fingerW_34_R0_S I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S
-+ I1_lin_default_gateConn_1_R0_D I1_lin_default_gateConn_1_R0_G
-+ I1_lin_default_gateConn_1_R0_S I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S
-+ I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G I1_lin_default_l_0_R0_S
-+ I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G I1_lin_default_l_1_R0_S
-+ I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G I1_lin_default_l_2_R0_S
-+ I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G I1_lin_default_l_3_R0_S
-+ I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G I1_lin_default_l_4_R0_S
-+ I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G I1_lin_default_l_5_R0_S
-+ I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G I1_lin_default_l_6_R0_S
-+ I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G I1_lin_default_l_7_R0_S
-+ I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G I1_lin_default_l_8_R0_S
-+ I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G I1_lin_default_l_9_R0_S
-+ I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G I1_lin_default_l_10_R0_S
-+ I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G I1_lin_default_l_11_R0_S
-+ I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G I1_lin_default_l_12_R0_S
-+ I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G I1_lin_default_l_13_R0_S
-+ I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G I1_lin_default_l_14_R0_S
-+ I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G I1_lin_default_l_15_R0_S
-+ I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G I1_lin_default_l_16_R0_S
-+ I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G I1_lin_default_l_17_R0_S
-+ I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G I1_lin_default_l_18_R0_S
-+ I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G I1_lin_default_l_19_R0_S
-+ I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G I1_lin_default_l_20_R0_S
-+ I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G I1_lin_default_l_21_R0_S
-+ I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G I1_lin_default_l_22_R0_S
-+ I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G I1_lin_default_l_23_R0_S
-+ I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G I1_lin_default_l_24_R0_S
-+ I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G I1_lin_default_l_25_R0_S
-+ I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G I1_lin_default_l_26_R0_S
-+ I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G I1_lin_default_l_27_R0_S
-+ I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G I1_lin_default_l_28_R0_S
-+ I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G I1_lin_default_l_29_R0_S
-+ I1_lin_default_leftTap_0_R0_D I1_lin_default_leftTap_0_R0_G
-+ I1_lin_default_leftTap_0_R0_S I1_lin_default_m_0_R0_D
-+ I1_lin_default_m_0_R0_G I1_lin_default_m_0_R0_S I1_lin_default_m_1_R0_D
-+ I1_lin_default_m_1_R0_G I1_lin_default_m_1_R0_S I1_lin_default_m_2_R0_D
-+ I1_lin_default_m_2_R0_G I1_lin_default_m_2_R0_S I1_lin_default_nf_0_R0_D
-+ I1_lin_default_nf_0_R0_G I1_lin_default_nf_0_R0_S I1_lin_default_nf_1_R0_D
-+ I1_lin_default_nf_1_R0_G I1_lin_default_nf_1_R0_S I1_lin_default_nf_2_R0_D
-+ I1_lin_default_nf_2_R0_G I1_lin_default_nf_2_R0_S
-+ I1_lin_default_rightTap_0_R0_D I1_lin_default_rightTap_0_R0_G
-+ I1_lin_default_rightTap_0_R0_S I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S
-+ I1_lin_default_sdConn_0_R0_D I1_lin_default_sdConn_0_R0_G
-+ I1_lin_default_sdConn_0_R0_S I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S
-+ I1_lin_default_sdConn_2_R0_D I1_lin_default_sdConn_2_R0_G
-+ I1_lin_default_sdConn_2_R0_S I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S
-+ I1_lin_default_sdWidth_1_R0_D I1_lin_default_sdWidth_1_R0_G
-+ I1_lin_default_sdWidth_1_R0_S I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S
-+ I1_lin_default_sdWidth_3_R0_D I1_lin_default_sdWidth_3_R0_G
-+ I1_lin_default_sdWidth_3_R0_S I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S
-+ I1_lin_default_sdWidth_5_R0_D I1_lin_default_sdWidth_5_R0_G
-+ I1_lin_default_sdWidth_5_R0_S I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S
-+ I1_lin_default_sdWidth_7_R0_D I1_lin_default_sdWidth_7_R0_G
-+ I1_lin_default_sdWidth_7_R0_S I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S
-+ I1_lin_default_sdWidth_9_R0_D I1_lin_default_sdWidth_9_R0_G
-+ I1_lin_default_sdWidth_9_R0_S I1_lin_default_tapCntRows_0_R0_D
-+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S
-+ I1_lin_default_tapCntRows_1_R0_D I1_lin_default_tapCntRows_1_R0_G
-+ I1_lin_default_tapCntRows_1_R0_S I1_lin_default_tapCntRows_2_R0_D
-+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S
-+ I1_lin_default_tapCntRows_3_R0_D I1_lin_default_tapCntRows_3_R0_G
-+ I1_lin_default_tapCntRows_3_R0_S I1_lin_default_tapCntRows_4_R0_D
-+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S
-+ I1_lin_default_topTap_0_R0_D I1_lin_default_topTap_0_R0_G
-+ I1_lin_default_topTap_0_R0_S vdd!
-*.PININFO I1_default_D:I I1_default_G:I I1_default_S:I
-*.PININFO I1_lin_default_bodytie_0_R0_D:I I1_lin_default_bodytie_0_R0_G:I
-*.PININFO I1_lin_default_bodytie_0_R0_S:I I1_lin_default_bodytie_1_R0_D:I
-*.PININFO I1_lin_default_bodytie_1_R0_G:I I1_lin_default_bodytie_1_R0_S:I
-*.PININFO I1_lin_default_bottomTap_0_R0_D:I I1_lin_default_bottomTap_0_R0_G:I
-*.PININFO I1_lin_default_bottomTap_0_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_S:I
-*.PININFO I1_lin_default_fingerW_0_R0_D:I I1_lin_default_fingerW_0_R0_G:I
-*.PININFO I1_lin_default_fingerW_0_R0_S:I I1_lin_default_fingerW_1_R0_D:I
-*.PININFO I1_lin_default_fingerW_1_R0_G:I I1_lin_default_fingerW_1_R0_S:I
-*.PININFO I1_lin_default_fingerW_2_R0_D:I I1_lin_default_fingerW_2_R0_G:I
-*.PININFO I1_lin_default_fingerW_2_R0_S:I I1_lin_default_fingerW_3_R0_D:I
-*.PININFO I1_lin_default_fingerW_3_R0_G:I I1_lin_default_fingerW_3_R0_S:I
-*.PININFO I1_lin_default_fingerW_4_R0_D:I I1_lin_default_fingerW_4_R0_G:I
-*.PININFO I1_lin_default_fingerW_4_R0_S:I I1_lin_default_fingerW_5_R0_D:I
-*.PININFO I1_lin_default_fingerW_5_R0_G:I I1_lin_default_fingerW_5_R0_S:I
-*.PININFO I1_lin_default_fingerW_6_R0_D:I I1_lin_default_fingerW_6_R0_G:I
-*.PININFO I1_lin_default_fingerW_6_R0_S:I I1_lin_default_fingerW_7_R0_D:I
-*.PININFO I1_lin_default_fingerW_7_R0_G:I I1_lin_default_fingerW_7_R0_S:I
-*.PININFO I1_lin_default_fingerW_8_R0_D:I I1_lin_default_fingerW_8_R0_G:I
-*.PININFO I1_lin_default_fingerW_8_R0_S:I I1_lin_default_fingerW_9_R0_D:I
-*.PININFO I1_lin_default_fingerW_9_R0_G:I I1_lin_default_fingerW_9_R0_S:I
-*.PININFO I1_lin_default_fingerW_10_R0_D:I I1_lin_default_fingerW_10_R0_G:I
-*.PININFO I1_lin_default_fingerW_10_R0_S:I I1_lin_default_fingerW_11_R0_D:I
-*.PININFO I1_lin_default_fingerW_11_R0_G:I I1_lin_default_fingerW_11_R0_S:I
-*.PININFO I1_lin_default_fingerW_12_R0_D:I I1_lin_default_fingerW_12_R0_G:I
-*.PININFO I1_lin_default_fingerW_12_R0_S:I I1_lin_default_fingerW_13_R0_D:I
-*.PININFO I1_lin_default_fingerW_13_R0_G:I I1_lin_default_fingerW_13_R0_S:I
-*.PININFO I1_lin_default_fingerW_14_R0_D:I I1_lin_default_fingerW_14_R0_G:I
-*.PININFO I1_lin_default_fingerW_14_R0_S:I I1_lin_default_fingerW_15_R0_D:I
-*.PININFO I1_lin_default_fingerW_15_R0_G:I I1_lin_default_fingerW_15_R0_S:I
-*.PININFO I1_lin_default_fingerW_16_R0_D:I I1_lin_default_fingerW_16_R0_G:I
-*.PININFO I1_lin_default_fingerW_16_R0_S:I I1_lin_default_fingerW_17_R0_D:I
-*.PININFO I1_lin_default_fingerW_17_R0_G:I I1_lin_default_fingerW_17_R0_S:I
-*.PININFO I1_lin_default_fingerW_18_R0_D:I I1_lin_default_fingerW_18_R0_G:I
-*.PININFO I1_lin_default_fingerW_18_R0_S:I I1_lin_default_fingerW_19_R0_D:I
-*.PININFO I1_lin_default_fingerW_19_R0_G:I I1_lin_default_fingerW_19_R0_S:I
-*.PININFO I1_lin_default_fingerW_20_R0_D:I I1_lin_default_fingerW_20_R0_G:I
-*.PININFO I1_lin_default_fingerW_20_R0_S:I I1_lin_default_fingerW_21_R0_D:I
-*.PININFO I1_lin_default_fingerW_21_R0_G:I I1_lin_default_fingerW_21_R0_S:I
-*.PININFO I1_lin_default_fingerW_22_R0_D:I I1_lin_default_fingerW_22_R0_G:I
-*.PININFO I1_lin_default_fingerW_22_R0_S:I I1_lin_default_fingerW_23_R0_D:I
-*.PININFO I1_lin_default_fingerW_23_R0_G:I I1_lin_default_fingerW_23_R0_S:I
-*.PININFO I1_lin_default_fingerW_24_R0_D:I I1_lin_default_fingerW_24_R0_G:I
-*.PININFO I1_lin_default_fingerW_24_R0_S:I I1_lin_default_fingerW_25_R0_D:I
-*.PININFO I1_lin_default_fingerW_25_R0_G:I I1_lin_default_fingerW_25_R0_S:I
-*.PININFO I1_lin_default_fingerW_26_R0_D:I I1_lin_default_fingerW_26_R0_G:I
-*.PININFO I1_lin_default_fingerW_26_R0_S:I I1_lin_default_fingerW_27_R0_D:I
-*.PININFO I1_lin_default_fingerW_27_R0_G:I I1_lin_default_fingerW_27_R0_S:I
-*.PININFO I1_lin_default_fingerW_28_R0_D:I I1_lin_default_fingerW_28_R0_G:I
-*.PININFO I1_lin_default_fingerW_28_R0_S:I I1_lin_default_fingerW_29_R0_D:I
-*.PININFO I1_lin_default_fingerW_29_R0_G:I I1_lin_default_fingerW_29_R0_S:I
-*.PININFO I1_lin_default_fingerW_30_R0_D:I I1_lin_default_fingerW_30_R0_G:I
-*.PININFO I1_lin_default_fingerW_30_R0_S:I I1_lin_default_fingerW_31_R0_D:I
-*.PININFO I1_lin_default_fingerW_31_R0_G:I I1_lin_default_fingerW_31_R0_S:I
-*.PININFO I1_lin_default_fingerW_32_R0_D:I I1_lin_default_fingerW_32_R0_G:I
-*.PININFO I1_lin_default_fingerW_32_R0_S:I I1_lin_default_fingerW_33_R0_D:I
-*.PININFO I1_lin_default_fingerW_33_R0_G:I I1_lin_default_fingerW_33_R0_S:I
-*.PININFO I1_lin_default_fingerW_34_R0_D:I I1_lin_default_fingerW_34_R0_G:I
-*.PININFO I1_lin_default_fingerW_34_R0_S:I I1_lin_default_gateConn_0_R0_D:I
-*.PININFO I1_lin_default_gateConn_0_R0_G:I I1_lin_default_gateConn_0_R0_S:I
-*.PININFO I1_lin_default_gateConn_1_R0_D:I I1_lin_default_gateConn_1_R0_G:I
-*.PININFO I1_lin_default_gateConn_1_R0_S:I I1_lin_default_gateConn_2_R0_D:I
-*.PININFO I1_lin_default_gateConn_2_R0_G:I I1_lin_default_gateConn_2_R0_S:I
-*.PININFO I1_lin_default_l_0_R0_D:I I1_lin_default_l_0_R0_G:I
-*.PININFO I1_lin_default_l_0_R0_S:I I1_lin_default_l_1_R0_D:I
-*.PININFO I1_lin_default_l_1_R0_G:I I1_lin_default_l_1_R0_S:I
-*.PININFO I1_lin_default_l_2_R0_D:I I1_lin_default_l_2_R0_G:I
-*.PININFO I1_lin_default_l_2_R0_S:I I1_lin_default_l_3_R0_D:I
-*.PININFO I1_lin_default_l_3_R0_G:I I1_lin_default_l_3_R0_S:I
-*.PININFO I1_lin_default_l_4_R0_D:I I1_lin_default_l_4_R0_G:I
-*.PININFO I1_lin_default_l_4_R0_S:I I1_lin_default_l_5_R0_D:I
-*.PININFO I1_lin_default_l_5_R0_G:I I1_lin_default_l_5_R0_S:I
-*.PININFO I1_lin_default_l_6_R0_D:I I1_lin_default_l_6_R0_G:I
-*.PININFO I1_lin_default_l_6_R0_S:I I1_lin_default_l_7_R0_D:I
-*.PININFO I1_lin_default_l_7_R0_G:I I1_lin_default_l_7_R0_S:I
-*.PININFO I1_lin_default_l_8_R0_D:I I1_lin_default_l_8_R0_G:I
-*.PININFO I1_lin_default_l_8_R0_S:I I1_lin_default_l_9_R0_D:I
-*.PININFO I1_lin_default_l_9_R0_G:I I1_lin_default_l_9_R0_S:I
-*.PININFO I1_lin_default_l_10_R0_D:I I1_lin_default_l_10_R0_G:I
-*.PININFO I1_lin_default_l_10_R0_S:I I1_lin_default_l_11_R0_D:I
-*.PININFO I1_lin_default_l_11_R0_G:I I1_lin_default_l_11_R0_S:I
-*.PININFO I1_lin_default_l_12_R0_D:I I1_lin_default_l_12_R0_G:I
-*.PININFO I1_lin_default_l_12_R0_S:I I1_lin_default_l_13_R0_D:I
-*.PININFO I1_lin_default_l_13_R0_G:I I1_lin_default_l_13_R0_S:I
-*.PININFO I1_lin_default_l_14_R0_D:I I1_lin_default_l_14_R0_G:I
-*.PININFO I1_lin_default_l_14_R0_S:I I1_lin_default_l_15_R0_D:I
-*.PININFO I1_lin_default_l_15_R0_G:I I1_lin_default_l_15_R0_S:I
-*.PININFO I1_lin_default_l_16_R0_D:I I1_lin_default_l_16_R0_G:I
-*.PININFO I1_lin_default_l_16_R0_S:I I1_lin_default_l_17_R0_D:I
-*.PININFO I1_lin_default_l_17_R0_G:I I1_lin_default_l_17_R0_S:I
-*.PININFO I1_lin_default_l_18_R0_D:I I1_lin_default_l_18_R0_G:I
-*.PININFO I1_lin_default_l_18_R0_S:I I1_lin_default_l_19_R0_D:I
-*.PININFO I1_lin_default_l_19_R0_G:I I1_lin_default_l_19_R0_S:I
-*.PININFO I1_lin_default_l_20_R0_D:I I1_lin_default_l_20_R0_G:I
-*.PININFO I1_lin_default_l_20_R0_S:I I1_lin_default_l_21_R0_D:I
-*.PININFO I1_lin_default_l_21_R0_G:I I1_lin_default_l_21_R0_S:I
-*.PININFO I1_lin_default_l_22_R0_D:I I1_lin_default_l_22_R0_G:I
-*.PININFO I1_lin_default_l_22_R0_S:I I1_lin_default_l_23_R0_D:I
-*.PININFO I1_lin_default_l_23_R0_G:I I1_lin_default_l_23_R0_S:I
-*.PININFO I1_lin_default_l_24_R0_D:I I1_lin_default_l_24_R0_G:I
-*.PININFO I1_lin_default_l_24_R0_S:I I1_lin_default_l_25_R0_D:I
-*.PININFO I1_lin_default_l_25_R0_G:I I1_lin_default_l_25_R0_S:I
-*.PININFO I1_lin_default_l_26_R0_D:I I1_lin_default_l_26_R0_G:I
-*.PININFO I1_lin_default_l_26_R0_S:I I1_lin_default_l_27_R0_D:I
-*.PININFO I1_lin_default_l_27_R0_G:I I1_lin_default_l_27_R0_S:I
-*.PININFO I1_lin_default_l_28_R0_D:I I1_lin_default_l_28_R0_G:I
-*.PININFO I1_lin_default_l_28_R0_S:I I1_lin_default_l_29_R0_D:I
-*.PININFO I1_lin_default_l_29_R0_G:I I1_lin_default_l_29_R0_S:I
-*.PININFO I1_lin_default_leftTap_0_R0_D:I I1_lin_default_leftTap_0_R0_G:I
-*.PININFO I1_lin_default_leftTap_0_R0_S:I I1_lin_default_m_0_R0_D:I
-*.PININFO I1_lin_default_m_0_R0_G:I I1_lin_default_m_0_R0_S:I
-*.PININFO I1_lin_default_m_1_R0_D:I I1_lin_default_m_1_R0_G:I
-*.PININFO I1_lin_default_m_1_R0_S:I I1_lin_default_m_2_R0_D:I
-*.PININFO I1_lin_default_m_2_R0_G:I I1_lin_default_m_2_R0_S:I
-*.PININFO I1_lin_default_nf_0_R0_D:I I1_lin_default_nf_0_R0_G:I
-*.PININFO I1_lin_default_nf_0_R0_S:I I1_lin_default_nf_1_R0_D:I
-*.PININFO I1_lin_default_nf_1_R0_G:I I1_lin_default_nf_1_R0_S:I
-*.PININFO I1_lin_default_nf_2_R0_D:I I1_lin_default_nf_2_R0_G:I
-*.PININFO I1_lin_default_nf_2_R0_S:I I1_lin_default_rightTap_0_R0_D:I
-*.PININFO I1_lin_default_rightTap_0_R0_G:I I1_lin_default_rightTap_0_R0_S:I
-*.PININFO I1_lin_default_sFirst_0_R0_D:I I1_lin_default_sFirst_0_R0_G:I
-*.PININFO I1_lin_default_sFirst_0_R0_S:I I1_lin_default_sdConn_0_R0_D:I
-*.PININFO I1_lin_default_sdConn_0_R0_G:I I1_lin_default_sdConn_0_R0_S:I
-*.PININFO I1_lin_default_sdConn_1_R0_D:I I1_lin_default_sdConn_1_R0_G:I
-*.PININFO I1_lin_default_sdConn_1_R0_S:I I1_lin_default_sdConn_2_R0_D:I
-*.PININFO I1_lin_default_sdConn_2_R0_G:I I1_lin_default_sdConn_2_R0_S:I
-*.PININFO I1_lin_default_sdWidth_0_R0_D:I I1_lin_default_sdWidth_0_R0_G:I
-*.PININFO I1_lin_default_sdWidth_0_R0_S:I I1_lin_default_sdWidth_1_R0_D:I
-*.PININFO I1_lin_default_sdWidth_1_R0_G:I I1_lin_default_sdWidth_1_R0_S:I
-*.PININFO I1_lin_default_sdWidth_2_R0_D:I I1_lin_default_sdWidth_2_R0_G:I
-*.PININFO I1_lin_default_sdWidth_2_R0_S:I I1_lin_default_sdWidth_3_R0_D:I
-*.PININFO I1_lin_default_sdWidth_3_R0_G:I I1_lin_default_sdWidth_3_R0_S:I
-*.PININFO I1_lin_default_sdWidth_4_R0_D:I I1_lin_default_sdWidth_4_R0_G:I
-*.PININFO I1_lin_default_sdWidth_4_R0_S:I I1_lin_default_sdWidth_5_R0_D:I
-*.PININFO I1_lin_default_sdWidth_5_R0_G:I I1_lin_default_sdWidth_5_R0_S:I
-*.PININFO I1_lin_default_sdWidth_6_R0_D:I I1_lin_default_sdWidth_6_R0_G:I
-*.PININFO I1_lin_default_sdWidth_6_R0_S:I I1_lin_default_sdWidth_7_R0_D:I
-*.PININFO I1_lin_default_sdWidth_7_R0_G:I I1_lin_default_sdWidth_7_R0_S:I
-*.PININFO I1_lin_default_sdWidth_8_R0_D:I I1_lin_default_sdWidth_8_R0_G:I
-*.PININFO I1_lin_default_sdWidth_8_R0_S:I I1_lin_default_sdWidth_9_R0_D:I
-*.PININFO I1_lin_default_sdWidth_9_R0_G:I I1_lin_default_sdWidth_9_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_S:I I1_lin_default_topTap_0_R0_D:I
-*.PININFO I1_lin_default_topTap_0_R0_G:I I1_lin_default_topTap_0_R0_S:I vdd!:I
-MI1_lin_default_fingerW_34_R0 I1_lin_default_fingerW_34_R0_D
-+ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S vdd! nmos_1p8_nat
-+ m=1 w=1e-3 l=280n nf=10 as=296e-12 ad=260e-12 ps=1.20592e-3 pd=1.0052e-3
-+ nrd=0.000260 nrs=0.000296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_fingerW_33_R0 I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S vdd! nmos_1p8_nat
-+ m=1 w=90.24e-6 l=280n nf=1 as=39.7056e-12 ad=39.7056e-12 ps=181.36e-6
-+ pd=181.36e-6 nrd=0.004876 nrs=0.004876 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_32_R0 I1_lin_default_fingerW_32_R0_D
-+ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S vdd! nmos_1p8_nat
-+ m=1 w=75.2e-6 l=280n nf=1 as=33.088e-12 ad=33.088e-12 ps=151.28e-6
-+ pd=151.28e-6 nrd=0.005851 nrs=0.005851 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_31_R0 I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S vdd! nmos_1p8_nat
-+ m=1 w=62.665e-6 l=280n nf=1 as=27.5726e-12 ad=27.5726e-12 ps=126.21e-6
-+ pd=126.21e-6 nrd=0.007021 nrs=0.007021 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_30_R0 I1_lin_default_fingerW_30_R0_D
-+ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S vdd! nmos_1p8_nat
-+ m=1 w=52.225e-6 l=280n nf=1 as=22.979e-12 ad=22.979e-12 ps=105.33e-6
-+ pd=105.33e-6 nrd=0.008425 nrs=0.008425 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_29_R0 I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S vdd! nmos_1p8_nat
-+ m=1 w=43.52e-6 l=280n nf=1 as=19.1488e-12 ad=19.1488e-12 ps=87.92e-6
-+ pd=87.92e-6 nrd=0.010110 nrs=0.010110 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_28_R0 I1_lin_default_fingerW_28_R0_D
-+ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S vdd! nmos_1p8_nat
-+ m=1 w=36.265e-6 l=280n nf=1 as=15.9566e-12 ad=15.9566e-12 ps=73.41e-6
-+ pd=73.41e-6 nrd=0.012133 nrs=0.012133 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_27_R0 I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S vdd! nmos_1p8_nat
-+ m=1 w=30.22e-6 l=280n nf=1 as=13.2968e-12 ad=13.2968e-12 ps=61.32e-6
-+ pd=61.32e-6 nrd=0.014560 nrs=0.014560 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_26_R0 I1_lin_default_fingerW_26_R0_D
-+ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S vdd! nmos_1p8_nat
-+ m=1 w=25.185e-6 l=280n nf=1 as=11.0814e-12 ad=11.0814e-12 ps=51.25e-6
-+ pd=51.25e-6 nrd=0.017471 nrs=0.017471 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_25_R0 I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S vdd! nmos_1p8_nat
-+ m=1 w=20.985e-6 l=280n nf=1 as=9.2334e-12 ad=9.2334e-12 ps=42.85e-6
-+ pd=42.85e-6 nrd=0.020967 nrs=0.020967 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_24_R0 I1_lin_default_fingerW_24_R0_D
-+ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S vdd! nmos_1p8_nat
-+ m=1 w=17.49e-6 l=280n nf=1 as=7.6956e-12 ad=7.6956e-12 ps=35.86e-6
-+ pd=35.86e-6 nrd=0.025157 nrs=0.025157 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_23_R0 I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S vdd! nmos_1p8_nat
-+ m=1 w=14.575e-6 l=280n nf=1 as=6.413e-12 ad=6.413e-12 ps=30.03e-6
-+ pd=30.03e-6 nrd=0.030189 nrs=0.030189 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_22_R0 I1_lin_default_fingerW_22_R0_D
-+ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S vdd! nmos_1p8_nat
-+ m=1 w=12.145e-6 l=280n nf=1 as=5.3438e-12 ad=5.3438e-12 ps=25.17e-6
-+ pd=25.17e-6 nrd=0.036229 nrs=0.036229 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_21_R0 I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S vdd! nmos_1p8_nat
-+ m=1 w=10.12e-6 l=280n nf=1 as=4.4528e-12 ad=4.4528e-12 ps=21.12e-6
-+ pd=21.12e-6 nrd=0.043478 nrs=0.043478 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_20_R0 I1_lin_default_fingerW_20_R0_D
-+ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S vdd! nmos_1p8_nat
-+ m=1 w=8.435e-6 l=280n nf=1 as=3.7114e-12 ad=3.7114e-12 ps=17.75e-6
-+ pd=17.75e-6 nrd=0.052164 nrs=0.052164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_19_R0 I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S vdd! nmos_1p8_nat
-+ m=1 w=7.03e-6 l=280n nf=1 as=3.0932e-12 ad=3.0932e-12 ps=14.94e-6
-+ pd=14.94e-6 nrd=0.062589 nrs=0.062589 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_18_R0 I1_lin_default_fingerW_18_R0_D
-+ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S vdd! nmos_1p8_nat
-+ m=1 w=5.855e-6 l=280n nf=1 as=2.5762e-12 ad=2.5762e-12 ps=12.59e-6
-+ pd=12.59e-6 nrd=0.075149 nrs=0.075149 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_17_R0 I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S vdd! nmos_1p8_nat
-+ m=1 w=4.88e-6 l=280n nf=1 as=2.1472e-12 ad=2.1472e-12 ps=10.64e-6
-+ pd=10.64e-6 nrd=0.090164 nrs=0.090164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_16_R0 I1_lin_default_fingerW_16_R0_D
-+ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S vdd! nmos_1p8_nat
-+ m=1 w=4.065e-6 l=280n nf=1 as=1.7886e-12 ad=1.7886e-12 ps=9.01e-6 pd=9.01e-6
-+ nrd=0.108241 nrs=0.108241 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_15_R0 I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S vdd! nmos_1p8_nat
-+ m=1 w=3.39e-6 l=280n nf=1 as=1.4916e-12 ad=1.4916e-12 ps=7.66e-6 pd=7.66e-6
-+ nrd=0.129794 nrs=0.129794 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_14_R0 I1_lin_default_fingerW_14_R0_D
-+ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S vdd! nmos_1p8_nat
-+ m=1 w=2.825e-6 l=280n nf=1 as=1.243e-12 ad=1.243e-12 ps=6.53e-6 pd=6.53e-6
-+ nrd=0.155752 nrs=0.155752 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_13_R0 I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S vdd! nmos_1p8_nat
-+ m=1 w=2.355e-6 l=280n nf=1 as=1.0362e-12 ad=1.0362e-12 ps=5.59e-6 pd=5.59e-6
-+ nrd=0.186837 nrs=0.186837 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_12_R0 I1_lin_default_fingerW_12_R0_D
-+ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S vdd! nmos_1p8_nat
-+ m=1 w=1.96e-6 l=280n nf=1 as=862.4e-15 ad=862.4e-15 ps=4.8e-6 pd=4.8e-6
-+ nrd=0.224490 nrs=0.224490 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_11_R0 I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S vdd! nmos_1p8_nat
-+ m=1 w=1.635e-6 l=280n nf=1 as=719.4e-15 ad=719.4e-15 ps=4.15e-6 pd=4.15e-6
-+ nrd=0.269113 nrs=0.269113 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_10_R0 I1_lin_default_fingerW_10_R0_D
-+ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S vdd! nmos_1p8_nat
-+ m=1 w=1.36e-6 l=280n nf=1 as=598.4e-15 ad=598.4e-15 ps=3.6e-6 pd=3.6e-6
-+ nrd=0.323529 nrs=0.323529 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_9_R0 I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S vdd! nmos_1p8_nat
-+ m=1 w=1.135e-6 l=280n nf=1 as=499.4e-15 ad=499.4e-15 ps=3.15e-6 pd=3.15e-6
-+ nrd=0.387665 nrs=0.387665 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_8_R0 I1_lin_default_fingerW_8_R0_D
-+ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S vdd! nmos_1p8_nat
-+ m=1 w=945e-9 l=280n nf=1 as=415.8e-15 ad=415.8e-15 ps=2.77e-6 pd=2.77e-6
-+ nrd=0.465608 nrs=0.465608 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_7_R0 I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S vdd! nmos_1p8_nat
-+ m=1 w=790e-9 l=280n nf=1 as=347.6e-15 ad=347.6e-15 ps=2.46e-6 pd=2.46e-6
-+ nrd=0.556962 nrs=0.556962 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_6_R0 I1_lin_default_fingerW_6_R0_D
-+ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S vdd! nmos_1p8_nat
-+ m=1 w=655e-9 l=280n nf=1 as=288.2e-15 ad=288.2e-15 ps=2.19e-6 pd=2.19e-6
-+ nrd=0.671756 nrs=0.671756 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_5_R0 I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S vdd! nmos_1p8_nat
-+ m=1 w=545e-9 l=280n nf=1 as=239.8e-15 ad=239.8e-15 ps=1.97e-6 pd=1.97e-6
-+ nrd=0.807339 nrs=0.807339 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_4_R0 I1_lin_default_fingerW_4_R0_D
-+ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S vdd! nmos_1p8_nat
-+ m=1 w=455e-9 l=280n nf=1 as=200.2e-15 ad=200.2e-15 ps=1.79e-6 pd=1.79e-6
-+ nrd=0.967033 nrs=0.967033 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_3_R0 I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S vdd! nmos_1p8_nat
-+ m=1 w=380e-9 l=280n nf=1 as=167.2e-15 ad=167.2e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=1.157895 nrs=1.157895 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_2_R0 I1_lin_default_fingerW_2_R0_D
-+ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S vdd! nmos_1p8_nat
-+ m=1 w=315e-9 l=280n nf=1 as=161.1e-15 ad=161.1e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=1.623583 nrs=1.623583 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_1_R0 I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S vdd! nmos_1p8_nat
-+ m=1 w=265e-9 l=280n nf=1 as=156.1e-15 ad=156.1e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=2.222855 nrs=2.222855 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_0_R0 I1_lin_default_fingerW_0_R0_D
-+ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S vdd! nmos_1p8_nat
-+ m=1 w=220e-9 l=280n nf=1 as=151.6e-15 ad=151.6e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=3.132231 nrs=3.132231 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_l_29_R0 I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G
-+ I1_lin_default_l_29_R0_S vdd! nmos_1p8_nat m=1 w=1.8e-6 l=50.000u nf=5
-+ as=532.8e-15 ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444
-+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_l_28_R0 I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G
-+ I1_lin_default_l_28_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=46.155u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_27_R0 I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G
-+ I1_lin_default_l_27_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=38.465u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_26_R0 I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G
-+ I1_lin_default_l_26_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=32.055u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_25_R0 I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G
-+ I1_lin_default_l_25_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=26.710u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_24_R0 I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G
-+ I1_lin_default_l_24_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=22.260u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_23_R0 I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G
-+ I1_lin_default_l_23_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=18.550u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_22_R0 I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G
-+ I1_lin_default_l_22_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=15.460u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_21_R0 I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G
-+ I1_lin_default_l_21_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=12.880u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_20_R0 I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G
-+ I1_lin_default_l_20_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=10.735u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_19_R0 I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G
-+ I1_lin_default_l_19_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=8.945u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_18_R0 I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G
-+ I1_lin_default_l_18_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=7.455u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_17_R0 I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G
-+ I1_lin_default_l_17_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=6.210u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_16_R0 I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G
-+ I1_lin_default_l_16_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=5.175u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_15_R0 I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G
-+ I1_lin_default_l_15_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=4.315u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_14_R0 I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G
-+ I1_lin_default_l_14_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=3.595u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_13_R0 I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G
-+ I1_lin_default_l_13_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=2.995u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_12_R0 I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G
-+ I1_lin_default_l_12_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=2.495u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_11_R0 I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G
-+ I1_lin_default_l_11_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=2.080u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_10_R0 I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G
-+ I1_lin_default_l_10_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=1.735u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_9_R0 I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G
-+ I1_lin_default_l_9_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=1.445u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_8_R0 I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G
-+ I1_lin_default_l_8_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=1.205u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_7_R0 I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G
-+ I1_lin_default_l_7_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=1.005u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_6_R0 I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G
-+ I1_lin_default_l_6_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=0.835u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_5_R0 I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G
-+ I1_lin_default_l_5_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=0.695u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_4_R0 I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G
-+ I1_lin_default_l_4_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=0.580u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_3_R0 I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G
-+ I1_lin_default_l_3_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=0.485u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_2_R0 I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G
-+ I1_lin_default_l_2_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=0.405u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_1_R0 I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G
-+ I1_lin_default_l_1_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=0.335u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_0_R0 I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G
-+ I1_lin_default_l_0_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=0.280u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_nf_2_R0 I1_lin_default_nf_2_R0_D I1_lin_default_nf_2_R0_G
-+ I1_lin_default_nf_2_R0_S vdd! nmos_1p8_nat m=1 w=36e-6 l=280n nf=100
-+ as=9.4896e-12 ad=9.36e-12 ps=89.44e-6 pd=88e-6 nrd=0.007222 nrs=0.007322
-+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_nf_1_R0 I1_lin_default_nf_1_R0_D I1_lin_default_nf_1_R0_G
-+ I1_lin_default_nf_1_R0_S vdd! nmos_1p8_nat m=1 w=18.36e-6 l=280n nf=51
-+ as=4.8384e-12 ad=4.8384e-12 ps=45.6e-6 pd=45.6e-6 nrd=0.014353 nrs=0.014353
-+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_nf_0_R0 I1_lin_default_nf_0_R0_D I1_lin_default_nf_0_R0_G
-+ I1_lin_default_nf_0_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15
-+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
-+ sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_m_2_R0 I1_lin_default_m_2_R0_D I1_lin_default_m_2_R0_G
-+ I1_lin_default_m_2_R0_S vdd! nmos_1p8_nat m=100 w=360e-9 l=280n nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=100
-MI1_lin_default_m_1_R0 I1_lin_default_m_1_R0_D I1_lin_default_m_1_R0_G
-+ I1_lin_default_m_1_R0_S vdd! nmos_1p8_nat m=51 w=1.8e-6 l=280n nf=5 as=532.8e-15
-+ ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444 sa=0.440u
-+ sb=0.440u sd=0.520u dtemp=0 par=51
-MI1_lin_default_m_0_R0 I1_lin_default_m_0_R0_D I1_lin_default_m_0_R0_G
-+ I1_lin_default_m_0_R0_S vdd! nmos_1p8_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15
-+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
-+ sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_calculatedParam_2_R0 I1_lin_default_calculatedParam_2_R0_D
-+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ vdd! nmos_1p8_nat m=1 w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6
-+ pd=1.76e-6 nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0
-+ par=1
-MI1_lin_default_calculatedParam_1_R0 I1_lin_default_calculatedParam_1_R0_D
-+ I1_lin_default_calculatedParam_1_R0_G I1_lin_default_calculatedParam_1_R0_S
-+ vdd! nmos_1p8_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_calculatedParam_0_R0 I1_lin_default_calculatedParam_0_R0_D
-+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ vdd! nmos_1p8_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_gateConn_2_R0 I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S vdd! nmos_1p8_nat
-+ m=1 w=16.08e-6 l=280n nf=3 as=5.1456e-12 ad=5.1456e-12 ps=23.36e-6
-+ pd=23.36e-6 nrd=0.019900 nrs=0.019900 sa=0.440u sb=0.440u sd=0.520u dtemp=0
-+ par=1
-MI1_lin_default_gateConn_1_R0 I1_lin_default_gateConn_1_R0_D
-+ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_gateConn_0_R0 I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_9_R0 I1_lin_default_sdWidth_9_R0_D
-+ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S vdd! nmos_1p8_nat
-+ m=1 w=26.8e-6 l=280n nf=5 as=20.3144e-12 ad=20.3144e-12 ps=39.74e-6
-+ pd=39.74e-6 nrd=0.028284 nrs=0.028284 sa=1.210u sb=1.210u sd=1.290u dtemp=0
-+ par=1
-MI1_lin_default_sdWidth_8_R0 I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=432e-15 ad=432e-15 ps=3.12e-6 pd=3.12e-6
-+ nrd=3.333333 nrs=3.333333 sa=1.200u sb=1.200u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_7_R0 I1_lin_default_sdWidth_7_R0_D
-+ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=372.6e-15 ad=372.6e-15 ps=2.79e-6 pd=2.79e-6
-+ nrd=2.875000 nrs=2.875000 sa=1.035u sb=1.035u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_6_R0 I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=322.2e-15 ad=322.2e-15 ps=2.51e-6 pd=2.51e-6
-+ nrd=2.486111 nrs=2.486111 sa=0.895u sb=0.895u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_5_R0 I1_lin_default_sdWidth_5_R0_D
-+ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=280.8e-15 ad=280.8e-15 ps=2.28e-6 pd=2.28e-6
-+ nrd=2.166667 nrs=2.166667 sa=0.780u sb=0.780u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_4_R0 I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=246.6e-15 ad=246.6e-15 ps=2.09e-6 pd=2.09e-6
-+ nrd=1.902778 nrs=1.902778 sa=0.685u sb=0.685u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_3_R0 I1_lin_default_sdWidth_3_R0_D
-+ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=217.8e-15 ad=217.8e-15 ps=1.93e-6 pd=1.93e-6
-+ nrd=1.680556 nrs=1.680556 sa=0.605u sb=0.605u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_2_R0 I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=194.4e-15 ad=194.4e-15 ps=1.8e-6 pd=1.8e-6
-+ nrd=1.500000 nrs=1.500000 sa=0.540u sb=0.540u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_1_R0 I1_lin_default_sdWidth_1_R0_D
-+ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=174.6e-15 ad=174.6e-15 ps=1.69e-6 pd=1.69e-6
-+ nrd=1.347222 nrs=1.347222 sa=0.485u sb=0.485u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_0_R0 I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_sFirst_0_R0 I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S vdd! nmos_1p8_nat m=1
-+ w=16.8e-6 l=280n nf=5 as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6
-+ nrd=0.017619 nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_2_R0 I1_lin_default_sdConn_2_R0_D
-+ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S vdd! nmos_1p8_nat m=1
-+ w=13.6e-6 l=280n nf=10 as=4.0256e-12 ad=3.536e-12 ps=22.24e-6 pd=18.8e-6
-+ nrd=0.019118 nrs=0.021765 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_1_R0 I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S vdd! nmos_1p8_nat m=1
-+ w=1.08e-6 l=280n nf=3 as=345.6e-15 ad=345.6e-15 ps=3.36e-6 pd=3.36e-6
-+ nrd=0.296296 nrs=0.296296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_0_R0 I1_lin_default_sdConn_0_R0_D
-+ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S vdd! nmos_1p8_nat m=1
-+ w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6 pd=1.76e-6
-+ nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_bodytie_1_R0 I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_bodytie_0_R0 I1_lin_default_bodytie_0_R0_D
-+ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_leftTap_0_R0 I1_lin_default_leftTap_0_R0_D
-+ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_rightTap_0_R0 I1_lin_default_rightTap_0_R0_D
-+ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S vdd! nmos_1p8_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_topTap_0_R0 I1_lin_default_topTap_0_R0_D
-+ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S vdd! nmos_1p8_nat m=1
-+ w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_bottomTap_0_R0 I1_lin_default_bottomTap_0_R0_D
-+ I1_lin_default_bottomTap_0_R0_G I1_lin_default_bottomTap_0_R0_S vdd!
-+ nmos_1p8_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_4_R0 I1_lin_default_tapCntRows_4_R0_D
-+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S vdd!
-+ nmos_1p8_nat m=1 w=25.08e-6 l=280n nf=3 as=8.0256e-12 ad=8.0256e-12 ps=35.36e-6
-+ pd=35.36e-6 nrd=0.012759 nrs=0.012759 sa=0.440u sb=0.440u sd=0.520u dtemp=0
-+ par=1
-MI1_lin_default_tapCntRows_3_R0 I1_lin_default_tapCntRows_3_R0_D
-+ I1_lin_default_tapCntRows_3_R0_G I1_lin_default_tapCntRows_3_R0_S vdd!
-+ nmos_1p8_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_2_R0 I1_lin_default_tapCntRows_2_R0_D
-+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S vdd!
-+ nmos_1p8_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_1_R0 I1_lin_default_tapCntRows_1_R0_D
-+ I1_lin_default_tapCntRows_1_R0_G I1_lin_default_tapCntRows_1_R0_S vdd!
-+ nmos_1p8_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_0_R0 I1_lin_default_tapCntRows_0_R0_D
-+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S vdd!
-+ nmos_1p8_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_default I1_default_D I1_default_G I1_default_S vdd! nmos_1p8_nat m=1 w=360e-9
-+ l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222
-+ nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_3p3.cdl b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_3p3.cdl
deleted file mode 100644
index 296d33f..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_3p3.cdl
+++ /dev/null
@@ -1,748 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_library_2
-* Top Cell Name: nmos_3p3
-* View Name: schematic
-* Netlisted on: Sep 10 16:28:03 2021
-************************************************************************
-
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-*.GLOBAL vdd!
-
-*.PIN vdd!
-
-************************************************************************
-* Library Name: TCG_library_2
-* Cell Name: nmos_3p3
-* View Name: schematic
-************************************************************************
-
-.SUBCKT nmos_3p3 I1_default_D I1_default_G I1_default_S
-+ I1_lin_default_bodytie_0_R0_D I1_lin_default_bodytie_0_R0_G
-+ I1_lin_default_bodytie_0_R0_S I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S
-+ I1_lin_default_bottomTap_0_R0_D I1_lin_default_bottomTap_0_R0_G
-+ I1_lin_default_bottomTap_0_R0_S I1_lin_default_calculatedParam_0_R0_D
-+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ I1_lin_default_calculatedParam_1_R0_D I1_lin_default_calculatedParam_1_R0_G
-+ I1_lin_default_calculatedParam_1_R0_S I1_lin_default_calculatedParam_2_R0_D
-+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ I1_lin_default_fingerW_0_R0_D I1_lin_default_fingerW_0_R0_G
-+ I1_lin_default_fingerW_0_R0_S I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S
-+ I1_lin_default_fingerW_2_R0_D I1_lin_default_fingerW_2_R0_G
-+ I1_lin_default_fingerW_2_R0_S I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S
-+ I1_lin_default_fingerW_4_R0_D I1_lin_default_fingerW_4_R0_G
-+ I1_lin_default_fingerW_4_R0_S I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S
-+ I1_lin_default_fingerW_6_R0_D I1_lin_default_fingerW_6_R0_G
-+ I1_lin_default_fingerW_6_R0_S I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S
-+ I1_lin_default_fingerW_8_R0_D I1_lin_default_fingerW_8_R0_G
-+ I1_lin_default_fingerW_8_R0_S I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S
-+ I1_lin_default_fingerW_10_R0_D I1_lin_default_fingerW_10_R0_G
-+ I1_lin_default_fingerW_10_R0_S I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S
-+ I1_lin_default_fingerW_12_R0_D I1_lin_default_fingerW_12_R0_G
-+ I1_lin_default_fingerW_12_R0_S I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S
-+ I1_lin_default_fingerW_14_R0_D I1_lin_default_fingerW_14_R0_G
-+ I1_lin_default_fingerW_14_R0_S I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S
-+ I1_lin_default_fingerW_16_R0_D I1_lin_default_fingerW_16_R0_G
-+ I1_lin_default_fingerW_16_R0_S I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S
-+ I1_lin_default_fingerW_18_R0_D I1_lin_default_fingerW_18_R0_G
-+ I1_lin_default_fingerW_18_R0_S I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S
-+ I1_lin_default_fingerW_20_R0_D I1_lin_default_fingerW_20_R0_G
-+ I1_lin_default_fingerW_20_R0_S I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S
-+ I1_lin_default_fingerW_22_R0_D I1_lin_default_fingerW_22_R0_G
-+ I1_lin_default_fingerW_22_R0_S I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S
-+ I1_lin_default_fingerW_24_R0_D I1_lin_default_fingerW_24_R0_G
-+ I1_lin_default_fingerW_24_R0_S I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S
-+ I1_lin_default_fingerW_26_R0_D I1_lin_default_fingerW_26_R0_G
-+ I1_lin_default_fingerW_26_R0_S I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S
-+ I1_lin_default_fingerW_28_R0_D I1_lin_default_fingerW_28_R0_G
-+ I1_lin_default_fingerW_28_R0_S I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S
-+ I1_lin_default_fingerW_30_R0_D I1_lin_default_fingerW_30_R0_G
-+ I1_lin_default_fingerW_30_R0_S I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S
-+ I1_lin_default_fingerW_32_R0_D I1_lin_default_fingerW_32_R0_G
-+ I1_lin_default_fingerW_32_R0_S I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S
-+ I1_lin_default_fingerW_34_R0_D I1_lin_default_fingerW_34_R0_G
-+ I1_lin_default_fingerW_34_R0_S I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S
-+ I1_lin_default_gateConn_1_R0_D I1_lin_default_gateConn_1_R0_G
-+ I1_lin_default_gateConn_1_R0_S I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S
-+ I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G I1_lin_default_l_0_R0_S
-+ I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G I1_lin_default_l_1_R0_S
-+ I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G I1_lin_default_l_2_R0_S
-+ I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G I1_lin_default_l_3_R0_S
-+ I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G I1_lin_default_l_4_R0_S
-+ I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G I1_lin_default_l_5_R0_S
-+ I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G I1_lin_default_l_6_R0_S
-+ I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G I1_lin_default_l_7_R0_S
-+ I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G I1_lin_default_l_8_R0_S
-+ I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G I1_lin_default_l_9_R0_S
-+ I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G I1_lin_default_l_10_R0_S
-+ I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G I1_lin_default_l_11_R0_S
-+ I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G I1_lin_default_l_12_R0_S
-+ I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G I1_lin_default_l_13_R0_S
-+ I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G I1_lin_default_l_14_R0_S
-+ I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G I1_lin_default_l_15_R0_S
-+ I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G I1_lin_default_l_16_R0_S
-+ I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G I1_lin_default_l_17_R0_S
-+ I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G I1_lin_default_l_18_R0_S
-+ I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G I1_lin_default_l_19_R0_S
-+ I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G I1_lin_default_l_20_R0_S
-+ I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G I1_lin_default_l_21_R0_S
-+ I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G I1_lin_default_l_22_R0_S
-+ I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G I1_lin_default_l_23_R0_S
-+ I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G I1_lin_default_l_24_R0_S
-+ I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G I1_lin_default_l_25_R0_S
-+ I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G I1_lin_default_l_26_R0_S
-+ I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G I1_lin_default_l_27_R0_S
-+ I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G I1_lin_default_l_28_R0_S
-+ I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G I1_lin_default_l_29_R0_S
-+ I1_lin_default_leftTap_0_R0_D I1_lin_default_leftTap_0_R0_G
-+ I1_lin_default_leftTap_0_R0_S I1_lin_default_m_0_R0_D
-+ I1_lin_default_m_0_R0_G I1_lin_default_m_0_R0_S I1_lin_default_m_1_R0_D
-+ I1_lin_default_m_1_R0_G I1_lin_default_m_1_R0_S I1_lin_default_m_2_R0_D
-+ I1_lin_default_m_2_R0_G I1_lin_default_m_2_R0_S I1_lin_default_nf_0_R0_D
-+ I1_lin_default_nf_0_R0_G I1_lin_default_nf_0_R0_S I1_lin_default_nf_1_R0_D
-+ I1_lin_default_nf_1_R0_G I1_lin_default_nf_1_R0_S I1_lin_default_nf_2_R0_D
-+ I1_lin_default_nf_2_R0_G I1_lin_default_nf_2_R0_S
-+ I1_lin_default_rightTap_0_R0_D I1_lin_default_rightTap_0_R0_G
-+ I1_lin_default_rightTap_0_R0_S I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S
-+ I1_lin_default_sdConn_0_R0_D I1_lin_default_sdConn_0_R0_G
-+ I1_lin_default_sdConn_0_R0_S I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S
-+ I1_lin_default_sdConn_2_R0_D I1_lin_default_sdConn_2_R0_G
-+ I1_lin_default_sdConn_2_R0_S I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S
-+ I1_lin_default_sdWidth_1_R0_D I1_lin_default_sdWidth_1_R0_G
-+ I1_lin_default_sdWidth_1_R0_S I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S
-+ I1_lin_default_sdWidth_3_R0_D I1_lin_default_sdWidth_3_R0_G
-+ I1_lin_default_sdWidth_3_R0_S I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S
-+ I1_lin_default_sdWidth_5_R0_D I1_lin_default_sdWidth_5_R0_G
-+ I1_lin_default_sdWidth_5_R0_S I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S
-+ I1_lin_default_sdWidth_7_R0_D I1_lin_default_sdWidth_7_R0_G
-+ I1_lin_default_sdWidth_7_R0_S I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S
-+ I1_lin_default_sdWidth_9_R0_D I1_lin_default_sdWidth_9_R0_G
-+ I1_lin_default_sdWidth_9_R0_S I1_lin_default_tapCntRows_0_R0_D
-+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S
-+ I1_lin_default_tapCntRows_1_R0_D I1_lin_default_tapCntRows_1_R0_G
-+ I1_lin_default_tapCntRows_1_R0_S I1_lin_default_tapCntRows_2_R0_D
-+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S
-+ I1_lin_default_tapCntRows_3_R0_D I1_lin_default_tapCntRows_3_R0_G
-+ I1_lin_default_tapCntRows_3_R0_S I1_lin_default_tapCntRows_4_R0_D
-+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S
-+ I1_lin_default_topTap_0_R0_D I1_lin_default_topTap_0_R0_G
-+ I1_lin_default_topTap_0_R0_S vdd!
-*.PININFO I1_default_D:I I1_default_G:I I1_default_S:I
-*.PININFO I1_lin_default_bodytie_0_R0_D:I I1_lin_default_bodytie_0_R0_G:I
-*.PININFO I1_lin_default_bodytie_0_R0_S:I I1_lin_default_bodytie_1_R0_D:I
-*.PININFO I1_lin_default_bodytie_1_R0_G:I I1_lin_default_bodytie_1_R0_S:I
-*.PININFO I1_lin_default_bottomTap_0_R0_D:I I1_lin_default_bottomTap_0_R0_G:I
-*.PININFO I1_lin_default_bottomTap_0_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_S:I
-*.PININFO I1_lin_default_fingerW_0_R0_D:I I1_lin_default_fingerW_0_R0_G:I
-*.PININFO I1_lin_default_fingerW_0_R0_S:I I1_lin_default_fingerW_1_R0_D:I
-*.PININFO I1_lin_default_fingerW_1_R0_G:I I1_lin_default_fingerW_1_R0_S:I
-*.PININFO I1_lin_default_fingerW_2_R0_D:I I1_lin_default_fingerW_2_R0_G:I
-*.PININFO I1_lin_default_fingerW_2_R0_S:I I1_lin_default_fingerW_3_R0_D:I
-*.PININFO I1_lin_default_fingerW_3_R0_G:I I1_lin_default_fingerW_3_R0_S:I
-*.PININFO I1_lin_default_fingerW_4_R0_D:I I1_lin_default_fingerW_4_R0_G:I
-*.PININFO I1_lin_default_fingerW_4_R0_S:I I1_lin_default_fingerW_5_R0_D:I
-*.PININFO I1_lin_default_fingerW_5_R0_G:I I1_lin_default_fingerW_5_R0_S:I
-*.PININFO I1_lin_default_fingerW_6_R0_D:I I1_lin_default_fingerW_6_R0_G:I
-*.PININFO I1_lin_default_fingerW_6_R0_S:I I1_lin_default_fingerW_7_R0_D:I
-*.PININFO I1_lin_default_fingerW_7_R0_G:I I1_lin_default_fingerW_7_R0_S:I
-*.PININFO I1_lin_default_fingerW_8_R0_D:I I1_lin_default_fingerW_8_R0_G:I
-*.PININFO I1_lin_default_fingerW_8_R0_S:I I1_lin_default_fingerW_9_R0_D:I
-*.PININFO I1_lin_default_fingerW_9_R0_G:I I1_lin_default_fingerW_9_R0_S:I
-*.PININFO I1_lin_default_fingerW_10_R0_D:I I1_lin_default_fingerW_10_R0_G:I
-*.PININFO I1_lin_default_fingerW_10_R0_S:I I1_lin_default_fingerW_11_R0_D:I
-*.PININFO I1_lin_default_fingerW_11_R0_G:I I1_lin_default_fingerW_11_R0_S:I
-*.PININFO I1_lin_default_fingerW_12_R0_D:I I1_lin_default_fingerW_12_R0_G:I
-*.PININFO I1_lin_default_fingerW_12_R0_S:I I1_lin_default_fingerW_13_R0_D:I
-*.PININFO I1_lin_default_fingerW_13_R0_G:I I1_lin_default_fingerW_13_R0_S:I
-*.PININFO I1_lin_default_fingerW_14_R0_D:I I1_lin_default_fingerW_14_R0_G:I
-*.PININFO I1_lin_default_fingerW_14_R0_S:I I1_lin_default_fingerW_15_R0_D:I
-*.PININFO I1_lin_default_fingerW_15_R0_G:I I1_lin_default_fingerW_15_R0_S:I
-*.PININFO I1_lin_default_fingerW_16_R0_D:I I1_lin_default_fingerW_16_R0_G:I
-*.PININFO I1_lin_default_fingerW_16_R0_S:I I1_lin_default_fingerW_17_R0_D:I
-*.PININFO I1_lin_default_fingerW_17_R0_G:I I1_lin_default_fingerW_17_R0_S:I
-*.PININFO I1_lin_default_fingerW_18_R0_D:I I1_lin_default_fingerW_18_R0_G:I
-*.PININFO I1_lin_default_fingerW_18_R0_S:I I1_lin_default_fingerW_19_R0_D:I
-*.PININFO I1_lin_default_fingerW_19_R0_G:I I1_lin_default_fingerW_19_R0_S:I
-*.PININFO I1_lin_default_fingerW_20_R0_D:I I1_lin_default_fingerW_20_R0_G:I
-*.PININFO I1_lin_default_fingerW_20_R0_S:I I1_lin_default_fingerW_21_R0_D:I
-*.PININFO I1_lin_default_fingerW_21_R0_G:I I1_lin_default_fingerW_21_R0_S:I
-*.PININFO I1_lin_default_fingerW_22_R0_D:I I1_lin_default_fingerW_22_R0_G:I
-*.PININFO I1_lin_default_fingerW_22_R0_S:I I1_lin_default_fingerW_23_R0_D:I
-*.PININFO I1_lin_default_fingerW_23_R0_G:I I1_lin_default_fingerW_23_R0_S:I
-*.PININFO I1_lin_default_fingerW_24_R0_D:I I1_lin_default_fingerW_24_R0_G:I
-*.PININFO I1_lin_default_fingerW_24_R0_S:I I1_lin_default_fingerW_25_R0_D:I
-*.PININFO I1_lin_default_fingerW_25_R0_G:I I1_lin_default_fingerW_25_R0_S:I
-*.PININFO I1_lin_default_fingerW_26_R0_D:I I1_lin_default_fingerW_26_R0_G:I
-*.PININFO I1_lin_default_fingerW_26_R0_S:I I1_lin_default_fingerW_27_R0_D:I
-*.PININFO I1_lin_default_fingerW_27_R0_G:I I1_lin_default_fingerW_27_R0_S:I
-*.PININFO I1_lin_default_fingerW_28_R0_D:I I1_lin_default_fingerW_28_R0_G:I
-*.PININFO I1_lin_default_fingerW_28_R0_S:I I1_lin_default_fingerW_29_R0_D:I
-*.PININFO I1_lin_default_fingerW_29_R0_G:I I1_lin_default_fingerW_29_R0_S:I
-*.PININFO I1_lin_default_fingerW_30_R0_D:I I1_lin_default_fingerW_30_R0_G:I
-*.PININFO I1_lin_default_fingerW_30_R0_S:I I1_lin_default_fingerW_31_R0_D:I
-*.PININFO I1_lin_default_fingerW_31_R0_G:I I1_lin_default_fingerW_31_R0_S:I
-*.PININFO I1_lin_default_fingerW_32_R0_D:I I1_lin_default_fingerW_32_R0_G:I
-*.PININFO I1_lin_default_fingerW_32_R0_S:I I1_lin_default_fingerW_33_R0_D:I
-*.PININFO I1_lin_default_fingerW_33_R0_G:I I1_lin_default_fingerW_33_R0_S:I
-*.PININFO I1_lin_default_fingerW_34_R0_D:I I1_lin_default_fingerW_34_R0_G:I
-*.PININFO I1_lin_default_fingerW_34_R0_S:I I1_lin_default_gateConn_0_R0_D:I
-*.PININFO I1_lin_default_gateConn_0_R0_G:I I1_lin_default_gateConn_0_R0_S:I
-*.PININFO I1_lin_default_gateConn_1_R0_D:I I1_lin_default_gateConn_1_R0_G:I
-*.PININFO I1_lin_default_gateConn_1_R0_S:I I1_lin_default_gateConn_2_R0_D:I
-*.PININFO I1_lin_default_gateConn_2_R0_G:I I1_lin_default_gateConn_2_R0_S:I
-*.PININFO I1_lin_default_l_0_R0_D:I I1_lin_default_l_0_R0_G:I
-*.PININFO I1_lin_default_l_0_R0_S:I I1_lin_default_l_1_R0_D:I
-*.PININFO I1_lin_default_l_1_R0_G:I I1_lin_default_l_1_R0_S:I
-*.PININFO I1_lin_default_l_2_R0_D:I I1_lin_default_l_2_R0_G:I
-*.PININFO I1_lin_default_l_2_R0_S:I I1_lin_default_l_3_R0_D:I
-*.PININFO I1_lin_default_l_3_R0_G:I I1_lin_default_l_3_R0_S:I
-*.PININFO I1_lin_default_l_4_R0_D:I I1_lin_default_l_4_R0_G:I
-*.PININFO I1_lin_default_l_4_R0_S:I I1_lin_default_l_5_R0_D:I
-*.PININFO I1_lin_default_l_5_R0_G:I I1_lin_default_l_5_R0_S:I
-*.PININFO I1_lin_default_l_6_R0_D:I I1_lin_default_l_6_R0_G:I
-*.PININFO I1_lin_default_l_6_R0_S:I I1_lin_default_l_7_R0_D:I
-*.PININFO I1_lin_default_l_7_R0_G:I I1_lin_default_l_7_R0_S:I
-*.PININFO I1_lin_default_l_8_R0_D:I I1_lin_default_l_8_R0_G:I
-*.PININFO I1_lin_default_l_8_R0_S:I I1_lin_default_l_9_R0_D:I
-*.PININFO I1_lin_default_l_9_R0_G:I I1_lin_default_l_9_R0_S:I
-*.PININFO I1_lin_default_l_10_R0_D:I I1_lin_default_l_10_R0_G:I
-*.PININFO I1_lin_default_l_10_R0_S:I I1_lin_default_l_11_R0_D:I
-*.PININFO I1_lin_default_l_11_R0_G:I I1_lin_default_l_11_R0_S:I
-*.PININFO I1_lin_default_l_12_R0_D:I I1_lin_default_l_12_R0_G:I
-*.PININFO I1_lin_default_l_12_R0_S:I I1_lin_default_l_13_R0_D:I
-*.PININFO I1_lin_default_l_13_R0_G:I I1_lin_default_l_13_R0_S:I
-*.PININFO I1_lin_default_l_14_R0_D:I I1_lin_default_l_14_R0_G:I
-*.PININFO I1_lin_default_l_14_R0_S:I I1_lin_default_l_15_R0_D:I
-*.PININFO I1_lin_default_l_15_R0_G:I I1_lin_default_l_15_R0_S:I
-*.PININFO I1_lin_default_l_16_R0_D:I I1_lin_default_l_16_R0_G:I
-*.PININFO I1_lin_default_l_16_R0_S:I I1_lin_default_l_17_R0_D:I
-*.PININFO I1_lin_default_l_17_R0_G:I I1_lin_default_l_17_R0_S:I
-*.PININFO I1_lin_default_l_18_R0_D:I I1_lin_default_l_18_R0_G:I
-*.PININFO I1_lin_default_l_18_R0_S:I I1_lin_default_l_19_R0_D:I
-*.PININFO I1_lin_default_l_19_R0_G:I I1_lin_default_l_19_R0_S:I
-*.PININFO I1_lin_default_l_20_R0_D:I I1_lin_default_l_20_R0_G:I
-*.PININFO I1_lin_default_l_20_R0_S:I I1_lin_default_l_21_R0_D:I
-*.PININFO I1_lin_default_l_21_R0_G:I I1_lin_default_l_21_R0_S:I
-*.PININFO I1_lin_default_l_22_R0_D:I I1_lin_default_l_22_R0_G:I
-*.PININFO I1_lin_default_l_22_R0_S:I I1_lin_default_l_23_R0_D:I
-*.PININFO I1_lin_default_l_23_R0_G:I I1_lin_default_l_23_R0_S:I
-*.PININFO I1_lin_default_l_24_R0_D:I I1_lin_default_l_24_R0_G:I
-*.PININFO I1_lin_default_l_24_R0_S:I I1_lin_default_l_25_R0_D:I
-*.PININFO I1_lin_default_l_25_R0_G:I I1_lin_default_l_25_R0_S:I
-*.PININFO I1_lin_default_l_26_R0_D:I I1_lin_default_l_26_R0_G:I
-*.PININFO I1_lin_default_l_26_R0_S:I I1_lin_default_l_27_R0_D:I
-*.PININFO I1_lin_default_l_27_R0_G:I I1_lin_default_l_27_R0_S:I
-*.PININFO I1_lin_default_l_28_R0_D:I I1_lin_default_l_28_R0_G:I
-*.PININFO I1_lin_default_l_28_R0_S:I I1_lin_default_l_29_R0_D:I
-*.PININFO I1_lin_default_l_29_R0_G:I I1_lin_default_l_29_R0_S:I
-*.PININFO I1_lin_default_leftTap_0_R0_D:I I1_lin_default_leftTap_0_R0_G:I
-*.PININFO I1_lin_default_leftTap_0_R0_S:I I1_lin_default_m_0_R0_D:I
-*.PININFO I1_lin_default_m_0_R0_G:I I1_lin_default_m_0_R0_S:I
-*.PININFO I1_lin_default_m_1_R0_D:I I1_lin_default_m_1_R0_G:I
-*.PININFO I1_lin_default_m_1_R0_S:I I1_lin_default_m_2_R0_D:I
-*.PININFO I1_lin_default_m_2_R0_G:I I1_lin_default_m_2_R0_S:I
-*.PININFO I1_lin_default_nf_0_R0_D:I I1_lin_default_nf_0_R0_G:I
-*.PININFO I1_lin_default_nf_0_R0_S:I I1_lin_default_nf_1_R0_D:I
-*.PININFO I1_lin_default_nf_1_R0_G:I I1_lin_default_nf_1_R0_S:I
-*.PININFO I1_lin_default_nf_2_R0_D:I I1_lin_default_nf_2_R0_G:I
-*.PININFO I1_lin_default_nf_2_R0_S:I I1_lin_default_rightTap_0_R0_D:I
-*.PININFO I1_lin_default_rightTap_0_R0_G:I I1_lin_default_rightTap_0_R0_S:I
-*.PININFO I1_lin_default_sFirst_0_R0_D:I I1_lin_default_sFirst_0_R0_G:I
-*.PININFO I1_lin_default_sFirst_0_R0_S:I I1_lin_default_sdConn_0_R0_D:I
-*.PININFO I1_lin_default_sdConn_0_R0_G:I I1_lin_default_sdConn_0_R0_S:I
-*.PININFO I1_lin_default_sdConn_1_R0_D:I I1_lin_default_sdConn_1_R0_G:I
-*.PININFO I1_lin_default_sdConn_1_R0_S:I I1_lin_default_sdConn_2_R0_D:I
-*.PININFO I1_lin_default_sdConn_2_R0_G:I I1_lin_default_sdConn_2_R0_S:I
-*.PININFO I1_lin_default_sdWidth_0_R0_D:I I1_lin_default_sdWidth_0_R0_G:I
-*.PININFO I1_lin_default_sdWidth_0_R0_S:I I1_lin_default_sdWidth_1_R0_D:I
-*.PININFO I1_lin_default_sdWidth_1_R0_G:I I1_lin_default_sdWidth_1_R0_S:I
-*.PININFO I1_lin_default_sdWidth_2_R0_D:I I1_lin_default_sdWidth_2_R0_G:I
-*.PININFO I1_lin_default_sdWidth_2_R0_S:I I1_lin_default_sdWidth_3_R0_D:I
-*.PININFO I1_lin_default_sdWidth_3_R0_G:I I1_lin_default_sdWidth_3_R0_S:I
-*.PININFO I1_lin_default_sdWidth_4_R0_D:I I1_lin_default_sdWidth_4_R0_G:I
-*.PININFO I1_lin_default_sdWidth_4_R0_S:I I1_lin_default_sdWidth_5_R0_D:I
-*.PININFO I1_lin_default_sdWidth_5_R0_G:I I1_lin_default_sdWidth_5_R0_S:I
-*.PININFO I1_lin_default_sdWidth_6_R0_D:I I1_lin_default_sdWidth_6_R0_G:I
-*.PININFO I1_lin_default_sdWidth_6_R0_S:I I1_lin_default_sdWidth_7_R0_D:I
-*.PININFO I1_lin_default_sdWidth_7_R0_G:I I1_lin_default_sdWidth_7_R0_S:I
-*.PININFO I1_lin_default_sdWidth_8_R0_D:I I1_lin_default_sdWidth_8_R0_G:I
-*.PININFO I1_lin_default_sdWidth_8_R0_S:I I1_lin_default_sdWidth_9_R0_D:I
-*.PININFO I1_lin_default_sdWidth_9_R0_G:I I1_lin_default_sdWidth_9_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_S:I I1_lin_default_topTap_0_R0_D:I
-*.PININFO I1_lin_default_topTap_0_R0_G:I I1_lin_default_topTap_0_R0_S:I vdd!:I
-MI1_lin_default_fingerW_34_R0 I1_lin_default_fingerW_34_R0_D
-+ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S vdd! nmos_3p3
-+ m=1 w=1e-3 l=280n nf=10 as=296e-12 ad=260e-12 ps=1.20592e-3 pd=1.0052e-3
-+ nrd=0.000260 nrs=0.000296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_fingerW_33_R0 I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S vdd! nmos_3p3
-+ m=1 w=90.24e-6 l=280n nf=1 as=39.7056e-12 ad=39.7056e-12 ps=181.36e-6
-+ pd=181.36e-6 nrd=0.004876 nrs=0.004876 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_32_R0 I1_lin_default_fingerW_32_R0_D
-+ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S vdd! nmos_3p3
-+ m=1 w=75.2e-6 l=280n nf=1 as=33.088e-12 ad=33.088e-12 ps=151.28e-6
-+ pd=151.28e-6 nrd=0.005851 nrs=0.005851 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_31_R0 I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S vdd! nmos_3p3
-+ m=1 w=62.665e-6 l=280n nf=1 as=27.5726e-12 ad=27.5726e-12 ps=126.21e-6
-+ pd=126.21e-6 nrd=0.007021 nrs=0.007021 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_30_R0 I1_lin_default_fingerW_30_R0_D
-+ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S vdd! nmos_3p3
-+ m=1 w=52.225e-6 l=280n nf=1 as=22.979e-12 ad=22.979e-12 ps=105.33e-6
-+ pd=105.33e-6 nrd=0.008425 nrs=0.008425 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_29_R0 I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S vdd! nmos_3p3
-+ m=1 w=43.52e-6 l=280n nf=1 as=19.1488e-12 ad=19.1488e-12 ps=87.92e-6
-+ pd=87.92e-6 nrd=0.010110 nrs=0.010110 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_28_R0 I1_lin_default_fingerW_28_R0_D
-+ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S vdd! nmos_3p3
-+ m=1 w=36.265e-6 l=280n nf=1 as=15.9566e-12 ad=15.9566e-12 ps=73.41e-6
-+ pd=73.41e-6 nrd=0.012133 nrs=0.012133 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_27_R0 I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S vdd! nmos_3p3
-+ m=1 w=30.22e-6 l=280n nf=1 as=13.2968e-12 ad=13.2968e-12 ps=61.32e-6
-+ pd=61.32e-6 nrd=0.014560 nrs=0.014560 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_26_R0 I1_lin_default_fingerW_26_R0_D
-+ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S vdd! nmos_3p3
-+ m=1 w=25.185e-6 l=280n nf=1 as=11.0814e-12 ad=11.0814e-12 ps=51.25e-6
-+ pd=51.25e-6 nrd=0.017471 nrs=0.017471 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_25_R0 I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S vdd! nmos_3p3
-+ m=1 w=20.985e-6 l=280n nf=1 as=9.2334e-12 ad=9.2334e-12 ps=42.85e-6
-+ pd=42.85e-6 nrd=0.020967 nrs=0.020967 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_24_R0 I1_lin_default_fingerW_24_R0_D
-+ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S vdd! nmos_3p3
-+ m=1 w=17.49e-6 l=280n nf=1 as=7.6956e-12 ad=7.6956e-12 ps=35.86e-6
-+ pd=35.86e-6 nrd=0.025157 nrs=0.025157 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_23_R0 I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S vdd! nmos_3p3
-+ m=1 w=14.575e-6 l=280n nf=1 as=6.413e-12 ad=6.413e-12 ps=30.03e-6
-+ pd=30.03e-6 nrd=0.030189 nrs=0.030189 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_22_R0 I1_lin_default_fingerW_22_R0_D
-+ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S vdd! nmos_3p3
-+ m=1 w=12.145e-6 l=280n nf=1 as=5.3438e-12 ad=5.3438e-12 ps=25.17e-6
-+ pd=25.17e-6 nrd=0.036229 nrs=0.036229 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_21_R0 I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S vdd! nmos_3p3
-+ m=1 w=10.12e-6 l=280n nf=1 as=4.4528e-12 ad=4.4528e-12 ps=21.12e-6
-+ pd=21.12e-6 nrd=0.043478 nrs=0.043478 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_20_R0 I1_lin_default_fingerW_20_R0_D
-+ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S vdd! nmos_3p3
-+ m=1 w=8.435e-6 l=280n nf=1 as=3.7114e-12 ad=3.7114e-12 ps=17.75e-6
-+ pd=17.75e-6 nrd=0.052164 nrs=0.052164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_19_R0 I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S vdd! nmos_3p3
-+ m=1 w=7.03e-6 l=280n nf=1 as=3.0932e-12 ad=3.0932e-12 ps=14.94e-6
-+ pd=14.94e-6 nrd=0.062589 nrs=0.062589 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_18_R0 I1_lin_default_fingerW_18_R0_D
-+ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S vdd! nmos_3p3
-+ m=1 w=5.855e-6 l=280n nf=1 as=2.5762e-12 ad=2.5762e-12 ps=12.59e-6
-+ pd=12.59e-6 nrd=0.075149 nrs=0.075149 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_17_R0 I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S vdd! nmos_3p3
-+ m=1 w=4.88e-6 l=280n nf=1 as=2.1472e-12 ad=2.1472e-12 ps=10.64e-6
-+ pd=10.64e-6 nrd=0.090164 nrs=0.090164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_16_R0 I1_lin_default_fingerW_16_R0_D
-+ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S vdd! nmos_3p3
-+ m=1 w=4.065e-6 l=280n nf=1 as=1.7886e-12 ad=1.7886e-12 ps=9.01e-6 pd=9.01e-6
-+ nrd=0.108241 nrs=0.108241 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_15_R0 I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S vdd! nmos_3p3
-+ m=1 w=3.39e-6 l=280n nf=1 as=1.4916e-12 ad=1.4916e-12 ps=7.66e-6 pd=7.66e-6
-+ nrd=0.129794 nrs=0.129794 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_14_R0 I1_lin_default_fingerW_14_R0_D
-+ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S vdd! nmos_3p3
-+ m=1 w=2.825e-6 l=280n nf=1 as=1.243e-12 ad=1.243e-12 ps=6.53e-6 pd=6.53e-6
-+ nrd=0.155752 nrs=0.155752 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_13_R0 I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S vdd! nmos_3p3
-+ m=1 w=2.355e-6 l=280n nf=1 as=1.0362e-12 ad=1.0362e-12 ps=5.59e-6 pd=5.59e-6
-+ nrd=0.186837 nrs=0.186837 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_12_R0 I1_lin_default_fingerW_12_R0_D
-+ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S vdd! nmos_3p3
-+ m=1 w=1.96e-6 l=280n nf=1 as=862.4e-15 ad=862.4e-15 ps=4.8e-6 pd=4.8e-6
-+ nrd=0.224490 nrs=0.224490 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_11_R0 I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S vdd! nmos_3p3
-+ m=1 w=1.635e-6 l=280n nf=1 as=719.4e-15 ad=719.4e-15 ps=4.15e-6 pd=4.15e-6
-+ nrd=0.269113 nrs=0.269113 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_10_R0 I1_lin_default_fingerW_10_R0_D
-+ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S vdd! nmos_3p3
-+ m=1 w=1.36e-6 l=280n nf=1 as=598.4e-15 ad=598.4e-15 ps=3.6e-6 pd=3.6e-6
-+ nrd=0.323529 nrs=0.323529 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_9_R0 I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S vdd! nmos_3p3
-+ m=1 w=1.135e-6 l=280n nf=1 as=499.4e-15 ad=499.4e-15 ps=3.15e-6 pd=3.15e-6
-+ nrd=0.387665 nrs=0.387665 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_8_R0 I1_lin_default_fingerW_8_R0_D
-+ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S vdd! nmos_3p3
-+ m=1 w=945e-9 l=280n nf=1 as=415.8e-15 ad=415.8e-15 ps=2.77e-6 pd=2.77e-6
-+ nrd=0.465608 nrs=0.465608 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_7_R0 I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S vdd! nmos_3p3
-+ m=1 w=790e-9 l=280n nf=1 as=347.6e-15 ad=347.6e-15 ps=2.46e-6 pd=2.46e-6
-+ nrd=0.556962 nrs=0.556962 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_6_R0 I1_lin_default_fingerW_6_R0_D
-+ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S vdd! nmos_3p3
-+ m=1 w=655e-9 l=280n nf=1 as=288.2e-15 ad=288.2e-15 ps=2.19e-6 pd=2.19e-6
-+ nrd=0.671756 nrs=0.671756 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_5_R0 I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S vdd! nmos_3p3
-+ m=1 w=545e-9 l=280n nf=1 as=239.8e-15 ad=239.8e-15 ps=1.97e-6 pd=1.97e-6
-+ nrd=0.807339 nrs=0.807339 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_4_R0 I1_lin_default_fingerW_4_R0_D
-+ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S vdd! nmos_3p3
-+ m=1 w=455e-9 l=280n nf=1 as=200.2e-15 ad=200.2e-15 ps=1.79e-6 pd=1.79e-6
-+ nrd=0.967033 nrs=0.967033 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_3_R0 I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S vdd! nmos_3p3
-+ m=1 w=380e-9 l=280n nf=1 as=167.2e-15 ad=167.2e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=1.157895 nrs=1.157895 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_2_R0 I1_lin_default_fingerW_2_R0_D
-+ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S vdd! nmos_3p3
-+ m=1 w=315e-9 l=280n nf=1 as=161.1e-15 ad=161.1e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=1.623583 nrs=1.623583 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_1_R0 I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S vdd! nmos_3p3
-+ m=1 w=265e-9 l=280n nf=1 as=156.1e-15 ad=156.1e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=2.222855 nrs=2.222855 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_0_R0 I1_lin_default_fingerW_0_R0_D
-+ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S vdd! nmos_3p3
-+ m=1 w=220e-9 l=280n nf=1 as=151.6e-15 ad=151.6e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=3.132231 nrs=3.132231 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_l_29_R0 I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G
-+ I1_lin_default_l_29_R0_S vdd! nmos_3p3 m=1 w=1.8e-6 l=50.000u nf=5
-+ as=532.8e-15 ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444
-+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_l_28_R0 I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G
-+ I1_lin_default_l_28_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=46.155u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_27_R0 I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G
-+ I1_lin_default_l_27_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=38.465u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_26_R0 I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G
-+ I1_lin_default_l_26_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=32.055u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_25_R0 I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G
-+ I1_lin_default_l_25_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=26.710u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_24_R0 I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G
-+ I1_lin_default_l_24_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=22.260u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_23_R0 I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G
-+ I1_lin_default_l_23_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=18.550u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_22_R0 I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G
-+ I1_lin_default_l_22_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=15.460u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_21_R0 I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G
-+ I1_lin_default_l_21_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=12.880u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_20_R0 I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G
-+ I1_lin_default_l_20_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=10.735u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_19_R0 I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G
-+ I1_lin_default_l_19_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=8.945u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_18_R0 I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G
-+ I1_lin_default_l_18_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=7.455u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_17_R0 I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G
-+ I1_lin_default_l_17_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=6.210u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_16_R0 I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G
-+ I1_lin_default_l_16_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=5.175u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_15_R0 I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G
-+ I1_lin_default_l_15_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=4.315u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_14_R0 I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G
-+ I1_lin_default_l_14_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=3.595u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_13_R0 I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G
-+ I1_lin_default_l_13_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=2.995u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_12_R0 I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G
-+ I1_lin_default_l_12_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=2.495u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_11_R0 I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G
-+ I1_lin_default_l_11_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=2.080u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_10_R0 I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G
-+ I1_lin_default_l_10_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=1.735u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_9_R0 I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G
-+ I1_lin_default_l_9_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=1.445u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_8_R0 I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G
-+ I1_lin_default_l_8_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=1.205u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_7_R0 I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G
-+ I1_lin_default_l_7_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=1.005u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_6_R0 I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G
-+ I1_lin_default_l_6_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=0.835u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_5_R0 I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G
-+ I1_lin_default_l_5_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=0.695u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_4_R0 I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G
-+ I1_lin_default_l_4_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=0.580u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_3_R0 I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G
-+ I1_lin_default_l_3_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=0.485u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_2_R0 I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G
-+ I1_lin_default_l_2_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=0.405u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_1_R0 I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G
-+ I1_lin_default_l_1_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=0.335u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_0_R0 I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G
-+ I1_lin_default_l_0_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=0.280u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_nf_2_R0 I1_lin_default_nf_2_R0_D I1_lin_default_nf_2_R0_G
-+ I1_lin_default_nf_2_R0_S vdd! nmos_3p3 m=1 w=36e-6 l=280n nf=100
-+ as=9.4896e-12 ad=9.36e-12 ps=89.44e-6 pd=88e-6 nrd=0.007222 nrs=0.007322
-+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_nf_1_R0 I1_lin_default_nf_1_R0_D I1_lin_default_nf_1_R0_G
-+ I1_lin_default_nf_1_R0_S vdd! nmos_3p3 m=1 w=18.36e-6 l=280n nf=51
-+ as=4.8384e-12 ad=4.8384e-12 ps=45.6e-6 pd=45.6e-6 nrd=0.014353 nrs=0.014353
-+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_nf_0_R0 I1_lin_default_nf_0_R0_D I1_lin_default_nf_0_R0_G
-+ I1_lin_default_nf_0_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
-+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
-+ sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_m_2_R0 I1_lin_default_m_2_R0_D I1_lin_default_m_2_R0_G
-+ I1_lin_default_m_2_R0_S vdd! nmos_3p3 m=100 w=360e-9 l=280n nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=100
-MI1_lin_default_m_1_R0 I1_lin_default_m_1_R0_D I1_lin_default_m_1_R0_G
-+ I1_lin_default_m_1_R0_S vdd! nmos_3p3 m=51 w=1.8e-6 l=280n nf=5 as=532.8e-15
-+ ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444 sa=0.440u
-+ sb=0.440u sd=0.520u dtemp=0 par=51
-MI1_lin_default_m_0_R0 I1_lin_default_m_0_R0_D I1_lin_default_m_0_R0_G
-+ I1_lin_default_m_0_R0_S vdd! nmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
-+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
-+ sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_calculatedParam_2_R0 I1_lin_default_calculatedParam_2_R0_D
-+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ vdd! nmos_3p3 m=1 w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6
-+ pd=1.76e-6 nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0
-+ par=1
-MI1_lin_default_calculatedParam_1_R0 I1_lin_default_calculatedParam_1_R0_D
-+ I1_lin_default_calculatedParam_1_R0_G I1_lin_default_calculatedParam_1_R0_S
-+ vdd! nmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_calculatedParam_0_R0 I1_lin_default_calculatedParam_0_R0_D
-+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ vdd! nmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_gateConn_2_R0 I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S vdd! nmos_3p3
-+ m=1 w=16.08e-6 l=280n nf=3 as=5.1456e-12 ad=5.1456e-12 ps=23.36e-6
-+ pd=23.36e-6 nrd=0.019900 nrs=0.019900 sa=0.440u sb=0.440u sd=0.520u dtemp=0
-+ par=1
-MI1_lin_default_gateConn_1_R0 I1_lin_default_gateConn_1_R0_D
-+ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_gateConn_0_R0 I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_9_R0 I1_lin_default_sdWidth_9_R0_D
-+ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S vdd! nmos_3p3
-+ m=1 w=26.8e-6 l=280n nf=5 as=20.3144e-12 ad=20.3144e-12 ps=39.74e-6
-+ pd=39.74e-6 nrd=0.028284 nrs=0.028284 sa=1.210u sb=1.210u sd=1.290u dtemp=0
-+ par=1
-MI1_lin_default_sdWidth_8_R0 I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=432e-15 ad=432e-15 ps=3.12e-6 pd=3.12e-6
-+ nrd=3.333333 nrs=3.333333 sa=1.200u sb=1.200u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_7_R0 I1_lin_default_sdWidth_7_R0_D
-+ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=372.6e-15 ad=372.6e-15 ps=2.79e-6 pd=2.79e-6
-+ nrd=2.875000 nrs=2.875000 sa=1.035u sb=1.035u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_6_R0 I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=322.2e-15 ad=322.2e-15 ps=2.51e-6 pd=2.51e-6
-+ nrd=2.486111 nrs=2.486111 sa=0.895u sb=0.895u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_5_R0 I1_lin_default_sdWidth_5_R0_D
-+ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=280.8e-15 ad=280.8e-15 ps=2.28e-6 pd=2.28e-6
-+ nrd=2.166667 nrs=2.166667 sa=0.780u sb=0.780u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_4_R0 I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=246.6e-15 ad=246.6e-15 ps=2.09e-6 pd=2.09e-6
-+ nrd=1.902778 nrs=1.902778 sa=0.685u sb=0.685u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_3_R0 I1_lin_default_sdWidth_3_R0_D
-+ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=217.8e-15 ad=217.8e-15 ps=1.93e-6 pd=1.93e-6
-+ nrd=1.680556 nrs=1.680556 sa=0.605u sb=0.605u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_2_R0 I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=194.4e-15 ad=194.4e-15 ps=1.8e-6 pd=1.8e-6
-+ nrd=1.500000 nrs=1.500000 sa=0.540u sb=0.540u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_1_R0 I1_lin_default_sdWidth_1_R0_D
-+ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=174.6e-15 ad=174.6e-15 ps=1.69e-6 pd=1.69e-6
-+ nrd=1.347222 nrs=1.347222 sa=0.485u sb=0.485u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_0_R0 I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_sFirst_0_R0 I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S vdd! nmos_3p3 m=1
-+ w=16.8e-6 l=280n nf=5 as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6
-+ nrd=0.017619 nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_2_R0 I1_lin_default_sdConn_2_R0_D
-+ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S vdd! nmos_3p3 m=1
-+ w=13.6e-6 l=280n nf=10 as=4.0256e-12 ad=3.536e-12 ps=22.24e-6 pd=18.8e-6
-+ nrd=0.019118 nrs=0.021765 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_1_R0 I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S vdd! nmos_3p3 m=1
-+ w=1.08e-6 l=280n nf=3 as=345.6e-15 ad=345.6e-15 ps=3.36e-6 pd=3.36e-6
-+ nrd=0.296296 nrs=0.296296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_0_R0 I1_lin_default_sdConn_0_R0_D
-+ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S vdd! nmos_3p3 m=1
-+ w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6 pd=1.76e-6
-+ nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_bodytie_1_R0 I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_bodytie_0_R0 I1_lin_default_bodytie_0_R0_D
-+ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_leftTap_0_R0 I1_lin_default_leftTap_0_R0_D
-+ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_rightTap_0_R0 I1_lin_default_rightTap_0_R0_D
-+ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S vdd! nmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_topTap_0_R0 I1_lin_default_topTap_0_R0_D
-+ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S vdd! nmos_3p3 m=1
-+ w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_bottomTap_0_R0 I1_lin_default_bottomTap_0_R0_D
-+ I1_lin_default_bottomTap_0_R0_G I1_lin_default_bottomTap_0_R0_S vdd!
-+ nmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_4_R0 I1_lin_default_tapCntRows_4_R0_D
-+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S vdd!
-+ nmos_3p3 m=1 w=25.08e-6 l=280n nf=3 as=8.0256e-12 ad=8.0256e-12 ps=35.36e-6
-+ pd=35.36e-6 nrd=0.012759 nrs=0.012759 sa=0.440u sb=0.440u sd=0.520u dtemp=0
-+ par=1
-MI1_lin_default_tapCntRows_3_R0 I1_lin_default_tapCntRows_3_R0_D
-+ I1_lin_default_tapCntRows_3_R0_G I1_lin_default_tapCntRows_3_R0_S vdd!
-+ nmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_2_R0 I1_lin_default_tapCntRows_2_R0_D
-+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S vdd!
-+ nmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_1_R0 I1_lin_default_tapCntRows_1_R0_D
-+ I1_lin_default_tapCntRows_1_R0_G I1_lin_default_tapCntRows_1_R0_S vdd!
-+ nmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_0_R0 I1_lin_default_tapCntRows_0_R0_D
-+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S vdd!
-+ nmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_default I1_default_D I1_default_G I1_default_S vdd! nmos_3p3 m=1 w=360e-9
-+ l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222
-+ nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_3p3_nat.cdl b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_3p3_nat.cdl
deleted file mode 100644
index 2ceb742..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/nmos_3p3_nat.cdl
+++ /dev/null
@@ -1,748 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_library_2
-* Top Cell Name: nmos_3p3_nat
-* View Name: schematic
-* Netlisted on: Sep 10 16:28:03 2021
-************************************************************************
-
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-*.GLOBAL vdd!
-
-*.PIN vdd!
-
-************************************************************************
-* Library Name: TCG_library_2
-* Cell Name: nmos_3p3_nat
-* View Name: schematic
-************************************************************************
-
-.SUBCKT nmos_3p3_nat I1_default_D I1_default_G I1_default_S
-+ I1_lin_default_bodytie_0_R0_D I1_lin_default_bodytie_0_R0_G
-+ I1_lin_default_bodytie_0_R0_S I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S
-+ I1_lin_default_bottomTap_0_R0_D I1_lin_default_bottomTap_0_R0_G
-+ I1_lin_default_bottomTap_0_R0_S I1_lin_default_calculatedParam_0_R0_D
-+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ I1_lin_default_calculatedParam_1_R0_D I1_lin_default_calculatedParam_1_R0_G
-+ I1_lin_default_calculatedParam_1_R0_S I1_lin_default_calculatedParam_2_R0_D
-+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ I1_lin_default_fingerW_0_R0_D I1_lin_default_fingerW_0_R0_G
-+ I1_lin_default_fingerW_0_R0_S I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S
-+ I1_lin_default_fingerW_2_R0_D I1_lin_default_fingerW_2_R0_G
-+ I1_lin_default_fingerW_2_R0_S I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S
-+ I1_lin_default_fingerW_4_R0_D I1_lin_default_fingerW_4_R0_G
-+ I1_lin_default_fingerW_4_R0_S I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S
-+ I1_lin_default_fingerW_6_R0_D I1_lin_default_fingerW_6_R0_G
-+ I1_lin_default_fingerW_6_R0_S I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S
-+ I1_lin_default_fingerW_8_R0_D I1_lin_default_fingerW_8_R0_G
-+ I1_lin_default_fingerW_8_R0_S I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S
-+ I1_lin_default_fingerW_10_R0_D I1_lin_default_fingerW_10_R0_G
-+ I1_lin_default_fingerW_10_R0_S I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S
-+ I1_lin_default_fingerW_12_R0_D I1_lin_default_fingerW_12_R0_G
-+ I1_lin_default_fingerW_12_R0_S I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S
-+ I1_lin_default_fingerW_14_R0_D I1_lin_default_fingerW_14_R0_G
-+ I1_lin_default_fingerW_14_R0_S I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S
-+ I1_lin_default_fingerW_16_R0_D I1_lin_default_fingerW_16_R0_G
-+ I1_lin_default_fingerW_16_R0_S I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S
-+ I1_lin_default_fingerW_18_R0_D I1_lin_default_fingerW_18_R0_G
-+ I1_lin_default_fingerW_18_R0_S I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S
-+ I1_lin_default_fingerW_20_R0_D I1_lin_default_fingerW_20_R0_G
-+ I1_lin_default_fingerW_20_R0_S I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S
-+ I1_lin_default_fingerW_22_R0_D I1_lin_default_fingerW_22_R0_G
-+ I1_lin_default_fingerW_22_R0_S I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S
-+ I1_lin_default_fingerW_24_R0_D I1_lin_default_fingerW_24_R0_G
-+ I1_lin_default_fingerW_24_R0_S I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S
-+ I1_lin_default_fingerW_26_R0_D I1_lin_default_fingerW_26_R0_G
-+ I1_lin_default_fingerW_26_R0_S I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S
-+ I1_lin_default_fingerW_28_R0_D I1_lin_default_fingerW_28_R0_G
-+ I1_lin_default_fingerW_28_R0_S I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S
-+ I1_lin_default_fingerW_30_R0_D I1_lin_default_fingerW_30_R0_G
-+ I1_lin_default_fingerW_30_R0_S I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S
-+ I1_lin_default_fingerW_32_R0_D I1_lin_default_fingerW_32_R0_G
-+ I1_lin_default_fingerW_32_R0_S I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S
-+ I1_lin_default_fingerW_34_R0_D I1_lin_default_fingerW_34_R0_G
-+ I1_lin_default_fingerW_34_R0_S I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S
-+ I1_lin_default_gateConn_1_R0_D I1_lin_default_gateConn_1_R0_G
-+ I1_lin_default_gateConn_1_R0_S I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S
-+ I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G I1_lin_default_l_0_R0_S
-+ I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G I1_lin_default_l_1_R0_S
-+ I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G I1_lin_default_l_2_R0_S
-+ I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G I1_lin_default_l_3_R0_S
-+ I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G I1_lin_default_l_4_R0_S
-+ I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G I1_lin_default_l_5_R0_S
-+ I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G I1_lin_default_l_6_R0_S
-+ I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G I1_lin_default_l_7_R0_S
-+ I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G I1_lin_default_l_8_R0_S
-+ I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G I1_lin_default_l_9_R0_S
-+ I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G I1_lin_default_l_10_R0_S
-+ I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G I1_lin_default_l_11_R0_S
-+ I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G I1_lin_default_l_12_R0_S
-+ I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G I1_lin_default_l_13_R0_S
-+ I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G I1_lin_default_l_14_R0_S
-+ I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G I1_lin_default_l_15_R0_S
-+ I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G I1_lin_default_l_16_R0_S
-+ I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G I1_lin_default_l_17_R0_S
-+ I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G I1_lin_default_l_18_R0_S
-+ I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G I1_lin_default_l_19_R0_S
-+ I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G I1_lin_default_l_20_R0_S
-+ I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G I1_lin_default_l_21_R0_S
-+ I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G I1_lin_default_l_22_R0_S
-+ I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G I1_lin_default_l_23_R0_S
-+ I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G I1_lin_default_l_24_R0_S
-+ I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G I1_lin_default_l_25_R0_S
-+ I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G I1_lin_default_l_26_R0_S
-+ I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G I1_lin_default_l_27_R0_S
-+ I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G I1_lin_default_l_28_R0_S
-+ I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G I1_lin_default_l_29_R0_S
-+ I1_lin_default_leftTap_0_R0_D I1_lin_default_leftTap_0_R0_G
-+ I1_lin_default_leftTap_0_R0_S I1_lin_default_m_0_R0_D
-+ I1_lin_default_m_0_R0_G I1_lin_default_m_0_R0_S I1_lin_default_m_1_R0_D
-+ I1_lin_default_m_1_R0_G I1_lin_default_m_1_R0_S I1_lin_default_m_2_R0_D
-+ I1_lin_default_m_2_R0_G I1_lin_default_m_2_R0_S I1_lin_default_nf_0_R0_D
-+ I1_lin_default_nf_0_R0_G I1_lin_default_nf_0_R0_S I1_lin_default_nf_1_R0_D
-+ I1_lin_default_nf_1_R0_G I1_lin_default_nf_1_R0_S I1_lin_default_nf_2_R0_D
-+ I1_lin_default_nf_2_R0_G I1_lin_default_nf_2_R0_S
-+ I1_lin_default_rightTap_0_R0_D I1_lin_default_rightTap_0_R0_G
-+ I1_lin_default_rightTap_0_R0_S I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S
-+ I1_lin_default_sdConn_0_R0_D I1_lin_default_sdConn_0_R0_G
-+ I1_lin_default_sdConn_0_R0_S I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S
-+ I1_lin_default_sdConn_2_R0_D I1_lin_default_sdConn_2_R0_G
-+ I1_lin_default_sdConn_2_R0_S I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S
-+ I1_lin_default_sdWidth_1_R0_D I1_lin_default_sdWidth_1_R0_G
-+ I1_lin_default_sdWidth_1_R0_S I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S
-+ I1_lin_default_sdWidth_3_R0_D I1_lin_default_sdWidth_3_R0_G
-+ I1_lin_default_sdWidth_3_R0_S I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S
-+ I1_lin_default_sdWidth_5_R0_D I1_lin_default_sdWidth_5_R0_G
-+ I1_lin_default_sdWidth_5_R0_S I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S
-+ I1_lin_default_sdWidth_7_R0_D I1_lin_default_sdWidth_7_R0_G
-+ I1_lin_default_sdWidth_7_R0_S I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S
-+ I1_lin_default_sdWidth_9_R0_D I1_lin_default_sdWidth_9_R0_G
-+ I1_lin_default_sdWidth_9_R0_S I1_lin_default_tapCntRows_0_R0_D
-+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S
-+ I1_lin_default_tapCntRows_1_R0_D I1_lin_default_tapCntRows_1_R0_G
-+ I1_lin_default_tapCntRows_1_R0_S I1_lin_default_tapCntRows_2_R0_D
-+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S
-+ I1_lin_default_tapCntRows_3_R0_D I1_lin_default_tapCntRows_3_R0_G
-+ I1_lin_default_tapCntRows_3_R0_S I1_lin_default_tapCntRows_4_R0_D
-+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S
-+ I1_lin_default_topTap_0_R0_D I1_lin_default_topTap_0_R0_G
-+ I1_lin_default_topTap_0_R0_S vdd!
-*.PININFO I1_default_D:I I1_default_G:I I1_default_S:I
-*.PININFO I1_lin_default_bodytie_0_R0_D:I I1_lin_default_bodytie_0_R0_G:I
-*.PININFO I1_lin_default_bodytie_0_R0_S:I I1_lin_default_bodytie_1_R0_D:I
-*.PININFO I1_lin_default_bodytie_1_R0_G:I I1_lin_default_bodytie_1_R0_S:I
-*.PININFO I1_lin_default_bottomTap_0_R0_D:I I1_lin_default_bottomTap_0_R0_G:I
-*.PININFO I1_lin_default_bottomTap_0_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_S:I
-*.PININFO I1_lin_default_fingerW_0_R0_D:I I1_lin_default_fingerW_0_R0_G:I
-*.PININFO I1_lin_default_fingerW_0_R0_S:I I1_lin_default_fingerW_1_R0_D:I
-*.PININFO I1_lin_default_fingerW_1_R0_G:I I1_lin_default_fingerW_1_R0_S:I
-*.PININFO I1_lin_default_fingerW_2_R0_D:I I1_lin_default_fingerW_2_R0_G:I
-*.PININFO I1_lin_default_fingerW_2_R0_S:I I1_lin_default_fingerW_3_R0_D:I
-*.PININFO I1_lin_default_fingerW_3_R0_G:I I1_lin_default_fingerW_3_R0_S:I
-*.PININFO I1_lin_default_fingerW_4_R0_D:I I1_lin_default_fingerW_4_R0_G:I
-*.PININFO I1_lin_default_fingerW_4_R0_S:I I1_lin_default_fingerW_5_R0_D:I
-*.PININFO I1_lin_default_fingerW_5_R0_G:I I1_lin_default_fingerW_5_R0_S:I
-*.PININFO I1_lin_default_fingerW_6_R0_D:I I1_lin_default_fingerW_6_R0_G:I
-*.PININFO I1_lin_default_fingerW_6_R0_S:I I1_lin_default_fingerW_7_R0_D:I
-*.PININFO I1_lin_default_fingerW_7_R0_G:I I1_lin_default_fingerW_7_R0_S:I
-*.PININFO I1_lin_default_fingerW_8_R0_D:I I1_lin_default_fingerW_8_R0_G:I
-*.PININFO I1_lin_default_fingerW_8_R0_S:I I1_lin_default_fingerW_9_R0_D:I
-*.PININFO I1_lin_default_fingerW_9_R0_G:I I1_lin_default_fingerW_9_R0_S:I
-*.PININFO I1_lin_default_fingerW_10_R0_D:I I1_lin_default_fingerW_10_R0_G:I
-*.PININFO I1_lin_default_fingerW_10_R0_S:I I1_lin_default_fingerW_11_R0_D:I
-*.PININFO I1_lin_default_fingerW_11_R0_G:I I1_lin_default_fingerW_11_R0_S:I
-*.PININFO I1_lin_default_fingerW_12_R0_D:I I1_lin_default_fingerW_12_R0_G:I
-*.PININFO I1_lin_default_fingerW_12_R0_S:I I1_lin_default_fingerW_13_R0_D:I
-*.PININFO I1_lin_default_fingerW_13_R0_G:I I1_lin_default_fingerW_13_R0_S:I
-*.PININFO I1_lin_default_fingerW_14_R0_D:I I1_lin_default_fingerW_14_R0_G:I
-*.PININFO I1_lin_default_fingerW_14_R0_S:I I1_lin_default_fingerW_15_R0_D:I
-*.PININFO I1_lin_default_fingerW_15_R0_G:I I1_lin_default_fingerW_15_R0_S:I
-*.PININFO I1_lin_default_fingerW_16_R0_D:I I1_lin_default_fingerW_16_R0_G:I
-*.PININFO I1_lin_default_fingerW_16_R0_S:I I1_lin_default_fingerW_17_R0_D:I
-*.PININFO I1_lin_default_fingerW_17_R0_G:I I1_lin_default_fingerW_17_R0_S:I
-*.PININFO I1_lin_default_fingerW_18_R0_D:I I1_lin_default_fingerW_18_R0_G:I
-*.PININFO I1_lin_default_fingerW_18_R0_S:I I1_lin_default_fingerW_19_R0_D:I
-*.PININFO I1_lin_default_fingerW_19_R0_G:I I1_lin_default_fingerW_19_R0_S:I
-*.PININFO I1_lin_default_fingerW_20_R0_D:I I1_lin_default_fingerW_20_R0_G:I
-*.PININFO I1_lin_default_fingerW_20_R0_S:I I1_lin_default_fingerW_21_R0_D:I
-*.PININFO I1_lin_default_fingerW_21_R0_G:I I1_lin_default_fingerW_21_R0_S:I
-*.PININFO I1_lin_default_fingerW_22_R0_D:I I1_lin_default_fingerW_22_R0_G:I
-*.PININFO I1_lin_default_fingerW_22_R0_S:I I1_lin_default_fingerW_23_R0_D:I
-*.PININFO I1_lin_default_fingerW_23_R0_G:I I1_lin_default_fingerW_23_R0_S:I
-*.PININFO I1_lin_default_fingerW_24_R0_D:I I1_lin_default_fingerW_24_R0_G:I
-*.PININFO I1_lin_default_fingerW_24_R0_S:I I1_lin_default_fingerW_25_R0_D:I
-*.PININFO I1_lin_default_fingerW_25_R0_G:I I1_lin_default_fingerW_25_R0_S:I
-*.PININFO I1_lin_default_fingerW_26_R0_D:I I1_lin_default_fingerW_26_R0_G:I
-*.PININFO I1_lin_default_fingerW_26_R0_S:I I1_lin_default_fingerW_27_R0_D:I
-*.PININFO I1_lin_default_fingerW_27_R0_G:I I1_lin_default_fingerW_27_R0_S:I
-*.PININFO I1_lin_default_fingerW_28_R0_D:I I1_lin_default_fingerW_28_R0_G:I
-*.PININFO I1_lin_default_fingerW_28_R0_S:I I1_lin_default_fingerW_29_R0_D:I
-*.PININFO I1_lin_default_fingerW_29_R0_G:I I1_lin_default_fingerW_29_R0_S:I
-*.PININFO I1_lin_default_fingerW_30_R0_D:I I1_lin_default_fingerW_30_R0_G:I
-*.PININFO I1_lin_default_fingerW_30_R0_S:I I1_lin_default_fingerW_31_R0_D:I
-*.PININFO I1_lin_default_fingerW_31_R0_G:I I1_lin_default_fingerW_31_R0_S:I
-*.PININFO I1_lin_default_fingerW_32_R0_D:I I1_lin_default_fingerW_32_R0_G:I
-*.PININFO I1_lin_default_fingerW_32_R0_S:I I1_lin_default_fingerW_33_R0_D:I
-*.PININFO I1_lin_default_fingerW_33_R0_G:I I1_lin_default_fingerW_33_R0_S:I
-*.PININFO I1_lin_default_fingerW_34_R0_D:I I1_lin_default_fingerW_34_R0_G:I
-*.PININFO I1_lin_default_fingerW_34_R0_S:I I1_lin_default_gateConn_0_R0_D:I
-*.PININFO I1_lin_default_gateConn_0_R0_G:I I1_lin_default_gateConn_0_R0_S:I
-*.PININFO I1_lin_default_gateConn_1_R0_D:I I1_lin_default_gateConn_1_R0_G:I
-*.PININFO I1_lin_default_gateConn_1_R0_S:I I1_lin_default_gateConn_2_R0_D:I
-*.PININFO I1_lin_default_gateConn_2_R0_G:I I1_lin_default_gateConn_2_R0_S:I
-*.PININFO I1_lin_default_l_0_R0_D:I I1_lin_default_l_0_R0_G:I
-*.PININFO I1_lin_default_l_0_R0_S:I I1_lin_default_l_1_R0_D:I
-*.PININFO I1_lin_default_l_1_R0_G:I I1_lin_default_l_1_R0_S:I
-*.PININFO I1_lin_default_l_2_R0_D:I I1_lin_default_l_2_R0_G:I
-*.PININFO I1_lin_default_l_2_R0_S:I I1_lin_default_l_3_R0_D:I
-*.PININFO I1_lin_default_l_3_R0_G:I I1_lin_default_l_3_R0_S:I
-*.PININFO I1_lin_default_l_4_R0_D:I I1_lin_default_l_4_R0_G:I
-*.PININFO I1_lin_default_l_4_R0_S:I I1_lin_default_l_5_R0_D:I
-*.PININFO I1_lin_default_l_5_R0_G:I I1_lin_default_l_5_R0_S:I
-*.PININFO I1_lin_default_l_6_R0_D:I I1_lin_default_l_6_R0_G:I
-*.PININFO I1_lin_default_l_6_R0_S:I I1_lin_default_l_7_R0_D:I
-*.PININFO I1_lin_default_l_7_R0_G:I I1_lin_default_l_7_R0_S:I
-*.PININFO I1_lin_default_l_8_R0_D:I I1_lin_default_l_8_R0_G:I
-*.PININFO I1_lin_default_l_8_R0_S:I I1_lin_default_l_9_R0_D:I
-*.PININFO I1_lin_default_l_9_R0_G:I I1_lin_default_l_9_R0_S:I
-*.PININFO I1_lin_default_l_10_R0_D:I I1_lin_default_l_10_R0_G:I
-*.PININFO I1_lin_default_l_10_R0_S:I I1_lin_default_l_11_R0_D:I
-*.PININFO I1_lin_default_l_11_R0_G:I I1_lin_default_l_11_R0_S:I
-*.PININFO I1_lin_default_l_12_R0_D:I I1_lin_default_l_12_R0_G:I
-*.PININFO I1_lin_default_l_12_R0_S:I I1_lin_default_l_13_R0_D:I
-*.PININFO I1_lin_default_l_13_R0_G:I I1_lin_default_l_13_R0_S:I
-*.PININFO I1_lin_default_l_14_R0_D:I I1_lin_default_l_14_R0_G:I
-*.PININFO I1_lin_default_l_14_R0_S:I I1_lin_default_l_15_R0_D:I
-*.PININFO I1_lin_default_l_15_R0_G:I I1_lin_default_l_15_R0_S:I
-*.PININFO I1_lin_default_l_16_R0_D:I I1_lin_default_l_16_R0_G:I
-*.PININFO I1_lin_default_l_16_R0_S:I I1_lin_default_l_17_R0_D:I
-*.PININFO I1_lin_default_l_17_R0_G:I I1_lin_default_l_17_R0_S:I
-*.PININFO I1_lin_default_l_18_R0_D:I I1_lin_default_l_18_R0_G:I
-*.PININFO I1_lin_default_l_18_R0_S:I I1_lin_default_l_19_R0_D:I
-*.PININFO I1_lin_default_l_19_R0_G:I I1_lin_default_l_19_R0_S:I
-*.PININFO I1_lin_default_l_20_R0_D:I I1_lin_default_l_20_R0_G:I
-*.PININFO I1_lin_default_l_20_R0_S:I I1_lin_default_l_21_R0_D:I
-*.PININFO I1_lin_default_l_21_R0_G:I I1_lin_default_l_21_R0_S:I
-*.PININFO I1_lin_default_l_22_R0_D:I I1_lin_default_l_22_R0_G:I
-*.PININFO I1_lin_default_l_22_R0_S:I I1_lin_default_l_23_R0_D:I
-*.PININFO I1_lin_default_l_23_R0_G:I I1_lin_default_l_23_R0_S:I
-*.PININFO I1_lin_default_l_24_R0_D:I I1_lin_default_l_24_R0_G:I
-*.PININFO I1_lin_default_l_24_R0_S:I I1_lin_default_l_25_R0_D:I
-*.PININFO I1_lin_default_l_25_R0_G:I I1_lin_default_l_25_R0_S:I
-*.PININFO I1_lin_default_l_26_R0_D:I I1_lin_default_l_26_R0_G:I
-*.PININFO I1_lin_default_l_26_R0_S:I I1_lin_default_l_27_R0_D:I
-*.PININFO I1_lin_default_l_27_R0_G:I I1_lin_default_l_27_R0_S:I
-*.PININFO I1_lin_default_l_28_R0_D:I I1_lin_default_l_28_R0_G:I
-*.PININFO I1_lin_default_l_28_R0_S:I I1_lin_default_l_29_R0_D:I
-*.PININFO I1_lin_default_l_29_R0_G:I I1_lin_default_l_29_R0_S:I
-*.PININFO I1_lin_default_leftTap_0_R0_D:I I1_lin_default_leftTap_0_R0_G:I
-*.PININFO I1_lin_default_leftTap_0_R0_S:I I1_lin_default_m_0_R0_D:I
-*.PININFO I1_lin_default_m_0_R0_G:I I1_lin_default_m_0_R0_S:I
-*.PININFO I1_lin_default_m_1_R0_D:I I1_lin_default_m_1_R0_G:I
-*.PININFO I1_lin_default_m_1_R0_S:I I1_lin_default_m_2_R0_D:I
-*.PININFO I1_lin_default_m_2_R0_G:I I1_lin_default_m_2_R0_S:I
-*.PININFO I1_lin_default_nf_0_R0_D:I I1_lin_default_nf_0_R0_G:I
-*.PININFO I1_lin_default_nf_0_R0_S:I I1_lin_default_nf_1_R0_D:I
-*.PININFO I1_lin_default_nf_1_R0_G:I I1_lin_default_nf_1_R0_S:I
-*.PININFO I1_lin_default_nf_2_R0_D:I I1_lin_default_nf_2_R0_G:I
-*.PININFO I1_lin_default_nf_2_R0_S:I I1_lin_default_rightTap_0_R0_D:I
-*.PININFO I1_lin_default_rightTap_0_R0_G:I I1_lin_default_rightTap_0_R0_S:I
-*.PININFO I1_lin_default_sFirst_0_R0_D:I I1_lin_default_sFirst_0_R0_G:I
-*.PININFO I1_lin_default_sFirst_0_R0_S:I I1_lin_default_sdConn_0_R0_D:I
-*.PININFO I1_lin_default_sdConn_0_R0_G:I I1_lin_default_sdConn_0_R0_S:I
-*.PININFO I1_lin_default_sdConn_1_R0_D:I I1_lin_default_sdConn_1_R0_G:I
-*.PININFO I1_lin_default_sdConn_1_R0_S:I I1_lin_default_sdConn_2_R0_D:I
-*.PININFO I1_lin_default_sdConn_2_R0_G:I I1_lin_default_sdConn_2_R0_S:I
-*.PININFO I1_lin_default_sdWidth_0_R0_D:I I1_lin_default_sdWidth_0_R0_G:I
-*.PININFO I1_lin_default_sdWidth_0_R0_S:I I1_lin_default_sdWidth_1_R0_D:I
-*.PININFO I1_lin_default_sdWidth_1_R0_G:I I1_lin_default_sdWidth_1_R0_S:I
-*.PININFO I1_lin_default_sdWidth_2_R0_D:I I1_lin_default_sdWidth_2_R0_G:I
-*.PININFO I1_lin_default_sdWidth_2_R0_S:I I1_lin_default_sdWidth_3_R0_D:I
-*.PININFO I1_lin_default_sdWidth_3_R0_G:I I1_lin_default_sdWidth_3_R0_S:I
-*.PININFO I1_lin_default_sdWidth_4_R0_D:I I1_lin_default_sdWidth_4_R0_G:I
-*.PININFO I1_lin_default_sdWidth_4_R0_S:I I1_lin_default_sdWidth_5_R0_D:I
-*.PININFO I1_lin_default_sdWidth_5_R0_G:I I1_lin_default_sdWidth_5_R0_S:I
-*.PININFO I1_lin_default_sdWidth_6_R0_D:I I1_lin_default_sdWidth_6_R0_G:I
-*.PININFO I1_lin_default_sdWidth_6_R0_S:I I1_lin_default_sdWidth_7_R0_D:I
-*.PININFO I1_lin_default_sdWidth_7_R0_G:I I1_lin_default_sdWidth_7_R0_S:I
-*.PININFO I1_lin_default_sdWidth_8_R0_D:I I1_lin_default_sdWidth_8_R0_G:I
-*.PININFO I1_lin_default_sdWidth_8_R0_S:I I1_lin_default_sdWidth_9_R0_D:I
-*.PININFO I1_lin_default_sdWidth_9_R0_G:I I1_lin_default_sdWidth_9_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_S:I I1_lin_default_topTap_0_R0_D:I
-*.PININFO I1_lin_default_topTap_0_R0_G:I I1_lin_default_topTap_0_R0_S:I vdd!:I
-MI1_lin_default_fingerW_34_R0 I1_lin_default_fingerW_34_R0_D
-+ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S vdd! nmos_3p3_nat
-+ m=1 w=1e-3 l=280n nf=10 as=296e-12 ad=260e-12 ps=1.20592e-3 pd=1.0052e-3
-+ nrd=0.000260 nrs=0.000296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_fingerW_33_R0 I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S vdd! nmos_3p3_nat
-+ m=1 w=90.24e-6 l=280n nf=1 as=39.7056e-12 ad=39.7056e-12 ps=181.36e-6
-+ pd=181.36e-6 nrd=0.004876 nrs=0.004876 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_32_R0 I1_lin_default_fingerW_32_R0_D
-+ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S vdd! nmos_3p3_nat
-+ m=1 w=75.2e-6 l=280n nf=1 as=33.088e-12 ad=33.088e-12 ps=151.28e-6
-+ pd=151.28e-6 nrd=0.005851 nrs=0.005851 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_31_R0 I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S vdd! nmos_3p3_nat
-+ m=1 w=62.665e-6 l=280n nf=1 as=27.5726e-12 ad=27.5726e-12 ps=126.21e-6
-+ pd=126.21e-6 nrd=0.007021 nrs=0.007021 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_30_R0 I1_lin_default_fingerW_30_R0_D
-+ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S vdd! nmos_3p3_nat
-+ m=1 w=52.225e-6 l=280n nf=1 as=22.979e-12 ad=22.979e-12 ps=105.33e-6
-+ pd=105.33e-6 nrd=0.008425 nrs=0.008425 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_29_R0 I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S vdd! nmos_3p3_nat
-+ m=1 w=43.52e-6 l=280n nf=1 as=19.1488e-12 ad=19.1488e-12 ps=87.92e-6
-+ pd=87.92e-6 nrd=0.010110 nrs=0.010110 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_28_R0 I1_lin_default_fingerW_28_R0_D
-+ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S vdd! nmos_3p3_nat
-+ m=1 w=36.265e-6 l=280n nf=1 as=15.9566e-12 ad=15.9566e-12 ps=73.41e-6
-+ pd=73.41e-6 nrd=0.012133 nrs=0.012133 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_27_R0 I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S vdd! nmos_3p3_nat
-+ m=1 w=30.22e-6 l=280n nf=1 as=13.2968e-12 ad=13.2968e-12 ps=61.32e-6
-+ pd=61.32e-6 nrd=0.014560 nrs=0.014560 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_26_R0 I1_lin_default_fingerW_26_R0_D
-+ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S vdd! nmos_3p3_nat
-+ m=1 w=25.185e-6 l=280n nf=1 as=11.0814e-12 ad=11.0814e-12 ps=51.25e-6
-+ pd=51.25e-6 nrd=0.017471 nrs=0.017471 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_25_R0 I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S vdd! nmos_3p3_nat
-+ m=1 w=20.985e-6 l=280n nf=1 as=9.2334e-12 ad=9.2334e-12 ps=42.85e-6
-+ pd=42.85e-6 nrd=0.020967 nrs=0.020967 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_24_R0 I1_lin_default_fingerW_24_R0_D
-+ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S vdd! nmos_3p3_nat
-+ m=1 w=17.49e-6 l=280n nf=1 as=7.6956e-12 ad=7.6956e-12 ps=35.86e-6
-+ pd=35.86e-6 nrd=0.025157 nrs=0.025157 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_23_R0 I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S vdd! nmos_3p3_nat
-+ m=1 w=14.575e-6 l=280n nf=1 as=6.413e-12 ad=6.413e-12 ps=30.03e-6
-+ pd=30.03e-6 nrd=0.030189 nrs=0.030189 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_22_R0 I1_lin_default_fingerW_22_R0_D
-+ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S vdd! nmos_3p3_nat
-+ m=1 w=12.145e-6 l=280n nf=1 as=5.3438e-12 ad=5.3438e-12 ps=25.17e-6
-+ pd=25.17e-6 nrd=0.036229 nrs=0.036229 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_21_R0 I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S vdd! nmos_3p3_nat
-+ m=1 w=10.12e-6 l=280n nf=1 as=4.4528e-12 ad=4.4528e-12 ps=21.12e-6
-+ pd=21.12e-6 nrd=0.043478 nrs=0.043478 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_20_R0 I1_lin_default_fingerW_20_R0_D
-+ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S vdd! nmos_3p3_nat
-+ m=1 w=8.435e-6 l=280n nf=1 as=3.7114e-12 ad=3.7114e-12 ps=17.75e-6
-+ pd=17.75e-6 nrd=0.052164 nrs=0.052164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_19_R0 I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S vdd! nmos_3p3_nat
-+ m=1 w=7.03e-6 l=280n nf=1 as=3.0932e-12 ad=3.0932e-12 ps=14.94e-6
-+ pd=14.94e-6 nrd=0.062589 nrs=0.062589 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_18_R0 I1_lin_default_fingerW_18_R0_D
-+ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S vdd! nmos_3p3_nat
-+ m=1 w=5.855e-6 l=280n nf=1 as=2.5762e-12 ad=2.5762e-12 ps=12.59e-6
-+ pd=12.59e-6 nrd=0.075149 nrs=0.075149 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_17_R0 I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S vdd! nmos_3p3_nat
-+ m=1 w=4.88e-6 l=280n nf=1 as=2.1472e-12 ad=2.1472e-12 ps=10.64e-6
-+ pd=10.64e-6 nrd=0.090164 nrs=0.090164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_16_R0 I1_lin_default_fingerW_16_R0_D
-+ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S vdd! nmos_3p3_nat
-+ m=1 w=4.065e-6 l=280n nf=1 as=1.7886e-12 ad=1.7886e-12 ps=9.01e-6 pd=9.01e-6
-+ nrd=0.108241 nrs=0.108241 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_15_R0 I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S vdd! nmos_3p3_nat
-+ m=1 w=3.39e-6 l=280n nf=1 as=1.4916e-12 ad=1.4916e-12 ps=7.66e-6 pd=7.66e-6
-+ nrd=0.129794 nrs=0.129794 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_14_R0 I1_lin_default_fingerW_14_R0_D
-+ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S vdd! nmos_3p3_nat
-+ m=1 w=2.825e-6 l=280n nf=1 as=1.243e-12 ad=1.243e-12 ps=6.53e-6 pd=6.53e-6
-+ nrd=0.155752 nrs=0.155752 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_13_R0 I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S vdd! nmos_3p3_nat
-+ m=1 w=2.355e-6 l=280n nf=1 as=1.0362e-12 ad=1.0362e-12 ps=5.59e-6 pd=5.59e-6
-+ nrd=0.186837 nrs=0.186837 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_12_R0 I1_lin_default_fingerW_12_R0_D
-+ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S vdd! nmos_3p3_nat
-+ m=1 w=1.96e-6 l=280n nf=1 as=862.4e-15 ad=862.4e-15 ps=4.8e-6 pd=4.8e-6
-+ nrd=0.224490 nrs=0.224490 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_11_R0 I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S vdd! nmos_3p3_nat
-+ m=1 w=1.635e-6 l=280n nf=1 as=719.4e-15 ad=719.4e-15 ps=4.15e-6 pd=4.15e-6
-+ nrd=0.269113 nrs=0.269113 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_10_R0 I1_lin_default_fingerW_10_R0_D
-+ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S vdd! nmos_3p3_nat
-+ m=1 w=1.36e-6 l=280n nf=1 as=598.4e-15 ad=598.4e-15 ps=3.6e-6 pd=3.6e-6
-+ nrd=0.323529 nrs=0.323529 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_9_R0 I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S vdd! nmos_3p3_nat
-+ m=1 w=1.135e-6 l=280n nf=1 as=499.4e-15 ad=499.4e-15 ps=3.15e-6 pd=3.15e-6
-+ nrd=0.387665 nrs=0.387665 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_8_R0 I1_lin_default_fingerW_8_R0_D
-+ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S vdd! nmos_3p3_nat
-+ m=1 w=945e-9 l=280n nf=1 as=415.8e-15 ad=415.8e-15 ps=2.77e-6 pd=2.77e-6
-+ nrd=0.465608 nrs=0.465608 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_7_R0 I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S vdd! nmos_3p3_nat
-+ m=1 w=790e-9 l=280n nf=1 as=347.6e-15 ad=347.6e-15 ps=2.46e-6 pd=2.46e-6
-+ nrd=0.556962 nrs=0.556962 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_6_R0 I1_lin_default_fingerW_6_R0_D
-+ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S vdd! nmos_3p3_nat
-+ m=1 w=655e-9 l=280n nf=1 as=288.2e-15 ad=288.2e-15 ps=2.19e-6 pd=2.19e-6
-+ nrd=0.671756 nrs=0.671756 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_5_R0 I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S vdd! nmos_3p3_nat
-+ m=1 w=545e-9 l=280n nf=1 as=239.8e-15 ad=239.8e-15 ps=1.97e-6 pd=1.97e-6
-+ nrd=0.807339 nrs=0.807339 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_4_R0 I1_lin_default_fingerW_4_R0_D
-+ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S vdd! nmos_3p3_nat
-+ m=1 w=455e-9 l=280n nf=1 as=200.2e-15 ad=200.2e-15 ps=1.79e-6 pd=1.79e-6
-+ nrd=0.967033 nrs=0.967033 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_3_R0 I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S vdd! nmos_3p3_nat
-+ m=1 w=380e-9 l=280n nf=1 as=167.2e-15 ad=167.2e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=1.157895 nrs=1.157895 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_2_R0 I1_lin_default_fingerW_2_R0_D
-+ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S vdd! nmos_3p3_nat
-+ m=1 w=315e-9 l=280n nf=1 as=161.1e-15 ad=161.1e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=1.623583 nrs=1.623583 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_1_R0 I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S vdd! nmos_3p3_nat
-+ m=1 w=265e-9 l=280n nf=1 as=156.1e-15 ad=156.1e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=2.222855 nrs=2.222855 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_0_R0 I1_lin_default_fingerW_0_R0_D
-+ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S vdd! nmos_3p3_nat
-+ m=1 w=220e-9 l=280n nf=1 as=151.6e-15 ad=151.6e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=3.132231 nrs=3.132231 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_l_29_R0 I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G
-+ I1_lin_default_l_29_R0_S vdd! nmos_3p3_nat m=1 w=1.8e-6 l=50.000u nf=5
-+ as=532.8e-15 ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444
-+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_l_28_R0 I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G
-+ I1_lin_default_l_28_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=46.155u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_27_R0 I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G
-+ I1_lin_default_l_27_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=38.465u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_26_R0 I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G
-+ I1_lin_default_l_26_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=32.055u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_25_R0 I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G
-+ I1_lin_default_l_25_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=26.710u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_24_R0 I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G
-+ I1_lin_default_l_24_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=22.260u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_23_R0 I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G
-+ I1_lin_default_l_23_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=18.550u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_22_R0 I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G
-+ I1_lin_default_l_22_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=15.460u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_21_R0 I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G
-+ I1_lin_default_l_21_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=12.880u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_20_R0 I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G
-+ I1_lin_default_l_20_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=10.735u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_19_R0 I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G
-+ I1_lin_default_l_19_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=8.945u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_18_R0 I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G
-+ I1_lin_default_l_18_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=7.455u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_17_R0 I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G
-+ I1_lin_default_l_17_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=6.210u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_16_R0 I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G
-+ I1_lin_default_l_16_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=5.175u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_15_R0 I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G
-+ I1_lin_default_l_15_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=4.315u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_14_R0 I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G
-+ I1_lin_default_l_14_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=3.595u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_13_R0 I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G
-+ I1_lin_default_l_13_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=2.995u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_12_R0 I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G
-+ I1_lin_default_l_12_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=2.495u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_11_R0 I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G
-+ I1_lin_default_l_11_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=2.080u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_10_R0 I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G
-+ I1_lin_default_l_10_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=1.735u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_9_R0 I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G
-+ I1_lin_default_l_9_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=1.445u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_8_R0 I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G
-+ I1_lin_default_l_8_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=1.205u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_7_R0 I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G
-+ I1_lin_default_l_7_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=1.005u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_6_R0 I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G
-+ I1_lin_default_l_6_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=0.835u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_5_R0 I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G
-+ I1_lin_default_l_5_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=0.695u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_4_R0 I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G
-+ I1_lin_default_l_4_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=0.580u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_3_R0 I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G
-+ I1_lin_default_l_3_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=0.485u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_2_R0 I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G
-+ I1_lin_default_l_2_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=0.405u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_1_R0 I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G
-+ I1_lin_default_l_1_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=0.335u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_0_R0 I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G
-+ I1_lin_default_l_0_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=0.280u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_nf_2_R0 I1_lin_default_nf_2_R0_D I1_lin_default_nf_2_R0_G
-+ I1_lin_default_nf_2_R0_S vdd! nmos_3p3_nat m=1 w=36e-6 l=280n nf=100
-+ as=9.4896e-12 ad=9.36e-12 ps=89.44e-6 pd=88e-6 nrd=0.007222 nrs=0.007322
-+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_nf_1_R0 I1_lin_default_nf_1_R0_D I1_lin_default_nf_1_R0_G
-+ I1_lin_default_nf_1_R0_S vdd! nmos_3p3_nat m=1 w=18.36e-6 l=280n nf=51
-+ as=4.8384e-12 ad=4.8384e-12 ps=45.6e-6 pd=45.6e-6 nrd=0.014353 nrs=0.014353
-+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_nf_0_R0 I1_lin_default_nf_0_R0_D I1_lin_default_nf_0_R0_G
-+ I1_lin_default_nf_0_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15
-+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
-+ sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_m_2_R0 I1_lin_default_m_2_R0_D I1_lin_default_m_2_R0_G
-+ I1_lin_default_m_2_R0_S vdd! nmos_3p3_nat m=100 w=360e-9 l=280n nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=100
-MI1_lin_default_m_1_R0 I1_lin_default_m_1_R0_D I1_lin_default_m_1_R0_G
-+ I1_lin_default_m_1_R0_S vdd! nmos_3p3_nat m=51 w=1.8e-6 l=280n nf=5 as=532.8e-15
-+ ad=532.8e-15 ps=5.12e-6 pd=5.12e-6 nrd=0.164444 nrs=0.164444 sa=0.440u
-+ sb=0.440u sd=0.520u dtemp=0 par=51
-MI1_lin_default_m_0_R0 I1_lin_default_m_0_R0_D I1_lin_default_m_0_R0_G
-+ I1_lin_default_m_0_R0_S vdd! nmos_3p3_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15
-+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
-+ sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_calculatedParam_2_R0 I1_lin_default_calculatedParam_2_R0_D
-+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ vdd! nmos_3p3_nat m=1 w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6
-+ pd=1.76e-6 nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0
-+ par=1
-MI1_lin_default_calculatedParam_1_R0 I1_lin_default_calculatedParam_1_R0_D
-+ I1_lin_default_calculatedParam_1_R0_G I1_lin_default_calculatedParam_1_R0_S
-+ vdd! nmos_3p3_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_calculatedParam_0_R0 I1_lin_default_calculatedParam_0_R0_D
-+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ vdd! nmos_3p3_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_gateConn_2_R0 I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S vdd! nmos_3p3_nat
-+ m=1 w=16.08e-6 l=280n nf=3 as=5.1456e-12 ad=5.1456e-12 ps=23.36e-6
-+ pd=23.36e-6 nrd=0.019900 nrs=0.019900 sa=0.440u sb=0.440u sd=0.520u dtemp=0
-+ par=1
-MI1_lin_default_gateConn_1_R0 I1_lin_default_gateConn_1_R0_D
-+ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_gateConn_0_R0 I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_9_R0 I1_lin_default_sdWidth_9_R0_D
-+ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S vdd! nmos_3p3_nat
-+ m=1 w=26.8e-6 l=280n nf=5 as=20.3144e-12 ad=20.3144e-12 ps=39.74e-6
-+ pd=39.74e-6 nrd=0.028284 nrs=0.028284 sa=1.210u sb=1.210u sd=1.290u dtemp=0
-+ par=1
-MI1_lin_default_sdWidth_8_R0 I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=432e-15 ad=432e-15 ps=3.12e-6 pd=3.12e-6
-+ nrd=3.333333 nrs=3.333333 sa=1.200u sb=1.200u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_7_R0 I1_lin_default_sdWidth_7_R0_D
-+ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=372.6e-15 ad=372.6e-15 ps=2.79e-6 pd=2.79e-6
-+ nrd=2.875000 nrs=2.875000 sa=1.035u sb=1.035u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_6_R0 I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=322.2e-15 ad=322.2e-15 ps=2.51e-6 pd=2.51e-6
-+ nrd=2.486111 nrs=2.486111 sa=0.895u sb=0.895u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_5_R0 I1_lin_default_sdWidth_5_R0_D
-+ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=280.8e-15 ad=280.8e-15 ps=2.28e-6 pd=2.28e-6
-+ nrd=2.166667 nrs=2.166667 sa=0.780u sb=0.780u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_4_R0 I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=246.6e-15 ad=246.6e-15 ps=2.09e-6 pd=2.09e-6
-+ nrd=1.902778 nrs=1.902778 sa=0.685u sb=0.685u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_3_R0 I1_lin_default_sdWidth_3_R0_D
-+ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=217.8e-15 ad=217.8e-15 ps=1.93e-6 pd=1.93e-6
-+ nrd=1.680556 nrs=1.680556 sa=0.605u sb=0.605u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_2_R0 I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=194.4e-15 ad=194.4e-15 ps=1.8e-6 pd=1.8e-6
-+ nrd=1.500000 nrs=1.500000 sa=0.540u sb=0.540u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_1_R0 I1_lin_default_sdWidth_1_R0_D
-+ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=174.6e-15 ad=174.6e-15 ps=1.69e-6 pd=1.69e-6
-+ nrd=1.347222 nrs=1.347222 sa=0.485u sb=0.485u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_0_R0 I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_sFirst_0_R0 I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S vdd! nmos_3p3_nat m=1
-+ w=16.8e-6 l=280n nf=5 as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6
-+ nrd=0.017619 nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_2_R0 I1_lin_default_sdConn_2_R0_D
-+ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S vdd! nmos_3p3_nat m=1
-+ w=13.6e-6 l=280n nf=10 as=4.0256e-12 ad=3.536e-12 ps=22.24e-6 pd=18.8e-6
-+ nrd=0.019118 nrs=0.021765 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_1_R0 I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S vdd! nmos_3p3_nat m=1
-+ w=1.08e-6 l=280n nf=3 as=345.6e-15 ad=345.6e-15 ps=3.36e-6 pd=3.36e-6
-+ nrd=0.296296 nrs=0.296296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_0_R0 I1_lin_default_sdConn_0_R0_D
-+ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S vdd! nmos_3p3_nat m=1
-+ w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6 pd=1.76e-6
-+ nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_bodytie_1_R0 I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_bodytie_0_R0 I1_lin_default_bodytie_0_R0_D
-+ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_leftTap_0_R0 I1_lin_default_leftTap_0_R0_D
-+ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_rightTap_0_R0 I1_lin_default_rightTap_0_R0_D
-+ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S vdd! nmos_3p3_nat
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_topTap_0_R0 I1_lin_default_topTap_0_R0_D
-+ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S vdd! nmos_3p3_nat m=1
-+ w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_bottomTap_0_R0 I1_lin_default_bottomTap_0_R0_D
-+ I1_lin_default_bottomTap_0_R0_G I1_lin_default_bottomTap_0_R0_S vdd!
-+ nmos_3p3_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_4_R0 I1_lin_default_tapCntRows_4_R0_D
-+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S vdd!
-+ nmos_3p3_nat m=1 w=25.08e-6 l=280n nf=3 as=8.0256e-12 ad=8.0256e-12 ps=35.36e-6
-+ pd=35.36e-6 nrd=0.012759 nrs=0.012759 sa=0.440u sb=0.440u sd=0.520u dtemp=0
-+ par=1
-MI1_lin_default_tapCntRows_3_R0 I1_lin_default_tapCntRows_3_R0_D
-+ I1_lin_default_tapCntRows_3_R0_G I1_lin_default_tapCntRows_3_R0_S vdd!
-+ nmos_3p3_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_2_R0 I1_lin_default_tapCntRows_2_R0_D
-+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S vdd!
-+ nmos_3p3_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_1_R0 I1_lin_default_tapCntRows_1_R0_D
-+ I1_lin_default_tapCntRows_1_R0_G I1_lin_default_tapCntRows_1_R0_S vdd!
-+ nmos_3p3_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_0_R0 I1_lin_default_tapCntRows_0_R0_D
-+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S vdd!
-+ nmos_3p3_nat m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_default I1_default_D I1_default_G I1_default_S vdd! nmos_3p3_nat m=1 w=360e-9
-+ l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222
-+ nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pmos_1p8.cdl b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pfet_01v8.cdl
similarity index 91%
rename from IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pmos_1p8.cdl
rename to IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pfet_01v8.cdl
index 2169f2b..d45a0a5 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pmos_1p8.cdl
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pfet_01v8.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_library_2
-* Top Cell Name: pmos_1p8
+* Top Cell Name: pfet_01v8
* View Name: schematic
* Netlisted on: Sep 10 16:52:08 2021
************************************************************************
@@ -18,11 +18,11 @@
************************************************************************
* Library Name: TCG_library_2
-* Cell Name: pmos_1p8
+* Cell Name: pfet_01v8
* View Name: schematic
************************************************************************
-.SUBCKT pmos_1p8 I1_default_D I1_default_G I1_default_S
+.SUBCKT pfet_01v8 I1_default_D I1_default_G I1_default_S
+ I1_lin_default_bodytie_0_R0_D I1_lin_default_bodytie_0_R0_G
+ I1_lin_default_bodytie_0_R0_S I1_lin_default_bodytie_1_R0_D
+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S I1_lin_default_bodytie_2_R0_D
@@ -328,428 +328,428 @@
*.PININFO I1_lin_default_tapCntRows_4_R0_S:I I1_lin_default_topTap_0_R0_D:I
*.PININFO I1_lin_default_topTap_0_R0_G:I I1_lin_default_topTap_0_R0_S:I gnd!:I
MMP1 I1_lin_default_bodytie_2_R0_D I1_lin_default_bodytie_2_R0_G
-+ I1_lin_default_bodytie_2_R0_S gnd! pmos_1p8 m=1 w=720e-9 l=280n nf=2
++ I1_lin_default_bodytie_2_R0_S gnd! pfet_01v8 m=1 w=720e-9 l=280n nf=2
+ as=327.6e-15 ad=187.2e-15 ps=3.26e-6 pd=1.76e-6 nrd=0.361111 nrs=0.631944
+ sa=0.470u sb=0.440u sd=0.520u dtemp=0 par=1
MMP0 I1_lin_default_sFirst_1_R0_D I1_lin_default_sFirst_1_R0_G
-+ I1_lin_default_sFirst_1_R0_S gnd! pmos_1p8 m=1 w=16.8e-6 l=280n nf=5
++ I1_lin_default_sFirst_1_R0_S gnd! pfet_01v8 m=1 w=16.8e-6 l=280n nf=5
+ as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6 nrd=0.017619
+ nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_fingerW_34_R0 I1_lin_default_fingerW_34_R0_D
-+ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S gnd! pfet_01v8
+ m=1 w=1e-3 l=280n nf=10 as=296e-12 ad=260e-12 ps=1.20592e-3 pd=1.0052e-3
+ nrd=0.000260 nrs=0.000296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_fingerW_33_R0 I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S gnd! pfet_01v8
+ m=1 w=90.24e-6 l=280n nf=1 as=39.7056e-12 ad=39.7056e-12 ps=181.36e-6
+ pd=181.36e-6 nrd=0.004876 nrs=0.004876 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_32_R0 I1_lin_default_fingerW_32_R0_D
-+ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S gnd! pfet_01v8
+ m=1 w=75.2e-6 l=280n nf=1 as=33.088e-12 ad=33.088e-12 ps=151.28e-6
+ pd=151.28e-6 nrd=0.005851 nrs=0.005851 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_31_R0 I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S gnd! pfet_01v8
+ m=1 w=62.665e-6 l=280n nf=1 as=27.5726e-12 ad=27.5726e-12 ps=126.21e-6
+ pd=126.21e-6 nrd=0.007021 nrs=0.007021 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_30_R0 I1_lin_default_fingerW_30_R0_D
-+ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S gnd! pfet_01v8
+ m=1 w=52.225e-6 l=280n nf=1 as=22.979e-12 ad=22.979e-12 ps=105.33e-6
+ pd=105.33e-6 nrd=0.008425 nrs=0.008425 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_29_R0 I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S gnd! pfet_01v8
+ m=1 w=43.52e-6 l=280n nf=1 as=19.1488e-12 ad=19.1488e-12 ps=87.92e-6
+ pd=87.92e-6 nrd=0.010110 nrs=0.010110 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_28_R0 I1_lin_default_fingerW_28_R0_D
-+ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S gnd! pfet_01v8
+ m=1 w=36.265e-6 l=280n nf=1 as=15.9566e-12 ad=15.9566e-12 ps=73.41e-6
+ pd=73.41e-6 nrd=0.012133 nrs=0.012133 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_27_R0 I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S gnd! pfet_01v8
+ m=1 w=30.22e-6 l=280n nf=1 as=13.2968e-12 ad=13.2968e-12 ps=61.32e-6
+ pd=61.32e-6 nrd=0.014560 nrs=0.014560 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_26_R0 I1_lin_default_fingerW_26_R0_D
-+ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S gnd! pfet_01v8
+ m=1 w=25.185e-6 l=280n nf=1 as=11.0814e-12 ad=11.0814e-12 ps=51.25e-6
+ pd=51.25e-6 nrd=0.017471 nrs=0.017471 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_25_R0 I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S gnd! pfet_01v8
+ m=1 w=20.985e-6 l=280n nf=1 as=9.2334e-12 ad=9.2334e-12 ps=42.85e-6
+ pd=42.85e-6 nrd=0.020967 nrs=0.020967 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_24_R0 I1_lin_default_fingerW_24_R0_D
-+ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S gnd! pfet_01v8
+ m=1 w=17.49e-6 l=280n nf=1 as=7.6956e-12 ad=7.6956e-12 ps=35.86e-6
+ pd=35.86e-6 nrd=0.025157 nrs=0.025157 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_23_R0 I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S gnd! pfet_01v8
+ m=1 w=14.575e-6 l=280n nf=1 as=6.413e-12 ad=6.413e-12 ps=30.03e-6
+ pd=30.03e-6 nrd=0.030189 nrs=0.030189 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_22_R0 I1_lin_default_fingerW_22_R0_D
-+ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S gnd! pfet_01v8
+ m=1 w=12.145e-6 l=280n nf=1 as=5.3438e-12 ad=5.3438e-12 ps=25.17e-6
+ pd=25.17e-6 nrd=0.036229 nrs=0.036229 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_21_R0 I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S gnd! pfet_01v8
+ m=1 w=10.12e-6 l=280n nf=1 as=4.4528e-12 ad=4.4528e-12 ps=21.12e-6
+ pd=21.12e-6 nrd=0.043478 nrs=0.043478 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_20_R0 I1_lin_default_fingerW_20_R0_D
-+ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S gnd! pfet_01v8
+ m=1 w=8.435e-6 l=280n nf=1 as=3.7114e-12 ad=3.7114e-12 ps=17.75e-6
+ pd=17.75e-6 nrd=0.052164 nrs=0.052164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_19_R0 I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S gnd! pfet_01v8
+ m=1 w=7.03e-6 l=280n nf=1 as=3.0932e-12 ad=3.0932e-12 ps=14.94e-6
+ pd=14.94e-6 nrd=0.062589 nrs=0.062589 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_18_R0 I1_lin_default_fingerW_18_R0_D
-+ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S gnd! pfet_01v8
+ m=1 w=5.855e-6 l=280n nf=1 as=2.5762e-12 ad=2.5762e-12 ps=12.59e-6
+ pd=12.59e-6 nrd=0.075149 nrs=0.075149 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_17_R0 I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S gnd! pfet_01v8
+ m=1 w=4.88e-6 l=280n nf=1 as=2.1472e-12 ad=2.1472e-12 ps=10.64e-6
+ pd=10.64e-6 nrd=0.090164 nrs=0.090164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_16_R0 I1_lin_default_fingerW_16_R0_D
-+ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S gnd! pfet_01v8
+ m=1 w=4.065e-6 l=280n nf=1 as=1.7886e-12 ad=1.7886e-12 ps=9.01e-6 pd=9.01e-6
+ nrd=0.108241 nrs=0.108241 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_15_R0 I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S gnd! pfet_01v8
+ m=1 w=3.39e-6 l=280n nf=1 as=1.4916e-12 ad=1.4916e-12 ps=7.66e-6 pd=7.66e-6
+ nrd=0.129794 nrs=0.129794 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_14_R0 I1_lin_default_fingerW_14_R0_D
-+ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S gnd! pfet_01v8
+ m=1 w=2.825e-6 l=280n nf=1 as=1.243e-12 ad=1.243e-12 ps=6.53e-6 pd=6.53e-6
+ nrd=0.155752 nrs=0.155752 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_13_R0 I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S gnd! pfet_01v8
+ m=1 w=2.355e-6 l=280n nf=1 as=1.0362e-12 ad=1.0362e-12 ps=5.59e-6 pd=5.59e-6
+ nrd=0.186837 nrs=0.186837 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_12_R0 I1_lin_default_fingerW_12_R0_D
-+ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S gnd! pfet_01v8
+ m=1 w=1.96e-6 l=280n nf=1 as=862.4e-15 ad=862.4e-15 ps=4.8e-6 pd=4.8e-6
+ nrd=0.224490 nrs=0.224490 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_11_R0 I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S gnd! pfet_01v8
+ m=1 w=1.635e-6 l=280n nf=1 as=719.4e-15 ad=719.4e-15 ps=4.15e-6 pd=4.15e-6
+ nrd=0.269113 nrs=0.269113 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_10_R0 I1_lin_default_fingerW_10_R0_D
-+ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S gnd! pfet_01v8
+ m=1 w=1.36e-6 l=280n nf=1 as=598.4e-15 ad=598.4e-15 ps=3.6e-6 pd=3.6e-6
+ nrd=0.323529 nrs=0.323529 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_9_R0 I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S gnd! pfet_01v8
+ m=1 w=1.135e-6 l=280n nf=1 as=499.4e-15 ad=499.4e-15 ps=3.15e-6 pd=3.15e-6
+ nrd=0.387665 nrs=0.387665 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_8_R0 I1_lin_default_fingerW_8_R0_D
-+ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S gnd! pfet_01v8
+ m=1 w=945e-9 l=280n nf=1 as=415.8e-15 ad=415.8e-15 ps=2.77e-6 pd=2.77e-6
+ nrd=0.465608 nrs=0.465608 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_7_R0 I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S gnd! pfet_01v8
+ m=1 w=790e-9 l=280n nf=1 as=347.6e-15 ad=347.6e-15 ps=2.46e-6 pd=2.46e-6
+ nrd=0.556962 nrs=0.556962 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_6_R0 I1_lin_default_fingerW_6_R0_D
-+ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S gnd! pfet_01v8
+ m=1 w=655e-9 l=280n nf=1 as=288.2e-15 ad=288.2e-15 ps=2.19e-6 pd=2.19e-6
+ nrd=0.671756 nrs=0.671756 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_5_R0 I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S gnd! pfet_01v8
+ m=1 w=545e-9 l=280n nf=1 as=239.8e-15 ad=239.8e-15 ps=1.97e-6 pd=1.97e-6
+ nrd=0.807339 nrs=0.807339 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_4_R0 I1_lin_default_fingerW_4_R0_D
-+ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S gnd! pfet_01v8
+ m=1 w=455e-9 l=280n nf=1 as=200.2e-15 ad=200.2e-15 ps=1.79e-6 pd=1.79e-6
+ nrd=0.967033 nrs=0.967033 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_3_R0 I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S gnd! pfet_01v8
+ m=1 w=380e-9 l=280n nf=1 as=167.2e-15 ad=167.2e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.157895 nrs=1.157895 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_2_R0 I1_lin_default_fingerW_2_R0_D
-+ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S gnd! pfet_01v8
+ m=1 w=315e-9 l=280n nf=1 as=161.1e-15 ad=161.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.623583 nrs=1.623583 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_1_R0 I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S gnd! pfet_01v8
+ m=1 w=265e-9 l=280n nf=1 as=156.1e-15 ad=156.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=2.222855 nrs=2.222855 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_0_R0 I1_lin_default_fingerW_0_R0_D
-+ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S gnd! pfet_01v8
+ m=1 w=220e-9 l=280n nf=1 as=151.6e-15 ad=151.6e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=3.132231 nrs=3.132231 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_l_29_R0 I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G
-+ I1_lin_default_l_29_R0_S gnd! pmos_1p8 m=1 w=26.8e-6 l=50.000u nf=5
++ I1_lin_default_l_29_R0_S gnd! pfet_01v8 m=1 w=26.8e-6 l=50.000u nf=5
+ as=7.9328e-12 ad=7.9328e-12 ps=35.12e-6 pd=35.12e-6 nrd=0.011045
+ nrs=0.011045 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_l_28_R0 I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G
-+ I1_lin_default_l_28_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=46.155u nf=1
++ I1_lin_default_l_28_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=46.155u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_27_R0 I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G
-+ I1_lin_default_l_27_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=38.465u nf=1
++ I1_lin_default_l_27_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=38.465u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_26_R0 I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G
-+ I1_lin_default_l_26_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=32.055u nf=1
++ I1_lin_default_l_26_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=32.055u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_25_R0 I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G
-+ I1_lin_default_l_25_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=26.710u nf=1
++ I1_lin_default_l_25_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=26.710u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_24_R0 I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G
-+ I1_lin_default_l_24_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=22.260u nf=1
++ I1_lin_default_l_24_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=22.260u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_23_R0 I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G
-+ I1_lin_default_l_23_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=18.550u nf=1
++ I1_lin_default_l_23_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=18.550u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_22_R0 I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G
-+ I1_lin_default_l_22_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=15.460u nf=1
++ I1_lin_default_l_22_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=15.460u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_21_R0 I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G
-+ I1_lin_default_l_21_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=12.880u nf=1
++ I1_lin_default_l_21_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=12.880u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_20_R0 I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G
-+ I1_lin_default_l_20_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=10.735u nf=1
++ I1_lin_default_l_20_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=10.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_19_R0 I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G
-+ I1_lin_default_l_19_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=8.945u nf=1
++ I1_lin_default_l_19_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=8.945u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_18_R0 I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G
-+ I1_lin_default_l_18_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=7.455u nf=1
++ I1_lin_default_l_18_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=7.455u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_17_R0 I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G
-+ I1_lin_default_l_17_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=6.210u nf=1
++ I1_lin_default_l_17_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=6.210u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_16_R0 I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G
-+ I1_lin_default_l_16_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=5.175u nf=1
++ I1_lin_default_l_16_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=5.175u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_15_R0 I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G
-+ I1_lin_default_l_15_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=4.315u nf=1
++ I1_lin_default_l_15_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=4.315u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_14_R0 I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G
-+ I1_lin_default_l_14_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=3.595u nf=1
++ I1_lin_default_l_14_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=3.595u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_13_R0 I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G
-+ I1_lin_default_l_13_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=2.995u nf=1
++ I1_lin_default_l_13_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=2.995u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_12_R0 I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G
-+ I1_lin_default_l_12_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=2.495u nf=1
++ I1_lin_default_l_12_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=2.495u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_11_R0 I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G
-+ I1_lin_default_l_11_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=2.080u nf=1
++ I1_lin_default_l_11_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=2.080u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_10_R0 I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G
-+ I1_lin_default_l_10_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=1.735u nf=1
++ I1_lin_default_l_10_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=1.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_9_R0 I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G
-+ I1_lin_default_l_9_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=1.445u nf=1
++ I1_lin_default_l_9_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=1.445u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_8_R0 I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G
-+ I1_lin_default_l_8_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=1.205u nf=1
++ I1_lin_default_l_8_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=1.205u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_7_R0 I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G
-+ I1_lin_default_l_7_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=1.005u nf=1
++ I1_lin_default_l_7_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=1.005u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_6_R0 I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G
-+ I1_lin_default_l_6_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.835u nf=1
++ I1_lin_default_l_6_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=0.835u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_5_R0 I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G
-+ I1_lin_default_l_5_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.695u nf=1
++ I1_lin_default_l_5_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=0.695u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_4_R0 I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G
-+ I1_lin_default_l_4_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.580u nf=1
++ I1_lin_default_l_4_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=0.580u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_3_R0 I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G
-+ I1_lin_default_l_3_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.485u nf=1
++ I1_lin_default_l_3_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=0.485u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_2_R0 I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G
-+ I1_lin_default_l_2_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.405u nf=1
++ I1_lin_default_l_2_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=0.405u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_1_R0 I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G
-+ I1_lin_default_l_1_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.335u nf=1
++ I1_lin_default_l_1_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=0.335u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_0_R0 I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G
-+ I1_lin_default_l_0_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.280u nf=1
++ I1_lin_default_l_0_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=0.280u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_nf_2_R0 I1_lin_default_nf_2_R0_D I1_lin_default_nf_2_R0_G
-+ I1_lin_default_nf_2_R0_S gnd! pmos_1p8 m=1 w=36e-6 l=280n nf=100
++ I1_lin_default_nf_2_R0_S gnd! pfet_01v8 m=1 w=36e-6 l=280n nf=100
+ as=9.4896e-12 ad=9.36e-12 ps=89.44e-6 pd=88e-6 nrd=0.007222 nrs=0.007322
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_1_R0 I1_lin_default_nf_1_R0_D I1_lin_default_nf_1_R0_G
-+ I1_lin_default_nf_1_R0_S gnd! pmos_1p8 m=1 w=18.36e-6 l=280n nf=51
++ I1_lin_default_nf_1_R0_S gnd! pfet_01v8 m=1 w=18.36e-6 l=280n nf=51
+ as=4.8384e-12 ad=4.8384e-12 ps=45.6e-6 pd=45.6e-6 nrd=0.014353 nrs=0.014353
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_0_R0 I1_lin_default_nf_0_R0_D I1_lin_default_nf_0_R0_G
-+ I1_lin_default_nf_0_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_nf_0_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_m_2_R0 I1_lin_default_m_2_R0_D I1_lin_default_m_2_R0_G
-+ I1_lin_default_m_2_R0_S gnd! pmos_1p8 m=100 w=360e-9 l=280n nf=1
++ I1_lin_default_m_2_R0_S gnd! pfet_01v8 m=100 w=360e-9 l=280n nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=100
MI1_lin_default_m_1_R0 I1_lin_default_m_1_R0_D I1_lin_default_m_1_R0_G
-+ I1_lin_default_m_1_R0_S gnd! pmos_1p8 m=51 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_m_1_R0_S gnd! pfet_01v8 m=51 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=51
MI1_lin_default_m_0_R0 I1_lin_default_m_0_R0_D I1_lin_default_m_0_R0_G
-+ I1_lin_default_m_0_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_m_0_R0_S gnd! pfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_2_R0 I1_lin_default_calculatedParam_2_R0_D
+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ gnd! pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ gnd! pfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_1_R0 I1_lin_default_calculatedParam_1_R0_D
+ I1_lin_default_calculatedParam_1_R0_G I1_lin_default_calculatedParam_1_R0_S
-+ gnd! pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ gnd! pfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_0_R0 I1_lin_default_calculatedParam_0_R0_D
+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ gnd! pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ gnd! pfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_2_R0 I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S gnd! pmos_1p8
++ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S gnd! pfet_01v8
+ m=1 w=16.08e-6 l=280n nf=3 as=5.1456e-12 ad=5.1456e-12 ps=23.36e-6
+ pd=23.36e-6 nrd=0.019900 nrs=0.019900 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_gateConn_1_R0 I1_lin_default_gateConn_1_R0_D
-+ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S gnd! pmos_1p8
++ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_0_R0 I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S gnd! pmos_1p8
++ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_9_R0 I1_lin_default_sdWidth_9_R0_D
-+ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S gnd! pfet_01v8
+ m=1 w=1.8e-6 l=280n nf=5 as=1.3644e-12 ad=1.3644e-12 ps=9.74e-6 pd=9.74e-6
+ nrd=0.421111 nrs=0.421111 sa=1.210u sb=1.210u sd=1.290u dtemp=0 par=1
MI1_lin_default_sdWidth_8_R0 I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=432e-15 ad=432e-15 ps=3.12e-6 pd=3.12e-6
+ nrd=3.333333 nrs=3.333333 sa=1.200u sb=1.200u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_7_R0 I1_lin_default_sdWidth_7_R0_D
-+ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=372.6e-15 ad=372.6e-15 ps=2.79e-6 pd=2.79e-6
+ nrd=2.875000 nrs=2.875000 sa=1.035u sb=1.035u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_6_R0 I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=322.2e-15 ad=322.2e-15 ps=2.51e-6 pd=2.51e-6
+ nrd=2.486111 nrs=2.486111 sa=0.895u sb=0.895u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_5_R0 I1_lin_default_sdWidth_5_R0_D
-+ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=280.8e-15 ad=280.8e-15 ps=2.28e-6 pd=2.28e-6
+ nrd=2.166667 nrs=2.166667 sa=0.780u sb=0.780u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_4_R0 I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=246.6e-15 ad=246.6e-15 ps=2.09e-6 pd=2.09e-6
+ nrd=1.902778 nrs=1.902778 sa=0.685u sb=0.685u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_3_R0 I1_lin_default_sdWidth_3_R0_D
-+ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=217.8e-15 ad=217.8e-15 ps=1.93e-6 pd=1.93e-6
+ nrd=1.680556 nrs=1.680556 sa=0.605u sb=0.605u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_2_R0 I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=194.4e-15 ad=194.4e-15 ps=1.8e-6 pd=1.8e-6
+ nrd=1.500000 nrs=1.500000 sa=0.540u sb=0.540u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_1_R0 I1_lin_default_sdWidth_1_R0_D
-+ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=174.6e-15 ad=174.6e-15 ps=1.69e-6 pd=1.69e-6
+ nrd=1.347222 nrs=1.347222 sa=0.485u sb=0.485u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_0_R0 I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sFirst_0_R0 I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S gnd! pmos_1p8 m=1
++ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S gnd! pfet_01v8 m=1
+ w=16.8e-6 l=280n nf=5 as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6
+ nrd=0.017619 nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_2_R0 I1_lin_default_sdConn_2_R0_D
-+ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S gnd! pmos_1p8 m=1
++ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S gnd! pfet_01v8 m=1
+ w=1.08e-6 l=280n nf=3 as=345.6e-15 ad=345.6e-15 ps=3.36e-6 pd=3.36e-6
+ nrd=0.296296 nrs=0.296296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_1_R0 I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S gnd! pmos_1p8 m=1
++ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S gnd! pfet_01v8 m=1
+ w=720e-9 l=280n nf=2 as=187.2e-15 ad=316.8e-15 ps=1.76e-6 pd=3.2e-6
+ nrd=0.611111 nrs=0.361111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_0_R0 I1_lin_default_sdConn_0_R0_D
-+ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S gnd! pmos_1p8 m=1
++ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S gnd! pfet_01v8 m=1
+ w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6 pd=1.76e-6
+ nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_bodytie_1_R0 I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S gnd! pmos_1p8
++ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bodytie_0_R0 I1_lin_default_bodytie_0_R0_D
-+ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S gnd! pmos_1p8
++ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=169.2e-15 ad=158.4e-15 ps=1.66e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.305556 sa=0.470u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_leftTap_0_R0 I1_lin_default_leftTap_0_R0_D
-+ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S gnd! pmos_1p8
++ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_rightTap_0_R0 I1_lin_default_rightTap_0_R0_D
-+ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S gnd! pmos_1p8
++ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S gnd! pfet_01v8
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_topTap_0_R0 I1_lin_default_topTap_0_R0_D
-+ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S gnd! pmos_1p8 m=1
++ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S gnd! pfet_01v8 m=1
+ w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bottomTap_0_R0 I1_lin_default_bottomTap_0_R0_D
+ I1_lin_default_bottomTap_0_R0_G I1_lin_default_bottomTap_0_R0_S gnd!
-+ pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ pfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_4_R0 I1_lin_default_tapCntRows_4_R0_D
+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S gnd!
-+ pmos_1p8 m=1 w=26.8e-6 l=280n nf=5 as=7.9328e-12 ad=7.9328e-12 ps=35.12e-6
++ pfet_01v8 m=1 w=26.8e-6 l=280n nf=5 as=7.9328e-12 ad=7.9328e-12 ps=35.12e-6
+ pd=35.12e-6 nrd=0.011045 nrs=0.011045 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_tapCntRows_3_R0 I1_lin_default_tapCntRows_3_R0_D
+ I1_lin_default_tapCntRows_3_R0_G I1_lin_default_tapCntRows_3_R0_S gnd!
-+ pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ pfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_2_R0 I1_lin_default_tapCntRows_2_R0_D
+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S gnd!
-+ pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ pfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_1_R0 I1_lin_default_tapCntRows_1_R0_D
+ I1_lin_default_tapCntRows_1_R0_G I1_lin_default_tapCntRows_1_R0_S gnd!
-+ pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ pfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_0_R0 I1_lin_default_tapCntRows_0_R0_D
+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S gnd!
-+ pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ pfet_01v8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_default I1_default_D I1_default_G I1_default_S gnd! pmos_1p8 m=1 w=360e-9
+MI1_default I1_default_D I1_default_G I1_default_S gnd! pfet_01v8 m=1 w=360e-9
+ l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222
+ nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
.ENDS
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pmos_1p8.cdl b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pfet_03v3.cdl
similarity index 91%
copy from IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pmos_1p8.cdl
copy to IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pfet_03v3.cdl
index 2169f2b..58a455a 100644
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pmos_1p8.cdl
+++ b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pfet_03v3.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_library_2
-* Top Cell Name: pmos_1p8
+* Top Cell Name: pfet_03v3
* View Name: schematic
* Netlisted on: Sep 10 16:52:08 2021
************************************************************************
@@ -18,11 +18,11 @@
************************************************************************
* Library Name: TCG_library_2
-* Cell Name: pmos_1p8
+* Cell Name: pfet_03v3
* View Name: schematic
************************************************************************
-.SUBCKT pmos_1p8 I1_default_D I1_default_G I1_default_S
+.SUBCKT pfet_03v3 I1_default_D I1_default_G I1_default_S
+ I1_lin_default_bodytie_0_R0_D I1_lin_default_bodytie_0_R0_G
+ I1_lin_default_bodytie_0_R0_S I1_lin_default_bodytie_1_R0_D
+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S I1_lin_default_bodytie_2_R0_D
@@ -328,428 +328,428 @@
*.PININFO I1_lin_default_tapCntRows_4_R0_S:I I1_lin_default_topTap_0_R0_D:I
*.PININFO I1_lin_default_topTap_0_R0_G:I I1_lin_default_topTap_0_R0_S:I gnd!:I
MMP1 I1_lin_default_bodytie_2_R0_D I1_lin_default_bodytie_2_R0_G
-+ I1_lin_default_bodytie_2_R0_S gnd! pmos_1p8 m=1 w=720e-9 l=280n nf=2
++ I1_lin_default_bodytie_2_R0_S gnd! pfet_03v3 m=1 w=720e-9 l=280n nf=2
+ as=327.6e-15 ad=187.2e-15 ps=3.26e-6 pd=1.76e-6 nrd=0.361111 nrs=0.631944
+ sa=0.470u sb=0.440u sd=0.520u dtemp=0 par=1
MMP0 I1_lin_default_sFirst_1_R0_D I1_lin_default_sFirst_1_R0_G
-+ I1_lin_default_sFirst_1_R0_S gnd! pmos_1p8 m=1 w=16.8e-6 l=280n nf=5
++ I1_lin_default_sFirst_1_R0_S gnd! pfet_03v3 m=1 w=16.8e-6 l=280n nf=5
+ as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6 nrd=0.017619
+ nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_fingerW_34_R0 I1_lin_default_fingerW_34_R0_D
-+ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S gnd! pfet_03v3
+ m=1 w=1e-3 l=280n nf=10 as=296e-12 ad=260e-12 ps=1.20592e-3 pd=1.0052e-3
+ nrd=0.000260 nrs=0.000296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_fingerW_33_R0 I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S gnd! pfet_03v3
+ m=1 w=90.24e-6 l=280n nf=1 as=39.7056e-12 ad=39.7056e-12 ps=181.36e-6
+ pd=181.36e-6 nrd=0.004876 nrs=0.004876 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_32_R0 I1_lin_default_fingerW_32_R0_D
-+ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S gnd! pfet_03v3
+ m=1 w=75.2e-6 l=280n nf=1 as=33.088e-12 ad=33.088e-12 ps=151.28e-6
+ pd=151.28e-6 nrd=0.005851 nrs=0.005851 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_31_R0 I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S gnd! pfet_03v3
+ m=1 w=62.665e-6 l=280n nf=1 as=27.5726e-12 ad=27.5726e-12 ps=126.21e-6
+ pd=126.21e-6 nrd=0.007021 nrs=0.007021 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_30_R0 I1_lin_default_fingerW_30_R0_D
-+ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S gnd! pfet_03v3
+ m=1 w=52.225e-6 l=280n nf=1 as=22.979e-12 ad=22.979e-12 ps=105.33e-6
+ pd=105.33e-6 nrd=0.008425 nrs=0.008425 sa=0.440u sb=0.440u sd=0u dtemp=0
+ par=1
MI1_lin_default_fingerW_29_R0 I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S gnd! pfet_03v3
+ m=1 w=43.52e-6 l=280n nf=1 as=19.1488e-12 ad=19.1488e-12 ps=87.92e-6
+ pd=87.92e-6 nrd=0.010110 nrs=0.010110 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_28_R0 I1_lin_default_fingerW_28_R0_D
-+ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S gnd! pfet_03v3
+ m=1 w=36.265e-6 l=280n nf=1 as=15.9566e-12 ad=15.9566e-12 ps=73.41e-6
+ pd=73.41e-6 nrd=0.012133 nrs=0.012133 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_27_R0 I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S gnd! pfet_03v3
+ m=1 w=30.22e-6 l=280n nf=1 as=13.2968e-12 ad=13.2968e-12 ps=61.32e-6
+ pd=61.32e-6 nrd=0.014560 nrs=0.014560 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_26_R0 I1_lin_default_fingerW_26_R0_D
-+ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S gnd! pfet_03v3
+ m=1 w=25.185e-6 l=280n nf=1 as=11.0814e-12 ad=11.0814e-12 ps=51.25e-6
+ pd=51.25e-6 nrd=0.017471 nrs=0.017471 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_25_R0 I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S gnd! pfet_03v3
+ m=1 w=20.985e-6 l=280n nf=1 as=9.2334e-12 ad=9.2334e-12 ps=42.85e-6
+ pd=42.85e-6 nrd=0.020967 nrs=0.020967 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_24_R0 I1_lin_default_fingerW_24_R0_D
-+ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S gnd! pfet_03v3
+ m=1 w=17.49e-6 l=280n nf=1 as=7.6956e-12 ad=7.6956e-12 ps=35.86e-6
+ pd=35.86e-6 nrd=0.025157 nrs=0.025157 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_23_R0 I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S gnd! pfet_03v3
+ m=1 w=14.575e-6 l=280n nf=1 as=6.413e-12 ad=6.413e-12 ps=30.03e-6
+ pd=30.03e-6 nrd=0.030189 nrs=0.030189 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_22_R0 I1_lin_default_fingerW_22_R0_D
-+ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S gnd! pfet_03v3
+ m=1 w=12.145e-6 l=280n nf=1 as=5.3438e-12 ad=5.3438e-12 ps=25.17e-6
+ pd=25.17e-6 nrd=0.036229 nrs=0.036229 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_21_R0 I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S gnd! pfet_03v3
+ m=1 w=10.12e-6 l=280n nf=1 as=4.4528e-12 ad=4.4528e-12 ps=21.12e-6
+ pd=21.12e-6 nrd=0.043478 nrs=0.043478 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_20_R0 I1_lin_default_fingerW_20_R0_D
-+ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S gnd! pfet_03v3
+ m=1 w=8.435e-6 l=280n nf=1 as=3.7114e-12 ad=3.7114e-12 ps=17.75e-6
+ pd=17.75e-6 nrd=0.052164 nrs=0.052164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_19_R0 I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S gnd! pfet_03v3
+ m=1 w=7.03e-6 l=280n nf=1 as=3.0932e-12 ad=3.0932e-12 ps=14.94e-6
+ pd=14.94e-6 nrd=0.062589 nrs=0.062589 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_18_R0 I1_lin_default_fingerW_18_R0_D
-+ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S gnd! pfet_03v3
+ m=1 w=5.855e-6 l=280n nf=1 as=2.5762e-12 ad=2.5762e-12 ps=12.59e-6
+ pd=12.59e-6 nrd=0.075149 nrs=0.075149 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_17_R0 I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S gnd! pfet_03v3
+ m=1 w=4.88e-6 l=280n nf=1 as=2.1472e-12 ad=2.1472e-12 ps=10.64e-6
+ pd=10.64e-6 nrd=0.090164 nrs=0.090164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_16_R0 I1_lin_default_fingerW_16_R0_D
-+ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S gnd! pfet_03v3
+ m=1 w=4.065e-6 l=280n nf=1 as=1.7886e-12 ad=1.7886e-12 ps=9.01e-6 pd=9.01e-6
+ nrd=0.108241 nrs=0.108241 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_15_R0 I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S gnd! pfet_03v3
+ m=1 w=3.39e-6 l=280n nf=1 as=1.4916e-12 ad=1.4916e-12 ps=7.66e-6 pd=7.66e-6
+ nrd=0.129794 nrs=0.129794 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_14_R0 I1_lin_default_fingerW_14_R0_D
-+ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S gnd! pfet_03v3
+ m=1 w=2.825e-6 l=280n nf=1 as=1.243e-12 ad=1.243e-12 ps=6.53e-6 pd=6.53e-6
+ nrd=0.155752 nrs=0.155752 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_13_R0 I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S gnd! pfet_03v3
+ m=1 w=2.355e-6 l=280n nf=1 as=1.0362e-12 ad=1.0362e-12 ps=5.59e-6 pd=5.59e-6
+ nrd=0.186837 nrs=0.186837 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_12_R0 I1_lin_default_fingerW_12_R0_D
-+ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S gnd! pfet_03v3
+ m=1 w=1.96e-6 l=280n nf=1 as=862.4e-15 ad=862.4e-15 ps=4.8e-6 pd=4.8e-6
+ nrd=0.224490 nrs=0.224490 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_11_R0 I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S gnd! pfet_03v3
+ m=1 w=1.635e-6 l=280n nf=1 as=719.4e-15 ad=719.4e-15 ps=4.15e-6 pd=4.15e-6
+ nrd=0.269113 nrs=0.269113 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_10_R0 I1_lin_default_fingerW_10_R0_D
-+ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S gnd! pfet_03v3
+ m=1 w=1.36e-6 l=280n nf=1 as=598.4e-15 ad=598.4e-15 ps=3.6e-6 pd=3.6e-6
+ nrd=0.323529 nrs=0.323529 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_9_R0 I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S gnd! pfet_03v3
+ m=1 w=1.135e-6 l=280n nf=1 as=499.4e-15 ad=499.4e-15 ps=3.15e-6 pd=3.15e-6
+ nrd=0.387665 nrs=0.387665 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_8_R0 I1_lin_default_fingerW_8_R0_D
-+ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S gnd! pfet_03v3
+ m=1 w=945e-9 l=280n nf=1 as=415.8e-15 ad=415.8e-15 ps=2.77e-6 pd=2.77e-6
+ nrd=0.465608 nrs=0.465608 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_7_R0 I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S gnd! pfet_03v3
+ m=1 w=790e-9 l=280n nf=1 as=347.6e-15 ad=347.6e-15 ps=2.46e-6 pd=2.46e-6
+ nrd=0.556962 nrs=0.556962 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_6_R0 I1_lin_default_fingerW_6_R0_D
-+ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S gnd! pfet_03v3
+ m=1 w=655e-9 l=280n nf=1 as=288.2e-15 ad=288.2e-15 ps=2.19e-6 pd=2.19e-6
+ nrd=0.671756 nrs=0.671756 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_5_R0 I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S gnd! pfet_03v3
+ m=1 w=545e-9 l=280n nf=1 as=239.8e-15 ad=239.8e-15 ps=1.97e-6 pd=1.97e-6
+ nrd=0.807339 nrs=0.807339 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_4_R0 I1_lin_default_fingerW_4_R0_D
-+ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S gnd! pfet_03v3
+ m=1 w=455e-9 l=280n nf=1 as=200.2e-15 ad=200.2e-15 ps=1.79e-6 pd=1.79e-6
+ nrd=0.967033 nrs=0.967033 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_3_R0 I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S gnd! pfet_03v3
+ m=1 w=380e-9 l=280n nf=1 as=167.2e-15 ad=167.2e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.157895 nrs=1.157895 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_2_R0 I1_lin_default_fingerW_2_R0_D
-+ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S gnd! pfet_03v3
+ m=1 w=315e-9 l=280n nf=1 as=161.1e-15 ad=161.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=1.623583 nrs=1.623583 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_1_R0 I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S gnd! pfet_03v3
+ m=1 w=265e-9 l=280n nf=1 as=156.1e-15 ad=156.1e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=2.222855 nrs=2.222855 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_fingerW_0_R0 I1_lin_default_fingerW_0_R0_D
-+ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S gnd! pmos_1p8
++ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S gnd! pfet_03v3
+ m=1 w=220e-9 l=280n nf=1 as=151.6e-15 ad=151.6e-15 ps=1.64e-6 pd=1.64e-6
+ nrd=3.132231 nrs=3.132231 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
MI1_lin_default_l_29_R0 I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G
-+ I1_lin_default_l_29_R0_S gnd! pmos_1p8 m=1 w=26.8e-6 l=50.000u nf=5
++ I1_lin_default_l_29_R0_S gnd! pfet_03v3 m=1 w=26.8e-6 l=50.000u nf=5
+ as=7.9328e-12 ad=7.9328e-12 ps=35.12e-6 pd=35.12e-6 nrd=0.011045
+ nrs=0.011045 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_l_28_R0 I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G
-+ I1_lin_default_l_28_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=46.155u nf=1
++ I1_lin_default_l_28_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=46.155u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_27_R0 I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G
-+ I1_lin_default_l_27_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=38.465u nf=1
++ I1_lin_default_l_27_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=38.465u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_26_R0 I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G
-+ I1_lin_default_l_26_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=32.055u nf=1
++ I1_lin_default_l_26_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=32.055u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_25_R0 I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G
-+ I1_lin_default_l_25_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=26.710u nf=1
++ I1_lin_default_l_25_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=26.710u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_24_R0 I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G
-+ I1_lin_default_l_24_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=22.260u nf=1
++ I1_lin_default_l_24_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=22.260u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_23_R0 I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G
-+ I1_lin_default_l_23_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=18.550u nf=1
++ I1_lin_default_l_23_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=18.550u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_22_R0 I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G
-+ I1_lin_default_l_22_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=15.460u nf=1
++ I1_lin_default_l_22_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=15.460u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_21_R0 I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G
-+ I1_lin_default_l_21_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=12.880u nf=1
++ I1_lin_default_l_21_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=12.880u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_20_R0 I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G
-+ I1_lin_default_l_20_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=10.735u nf=1
++ I1_lin_default_l_20_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=10.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_19_R0 I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G
-+ I1_lin_default_l_19_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=8.945u nf=1
++ I1_lin_default_l_19_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=8.945u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_18_R0 I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G
-+ I1_lin_default_l_18_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=7.455u nf=1
++ I1_lin_default_l_18_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=7.455u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_17_R0 I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G
-+ I1_lin_default_l_17_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=6.210u nf=1
++ I1_lin_default_l_17_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=6.210u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_16_R0 I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G
-+ I1_lin_default_l_16_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=5.175u nf=1
++ I1_lin_default_l_16_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=5.175u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_15_R0 I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G
-+ I1_lin_default_l_15_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=4.315u nf=1
++ I1_lin_default_l_15_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=4.315u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_14_R0 I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G
-+ I1_lin_default_l_14_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=3.595u nf=1
++ I1_lin_default_l_14_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=3.595u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_13_R0 I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G
-+ I1_lin_default_l_13_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=2.995u nf=1
++ I1_lin_default_l_13_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=2.995u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_12_R0 I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G
-+ I1_lin_default_l_12_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=2.495u nf=1
++ I1_lin_default_l_12_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=2.495u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_11_R0 I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G
-+ I1_lin_default_l_11_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=2.080u nf=1
++ I1_lin_default_l_11_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=2.080u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_10_R0 I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G
-+ I1_lin_default_l_10_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=1.735u nf=1
++ I1_lin_default_l_10_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=1.735u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_9_R0 I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G
-+ I1_lin_default_l_9_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=1.445u nf=1
++ I1_lin_default_l_9_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=1.445u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_8_R0 I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G
-+ I1_lin_default_l_8_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=1.205u nf=1
++ I1_lin_default_l_8_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=1.205u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_7_R0 I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G
-+ I1_lin_default_l_7_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=1.005u nf=1
++ I1_lin_default_l_7_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=1.005u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_6_R0 I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G
-+ I1_lin_default_l_6_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.835u nf=1
++ I1_lin_default_l_6_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=0.835u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_5_R0 I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G
-+ I1_lin_default_l_5_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.695u nf=1
++ I1_lin_default_l_5_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=0.695u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_4_R0 I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G
-+ I1_lin_default_l_4_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.580u nf=1
++ I1_lin_default_l_4_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=0.580u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_3_R0 I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G
-+ I1_lin_default_l_3_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.485u nf=1
++ I1_lin_default_l_3_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=0.485u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_2_R0 I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G
-+ I1_lin_default_l_2_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.405u nf=1
++ I1_lin_default_l_2_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=0.405u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_1_R0 I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G
-+ I1_lin_default_l_1_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.335u nf=1
++ I1_lin_default_l_1_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=0.335u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_l_0_R0 I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G
-+ I1_lin_default_l_0_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=0.280u nf=1
++ I1_lin_default_l_0_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=0.280u nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_nf_2_R0 I1_lin_default_nf_2_R0_D I1_lin_default_nf_2_R0_G
-+ I1_lin_default_nf_2_R0_S gnd! pmos_1p8 m=1 w=36e-6 l=280n nf=100
++ I1_lin_default_nf_2_R0_S gnd! pfet_03v3 m=1 w=36e-6 l=280n nf=100
+ as=9.4896e-12 ad=9.36e-12 ps=89.44e-6 pd=88e-6 nrd=0.007222 nrs=0.007322
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_1_R0 I1_lin_default_nf_1_R0_D I1_lin_default_nf_1_R0_G
-+ I1_lin_default_nf_1_R0_S gnd! pmos_1p8 m=1 w=18.36e-6 l=280n nf=51
++ I1_lin_default_nf_1_R0_S gnd! pfet_03v3 m=1 w=18.36e-6 l=280n nf=51
+ as=4.8384e-12 ad=4.8384e-12 ps=45.6e-6 pd=45.6e-6 nrd=0.014353 nrs=0.014353
+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_nf_0_R0 I1_lin_default_nf_0_R0_D I1_lin_default_nf_0_R0_G
-+ I1_lin_default_nf_0_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_nf_0_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_m_2_R0 I1_lin_default_m_2_R0_D I1_lin_default_m_2_R0_G
-+ I1_lin_default_m_2_R0_S gnd! pmos_1p8 m=100 w=360e-9 l=280n nf=1
++ I1_lin_default_m_2_R0_S gnd! pfet_03v3 m=100 w=360e-9 l=280n nf=1
+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=100
MI1_lin_default_m_1_R0 I1_lin_default_m_1_R0_D I1_lin_default_m_1_R0_G
-+ I1_lin_default_m_1_R0_S gnd! pmos_1p8 m=51 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_m_1_R0_S gnd! pfet_03v3 m=51 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=51
MI1_lin_default_m_0_R0 I1_lin_default_m_0_R0_D I1_lin_default_m_0_R0_G
-+ I1_lin_default_m_0_R0_S gnd! pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
++ I1_lin_default_m_0_R0_S gnd! pfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
+ sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_2_R0 I1_lin_default_calculatedParam_2_R0_D
+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ gnd! pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ gnd! pfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_1_R0 I1_lin_default_calculatedParam_1_R0_D
+ I1_lin_default_calculatedParam_1_R0_G I1_lin_default_calculatedParam_1_R0_S
-+ gnd! pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ gnd! pfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_calculatedParam_0_R0 I1_lin_default_calculatedParam_0_R0_D
+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ gnd! pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ gnd! pfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_2_R0 I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S gnd! pmos_1p8
++ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S gnd! pfet_03v3
+ m=1 w=16.08e-6 l=280n nf=3 as=5.1456e-12 ad=5.1456e-12 ps=23.36e-6
+ pd=23.36e-6 nrd=0.019900 nrs=0.019900 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_gateConn_1_R0 I1_lin_default_gateConn_1_R0_D
-+ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S gnd! pmos_1p8
++ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_gateConn_0_R0 I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S gnd! pmos_1p8
++ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_9_R0 I1_lin_default_sdWidth_9_R0_D
-+ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S gnd! pfet_03v3
+ m=1 w=1.8e-6 l=280n nf=5 as=1.3644e-12 ad=1.3644e-12 ps=9.74e-6 pd=9.74e-6
+ nrd=0.421111 nrs=0.421111 sa=1.210u sb=1.210u sd=1.290u dtemp=0 par=1
MI1_lin_default_sdWidth_8_R0 I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=432e-15 ad=432e-15 ps=3.12e-6 pd=3.12e-6
+ nrd=3.333333 nrs=3.333333 sa=1.200u sb=1.200u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_7_R0 I1_lin_default_sdWidth_7_R0_D
-+ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=372.6e-15 ad=372.6e-15 ps=2.79e-6 pd=2.79e-6
+ nrd=2.875000 nrs=2.875000 sa=1.035u sb=1.035u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_6_R0 I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=322.2e-15 ad=322.2e-15 ps=2.51e-6 pd=2.51e-6
+ nrd=2.486111 nrs=2.486111 sa=0.895u sb=0.895u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_5_R0 I1_lin_default_sdWidth_5_R0_D
-+ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=280.8e-15 ad=280.8e-15 ps=2.28e-6 pd=2.28e-6
+ nrd=2.166667 nrs=2.166667 sa=0.780u sb=0.780u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_4_R0 I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=246.6e-15 ad=246.6e-15 ps=2.09e-6 pd=2.09e-6
+ nrd=1.902778 nrs=1.902778 sa=0.685u sb=0.685u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_3_R0 I1_lin_default_sdWidth_3_R0_D
-+ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=217.8e-15 ad=217.8e-15 ps=1.93e-6 pd=1.93e-6
+ nrd=1.680556 nrs=1.680556 sa=0.605u sb=0.605u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_2_R0 I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=194.4e-15 ad=194.4e-15 ps=1.8e-6 pd=1.8e-6
+ nrd=1.500000 nrs=1.500000 sa=0.540u sb=0.540u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_1_R0 I1_lin_default_sdWidth_1_R0_D
-+ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=174.6e-15 ad=174.6e-15 ps=1.69e-6 pd=1.69e-6
+ nrd=1.347222 nrs=1.347222 sa=0.485u sb=0.485u sd=0u dtemp=0 par=1
MI1_lin_default_sdWidth_0_R0 I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S gnd! pmos_1p8
++ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_sFirst_0_R0 I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S gnd! pmos_1p8 m=1
++ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S gnd! pfet_03v3 m=1
+ w=16.8e-6 l=280n nf=5 as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6
+ nrd=0.017619 nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_2_R0 I1_lin_default_sdConn_2_R0_D
-+ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S gnd! pmos_1p8 m=1
++ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S gnd! pfet_03v3 m=1
+ w=1.08e-6 l=280n nf=3 as=345.6e-15 ad=345.6e-15 ps=3.36e-6 pd=3.36e-6
+ nrd=0.296296 nrs=0.296296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_1_R0 I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S gnd! pmos_1p8 m=1
++ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S gnd! pfet_03v3 m=1
+ w=720e-9 l=280n nf=2 as=187.2e-15 ad=316.8e-15 ps=1.76e-6 pd=3.2e-6
+ nrd=0.611111 nrs=0.361111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_sdConn_0_R0 I1_lin_default_sdConn_0_R0_D
-+ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S gnd! pmos_1p8 m=1
++ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S gnd! pfet_03v3 m=1
+ w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6 pd=1.76e-6
+ nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
MI1_lin_default_bodytie_1_R0 I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S gnd! pmos_1p8
++ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bodytie_0_R0 I1_lin_default_bodytie_0_R0_D
-+ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S gnd! pmos_1p8
++ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=169.2e-15 ad=158.4e-15 ps=1.66e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.305556 sa=0.470u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_leftTap_0_R0 I1_lin_default_leftTap_0_R0_D
-+ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S gnd! pmos_1p8
++ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_rightTap_0_R0 I1_lin_default_rightTap_0_R0_D
-+ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S gnd! pmos_1p8
++ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S gnd! pfet_03v3
+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_topTap_0_R0 I1_lin_default_topTap_0_R0_D
-+ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S gnd! pmos_1p8 m=1
++ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S gnd! pfet_03v3 m=1
+ w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_bottomTap_0_R0 I1_lin_default_bottomTap_0_R0_D
+ I1_lin_default_bottomTap_0_R0_G I1_lin_default_bottomTap_0_R0_S gnd!
-+ pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ pfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_4_R0 I1_lin_default_tapCntRows_4_R0_D
+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S gnd!
-+ pmos_1p8 m=1 w=26.8e-6 l=280n nf=5 as=7.9328e-12 ad=7.9328e-12 ps=35.12e-6
++ pfet_03v3 m=1 w=26.8e-6 l=280n nf=5 as=7.9328e-12 ad=7.9328e-12 ps=35.12e-6
+ pd=35.12e-6 nrd=0.011045 nrs=0.011045 sa=0.440u sb=0.440u sd=0.520u dtemp=0
+ par=1
MI1_lin_default_tapCntRows_3_R0 I1_lin_default_tapCntRows_3_R0_D
+ I1_lin_default_tapCntRows_3_R0_G I1_lin_default_tapCntRows_3_R0_S gnd!
-+ pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ pfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_2_R0 I1_lin_default_tapCntRows_2_R0_D
+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S gnd!
-+ pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ pfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_1_R0 I1_lin_default_tapCntRows_1_R0_D
+ I1_lin_default_tapCntRows_1_R0_G I1_lin_default_tapCntRows_1_R0_S gnd!
-+ pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ pfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
MI1_lin_default_tapCntRows_0_R0 I1_lin_default_tapCntRows_0_R0_D
+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S gnd!
-+ pmos_1p8 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
++ pfet_03v3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_default I1_default_D I1_default_G I1_default_S gnd! pmos_1p8 m=1 w=360e-9
+MI1_default I1_default_D I1_default_G I1_default_S gnd! pfet_03v3 m=1 w=360e-9
+ l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222
+ nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
.ENDS
diff --git a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pmos_3p3.cdl b/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pmos_3p3.cdl
deleted file mode 100644
index c323e1f..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/mos_devices/netlist/pmos_3p3.cdl
+++ /dev/null
@@ -1,756 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_library_2
-* Top Cell Name: pmos_3p3
-* View Name: schematic
-* Netlisted on: Sep 10 16:52:08 2021
-************************************************************************
-
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-*.GLOBAL gnd!
-
-*.PIN gnd!
-
-************************************************************************
-* Library Name: TCG_library_2
-* Cell Name: pmos_3p3
-* View Name: schematic
-************************************************************************
-
-.SUBCKT pmos_3p3 I1_default_D I1_default_G I1_default_S
-+ I1_lin_default_bodytie_0_R0_D I1_lin_default_bodytie_0_R0_G
-+ I1_lin_default_bodytie_0_R0_S I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S I1_lin_default_bodytie_2_R0_D
-+ I1_lin_default_bodytie_2_R0_G I1_lin_default_bodytie_2_R0_S
-+ I1_lin_default_bottomTap_0_R0_D I1_lin_default_bottomTap_0_R0_G
-+ I1_lin_default_bottomTap_0_R0_S I1_lin_default_calculatedParam_0_R0_D
-+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ I1_lin_default_calculatedParam_1_R0_D I1_lin_default_calculatedParam_1_R0_G
-+ I1_lin_default_calculatedParam_1_R0_S I1_lin_default_calculatedParam_2_R0_D
-+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ I1_lin_default_fingerW_0_R0_D I1_lin_default_fingerW_0_R0_G
-+ I1_lin_default_fingerW_0_R0_S I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S
-+ I1_lin_default_fingerW_2_R0_D I1_lin_default_fingerW_2_R0_G
-+ I1_lin_default_fingerW_2_R0_S I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S
-+ I1_lin_default_fingerW_4_R0_D I1_lin_default_fingerW_4_R0_G
-+ I1_lin_default_fingerW_4_R0_S I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S
-+ I1_lin_default_fingerW_6_R0_D I1_lin_default_fingerW_6_R0_G
-+ I1_lin_default_fingerW_6_R0_S I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S
-+ I1_lin_default_fingerW_8_R0_D I1_lin_default_fingerW_8_R0_G
-+ I1_lin_default_fingerW_8_R0_S I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S
-+ I1_lin_default_fingerW_10_R0_D I1_lin_default_fingerW_10_R0_G
-+ I1_lin_default_fingerW_10_R0_S I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S
-+ I1_lin_default_fingerW_12_R0_D I1_lin_default_fingerW_12_R0_G
-+ I1_lin_default_fingerW_12_R0_S I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S
-+ I1_lin_default_fingerW_14_R0_D I1_lin_default_fingerW_14_R0_G
-+ I1_lin_default_fingerW_14_R0_S I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S
-+ I1_lin_default_fingerW_16_R0_D I1_lin_default_fingerW_16_R0_G
-+ I1_lin_default_fingerW_16_R0_S I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S
-+ I1_lin_default_fingerW_18_R0_D I1_lin_default_fingerW_18_R0_G
-+ I1_lin_default_fingerW_18_R0_S I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S
-+ I1_lin_default_fingerW_20_R0_D I1_lin_default_fingerW_20_R0_G
-+ I1_lin_default_fingerW_20_R0_S I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S
-+ I1_lin_default_fingerW_22_R0_D I1_lin_default_fingerW_22_R0_G
-+ I1_lin_default_fingerW_22_R0_S I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S
-+ I1_lin_default_fingerW_24_R0_D I1_lin_default_fingerW_24_R0_G
-+ I1_lin_default_fingerW_24_R0_S I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S
-+ I1_lin_default_fingerW_26_R0_D I1_lin_default_fingerW_26_R0_G
-+ I1_lin_default_fingerW_26_R0_S I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S
-+ I1_lin_default_fingerW_28_R0_D I1_lin_default_fingerW_28_R0_G
-+ I1_lin_default_fingerW_28_R0_S I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S
-+ I1_lin_default_fingerW_30_R0_D I1_lin_default_fingerW_30_R0_G
-+ I1_lin_default_fingerW_30_R0_S I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S
-+ I1_lin_default_fingerW_32_R0_D I1_lin_default_fingerW_32_R0_G
-+ I1_lin_default_fingerW_32_R0_S I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S
-+ I1_lin_default_fingerW_34_R0_D I1_lin_default_fingerW_34_R0_G
-+ I1_lin_default_fingerW_34_R0_S I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S
-+ I1_lin_default_gateConn_1_R0_D I1_lin_default_gateConn_1_R0_G
-+ I1_lin_default_gateConn_1_R0_S I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S
-+ I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G I1_lin_default_l_0_R0_S
-+ I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G I1_lin_default_l_1_R0_S
-+ I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G I1_lin_default_l_2_R0_S
-+ I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G I1_lin_default_l_3_R0_S
-+ I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G I1_lin_default_l_4_R0_S
-+ I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G I1_lin_default_l_5_R0_S
-+ I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G I1_lin_default_l_6_R0_S
-+ I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G I1_lin_default_l_7_R0_S
-+ I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G I1_lin_default_l_8_R0_S
-+ I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G I1_lin_default_l_9_R0_S
-+ I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G I1_lin_default_l_10_R0_S
-+ I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G I1_lin_default_l_11_R0_S
-+ I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G I1_lin_default_l_12_R0_S
-+ I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G I1_lin_default_l_13_R0_S
-+ I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G I1_lin_default_l_14_R0_S
-+ I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G I1_lin_default_l_15_R0_S
-+ I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G I1_lin_default_l_16_R0_S
-+ I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G I1_lin_default_l_17_R0_S
-+ I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G I1_lin_default_l_18_R0_S
-+ I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G I1_lin_default_l_19_R0_S
-+ I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G I1_lin_default_l_20_R0_S
-+ I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G I1_lin_default_l_21_R0_S
-+ I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G I1_lin_default_l_22_R0_S
-+ I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G I1_lin_default_l_23_R0_S
-+ I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G I1_lin_default_l_24_R0_S
-+ I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G I1_lin_default_l_25_R0_S
-+ I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G I1_lin_default_l_26_R0_S
-+ I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G I1_lin_default_l_27_R0_S
-+ I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G I1_lin_default_l_28_R0_S
-+ I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G I1_lin_default_l_29_R0_S
-+ I1_lin_default_leftTap_0_R0_D I1_lin_default_leftTap_0_R0_G
-+ I1_lin_default_leftTap_0_R0_S I1_lin_default_m_0_R0_D
-+ I1_lin_default_m_0_R0_G I1_lin_default_m_0_R0_S I1_lin_default_m_1_R0_D
-+ I1_lin_default_m_1_R0_G I1_lin_default_m_1_R0_S I1_lin_default_m_2_R0_D
-+ I1_lin_default_m_2_R0_G I1_lin_default_m_2_R0_S I1_lin_default_nf_0_R0_D
-+ I1_lin_default_nf_0_R0_G I1_lin_default_nf_0_R0_S I1_lin_default_nf_1_R0_D
-+ I1_lin_default_nf_1_R0_G I1_lin_default_nf_1_R0_S I1_lin_default_nf_2_R0_D
-+ I1_lin_default_nf_2_R0_G I1_lin_default_nf_2_R0_S
-+ I1_lin_default_rightTap_0_R0_D I1_lin_default_rightTap_0_R0_G
-+ I1_lin_default_rightTap_0_R0_S I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S I1_lin_default_sFirst_1_R0_D
-+ I1_lin_default_sFirst_1_R0_G I1_lin_default_sFirst_1_R0_S
-+ I1_lin_default_sdConn_0_R0_D I1_lin_default_sdConn_0_R0_G
-+ I1_lin_default_sdConn_0_R0_S I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S
-+ I1_lin_default_sdConn_2_R0_D I1_lin_default_sdConn_2_R0_G
-+ I1_lin_default_sdConn_2_R0_S I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S
-+ I1_lin_default_sdWidth_1_R0_D I1_lin_default_sdWidth_1_R0_G
-+ I1_lin_default_sdWidth_1_R0_S I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S
-+ I1_lin_default_sdWidth_3_R0_D I1_lin_default_sdWidth_3_R0_G
-+ I1_lin_default_sdWidth_3_R0_S I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S
-+ I1_lin_default_sdWidth_5_R0_D I1_lin_default_sdWidth_5_R0_G
-+ I1_lin_default_sdWidth_5_R0_S I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S
-+ I1_lin_default_sdWidth_7_R0_D I1_lin_default_sdWidth_7_R0_G
-+ I1_lin_default_sdWidth_7_R0_S I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S
-+ I1_lin_default_sdWidth_9_R0_D I1_lin_default_sdWidth_9_R0_G
-+ I1_lin_default_sdWidth_9_R0_S I1_lin_default_tapCntRows_0_R0_D
-+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S
-+ I1_lin_default_tapCntRows_1_R0_D I1_lin_default_tapCntRows_1_R0_G
-+ I1_lin_default_tapCntRows_1_R0_S I1_lin_default_tapCntRows_2_R0_D
-+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S
-+ I1_lin_default_tapCntRows_3_R0_D I1_lin_default_tapCntRows_3_R0_G
-+ I1_lin_default_tapCntRows_3_R0_S I1_lin_default_tapCntRows_4_R0_D
-+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S
-+ I1_lin_default_topTap_0_R0_D I1_lin_default_topTap_0_R0_G
-+ I1_lin_default_topTap_0_R0_S gnd!
-*.PININFO I1_default_D:I I1_default_G:I I1_default_S:I
-*.PININFO I1_lin_default_bodytie_0_R0_D:I I1_lin_default_bodytie_0_R0_G:I
-*.PININFO I1_lin_default_bodytie_0_R0_S:I I1_lin_default_bodytie_1_R0_D:I
-*.PININFO I1_lin_default_bodytie_1_R0_G:I I1_lin_default_bodytie_1_R0_S:I
-*.PININFO I1_lin_default_bottomTap_0_R0_D:I I1_lin_default_bottomTap_0_R0_G:I
-*.PININFO I1_lin_default_bottomTap_0_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_0_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_1_R0_S:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_D:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_G:I
-*.PININFO I1_lin_default_calculatedParam_2_R0_S:I
-*.PININFO I1_lin_default_fingerW_0_R0_D:I I1_lin_default_fingerW_0_R0_G:I
-*.PININFO I1_lin_default_fingerW_0_R0_S:I I1_lin_default_fingerW_1_R0_D:I
-*.PININFO I1_lin_default_fingerW_1_R0_G:I I1_lin_default_fingerW_1_R0_S:I
-*.PININFO I1_lin_default_fingerW_2_R0_D:I I1_lin_default_fingerW_2_R0_G:I
-*.PININFO I1_lin_default_fingerW_2_R0_S:I I1_lin_default_fingerW_3_R0_D:I
-*.PININFO I1_lin_default_fingerW_3_R0_G:I I1_lin_default_fingerW_3_R0_S:I
-*.PININFO I1_lin_default_fingerW_4_R0_D:I I1_lin_default_fingerW_4_R0_G:I
-*.PININFO I1_lin_default_fingerW_4_R0_S:I I1_lin_default_fingerW_5_R0_D:I
-*.PININFO I1_lin_default_fingerW_5_R0_G:I I1_lin_default_fingerW_5_R0_S:I
-*.PININFO I1_lin_default_fingerW_6_R0_D:I I1_lin_default_fingerW_6_R0_G:I
-*.PININFO I1_lin_default_fingerW_6_R0_S:I I1_lin_default_fingerW_7_R0_D:I
-*.PININFO I1_lin_default_fingerW_7_R0_G:I I1_lin_default_fingerW_7_R0_S:I
-*.PININFO I1_lin_default_fingerW_8_R0_D:I I1_lin_default_fingerW_8_R0_G:I
-*.PININFO I1_lin_default_fingerW_8_R0_S:I I1_lin_default_fingerW_9_R0_D:I
-*.PININFO I1_lin_default_fingerW_9_R0_G:I I1_lin_default_fingerW_9_R0_S:I
-*.PININFO I1_lin_default_fingerW_10_R0_D:I I1_lin_default_fingerW_10_R0_G:I
-*.PININFO I1_lin_default_fingerW_10_R0_S:I I1_lin_default_fingerW_11_R0_D:I
-*.PININFO I1_lin_default_fingerW_11_R0_G:I I1_lin_default_fingerW_11_R0_S:I
-*.PININFO I1_lin_default_fingerW_12_R0_D:I I1_lin_default_fingerW_12_R0_G:I
-*.PININFO I1_lin_default_fingerW_12_R0_S:I I1_lin_default_fingerW_13_R0_D:I
-*.PININFO I1_lin_default_fingerW_13_R0_G:I I1_lin_default_fingerW_13_R0_S:I
-*.PININFO I1_lin_default_fingerW_14_R0_D:I I1_lin_default_fingerW_14_R0_G:I
-*.PININFO I1_lin_default_fingerW_14_R0_S:I I1_lin_default_fingerW_15_R0_D:I
-*.PININFO I1_lin_default_fingerW_15_R0_G:I I1_lin_default_fingerW_15_R0_S:I
-*.PININFO I1_lin_default_fingerW_16_R0_D:I I1_lin_default_fingerW_16_R0_G:I
-*.PININFO I1_lin_default_fingerW_16_R0_S:I I1_lin_default_fingerW_17_R0_D:I
-*.PININFO I1_lin_default_fingerW_17_R0_G:I I1_lin_default_fingerW_17_R0_S:I
-*.PININFO I1_lin_default_fingerW_18_R0_D:I I1_lin_default_fingerW_18_R0_G:I
-*.PININFO I1_lin_default_fingerW_18_R0_S:I I1_lin_default_fingerW_19_R0_D:I
-*.PININFO I1_lin_default_fingerW_19_R0_G:I I1_lin_default_fingerW_19_R0_S:I
-*.PININFO I1_lin_default_fingerW_20_R0_D:I I1_lin_default_fingerW_20_R0_G:I
-*.PININFO I1_lin_default_fingerW_20_R0_S:I I1_lin_default_fingerW_21_R0_D:I
-*.PININFO I1_lin_default_fingerW_21_R0_G:I I1_lin_default_fingerW_21_R0_S:I
-*.PININFO I1_lin_default_fingerW_22_R0_D:I I1_lin_default_fingerW_22_R0_G:I
-*.PININFO I1_lin_default_fingerW_22_R0_S:I I1_lin_default_fingerW_23_R0_D:I
-*.PININFO I1_lin_default_fingerW_23_R0_G:I I1_lin_default_fingerW_23_R0_S:I
-*.PININFO I1_lin_default_fingerW_24_R0_D:I I1_lin_default_fingerW_24_R0_G:I
-*.PININFO I1_lin_default_fingerW_24_R0_S:I I1_lin_default_fingerW_25_R0_D:I
-*.PININFO I1_lin_default_fingerW_25_R0_G:I I1_lin_default_fingerW_25_R0_S:I
-*.PININFO I1_lin_default_fingerW_26_R0_D:I I1_lin_default_fingerW_26_R0_G:I
-*.PININFO I1_lin_default_fingerW_26_R0_S:I I1_lin_default_fingerW_27_R0_D:I
-*.PININFO I1_lin_default_fingerW_27_R0_G:I I1_lin_default_fingerW_27_R0_S:I
-*.PININFO I1_lin_default_fingerW_28_R0_D:I I1_lin_default_fingerW_28_R0_G:I
-*.PININFO I1_lin_default_fingerW_28_R0_S:I I1_lin_default_fingerW_29_R0_D:I
-*.PININFO I1_lin_default_fingerW_29_R0_G:I I1_lin_default_fingerW_29_R0_S:I
-*.PININFO I1_lin_default_fingerW_30_R0_D:I I1_lin_default_fingerW_30_R0_G:I
-*.PININFO I1_lin_default_fingerW_30_R0_S:I I1_lin_default_fingerW_31_R0_D:I
-*.PININFO I1_lin_default_fingerW_31_R0_G:I I1_lin_default_fingerW_31_R0_S:I
-*.PININFO I1_lin_default_fingerW_32_R0_D:I I1_lin_default_fingerW_32_R0_G:I
-*.PININFO I1_lin_default_fingerW_32_R0_S:I I1_lin_default_fingerW_33_R0_D:I
-*.PININFO I1_lin_default_fingerW_33_R0_G:I I1_lin_default_fingerW_33_R0_S:I
-*.PININFO I1_lin_default_fingerW_34_R0_D:I I1_lin_default_fingerW_34_R0_G:I
-*.PININFO I1_lin_default_fingerW_34_R0_S:I I1_lin_default_gateConn_0_R0_D:I
-*.PININFO I1_lin_default_gateConn_0_R0_G:I I1_lin_default_gateConn_0_R0_S:I
-*.PININFO I1_lin_default_gateConn_1_R0_D:I I1_lin_default_gateConn_1_R0_G:I
-*.PININFO I1_lin_default_gateConn_1_R0_S:I I1_lin_default_gateConn_2_R0_D:I
-*.PININFO I1_lin_default_gateConn_2_R0_G:I I1_lin_default_gateConn_2_R0_S:I
-*.PININFO I1_lin_default_l_0_R0_D:I I1_lin_default_l_0_R0_G:I
-*.PININFO I1_lin_default_l_0_R0_S:I I1_lin_default_l_1_R0_D:I
-*.PININFO I1_lin_default_l_1_R0_G:I I1_lin_default_l_1_R0_S:I
-*.PININFO I1_lin_default_l_2_R0_D:I I1_lin_default_l_2_R0_G:I
-*.PININFO I1_lin_default_l_2_R0_S:I I1_lin_default_l_3_R0_D:I
-*.PININFO I1_lin_default_l_3_R0_G:I I1_lin_default_l_3_R0_S:I
-*.PININFO I1_lin_default_l_4_R0_D:I I1_lin_default_l_4_R0_G:I
-*.PININFO I1_lin_default_l_4_R0_S:I I1_lin_default_l_5_R0_D:I
-*.PININFO I1_lin_default_l_5_R0_G:I I1_lin_default_l_5_R0_S:I
-*.PININFO I1_lin_default_l_6_R0_D:I I1_lin_default_l_6_R0_G:I
-*.PININFO I1_lin_default_l_6_R0_S:I I1_lin_default_l_7_R0_D:I
-*.PININFO I1_lin_default_l_7_R0_G:I I1_lin_default_l_7_R0_S:I
-*.PININFO I1_lin_default_l_8_R0_D:I I1_lin_default_l_8_R0_G:I
-*.PININFO I1_lin_default_l_8_R0_S:I I1_lin_default_l_9_R0_D:I
-*.PININFO I1_lin_default_l_9_R0_G:I I1_lin_default_l_9_R0_S:I
-*.PININFO I1_lin_default_l_10_R0_D:I I1_lin_default_l_10_R0_G:I
-*.PININFO I1_lin_default_l_10_R0_S:I I1_lin_default_l_11_R0_D:I
-*.PININFO I1_lin_default_l_11_R0_G:I I1_lin_default_l_11_R0_S:I
-*.PININFO I1_lin_default_l_12_R0_D:I I1_lin_default_l_12_R0_G:I
-*.PININFO I1_lin_default_l_12_R0_S:I I1_lin_default_l_13_R0_D:I
-*.PININFO I1_lin_default_l_13_R0_G:I I1_lin_default_l_13_R0_S:I
-*.PININFO I1_lin_default_l_14_R0_D:I I1_lin_default_l_14_R0_G:I
-*.PININFO I1_lin_default_l_14_R0_S:I I1_lin_default_l_15_R0_D:I
-*.PININFO I1_lin_default_l_15_R0_G:I I1_lin_default_l_15_R0_S:I
-*.PININFO I1_lin_default_l_16_R0_D:I I1_lin_default_l_16_R0_G:I
-*.PININFO I1_lin_default_l_16_R0_S:I I1_lin_default_l_17_R0_D:I
-*.PININFO I1_lin_default_l_17_R0_G:I I1_lin_default_l_17_R0_S:I
-*.PININFO I1_lin_default_l_18_R0_D:I I1_lin_default_l_18_R0_G:I
-*.PININFO I1_lin_default_l_18_R0_S:I I1_lin_default_l_19_R0_D:I
-*.PININFO I1_lin_default_l_19_R0_G:I I1_lin_default_l_19_R0_S:I
-*.PININFO I1_lin_default_l_20_R0_D:I I1_lin_default_l_20_R0_G:I
-*.PININFO I1_lin_default_l_20_R0_S:I I1_lin_default_l_21_R0_D:I
-*.PININFO I1_lin_default_l_21_R0_G:I I1_lin_default_l_21_R0_S:I
-*.PININFO I1_lin_default_l_22_R0_D:I I1_lin_default_l_22_R0_G:I
-*.PININFO I1_lin_default_l_22_R0_S:I I1_lin_default_l_23_R0_D:I
-*.PININFO I1_lin_default_l_23_R0_G:I I1_lin_default_l_23_R0_S:I
-*.PININFO I1_lin_default_l_24_R0_D:I I1_lin_default_l_24_R0_G:I
-*.PININFO I1_lin_default_l_24_R0_S:I I1_lin_default_l_25_R0_D:I
-*.PININFO I1_lin_default_l_25_R0_G:I I1_lin_default_l_25_R0_S:I
-*.PININFO I1_lin_default_l_26_R0_D:I I1_lin_default_l_26_R0_G:I
-*.PININFO I1_lin_default_l_26_R0_S:I I1_lin_default_l_27_R0_D:I
-*.PININFO I1_lin_default_l_27_R0_G:I I1_lin_default_l_27_R0_S:I
-*.PININFO I1_lin_default_l_28_R0_D:I I1_lin_default_l_28_R0_G:I
-*.PININFO I1_lin_default_l_28_R0_S:I I1_lin_default_l_29_R0_D:I
-*.PININFO I1_lin_default_l_29_R0_G:I I1_lin_default_l_29_R0_S:I
-*.PININFO I1_lin_default_leftTap_0_R0_D:I I1_lin_default_leftTap_0_R0_G:I
-*.PININFO I1_lin_default_leftTap_0_R0_S:I I1_lin_default_m_0_R0_D:I
-*.PININFO I1_lin_default_m_0_R0_G:I I1_lin_default_m_0_R0_S:I
-*.PININFO I1_lin_default_m_1_R0_D:I I1_lin_default_m_1_R0_G:I
-*.PININFO I1_lin_default_m_1_R0_S:I I1_lin_default_m_2_R0_D:I
-*.PININFO I1_lin_default_m_2_R0_G:I I1_lin_default_m_2_R0_S:I
-*.PININFO I1_lin_default_nf_0_R0_D:I I1_lin_default_nf_0_R0_G:I
-*.PININFO I1_lin_default_nf_0_R0_S:I I1_lin_default_nf_1_R0_D:I
-*.PININFO I1_lin_default_nf_1_R0_G:I I1_lin_default_nf_1_R0_S:I
-*.PININFO I1_lin_default_nf_2_R0_D:I I1_lin_default_nf_2_R0_G:I
-*.PININFO I1_lin_default_nf_2_R0_S:I I1_lin_default_rightTap_0_R0_D:I
-*.PININFO I1_lin_default_rightTap_0_R0_G:I I1_lin_default_rightTap_0_R0_S:I
-*.PININFO I1_lin_default_sFirst_0_R0_D:I I1_lin_default_sFirst_0_R0_G:I
-*.PININFO I1_lin_default_sFirst_0_R0_S:I I1_lin_default_sdConn_0_R0_D:I
-*.PININFO I1_lin_default_sdConn_0_R0_G:I I1_lin_default_sdConn_0_R0_S:I
-*.PININFO I1_lin_default_sdConn_1_R0_D:I I1_lin_default_sdConn_1_R0_G:I
-*.PININFO I1_lin_default_sdConn_1_R0_S:I I1_lin_default_sdConn_2_R0_D:I
-*.PININFO I1_lin_default_sdConn_2_R0_G:I I1_lin_default_sdConn_2_R0_S:I
-*.PININFO I1_lin_default_sdWidth_0_R0_D:I I1_lin_default_sdWidth_0_R0_G:I
-*.PININFO I1_lin_default_sdWidth_0_R0_S:I I1_lin_default_sdWidth_1_R0_D:I
-*.PININFO I1_lin_default_sdWidth_1_R0_G:I I1_lin_default_sdWidth_1_R0_S:I
-*.PININFO I1_lin_default_sdWidth_2_R0_D:I I1_lin_default_sdWidth_2_R0_G:I
-*.PININFO I1_lin_default_sdWidth_2_R0_S:I I1_lin_default_sdWidth_3_R0_D:I
-*.PININFO I1_lin_default_sdWidth_3_R0_G:I I1_lin_default_sdWidth_3_R0_S:I
-*.PININFO I1_lin_default_sdWidth_4_R0_D:I I1_lin_default_sdWidth_4_R0_G:I
-*.PININFO I1_lin_default_sdWidth_4_R0_S:I I1_lin_default_sdWidth_5_R0_D:I
-*.PININFO I1_lin_default_sdWidth_5_R0_G:I I1_lin_default_sdWidth_5_R0_S:I
-*.PININFO I1_lin_default_sdWidth_6_R0_D:I I1_lin_default_sdWidth_6_R0_G:I
-*.PININFO I1_lin_default_sdWidth_6_R0_S:I I1_lin_default_sdWidth_7_R0_D:I
-*.PININFO I1_lin_default_sdWidth_7_R0_G:I I1_lin_default_sdWidth_7_R0_S:I
-*.PININFO I1_lin_default_sdWidth_8_R0_D:I I1_lin_default_sdWidth_8_R0_G:I
-*.PININFO I1_lin_default_sdWidth_8_R0_S:I I1_lin_default_sdWidth_9_R0_D:I
-*.PININFO I1_lin_default_sdWidth_9_R0_G:I I1_lin_default_sdWidth_9_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_0_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_1_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_2_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_3_R0_S:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_D:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_G:I
-*.PININFO I1_lin_default_tapCntRows_4_R0_S:I I1_lin_default_topTap_0_R0_D:I
-*.PININFO I1_lin_default_topTap_0_R0_G:I I1_lin_default_topTap_0_R0_S:I gnd!:I
-MMP1 I1_lin_default_bodytie_2_R0_D I1_lin_default_bodytie_2_R0_G
-+ I1_lin_default_bodytie_2_R0_S gnd! pmos_3p3 m=1 w=720e-9 l=280n nf=2
-+ as=327.6e-15 ad=187.2e-15 ps=3.26e-6 pd=1.76e-6 nrd=0.361111 nrs=0.631944
-+ sa=0.470u sb=0.440u sd=0.520u dtemp=0 par=1
-MMP0 I1_lin_default_sFirst_1_R0_D I1_lin_default_sFirst_1_R0_G
-+ I1_lin_default_sFirst_1_R0_S gnd! pmos_3p3 m=1 w=16.8e-6 l=280n nf=5
-+ as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6 nrd=0.017619
-+ nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_fingerW_34_R0 I1_lin_default_fingerW_34_R0_D
-+ I1_lin_default_fingerW_34_R0_G I1_lin_default_fingerW_34_R0_S gnd! pmos_3p3
-+ m=1 w=1e-3 l=280n nf=10 as=296e-12 ad=260e-12 ps=1.20592e-3 pd=1.0052e-3
-+ nrd=0.000260 nrs=0.000296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_fingerW_33_R0 I1_lin_default_fingerW_33_R0_D
-+ I1_lin_default_fingerW_33_R0_G I1_lin_default_fingerW_33_R0_S gnd! pmos_3p3
-+ m=1 w=90.24e-6 l=280n nf=1 as=39.7056e-12 ad=39.7056e-12 ps=181.36e-6
-+ pd=181.36e-6 nrd=0.004876 nrs=0.004876 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_32_R0 I1_lin_default_fingerW_32_R0_D
-+ I1_lin_default_fingerW_32_R0_G I1_lin_default_fingerW_32_R0_S gnd! pmos_3p3
-+ m=1 w=75.2e-6 l=280n nf=1 as=33.088e-12 ad=33.088e-12 ps=151.28e-6
-+ pd=151.28e-6 nrd=0.005851 nrs=0.005851 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_31_R0 I1_lin_default_fingerW_31_R0_D
-+ I1_lin_default_fingerW_31_R0_G I1_lin_default_fingerW_31_R0_S gnd! pmos_3p3
-+ m=1 w=62.665e-6 l=280n nf=1 as=27.5726e-12 ad=27.5726e-12 ps=126.21e-6
-+ pd=126.21e-6 nrd=0.007021 nrs=0.007021 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_30_R0 I1_lin_default_fingerW_30_R0_D
-+ I1_lin_default_fingerW_30_R0_G I1_lin_default_fingerW_30_R0_S gnd! pmos_3p3
-+ m=1 w=52.225e-6 l=280n nf=1 as=22.979e-12 ad=22.979e-12 ps=105.33e-6
-+ pd=105.33e-6 nrd=0.008425 nrs=0.008425 sa=0.440u sb=0.440u sd=0u dtemp=0
-+ par=1
-MI1_lin_default_fingerW_29_R0 I1_lin_default_fingerW_29_R0_D
-+ I1_lin_default_fingerW_29_R0_G I1_lin_default_fingerW_29_R0_S gnd! pmos_3p3
-+ m=1 w=43.52e-6 l=280n nf=1 as=19.1488e-12 ad=19.1488e-12 ps=87.92e-6
-+ pd=87.92e-6 nrd=0.010110 nrs=0.010110 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_28_R0 I1_lin_default_fingerW_28_R0_D
-+ I1_lin_default_fingerW_28_R0_G I1_lin_default_fingerW_28_R0_S gnd! pmos_3p3
-+ m=1 w=36.265e-6 l=280n nf=1 as=15.9566e-12 ad=15.9566e-12 ps=73.41e-6
-+ pd=73.41e-6 nrd=0.012133 nrs=0.012133 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_27_R0 I1_lin_default_fingerW_27_R0_D
-+ I1_lin_default_fingerW_27_R0_G I1_lin_default_fingerW_27_R0_S gnd! pmos_3p3
-+ m=1 w=30.22e-6 l=280n nf=1 as=13.2968e-12 ad=13.2968e-12 ps=61.32e-6
-+ pd=61.32e-6 nrd=0.014560 nrs=0.014560 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_26_R0 I1_lin_default_fingerW_26_R0_D
-+ I1_lin_default_fingerW_26_R0_G I1_lin_default_fingerW_26_R0_S gnd! pmos_3p3
-+ m=1 w=25.185e-6 l=280n nf=1 as=11.0814e-12 ad=11.0814e-12 ps=51.25e-6
-+ pd=51.25e-6 nrd=0.017471 nrs=0.017471 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_25_R0 I1_lin_default_fingerW_25_R0_D
-+ I1_lin_default_fingerW_25_R0_G I1_lin_default_fingerW_25_R0_S gnd! pmos_3p3
-+ m=1 w=20.985e-6 l=280n nf=1 as=9.2334e-12 ad=9.2334e-12 ps=42.85e-6
-+ pd=42.85e-6 nrd=0.020967 nrs=0.020967 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_24_R0 I1_lin_default_fingerW_24_R0_D
-+ I1_lin_default_fingerW_24_R0_G I1_lin_default_fingerW_24_R0_S gnd! pmos_3p3
-+ m=1 w=17.49e-6 l=280n nf=1 as=7.6956e-12 ad=7.6956e-12 ps=35.86e-6
-+ pd=35.86e-6 nrd=0.025157 nrs=0.025157 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_23_R0 I1_lin_default_fingerW_23_R0_D
-+ I1_lin_default_fingerW_23_R0_G I1_lin_default_fingerW_23_R0_S gnd! pmos_3p3
-+ m=1 w=14.575e-6 l=280n nf=1 as=6.413e-12 ad=6.413e-12 ps=30.03e-6
-+ pd=30.03e-6 nrd=0.030189 nrs=0.030189 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_22_R0 I1_lin_default_fingerW_22_R0_D
-+ I1_lin_default_fingerW_22_R0_G I1_lin_default_fingerW_22_R0_S gnd! pmos_3p3
-+ m=1 w=12.145e-6 l=280n nf=1 as=5.3438e-12 ad=5.3438e-12 ps=25.17e-6
-+ pd=25.17e-6 nrd=0.036229 nrs=0.036229 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_21_R0 I1_lin_default_fingerW_21_R0_D
-+ I1_lin_default_fingerW_21_R0_G I1_lin_default_fingerW_21_R0_S gnd! pmos_3p3
-+ m=1 w=10.12e-6 l=280n nf=1 as=4.4528e-12 ad=4.4528e-12 ps=21.12e-6
-+ pd=21.12e-6 nrd=0.043478 nrs=0.043478 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_20_R0 I1_lin_default_fingerW_20_R0_D
-+ I1_lin_default_fingerW_20_R0_G I1_lin_default_fingerW_20_R0_S gnd! pmos_3p3
-+ m=1 w=8.435e-6 l=280n nf=1 as=3.7114e-12 ad=3.7114e-12 ps=17.75e-6
-+ pd=17.75e-6 nrd=0.052164 nrs=0.052164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_19_R0 I1_lin_default_fingerW_19_R0_D
-+ I1_lin_default_fingerW_19_R0_G I1_lin_default_fingerW_19_R0_S gnd! pmos_3p3
-+ m=1 w=7.03e-6 l=280n nf=1 as=3.0932e-12 ad=3.0932e-12 ps=14.94e-6
-+ pd=14.94e-6 nrd=0.062589 nrs=0.062589 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_18_R0 I1_lin_default_fingerW_18_R0_D
-+ I1_lin_default_fingerW_18_R0_G I1_lin_default_fingerW_18_R0_S gnd! pmos_3p3
-+ m=1 w=5.855e-6 l=280n nf=1 as=2.5762e-12 ad=2.5762e-12 ps=12.59e-6
-+ pd=12.59e-6 nrd=0.075149 nrs=0.075149 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_17_R0 I1_lin_default_fingerW_17_R0_D
-+ I1_lin_default_fingerW_17_R0_G I1_lin_default_fingerW_17_R0_S gnd! pmos_3p3
-+ m=1 w=4.88e-6 l=280n nf=1 as=2.1472e-12 ad=2.1472e-12 ps=10.64e-6
-+ pd=10.64e-6 nrd=0.090164 nrs=0.090164 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_16_R0 I1_lin_default_fingerW_16_R0_D
-+ I1_lin_default_fingerW_16_R0_G I1_lin_default_fingerW_16_R0_S gnd! pmos_3p3
-+ m=1 w=4.065e-6 l=280n nf=1 as=1.7886e-12 ad=1.7886e-12 ps=9.01e-6 pd=9.01e-6
-+ nrd=0.108241 nrs=0.108241 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_15_R0 I1_lin_default_fingerW_15_R0_D
-+ I1_lin_default_fingerW_15_R0_G I1_lin_default_fingerW_15_R0_S gnd! pmos_3p3
-+ m=1 w=3.39e-6 l=280n nf=1 as=1.4916e-12 ad=1.4916e-12 ps=7.66e-6 pd=7.66e-6
-+ nrd=0.129794 nrs=0.129794 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_14_R0 I1_lin_default_fingerW_14_R0_D
-+ I1_lin_default_fingerW_14_R0_G I1_lin_default_fingerW_14_R0_S gnd! pmos_3p3
-+ m=1 w=2.825e-6 l=280n nf=1 as=1.243e-12 ad=1.243e-12 ps=6.53e-6 pd=6.53e-6
-+ nrd=0.155752 nrs=0.155752 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_13_R0 I1_lin_default_fingerW_13_R0_D
-+ I1_lin_default_fingerW_13_R0_G I1_lin_default_fingerW_13_R0_S gnd! pmos_3p3
-+ m=1 w=2.355e-6 l=280n nf=1 as=1.0362e-12 ad=1.0362e-12 ps=5.59e-6 pd=5.59e-6
-+ nrd=0.186837 nrs=0.186837 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_12_R0 I1_lin_default_fingerW_12_R0_D
-+ I1_lin_default_fingerW_12_R0_G I1_lin_default_fingerW_12_R0_S gnd! pmos_3p3
-+ m=1 w=1.96e-6 l=280n nf=1 as=862.4e-15 ad=862.4e-15 ps=4.8e-6 pd=4.8e-6
-+ nrd=0.224490 nrs=0.224490 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_11_R0 I1_lin_default_fingerW_11_R0_D
-+ I1_lin_default_fingerW_11_R0_G I1_lin_default_fingerW_11_R0_S gnd! pmos_3p3
-+ m=1 w=1.635e-6 l=280n nf=1 as=719.4e-15 ad=719.4e-15 ps=4.15e-6 pd=4.15e-6
-+ nrd=0.269113 nrs=0.269113 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_10_R0 I1_lin_default_fingerW_10_R0_D
-+ I1_lin_default_fingerW_10_R0_G I1_lin_default_fingerW_10_R0_S gnd! pmos_3p3
-+ m=1 w=1.36e-6 l=280n nf=1 as=598.4e-15 ad=598.4e-15 ps=3.6e-6 pd=3.6e-6
-+ nrd=0.323529 nrs=0.323529 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_9_R0 I1_lin_default_fingerW_9_R0_D
-+ I1_lin_default_fingerW_9_R0_G I1_lin_default_fingerW_9_R0_S gnd! pmos_3p3
-+ m=1 w=1.135e-6 l=280n nf=1 as=499.4e-15 ad=499.4e-15 ps=3.15e-6 pd=3.15e-6
-+ nrd=0.387665 nrs=0.387665 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_8_R0 I1_lin_default_fingerW_8_R0_D
-+ I1_lin_default_fingerW_8_R0_G I1_lin_default_fingerW_8_R0_S gnd! pmos_3p3
-+ m=1 w=945e-9 l=280n nf=1 as=415.8e-15 ad=415.8e-15 ps=2.77e-6 pd=2.77e-6
-+ nrd=0.465608 nrs=0.465608 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_7_R0 I1_lin_default_fingerW_7_R0_D
-+ I1_lin_default_fingerW_7_R0_G I1_lin_default_fingerW_7_R0_S gnd! pmos_3p3
-+ m=1 w=790e-9 l=280n nf=1 as=347.6e-15 ad=347.6e-15 ps=2.46e-6 pd=2.46e-6
-+ nrd=0.556962 nrs=0.556962 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_6_R0 I1_lin_default_fingerW_6_R0_D
-+ I1_lin_default_fingerW_6_R0_G I1_lin_default_fingerW_6_R0_S gnd! pmos_3p3
-+ m=1 w=655e-9 l=280n nf=1 as=288.2e-15 ad=288.2e-15 ps=2.19e-6 pd=2.19e-6
-+ nrd=0.671756 nrs=0.671756 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_5_R0 I1_lin_default_fingerW_5_R0_D
-+ I1_lin_default_fingerW_5_R0_G I1_lin_default_fingerW_5_R0_S gnd! pmos_3p3
-+ m=1 w=545e-9 l=280n nf=1 as=239.8e-15 ad=239.8e-15 ps=1.97e-6 pd=1.97e-6
-+ nrd=0.807339 nrs=0.807339 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_4_R0 I1_lin_default_fingerW_4_R0_D
-+ I1_lin_default_fingerW_4_R0_G I1_lin_default_fingerW_4_R0_S gnd! pmos_3p3
-+ m=1 w=455e-9 l=280n nf=1 as=200.2e-15 ad=200.2e-15 ps=1.79e-6 pd=1.79e-6
-+ nrd=0.967033 nrs=0.967033 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_3_R0 I1_lin_default_fingerW_3_R0_D
-+ I1_lin_default_fingerW_3_R0_G I1_lin_default_fingerW_3_R0_S gnd! pmos_3p3
-+ m=1 w=380e-9 l=280n nf=1 as=167.2e-15 ad=167.2e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=1.157895 nrs=1.157895 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_2_R0 I1_lin_default_fingerW_2_R0_D
-+ I1_lin_default_fingerW_2_R0_G I1_lin_default_fingerW_2_R0_S gnd! pmos_3p3
-+ m=1 w=315e-9 l=280n nf=1 as=161.1e-15 ad=161.1e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=1.623583 nrs=1.623583 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_1_R0 I1_lin_default_fingerW_1_R0_D
-+ I1_lin_default_fingerW_1_R0_G I1_lin_default_fingerW_1_R0_S gnd! pmos_3p3
-+ m=1 w=265e-9 l=280n nf=1 as=156.1e-15 ad=156.1e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=2.222855 nrs=2.222855 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_fingerW_0_R0 I1_lin_default_fingerW_0_R0_D
-+ I1_lin_default_fingerW_0_R0_G I1_lin_default_fingerW_0_R0_S gnd! pmos_3p3
-+ m=1 w=220e-9 l=280n nf=1 as=151.6e-15 ad=151.6e-15 ps=1.64e-6 pd=1.64e-6
-+ nrd=3.132231 nrs=3.132231 sa=0.460u sb=0.460u sd=0u dtemp=0 par=1
-MI1_lin_default_l_29_R0 I1_lin_default_l_29_R0_D I1_lin_default_l_29_R0_G
-+ I1_lin_default_l_29_R0_S gnd! pmos_3p3 m=1 w=26.8e-6 l=50.000u nf=5
-+ as=7.9328e-12 ad=7.9328e-12 ps=35.12e-6 pd=35.12e-6 nrd=0.011045
-+ nrs=0.011045 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_l_28_R0 I1_lin_default_l_28_R0_D I1_lin_default_l_28_R0_G
-+ I1_lin_default_l_28_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=46.155u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_27_R0 I1_lin_default_l_27_R0_D I1_lin_default_l_27_R0_G
-+ I1_lin_default_l_27_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=38.465u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_26_R0 I1_lin_default_l_26_R0_D I1_lin_default_l_26_R0_G
-+ I1_lin_default_l_26_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=32.055u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_25_R0 I1_lin_default_l_25_R0_D I1_lin_default_l_25_R0_G
-+ I1_lin_default_l_25_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=26.710u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_24_R0 I1_lin_default_l_24_R0_D I1_lin_default_l_24_R0_G
-+ I1_lin_default_l_24_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=22.260u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_23_R0 I1_lin_default_l_23_R0_D I1_lin_default_l_23_R0_G
-+ I1_lin_default_l_23_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=18.550u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_22_R0 I1_lin_default_l_22_R0_D I1_lin_default_l_22_R0_G
-+ I1_lin_default_l_22_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=15.460u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_21_R0 I1_lin_default_l_21_R0_D I1_lin_default_l_21_R0_G
-+ I1_lin_default_l_21_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=12.880u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_20_R0 I1_lin_default_l_20_R0_D I1_lin_default_l_20_R0_G
-+ I1_lin_default_l_20_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=10.735u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_19_R0 I1_lin_default_l_19_R0_D I1_lin_default_l_19_R0_G
-+ I1_lin_default_l_19_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=8.945u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_18_R0 I1_lin_default_l_18_R0_D I1_lin_default_l_18_R0_G
-+ I1_lin_default_l_18_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=7.455u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_17_R0 I1_lin_default_l_17_R0_D I1_lin_default_l_17_R0_G
-+ I1_lin_default_l_17_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=6.210u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_16_R0 I1_lin_default_l_16_R0_D I1_lin_default_l_16_R0_G
-+ I1_lin_default_l_16_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=5.175u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_15_R0 I1_lin_default_l_15_R0_D I1_lin_default_l_15_R0_G
-+ I1_lin_default_l_15_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=4.315u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_14_R0 I1_lin_default_l_14_R0_D I1_lin_default_l_14_R0_G
-+ I1_lin_default_l_14_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=3.595u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_13_R0 I1_lin_default_l_13_R0_D I1_lin_default_l_13_R0_G
-+ I1_lin_default_l_13_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=2.995u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_12_R0 I1_lin_default_l_12_R0_D I1_lin_default_l_12_R0_G
-+ I1_lin_default_l_12_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=2.495u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_11_R0 I1_lin_default_l_11_R0_D I1_lin_default_l_11_R0_G
-+ I1_lin_default_l_11_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=2.080u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_10_R0 I1_lin_default_l_10_R0_D I1_lin_default_l_10_R0_G
-+ I1_lin_default_l_10_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=1.735u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_9_R0 I1_lin_default_l_9_R0_D I1_lin_default_l_9_R0_G
-+ I1_lin_default_l_9_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=1.445u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_8_R0 I1_lin_default_l_8_R0_D I1_lin_default_l_8_R0_G
-+ I1_lin_default_l_8_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=1.205u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_7_R0 I1_lin_default_l_7_R0_D I1_lin_default_l_7_R0_G
-+ I1_lin_default_l_7_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=1.005u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_6_R0 I1_lin_default_l_6_R0_D I1_lin_default_l_6_R0_G
-+ I1_lin_default_l_6_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=0.835u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_5_R0 I1_lin_default_l_5_R0_D I1_lin_default_l_5_R0_G
-+ I1_lin_default_l_5_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=0.695u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_4_R0 I1_lin_default_l_4_R0_D I1_lin_default_l_4_R0_G
-+ I1_lin_default_l_4_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=0.580u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_3_R0 I1_lin_default_l_3_R0_D I1_lin_default_l_3_R0_G
-+ I1_lin_default_l_3_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=0.485u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_2_R0 I1_lin_default_l_2_R0_D I1_lin_default_l_2_R0_G
-+ I1_lin_default_l_2_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=0.405u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_1_R0 I1_lin_default_l_1_R0_D I1_lin_default_l_1_R0_G
-+ I1_lin_default_l_1_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=0.335u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_l_0_R0 I1_lin_default_l_0_R0_D I1_lin_default_l_0_R0_G
-+ I1_lin_default_l_0_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=0.280u nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_nf_2_R0 I1_lin_default_nf_2_R0_D I1_lin_default_nf_2_R0_G
-+ I1_lin_default_nf_2_R0_S gnd! pmos_3p3 m=1 w=36e-6 l=280n nf=100
-+ as=9.4896e-12 ad=9.36e-12 ps=89.44e-6 pd=88e-6 nrd=0.007222 nrs=0.007322
-+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_nf_1_R0 I1_lin_default_nf_1_R0_D I1_lin_default_nf_1_R0_G
-+ I1_lin_default_nf_1_R0_S gnd! pmos_3p3 m=1 w=18.36e-6 l=280n nf=51
-+ as=4.8384e-12 ad=4.8384e-12 ps=45.6e-6 pd=45.6e-6 nrd=0.014353 nrs=0.014353
-+ sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_nf_0_R0 I1_lin_default_nf_0_R0_D I1_lin_default_nf_0_R0_G
-+ I1_lin_default_nf_0_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
-+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
-+ sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_m_2_R0 I1_lin_default_m_2_R0_D I1_lin_default_m_2_R0_G
-+ I1_lin_default_m_2_R0_S gnd! pmos_3p3 m=100 w=360e-9 l=280n nf=1
-+ as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222
-+ sa=0.440u sb=0.440u sd=0u dtemp=0 par=100
-MI1_lin_default_m_1_R0 I1_lin_default_m_1_R0_D I1_lin_default_m_1_R0_G
-+ I1_lin_default_m_1_R0_S gnd! pmos_3p3 m=51 w=360e-9 l=280n nf=1 as=158.4e-15
-+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
-+ sb=0.440u sd=0u dtemp=0 par=51
-MI1_lin_default_m_0_R0 I1_lin_default_m_0_R0_D I1_lin_default_m_0_R0_G
-+ I1_lin_default_m_0_R0_S gnd! pmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15
-+ ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u
-+ sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_calculatedParam_2_R0 I1_lin_default_calculatedParam_2_R0_D
-+ I1_lin_default_calculatedParam_2_R0_G I1_lin_default_calculatedParam_2_R0_S
-+ gnd! pmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_calculatedParam_1_R0 I1_lin_default_calculatedParam_1_R0_D
-+ I1_lin_default_calculatedParam_1_R0_G I1_lin_default_calculatedParam_1_R0_S
-+ gnd! pmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_calculatedParam_0_R0 I1_lin_default_calculatedParam_0_R0_D
-+ I1_lin_default_calculatedParam_0_R0_G I1_lin_default_calculatedParam_0_R0_S
-+ gnd! pmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_gateConn_2_R0 I1_lin_default_gateConn_2_R0_D
-+ I1_lin_default_gateConn_2_R0_G I1_lin_default_gateConn_2_R0_S gnd! pmos_3p3
-+ m=1 w=16.08e-6 l=280n nf=3 as=5.1456e-12 ad=5.1456e-12 ps=23.36e-6
-+ pd=23.36e-6 nrd=0.019900 nrs=0.019900 sa=0.440u sb=0.440u sd=0.520u dtemp=0
-+ par=1
-MI1_lin_default_gateConn_1_R0 I1_lin_default_gateConn_1_R0_D
-+ I1_lin_default_gateConn_1_R0_G I1_lin_default_gateConn_1_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_gateConn_0_R0 I1_lin_default_gateConn_0_R0_D
-+ I1_lin_default_gateConn_0_R0_G I1_lin_default_gateConn_0_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_9_R0 I1_lin_default_sdWidth_9_R0_D
-+ I1_lin_default_sdWidth_9_R0_G I1_lin_default_sdWidth_9_R0_S gnd! pmos_3p3
-+ m=1 w=1.8e-6 l=280n nf=5 as=1.3644e-12 ad=1.3644e-12 ps=9.74e-6 pd=9.74e-6
-+ nrd=0.421111 nrs=0.421111 sa=1.210u sb=1.210u sd=1.290u dtemp=0 par=1
-MI1_lin_default_sdWidth_8_R0 I1_lin_default_sdWidth_8_R0_D
-+ I1_lin_default_sdWidth_8_R0_G I1_lin_default_sdWidth_8_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=432e-15 ad=432e-15 ps=3.12e-6 pd=3.12e-6
-+ nrd=3.333333 nrs=3.333333 sa=1.200u sb=1.200u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_7_R0 I1_lin_default_sdWidth_7_R0_D
-+ I1_lin_default_sdWidth_7_R0_G I1_lin_default_sdWidth_7_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=372.6e-15 ad=372.6e-15 ps=2.79e-6 pd=2.79e-6
-+ nrd=2.875000 nrs=2.875000 sa=1.035u sb=1.035u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_6_R0 I1_lin_default_sdWidth_6_R0_D
-+ I1_lin_default_sdWidth_6_R0_G I1_lin_default_sdWidth_6_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=322.2e-15 ad=322.2e-15 ps=2.51e-6 pd=2.51e-6
-+ nrd=2.486111 nrs=2.486111 sa=0.895u sb=0.895u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_5_R0 I1_lin_default_sdWidth_5_R0_D
-+ I1_lin_default_sdWidth_5_R0_G I1_lin_default_sdWidth_5_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=280.8e-15 ad=280.8e-15 ps=2.28e-6 pd=2.28e-6
-+ nrd=2.166667 nrs=2.166667 sa=0.780u sb=0.780u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_4_R0 I1_lin_default_sdWidth_4_R0_D
-+ I1_lin_default_sdWidth_4_R0_G I1_lin_default_sdWidth_4_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=246.6e-15 ad=246.6e-15 ps=2.09e-6 pd=2.09e-6
-+ nrd=1.902778 nrs=1.902778 sa=0.685u sb=0.685u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_3_R0 I1_lin_default_sdWidth_3_R0_D
-+ I1_lin_default_sdWidth_3_R0_G I1_lin_default_sdWidth_3_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=217.8e-15 ad=217.8e-15 ps=1.93e-6 pd=1.93e-6
-+ nrd=1.680556 nrs=1.680556 sa=0.605u sb=0.605u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_2_R0 I1_lin_default_sdWidth_2_R0_D
-+ I1_lin_default_sdWidth_2_R0_G I1_lin_default_sdWidth_2_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=194.4e-15 ad=194.4e-15 ps=1.8e-6 pd=1.8e-6
-+ nrd=1.500000 nrs=1.500000 sa=0.540u sb=0.540u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_1_R0 I1_lin_default_sdWidth_1_R0_D
-+ I1_lin_default_sdWidth_1_R0_G I1_lin_default_sdWidth_1_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=174.6e-15 ad=174.6e-15 ps=1.69e-6 pd=1.69e-6
-+ nrd=1.347222 nrs=1.347222 sa=0.485u sb=0.485u sd=0u dtemp=0 par=1
-MI1_lin_default_sdWidth_0_R0 I1_lin_default_sdWidth_0_R0_D
-+ I1_lin_default_sdWidth_0_R0_G I1_lin_default_sdWidth_0_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_sFirst_0_R0 I1_lin_default_sFirst_0_R0_D
-+ I1_lin_default_sFirst_0_R0_G I1_lin_default_sFirst_0_R0_S gnd! pmos_3p3 m=1
-+ w=16.8e-6 l=280n nf=5 as=4.9728e-12 ad=4.9728e-12 ps=23.12e-6 pd=23.12e-6
-+ nrd=0.017619 nrs=0.017619 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_2_R0 I1_lin_default_sdConn_2_R0_D
-+ I1_lin_default_sdConn_2_R0_G I1_lin_default_sdConn_2_R0_S gnd! pmos_3p3 m=1
-+ w=1.08e-6 l=280n nf=3 as=345.6e-15 ad=345.6e-15 ps=3.36e-6 pd=3.36e-6
-+ nrd=0.296296 nrs=0.296296 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_1_R0 I1_lin_default_sdConn_1_R0_D
-+ I1_lin_default_sdConn_1_R0_G I1_lin_default_sdConn_1_R0_S gnd! pmos_3p3 m=1
-+ w=720e-9 l=280n nf=2 as=187.2e-15 ad=316.8e-15 ps=1.76e-6 pd=3.2e-6
-+ nrd=0.611111 nrs=0.361111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_sdConn_0_R0 I1_lin_default_sdConn_0_R0_D
-+ I1_lin_default_sdConn_0_R0_G I1_lin_default_sdConn_0_R0_S gnd! pmos_3p3 m=1
-+ w=720e-9 l=280n nf=2 as=316.8e-15 ad=187.2e-15 ps=3.2e-6 pd=1.76e-6
-+ nrd=0.361111 nrs=0.611111 sa=0.440u sb=0.440u sd=0.520u dtemp=0 par=1
-MI1_lin_default_bodytie_1_R0 I1_lin_default_bodytie_1_R0_D
-+ I1_lin_default_bodytie_1_R0_G I1_lin_default_bodytie_1_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_bodytie_0_R0 I1_lin_default_bodytie_0_R0_D
-+ I1_lin_default_bodytie_0_R0_G I1_lin_default_bodytie_0_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=169.2e-15 ad=158.4e-15 ps=1.66e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.305556 sa=0.470u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_leftTap_0_R0 I1_lin_default_leftTap_0_R0_D
-+ I1_lin_default_leftTap_0_R0_G I1_lin_default_leftTap_0_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_rightTap_0_R0 I1_lin_default_rightTap_0_R0_D
-+ I1_lin_default_rightTap_0_R0_G I1_lin_default_rightTap_0_R0_S gnd! pmos_3p3
-+ m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_topTap_0_R0 I1_lin_default_topTap_0_R0_D
-+ I1_lin_default_topTap_0_R0_G I1_lin_default_topTap_0_R0_S gnd! pmos_3p3 m=1
-+ w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6
-+ nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_bottomTap_0_R0 I1_lin_default_bottomTap_0_R0_D
-+ I1_lin_default_bottomTap_0_R0_G I1_lin_default_bottomTap_0_R0_S gnd!
-+ pmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_4_R0 I1_lin_default_tapCntRows_4_R0_D
-+ I1_lin_default_tapCntRows_4_R0_G I1_lin_default_tapCntRows_4_R0_S gnd!
-+ pmos_3p3 m=1 w=26.8e-6 l=280n nf=5 as=7.9328e-12 ad=7.9328e-12 ps=35.12e-6
-+ pd=35.12e-6 nrd=0.011045 nrs=0.011045 sa=0.440u sb=0.440u sd=0.520u dtemp=0
-+ par=1
-MI1_lin_default_tapCntRows_3_R0 I1_lin_default_tapCntRows_3_R0_D
-+ I1_lin_default_tapCntRows_3_R0_G I1_lin_default_tapCntRows_3_R0_S gnd!
-+ pmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_2_R0 I1_lin_default_tapCntRows_2_R0_D
-+ I1_lin_default_tapCntRows_2_R0_G I1_lin_default_tapCntRows_2_R0_S gnd!
-+ pmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_1_R0 I1_lin_default_tapCntRows_1_R0_D
-+ I1_lin_default_tapCntRows_1_R0_G I1_lin_default_tapCntRows_1_R0_S gnd!
-+ pmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_lin_default_tapCntRows_0_R0 I1_lin_default_tapCntRows_0_R0_D
-+ I1_lin_default_tapCntRows_0_R0_G I1_lin_default_tapCntRows_0_R0_S gnd!
-+ pmos_3p3 m=1 w=360e-9 l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6
-+ pd=1.6e-6 nrd=1.222222 nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-MI1_default I1_default_D I1_default_G I1_default_S gnd! pmos_3p3 m=1 w=360e-9
-+ l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222
-+ nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-.ENDS
-
diff --git a/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/layout/pnvar_1p8.gds b/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/layout/pnvar_1p8.gds
deleted file mode 100644
index 0770ae8..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/layout/pnvar_1p8.gds
+++ /dev/null
Binary files differ
diff --git a/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/netlist/pnvar_1p8.cdl b/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/netlist/pnvar_1p8.cdl
deleted file mode 100644
index 7ff65b0..0000000
--- a/IC/klayout/lvs/testing/testcases/unit/pn_varactor_devices/netlist/pnvar_1p8.cdl
+++ /dev/null
@@ -1,40 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: pnvar_1p8
-* View Name: schematic
-* Netlisted on: Nov 24 09:16:13 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-*.GLOBAL vdd!
-
-*.PIN vdd!
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: pnvar_1p8
-* View Name: schematic
-************************************************************************
-
-.SUBCKT pnvar_1p8 I1_0_2_0_0_R0_MINUS I1_0_1_0_0_R0_MINUS
-+ I1_0_0_0_0_R0_MINUS I1_default_MINUS
-+ I1_0_2_0_0_R0_PLUS I1_0_1_0_0_R0_PLUS I1_0_0_0_0_R0_PLUS I1_default_PLUS
-
-CI1_0_2_0_0_R0 I1_0_2_0_0_R0_PLUS I1_0_2_0_0_R0_MINUS pnvar_1p8 AREA=4.752p PJ=27.12u
-CI1_0_1_0_0_R0 I1_0_1_0_0_R0_PLUS I1_0_1_0_0_R0_MINUS pnvar_1p8 AREA=396f PJ=2.92u
-CI1_0_0_0_0_R0 I1_0_0_0_0_R0_PLUS I1_0_0_0_0_R0_MINUS pnvar_1p8 AREA=203.4f PJ=1.85u
-CI1_default I1_default_PLUS I1_default_MINUS pnvar_1p8 AREA=1p PJ=4u
-.ENDS
-
diff --git a/ULL/klayout/lvs/gf180ull.lvs b/ULL/klayout/lvs/gf180ULL.lvs
similarity index 96%
rename from ULL/klayout/lvs/gf180ull.lvs
rename to ULL/klayout/lvs/gf180ULL.lvs
index f15323e..6b85d97 100644
--- a/ULL/klayout/lvs/gf180ull.lvs
+++ b/ULL/klayout/lvs/gf180ULL.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -114,11 +114,6 @@
logger.info("Selected NET_ONLY option: #{NET_ONLY}")
-# NET_ONLY
-NET_ONLY = bool_check?($net_only)
-
-logger.info("Selected NET_ONLY option: #{NET_ONLY}")
-
# TOP_LVL_PINS
TOP_LVL_PINS = bool_check?($top_lvl_pins)
@@ -140,7 +135,7 @@
logger.info("Selected PURGE_NETS option: #{PURGE_NETS}")
# SIMPLIFY
-SIMPLIFY = if $net_only || $top_lvl_pins || $combine || $purge || $purge_nets
+SIMPLIFY = if NET_ONLY || TOP_LVL_PINS || COMBINE || PURGE || PURGE_NETS
false
else
true
@@ -263,7 +258,6 @@
# ------ DIODE DERIVATIONS --------
#================================
-# %include 'rule_decks/diode_derivations.lvs'
#================================
# ------ MOSCAP DERIVATIONS -----
@@ -317,7 +311,6 @@
# ------- Diode EXTRACTION ------
#================================
-# %include 'rule_decks/diode_extraction.lvs'
#================================
# ------- MOSCAP EXTRACTION -----
diff --git a/ULL/klayout/lvs/rule_decks/bjt_connection.lvs b/ULL/klayout/lvs/rule_decks/bjt_connections.lvs
similarity index 98%
rename from ULL/klayout/lvs/rule_decks/bjt_connection.lvs
rename to ULL/klayout/lvs/rule_decks/bjt_connections.lvs
index d0a894f..9ce6800 100644
--- a/ULL/klayout/lvs/rule_decks/bjt_connection.lvs
+++ b/ULL/klayout/lvs/rule_decks/bjt_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/bjt_derivations.lvs b/ULL/klayout/lvs/rule_decks/bjt_derivations.lvs
index 3e90979..91e01af 100644
--- a/ULL/klayout/lvs/rule_decks/bjt_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/bjt_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -20,27 +20,29 @@
logger.info('Starting BJT DERIVATIONS')
+#============================
+# ------ BJT EXCLUDE --------
+#============================
+
+bjt_exclude = sab.join(esd).join(resistor)
+ .join(fusetop).join(polyfuse).join(cap_mk)
+ .join(diode_mk).join(nat).join(v5_xtor)
+ .join(fhres).join(fusewindow_d).join(piscap)
+ .join(mos_cap_mk).join(mim_l_mk).join(res_mk)
+
# ========================================
# ---- VNPN (isolated collector) (5V) ----
# ========================================
logger.info('Starting VNPN (5V) layers DERIVATIONS')
+ncomp_dn = ncomp.and(dnwell)
+ncomp_dn_pw = ncomp_dn.and(lvpwell)
+pcomp_dn_pw = pcomp.and(dnwell).and(lvpwell)
+
# VNPN (5V) general nodes DERIVATIONS
-vnpn_5v_e = ncomp.inside(dnwell).inside(lvpwell).and(lvs_bjt).inside(drc_bjt).and(dv2).not(dualgate)
- .not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse).not_interacting(cap_mk)
- .not_interacting(diode_mk).not(nat).not(v5_xtor).outside(fhres).not(fusewindow_d)
- .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
-
-vnpn_5v_b = pcomp.and(lvpwell).inside(dnwell).inside(drc_bjt).and(dv2).not(dualgate)
- .not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse).not_interacting(cap_mk)
- .not_interacting(diode_mk).not(nat).not(v5_xtor).outside(fhres).not(fusewindow_d)
- .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
-
-vnpn_5v_c = ncomp.inside(dnwell).outside(lvs_bjt).inside(drc_bjt).and(dv2).not(dualgate)
- .not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse).not_interacting(cap_mk)
- .not_interacting(diode_mk).not(nat).not(v5_xtor).outside(fhres).not(fusewindow_d)
- .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
-
+vnpn_5v_e = ncomp_dn_pw.and(lvs_bjt).and(drc_bjt).and(dv2).not(dualgate).not(bjt_exclude)
+vnpn_5v_b = pcomp_dn_pw.and(drc_bjt).and(dv2).not(dualgate).not(bjt_exclude)
+vnpn_5v_c = ncomp_dn.not(lvs_bjt).and(drc_bjt).and(dv2).not(dualgate).not(bjt_exclude)
# vnpn_0p54x16 nodes DERIVATIONS
npn_00p54x16p00_e = vnpn_5v_e.with_area(8.um, 9.um).interacting(vnpn_5v_e.edges.with_length(15.5.um, 16.5.um))
@@ -62,28 +64,15 @@
npn_05p00x05p00_b = vnpn_5v_b.interacting(vnpn_5v_b.extents.interacting(npn_05p00x05p00_e))
npn_05p00x05p00_c = vnpn_5v_c.interacting(vnpn_5v_c.extents.interacting(npn_05p00x05p00_e))
-
# ===========================================
# ---- VNPN (isolated collector) (3.3V) ----
# ===========================================
logger.info('Starting VNPN (3.3V) layers DERIVATIONS')
# VNPN (3.3V) general nodes DERIVATIONS
-vnpn_e = ncomp.inside(dnwell).inside(lvpwell).and(lvs_bjt).inside(drc_bjt).not(dv2).and(dualgate)
- .not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse).not_interacting(cap_mk)
- .not_interacting(diode_mk).not(nat).not(v5_xtor).outside(fhres).not(fusewindow_d)
- .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
-
-vnpn_b = pcomp.and(lvpwell).inside(dnwell).inside(drc_bjt).not(dv2).and(dualgate)
- .not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse).not_interacting(cap_mk)
- .not_interacting(diode_mk).not(nat).not(v5_xtor).outside(fhres).not(fusewindow_d)
- .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
-
-vnpn_c = ncomp.inside(dnwell).outside(lvs_bjt).inside(drc_bjt).not(dv2).and(dualgate)
- .not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse).not_interacting(cap_mk)
- .not_interacting(diode_mk).not(nat).not(v5_xtor).outside(fhres).not(fusewindow_d)
- .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
-
+vnpn_e = ncomp_dn_pw.and(lvs_bjt).and(drc_bjt).not(dv2).and(dualgate).not(bjt_exclude)
+vnpn_b = pcomp_dn_pw.and(drc_bjt).not(dv2).and(dualgate).not(bjt_exclude)
+vnpn_c = ncomp_dn.not(lvs_bjt).and(drc_bjt).not(dv2).and(dualgate).not(bjt_exclude)
# vnpn_0p54x16_3p3 nodes DERIVATIONS
npn_00p54x16p00_e_3p3 = vnpn_e.with_area(8.um, 9.um).interacting(vnpn_e.edges.with_length(15.5.um, 16.5.um))
@@ -105,27 +94,14 @@
npn_05p00x05p00_b_3p3 = vnpn_b.interacting(vnpn_b.extents.interacting(npn_05p00x05p00_e_3p3))
npn_05p00x05p00_c_3p3 = vnpn_c.interacting(vnpn_c.extents.interacting(npn_05p00x05p00_e_3p3))
-
# ========================================
# ---- VPNP (Psub as collector) (6V) ----
# ========================================
logger.info('Starting VPNP (6V) layers DERIVATIONS')
-vpnp_e = pcomp.inside(nwell).not(lvpwell).outside(dnwell).and(lvs_bjt).inside(drc_bjt).and(dv2).not(dualgate)
- .not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse).not_interacting(cap_mk)
- .not_interacting(diode_mk).not(nat).not(v5_xtor).outside(fhres).not(fusewindow_d)
- .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
-
-vpnp_b = ncomp.and(nwell).not(lvpwell).outside(dnwell).inside(drc_bjt).and(dv2).not(dualgate).not(res_mk)
- .not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse).not_interacting(cap_mk)
- .not_interacting(diode_mk).not(nat).not(v5_xtor).outside(fhres).not(fusewindow_d)
- .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)
-
-vpnp_c = ptap.outside(lvs_bjt).not(lvpwell).inside(drc_bjt).and(dv2).not(dualgate)
- .not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse).not_interacting(cap_mk)
- .not_interacting(diode_mk).not(nat).not(v5_xtor).outside(fhres).not(fusewindow_d)
- .not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk)
-
+vpnp_e = pcomp.and(nwell).not(lvpwell).not(dnwell).and(lvs_bjt).and(drc_bjt).and(dv2).not(dualgate).not(bjt_exclude)
+vpnp_b = ncomp.and(nwell).not(lvpwell).not(dnwell).and(drc_bjt).and(dv2).not(dualgate).not(bjt_exclude)
+vpnp_c = ptap.not(lvs_bjt).not(lvpwell).and(drc_bjt).and(dv2).not(dualgate).not(bjt_exclude)
# vpnp_6p0_10x10 nodes DERIVATIONS
pnp_10p00x10p00_e = vpnp_e.with_area(99.5.um, 100.5.um).interacting(vpnp_e.edges.with_length(9.8.um, 10.2.um))
diff --git a/ULL/klayout/lvs/rule_decks/bjt_extraction.lvs b/ULL/klayout/lvs/rule_decks/bjt_extraction.lvs
index d1090fe..e0c478d 100644
--- a/ULL/klayout/lvs/rule_decks/bjt_extraction.lvs
+++ b/ULL/klayout/lvs/rule_decks/bjt_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -26,10 +26,9 @@
# ========================================
logger.info('Starting VNPN (5V) BJT EXTRACTION')
-# vnpn_0p54x16 BJT
-ignore_parameter('vnpn_0p54x16', 'AE')
-logger.info('Extracting vnpn_0p54x16 BJT')
-extract_devices(bjt4('vnpn_0p54x16'), { 'C' => npn_00p54x16p00_c.extents,
+# npn_00p54x16p00 BJT: Gummel-Poon model for VNPN with emitter size 0.54um x 16um [vnpn_0p54x16]
+logger.info('Extracting npn_00p54x16p00 BJT')
+extract_devices(bjt4('npn_00p54x16p00'), { 'C' => npn_00p54x16p00_c.extents,
'B' => npn_00p54x16p00_b.extents,
'E' => npn_00p54x16p00_e,
'S' => sub.extents,
@@ -37,12 +36,11 @@
'tB' => npn_00p54x16p00_b,
'tE' => npn_00p54x16p00_e,
'tS' => sub })
+ignore_parameter('npn_00p54x16p00', 'AE')
-
-# vnpn_0p54x8 BJT
-ignore_parameter('vnpn_0p54x8', 'AE')
-logger.info('Extracting vnpn_0p54x8 BJT')
-extract_devices(bjt4('vnpn_0p54x8'), { 'C' => npn_00p54x08p00_c.extents,
+# npn_00p54x08p00 BJT: Gummel-Poon model for VNPN with emitter size 0.54um x 8um [vnpn_0p54x8]
+logger.info('Extracting npn_00p54x08p00 BJT')
+extract_devices(bjt4('npn_00p54x08p00'), { 'C' => npn_00p54x08p00_c.extents,
'B' => npn_00p54x08p00_b.extents,
'E' => npn_00p54x08p00_e,
'S' => sub.extents,
@@ -50,11 +48,11 @@
'tB' => npn_00p54x08p00_b,
'tE' => npn_00p54x08p00_e,
'tS' => sub })
+ignore_parameter('npn_00p54x08p00', 'AE')
-# vnpn_0p54x2 BJT
-ignore_parameter('vnpn_0p54x2', 'AE')
-logger.info('Extracting vnpn_0p54x2 BJT')
-extract_devices(bjt4('vnpn_0p54x2'), { 'C' => npn_00p54x02p00_c.extents,
+# npn_00p54x02p00 BJT: Gummel-Poon model for VNPN with emitter size 0.54um x 2um [vnpn_0p54x2]
+logger.info('Extracting npn_00p54x02p00 BJT')
+extract_devices(bjt4('npn_00p54x02p00'), { 'C' => npn_00p54x02p00_c.extents,
'B' => npn_00p54x02p00_b.extents,
'E' => npn_00p54x02p00_e,
'S' => sub.extents,
@@ -62,11 +60,11 @@
'tB' => npn_00p54x02p00_b,
'tE' => npn_00p54x02p00_e,
'tS' => sub })
+ignore_parameter('npn_00p54x02p00', 'AE')
-# vnpn_5x5 BJT
-ignore_parameter('vnpn_5x5', 'AE')
-logger.info('Extracting vnpn_5x5 BJT')
-extract_devices(bjt4('vnpn_5x5'), { 'C' => npn_05p00x05p00_c.extents,
+# npn_05p00x05p00 BJT: Gummel-Poon model for VNPN with emitter size 5um x 5um [vnpn_5x5]
+logger.info('Extracting npn_05p00x05p00 BJT')
+extract_devices(bjt4('npn_05p00x05p00'), { 'C' => npn_05p00x05p00_c.extents,
'B' => npn_05p00x05p00_b.extents,
'E' => npn_05p00x05p00_e,
'S' => sub.extents,
@@ -74,17 +72,17 @@
'tB' => npn_05p00x05p00_b,
'tE' => npn_05p00x05p00_e,
'tS' => sub })
-
+ignore_parameter('npn_05p00x05p00', 'AE')
# ===========================================
# ---- VNPN (isolated collector) (3.3V) ----
# ===========================================
+
logger.info('Starting VNPN (3.3V) BJT EXTRACTION')
-# vnpn_0p54x16_3p3
-ignore_parameter('vnpn_0p54x16_3p3', 'AE')
-logger.info('Extracting vnpn_0p54x16_3p3 BJT')
-extract_devices(bjt4('vnpn_0p54x16_3p3'), { 'C' => npn_00p54x16p00_c_3p3.extents,
+# npn_00p54x16p00_03v3 BJT: Gummel-Poon model for 3.3v VNPN with emitter size 0.54um x 16um [vnpn_0p54x16_3p3]
+logger.info('Extracting npn_00p54x16p00_03v3 BJT')
+extract_devices(bjt4('npn_00p54x16p00_03v3'), { 'C' => npn_00p54x16p00_c_3p3.extents,
'B' => npn_00p54x16p00_b_3p3.extents,
'E' => npn_00p54x16p00_e_3p3,
'S' => sub.extents,
@@ -92,96 +90,96 @@
'tB' => npn_00p54x16p00_b_3p3,
'tE' => npn_00p54x16p00_e_3p3,
'tS' => sub })
+ignore_parameter('npn_00p54x16p00_03v3', 'AE')
-# vnpn_0p54x8_3p3
-ignore_parameter('vnpn_0p54x8_3p3', 'AE')
-logger.info('Extracting vnpn_0p54x8_3p3 BJT')
-extract_devices(bjt4('vnpn_0p54x8_3p3'), { 'C' => npn_00p54x08p00_c_3p3.extents,
- 'B' => npn_00p54x08p00_b_3p3.extents,
- 'E' => npn_00p54x08p00_e_3p3,
- 'S' => sub.extents,
- 'tC' => npn_00p54x08p00_c_3p3,
- 'tB' => npn_00p54x08p00_b_3p3,
- 'tE' => npn_00p54x08p00_e_3p3,
- 'tS' => sub })
+# npn_00p54x08p00_03v3: Gummel-Poon model for 3.3v VNPN with emitter size 0.54um x 8um [vnpn_0p54x8_3p3]
+logger.info('Extracting npn_00p54x08p00_03v3 BJT')
+extract_devices(bjt4('npn_00p54x08p00_03v3'), { 'C' => npn_00p54x08p00_c_3p3.extents,
+ 'B' => npn_00p54x08p00_b_3p3.extents,
+ 'E' => npn_00p54x08p00_e_3p3,
+ 'S' => sub.extents,
+ 'tC' => npn_00p54x08p00_c_3p3,
+ 'tB' => npn_00p54x08p00_b_3p3,
+ 'tE' => npn_00p54x08p00_e_3p3,
+ 'tS' => sub })
+ignore_parameter('npn_00p54x08p00_03v3', 'AE')
-# vnpn_0p54x2_3p3
-ignore_parameter('vnpn_0p54x2_3p3', 'AE')
-logger.info('Extracting vnpn_0p54x2_3p3 BJT')
-extract_devices(bjt4('vnpn_0p54x2_3p3'), { 'C' => npn_00p54x02p00_c_3p3.extents,
- 'B' => npn_00p54x02p00_b_3p3.extents,
- 'E' => npn_00p54x02p00_e_3p3,
- 'S' => sub.extents,
- 'tC' => npn_00p54x02p00_c_3p3,
- 'tB' => npn_00p54x02p00_b_3p3,
- 'tE' => npn_00p54x02p00_e_3p3,
- 'tS' => sub })
+# npn_00p54x02p00_03v3 BJT: Gummel-Poon model for 3.3v VNPN with emitter size 0.54um x 2um [vnpn_0p54x2_3p3]
+logger.info('Extracting npn_00p54x02p00_03v3 BJT')
+extract_devices(bjt4('npn_00p54x02p00_03v3'), { 'C' => npn_00p54x02p00_c_3p3.extents,
+ 'B' => npn_00p54x02p00_b_3p3.extents,
+ 'E' => npn_00p54x02p00_e_3p3,
+ 'S' => sub.extents,
+ 'tC' => npn_00p54x02p00_c_3p3,
+ 'tB' => npn_00p54x02p00_b_3p3,
+ 'tE' => npn_00p54x02p00_e_3p3,
+ 'tS' => sub })
+ignore_parameter('npn_00p54x02p00_03v3', 'AE')
-# vnpn_5x5_3p3
-ignore_parameter('vnpn_5x5_3p3', 'AE')
-logger.info('Extracting vnpn_5x5_3p3 BJT')
-extract_devices(bjt4('vnpn_5x5_3p3'), { 'C' => npn_05p00x05p00_c_3p3.extents,
- 'B' => npn_05p00x05p00_b_3p3.extents,
- 'E' => npn_05p00x05p00_e_3p3,
- 'S' => sub.extents,
- 'tC' => npn_05p00x05p00_c_3p3,
- 'tB' => npn_05p00x05p00_b_3p3,
- 'tE' => npn_05p00x05p00_e_3p3,
- 'tS' => sub })
+# npn_05p00x05p00_03v3 BJT: Gummel-Poon model for 3.3v VNPN with emitter size 5um x 5um [vnpn_5x5_3p3]
+logger.info('Extracting npn_05p00x05p00_03v3 BJT')
+extract_devices(bjt4('npn_05p00x05p00_03v3'), { 'C' => npn_05p00x05p00_c_3p3.extents,
+ 'B' => npn_05p00x05p00_b_3p3.extents,
+ 'E' => npn_05p00x05p00_e_3p3,
+ 'S' => sub.extents,
+ 'tC' => npn_05p00x05p00_c_3p3,
+ 'tB' => npn_05p00x05p00_b_3p3,
+ 'tE' => npn_05p00x05p00_e_3p3,
+ 'tS' => sub })
+ignore_parameter('npn_05p00x05p00_03v3', 'AE')
-
# ========================================
# ---- VPNP (Psub as collector) (6V) ----
# ========================================
+
logger.info('Starting VPNP (6V) BJT EXTRACTION')
+# pnp_10p00x10p00_06v0: Gummel-Poon model for VPNP emitter size of 10um x 10um [vpnp_6p0_10x10]
+logger.info('Extracting pnp_10p00x10p00_06v0 BJT')
+extract_devices(bjt3('pnp_10p00x10p00_06v0'), { 'C' => pnp_10p00x10p00_c.extents,
+ 'B' => pnp_10p00x10p00_b.extents,
+ 'E' => pnp_10p00x10p00_e,
+ 'tC' => pnp_10p00x10p00_c,
+ 'tB' => pnp_10p00x10p00_b,
+ 'tE' => pnp_10p00x10p00_e })
+ignore_parameter('pnp_10p00x10p00_06v0', 'AE')
-# vpnp_6p0_10x10
-ignore_parameter('vpnp_6p0_10x10', 'AE')
-logger.info('Extracting vpnp_6p0_10x10 BJT')
-extract_devices(bjt3('vpnp_6p0_10x10'), { 'C' => pnp_10p00x10p00_c.extents,
- 'B' => pnp_10p00x10p00_b.extents,
- 'E' => pnp_10p00x10p00_e,
- 'tC' => pnp_10p00x10p00_c,
- 'tB' => pnp_10p00x10p00_b,
- 'tE' => pnp_10p00x10p00_e })
+# pnp_05p00x05p00_06v0 BJT: Gummel-Poon model for VPNP emitter size of 5um x 5um [vpnp_6p0_5x5]
+logger.info('Extracting pnp_05p00x05p00_06v0 BJT')
+extract_devices(bjt3('pnp_05p00x05p00_06v0'), { 'C' => pnp_05p00x05p00_c.extents,
+ 'B' => pnp_05p00x05p00_b.extents,
+ 'E' => pnp_05p00x05p00_e,
+ 'tC' => pnp_05p00x05p00_c,
+ 'tB' => pnp_05p00x05p00_b,
+ 'tE' => pnp_05p00x05p00_e })
+ignore_parameter('pnp_05p00x05p00_06v0', 'AE')
-# vpnp_6p0_5x5
-ignore_parameter('vpnp_6p0_5x5', 'AE')
-logger.info('Extracting vpnp_6p0_5x5 BJT')
-extract_devices(bjt3('vpnp_6p0_5x5'), { 'C' => pnp_05p00x05p00_c.extents,
- 'B' => pnp_05p00x05p00_b.extents,
- 'E' => pnp_05p00x05p00_e,
- 'tC' => pnp_05p00x05p00_c,
- 'tB' => pnp_05p00x05p00_b,
- 'tE' => pnp_05p00x05p00_e })
+# pnp_00p42x20p00_06v0 BJT: Gummel-Poon model for VPNP emitter size of 0.42um x 20um [vpnp_6p0_0p42x20]
+logger.info('Extracting pnp_00p42x20p00_06v0 BJT')
+extract_devices(bjt3('pnp_00p42x20p00_06v0'), { 'C' => pnp_00p42x20p00_c.extents,
+ 'B' => pnp_00p42x20p00_b.extents,
+ 'E' => pnp_00p42x20p00_e,
+ 'tC' => pnp_00p42x20p00_c,
+ 'tB' => pnp_00p42x20p00_b,
+ 'tE' => pnp_00p42x20p00_e })
+ignore_parameter('pnp_00p42x20p00_06v0', 'AE')
-# vpnp_6p0_0p42x20
-ignore_parameter('vpnp_6p0_0p42x20', 'AE')
-logger.info('Extracting vpnp_6p0_0p42x20 BJT')
-extract_devices(bjt3('vpnp_6p0_0p42x20'), { 'C' => pnp_00p42x20p00_c.extents,
- 'B' => pnp_00p42x20p00_b.extents,
- 'E' => pnp_00p42x20p00_e,
- 'tC' => pnp_00p42x20p00_c,
- 'tB' => pnp_00p42x20p00_b,
- 'tE' => pnp_00p42x20p00_e })
+# pnp_00p42x10p00_06v0 BJT: Gummel-Poon model for VPNP emitter size of 0.42um x 10um [vpnp_6p0_0p42x10]
+logger.info('Extracting pnp_00p42x10p00_06v0 BJT')
+extract_devices(bjt3('pnp_00p42x10p00_06v0'), { 'C' => pnp_00p42x10p00_c.extents,
+ 'B' => pnp_00p42x10p00_b.extents,
+ 'E' => pnp_00p42x10p00_e,
+ 'tC' => pnp_00p42x10p00_c,
+ 'tB' => pnp_00p42x10p00_b,
+ 'tE' => pnp_00p42x10p00_e })
+ignore_parameter('pnp_00p42x10p00_06v0', 'AE')
-# vpnp_6p0_0p42x10
-ignore_parameter('vpnp_6p0_0p42x10', 'AE')
-logger.info('Extracting vpnp_6p0_0p42x10 BJT')
-extract_devices(bjt3('vpnp_6p0_0p42x10'), { 'C' => pnp_00p42x10p00_c.extents,
- 'B' => pnp_00p42x10p00_b.extents,
- 'E' => pnp_00p42x10p00_e,
- 'tC' => pnp_00p42x10p00_c,
- 'tB' => pnp_00p42x10p00_b,
- 'tE' => pnp_00p42x10p00_e })
-
-# vpnp_6p0_0p42x5
-ignore_parameter('vpnp_6p0_0p42x5', 'AE')
-logger.info('Extracting vpnp_6p0_0p42x5 BJT')
-extract_devices(bjt3('vpnp_6p0_0p42x5'), { 'C' => pnp_00p42x05p00_c.extents,
- 'B' => pnp_00p42x05p00_b.extents,
- 'E' => pnp_00p42x05p00_e,
- 'tC' => pnp_00p42x05p00_c,
- 'tB' => pnp_00p42x05p00_b,
- 'tE' => pnp_00p42x05p00_e })
\ No newline at end of file
+# pnp_00p42x05p00_06v0 BJT: Gummel-Poon model for VPNP emitter size of 0.42um x 5um [vpnp_6p0_0p42x5]
+logger.info('Extracting pnp_00p42x05p00_06v0 BJT')
+extract_devices(bjt3('pnp_00p42x05p00_06v0'), { 'C' => pnp_00p42x05p00_c.extents,
+ 'B' => pnp_00p42x05p00_b.extents,
+ 'E' => pnp_00p42x05p00_e,
+ 'tC' => pnp_00p42x05p00_c,
+ 'tB' => pnp_00p42x05p00_b,
+ 'tE' => pnp_00p42x05p00_e })
+ignore_parameter('pnp_00p42x05p00_06v0', 'AE')
diff --git a/ULL/klayout/lvs/rule_decks/custom_classes.lvs b/ULL/klayout/lvs/rule_decks/custom_classes.lvs
index 11fcf5d..0f16ade 100644
--- a/ULL/klayout/lvs/rule_decks/custom_classes.lvs
+++ b/ULL/klayout/lvs/rule_decks/custom_classes.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/devices_connections.lvs b/ULL/klayout/lvs/rule_decks/devices_connections.lvs
index 1cd89c1..d160a40 100644
--- a/ULL/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/ULL/klayout/lvs/rule_decks/devices_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -24,100 +24,33 @@
# ----- GENERAL CONNECTIONS -----
#================================
-logger.info('Starting GF180 LVS connectivity setup (Inter-layer)')
-
-# Inter-layer
-connect(sub, ptap)
-connect(lvpwell_con, ptap)
-connect(lvpwell_con, ptap_dw)
-connect(dnwell, ntap_dw)
-connect(nwell_con, ntap)
-connect(ptap, contact)
-connect(ptap_dw, contact)
-connect(ntap, contact)
-connect(ntap_dw, contact)
-connect(psd, contact)
-connect(psd_dw, contact)
-connect(nsd, contact)
-connect(poly2_con, contact)
-connect(contact, metal1)
-connect(metal1, via1)
-connect(via1, metal2)
-if METAL_LEVEL != '2LM'
- connect(metal2, via2_ncap)
- connect(via2_ncap, metal3)
- connect(via2_cap, fusetop)
- if METAL_LEVEL != '3LM'
- connect(metal3, via3_ncap)
- connect(via3_ncap, metal4)
- connect(via3_cap, fusetop)
- if METAL_LEVEL != '4LM'
- connect(metal4, via4_ncap)
- connect(via4_ncap, metal5)
- connect(via4_cap, fusetop)
- if METAL_LEVEL != '5LM'
- connect(metal5, via5_ncap)
- connect(via5_ncap, metaltop)
- connect(via5_cap, fusetop)
- end
- end
- end
-end
-
-
-logger.info('Starting GF180 LVS connectivity setup (Attaching labels)')
-
-# Attaching labels
-connect(metal1, metal1_label)
-connect(metal2, metal2_label)
-if METAL_LEVEL != '2LM'
- connect(metal3, metal3_label)
- if METAL_LEVEL != '3LM'
- connect(metal4, metal4_label)
- if METAL_LEVEL != '4LM'
- connect(metal5, metal5_label)
- connect(metaltop, metaltop_label) if METAL_LEVEL != '5LM'
- end
- end
-end
-
-logger.info('Starting GF180 LVS connectivity setup (Global)')
-
-# Global
-connect_global(sub, substrate_name)
-
-logger.info('Starting GF180 LVS connectivity setup (Multifinger Devices)')
-
-# Multifinger Devices
-connect_implicit('*')
+# %include general_connections.lvs
#================================
# ----- MOSFET CONNECTIONS ------
#================================
-# %include mos_connection.lvs
+# %include mos_connections.lvs
#================================
# ------ BJT CONNECTIONS --------
#================================
-# %include bjt_connection.lvs
+# %include bjt_connections.lvs
#================================
# ----- DIODE CONNECTIONS -------
#================================
-# %include diode_connection.lvs
#================================
# ---- Varactor CONNECTIONS -----
#================================
-# %include varactor_connection.lvs
-
+# %include varactor_connections.lvs
#==================================
# ------ MIMCAP CONNECTIONS -------
#==================================
-# %include mimcap_connection.lvs
\ No newline at end of file
+# %include mimcap_connections.lvs
\ No newline at end of file
diff --git a/ULL/klayout/lvs/rule_decks/diode_connection.lvs b/ULL/klayout/lvs/rule_decks/diode_connections.lvs
similarity index 97%
rename from ULL/klayout/lvs/rule_decks/diode_connection.lvs
rename to ULL/klayout/lvs/rule_decks/diode_connections.lvs
index a8c8769..6b1aabc 100644
--- a/ULL/klayout/lvs/rule_decks/diode_connection.lvs
+++ b/ULL/klayout/lvs/rule_decks/diode_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/diode_derivations.lvs b/ULL/klayout/lvs/rule_decks/diode_derivations.lvs
index 7203bff..5ed24bc 100644
--- a/ULL/klayout/lvs/rule_decks/diode_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/diode_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -100,5 +100,3 @@
.not(lvs_bjt).not(drc_bjt).not(sab).not(esd).not(resistor).not(fusetop).not(polyfuse)
.not_interacting(cap_mk).not(nat).outside(fhres).not(fusewindow_d)
.not(piscap).not_interacting(mos_cap_mk).not_interacting(mim_l_mk).not(res_mk)
-
-
diff --git a/ULL/klayout/lvs/rule_decks/general_connections.lvs b/ULL/klayout/lvs/rule_decks/general_connections.lvs
new file mode 100644
index 0000000..ee1aa1f
--- /dev/null
+++ b/ULL/klayout/lvs/rule_decks/general_connections.lvs
@@ -0,0 +1,86 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+#================================
+# ----- GENERAL CONNECTIONS -----
+#================================
+
+logger.info('Starting GF180 LVS connectivity setup (Inter-layer)')
+
+# Inter-layer
+connect(sub, ptap)
+connect(lvpwell_con, ptap)
+connect(lvpwell_con, ptap_dw)
+connect(dnwell, ntap_dw)
+connect(nwell_con, ntap)
+connect(ptap, contact)
+connect(ptap_dw, contact)
+connect(ntap, contact)
+connect(ntap_dw, contact)
+connect(psd, contact)
+connect(psd_dw, contact)
+connect(nsd, contact)
+connect(poly2_con, contact)
+connect(contact, metal1)
+connect(metal1, via1)
+connect(via1, metal2)
+if METAL_LEVEL != '2LM'
+ connect(metal2, via2_ncap)
+ connect(via2_ncap, metal3)
+ connect(via2_cap, fusetop)
+ if METAL_LEVEL != '3LM'
+ connect(metal3, via3_ncap)
+ connect(via3_ncap, metal4)
+ connect(via3_cap, fusetop)
+ if METAL_LEVEL != '4LM'
+ connect(metal4, via4_ncap)
+ connect(via4_ncap, metal5)
+ connect(via4_cap, fusetop)
+ if METAL_LEVEL != '5LM'
+ connect(metal5, via5_ncap)
+ connect(via5_ncap, metaltop)
+ connect(via5_cap, fusetop)
+ end
+ end
+ end
+end
+
+
+logger.info('Starting GF180 LVS connectivity setup (Attaching labels)')
+
+# Attaching labels
+connect(metal1, metal1_label)
+connect(metal2, metal2_label)
+if METAL_LEVEL != '2LM'
+ connect(metal3, metal3_label)
+ if METAL_LEVEL != '3LM'
+ connect(metal4, metal4_label)
+ if METAL_LEVEL != '4LM'
+ connect(metal5, metal5_label)
+ connect(metaltop, metaltop_label) if METAL_LEVEL != '5LM'
+ end
+ end
+end
+
+logger.info('Starting GF180 LVS connectivity setup (Global)')
+
+# Global
+connect_global(sub, substrate_name)
+
+logger.info('Starting GF180 LVS connectivity setup (Multifinger Devices)')
+
+# Multifinger Devices
+connect_implicit('*')
diff --git a/ULL/klayout/lvs/rule_decks/general_derivations.lvs b/ULL/klayout/lvs/rule_decks/general_derivations.lvs
index d365520..f670022 100644
--- a/ULL/klayout/lvs/rule_decks/general_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/general_derivations.lvs
@@ -1,6 +1,6 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/layers_definition.lvs b/ULL/klayout/lvs/rule_decks/layers_definition.lvs
index b23ed60..6da62b7 100644
--- a/ULL/klayout/lvs/rule_decks/layers_definition.lvs
+++ b/ULL/klayout/lvs/rule_decks/layers_definition.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -15,529 +15,513 @@
################################################################################################
#================================================
-#------------- LAYERS DEFINITIONS ---------------
+#------------- LAYERS DERIVATIONS ---------------
#================================================
-polygons_count = 0
-logger.info("Read in polygons from layers.")
-comp = polygons(22 , 0 ).merged
-count = comp.count()
-logger.info("comp has %d polygons" % [count])
+polygons_count = 0
+logger.info('Read in polygons from layers.')
+
+def get_polygons(layer, data_type)
+ ps = polygons(layer, data_type)
+ $run_mode == 'deep' ? ps : ps.merged
+end
+
+comp = get_polygons(22, 0)
+count = comp.count
+logger.info("comp has #{count} polygons")
polygons_count += count
-dnwell = polygons(12 , 0 ).merged
-count = dnwell.count()
-logger.info("dnwell has %d polygons" % [count])
-polygons_count += count
+dnwell = get_polygons(12, 0)
+count = dnwell.count
+logger.info("dnwell has #{count} polygons")
+polygons_count += count
-nwell = polygons(21 , 0 ).merged
-count = nwell.count()
-logger.info("nwell has %d polygons" % [count])
-polygons_count += count
+nwell = get_polygons(21, 0)
+count = nwell.count
+logger.info("nwell has #{count} polygons")
+polygons_count += count
-lvpwell = polygons(204, 0 ).merged
-count = lvpwell.count()
-logger.info("lvpwell has %d polygons" % [count])
-polygons_count += count
+lvpwell = get_polygons(204, 0)
+count = lvpwell.count
+logger.info("lvpwell has #{count} polygons")
+polygons_count += count
-dualgate = polygons(55 , 0 ).merged
-count = dualgate.count()
-logger.info("dualgate has %d polygons" % [count])
-polygons_count += count
+dualgate = get_polygons(55, 0)
+count = dualgate.count
+logger.info("dualgate has #{count} polygons")
+polygons_count += count
-dualgate_2 = polygons(144 , 0 ).merged
-count = dualgate_2.count()
-logger.info("dualgate_2 has %d polygons" % [count])
-polygons_count += count
+dualgate_2 = get_polygons(144, 0)
+count = dualgate_2.count
+logger.info("dualgate_2 has #{count} polygons")
+polygons_count += count
-poly2 = polygons(30 , 0 ).merged
-count = poly2.count()
-logger.info("poly2 has %d polygons" % [count])
-polygons_count += count
+poly2 = get_polygons(30, 0)
+count = poly2.count
+logger.info("poly2 has #{count} polygons")
+polygons_count += count
-nplus = polygons(32 , 0 ).merged
-count = nplus.count()
-logger.info("nplus has %d polygons" % [count])
-polygons_count += count
+nplus = get_polygons(32, 0)
+count = nplus.count
+logger.info("nplus has #{count} polygons")
+polygons_count += count
-pplus = polygons(31 , 0 ).merged
-count = pplus.count()
-logger.info("pplus has %d polygons" % [count])
-polygons_count += count
+pplus = get_polygons(31, 0)
+count = pplus.count
+logger.info("pplus has #{count} polygons")
+polygons_count += count
-sab = polygons(49 , 0 ).merged
-count = sab.count()
-logger.info("sab has %d polygons" % [count])
-polygons_count += count
+sab = get_polygons(49, 0)
+count = sab.count
+logger.info("sab has #{count} polygons")
+polygons_count += count
-esd = polygons(24 , 0 ).merged
-count = esd.count()
-logger.info("esd has %d polygons" % [count])
-polygons_count += count
+esd = get_polygons(24, 0)
+count = esd.count
+logger.info("esd has #{count} polygons")
+polygons_count += count
-resistor = polygons(62 , 0 ).merged
-count = resistor.count()
-logger.info("resistor has %d polygons" % [count])
-polygons_count += count
+resistor = get_polygons(62, 0)
+count = resistor.count
+logger.info("resistor has #{count} polygons")
+polygons_count += count
-piscap = polygons(120, 0 ).merged
-count = piscap.count()
-logger.info("piscap has %d polygons" % [count])
-polygons_count += count
+piscap = get_polygons(120, 0)
+count = piscap.count
+logger.info("piscap has #{count} polygons")
+polygons_count += count
-dv2 = polygons(144, 0 ).merged
+dv2 = get_polygons(144, 0)
count = dv2.count()
-logger.info("dv2 has %d polygons" % [count])
+logger.info("dv2 has #{count} polygons")
polygons_count += count
-fhres = polygons(227, 0 ).merged
-count = fhres.count()
-logger.info("fhres has %d polygons" % [count])
-polygons_count += count
+fhres = get_polygons(227, 0)
+count = fhres.count
+logger.info("fhres has #{count} polygons")
+polygons_count += count
-fusetop = polygons(75 , 0 ).merged
-count = fusetop.count()
-logger.info("fusetop has %d polygons" % [count])
-polygons_count += count
+fusetop = get_polygons(75, 0)
+count = fusetop.count
+logger.info("fusetop has #{count} polygons")
+polygons_count += count
-fusewindow_d = polygons(96 , 1 ).merged
-count = fusewindow_d.count()
-logger.info("fusewindow_d has %d polygons" % [count])
-polygons_count += count
+fusewindow_d = get_polygons(96, 1)
+count = fusewindow_d.count
+logger.info("fusewindow_d has #{count} polygons")
+polygons_count += count
-polyfuse = polygons(220, 0 ).merged
-count = polyfuse.count()
-logger.info("polyfuse has %d polygons" % [count])
-polygons_count += count
+polyfuse = get_polygons(220, 0)
+count = polyfuse.count
+logger.info("polyfuse has #{count} polygons")
+polygons_count += count
-nat = polygons(5 , 0 ).merged
-count = nat.count()
-logger.info("nat has %d polygons" % [count])
-polygons_count += count
+nat = get_polygons(5, 0)
+count = nat.count
+logger.info("nat has #{count} polygons")
+polygons_count += count
-comp_dummy = polygons(22 , 4 ).merged
-count = comp_dummy.count()
-logger.info("comp_dummy has %d polygons" % [count])
-polygons_count += count
+comp_dummy = get_polygons(22, 4)
+count = comp_dummy.count
+logger.info("comp_dummy has #{count} polygons")
+polygons_count += count
-poly2_dummy = polygons(30 , 4 ).merged
-count = poly2_dummy.count()
-logger.info("poly2_dummy has %d polygons" % [count])
-polygons_count += count
+poly2_dummy = get_polygons(30, 4)
+count = poly2_dummy.count
+logger.info("poly2_dummy has #{count} polygons")
+polygons_count += count
-res_mk = polygons(110, 5 ).merged
-count = res_mk.count()
-logger.info("res_mk has %d polygons" % [count])
-polygons_count += count
+res_mk = get_polygons(110, 5)
+count = res_mk.count
+logger.info("res_mk has #{count} polygons")
+polygons_count += count
-opc_drc = polygons(124, 5 ).merged
-count = opc_drc.count()
-logger.info("opc_drc has %d polygons" % [count])
-polygons_count += count
+opc_drc = get_polygons(124, 5)
+count = opc_drc.count
+logger.info("opc_drc has #{count} polygons")
+polygons_count += count
-ndmy = polygons(111, 5 ).merged
-count = ndmy.count()
-logger.info("ndmy has %d polygons" % [count])
-polygons_count += count
+ndmy = get_polygons(111, 5)
+count = ndmy.count
+logger.info("ndmy has #{count} polygons")
+polygons_count += count
-pmndmy = polygons(152, 5 ).merged
-count = pmndmy.count()
-logger.info("pmndmy has %d polygons" % [count])
-polygons_count += count
+pmndmy = get_polygons(152, 5)
+count = pmndmy.count
+logger.info("pmndmy has #{count} polygons")
+polygons_count += count
-v5_xtor = polygons(112, 1 ).merged
-count = v5_xtor.count()
-logger.info("v5_xtor has %d polygons" % [count])
-polygons_count += count
+v5_xtor = get_polygons(112, 1)
+count = v5_xtor.count
+logger.info("v5_xtor has #{count} polygons")
+polygons_count += count
-cap_mk = polygons(117, 5 ).merged
-count = cap_mk.count()
-logger.info("cap_mk has %d polygons" % [count])
-polygons_count += count
+cap_mk = get_polygons(117, 5)
+count = cap_mk.count
+logger.info("cap_mk has #{count} polygons")
+polygons_count += count
-mos_cap_mk = polygons(166, 5 ).merged
-count = mos_cap_mk.count()
-logger.info("mos_cap_mk has %d polygons" % [count])
-polygons_count += count
+mos_cap_mk = get_polygons(166, 5)
+count = mos_cap_mk.count
+logger.info("mos_cap_mk has #{count} polygons")
+polygons_count += count
-ind_mk = polygons(151, 5 ).merged
-count = ind_mk.count()
-logger.info("ind_mk has %d polygons" % [count])
-polygons_count += count
+ind_mk = get_polygons(151, 5)
+count = ind_mk.count
+logger.info("ind_mk has #{count} polygons")
+polygons_count += count
-diode_mk = polygons(115, 5 ).merged
-count = diode_mk.count()
-logger.info("diode_mk has %d polygons" % [count])
-polygons_count += count
+diode_mk = get_polygons(115, 5)
+count = diode_mk.count
+logger.info("diode_mk has #{count} polygons")
+polygons_count += count
-drc_bjt = polygons(127, 5 ).merged
-count = drc_bjt.count()
-logger.info("drc_bjt has %d polygons" % [count])
-polygons_count += count
+drc_bjt = get_polygons(127, 5)
+count = drc_bjt.count
+logger.info("drc_bjt has #{count} polygons")
+polygons_count += count
-lvs_bjt = polygons(118, 5 ).merged
-count = lvs_bjt.count()
-logger.info("lvs_bjt has %d polygons" % [count])
-polygons_count += count
+lvs_bjt = get_polygons(118, 5)
+count = lvs_bjt.count
+logger.info("lvs_bjt has #{count} polygons")
+polygons_count += count
-mim_l_mk = polygons(117, 10).merged
-count = mim_l_mk.count()
-logger.info("mim_l_mk has %d polygons" % [count])
-polygons_count += count
+mim_l_mk = get_polygons(117, 10)
+count = mim_l_mk.count
+logger.info("mim_l_mk has #{count} polygons")
+polygons_count += count
-latchup_mk = polygons(137, 5 ).merged
-count = latchup_mk.count()
-logger.info("latchup_mk has %d polygons" % [count])
-polygons_count += count
+latchup_mk = get_polygons(137, 5)
+count = latchup_mk.count
+logger.info("latchup_mk has #{count} polygons")
+polygons_count += count
-guard_ring_mk = polygons(167, 5 ).merged
-count = guard_ring_mk.count()
-logger.info("guard_ring_mk has %d polygons" % [count])
-polygons_count += count
+guard_ring_mk = get_polygons(167, 5)
+count = guard_ring_mk.count
+logger.info("guard_ring_mk has #{count} polygons")
+polygons_count += count
-otp_mk = polygons(173, 5 ).merged
-count = otp_mk.count()
-logger.info("otp_mk has %d polygons" % [count])
-polygons_count += count
+otp_mk = get_polygons(173, 5)
+count = otp_mk.count
+logger.info("otp_mk has #{count} polygons")
+polygons_count += count
-mtpmark = polygons(122, 5 ).merged
-count = mtpmark.count()
-logger.info("mtpmark has %d polygons" % [count])
-polygons_count += count
+mtpmark = get_polygons(122, 5)
+count = mtpmark.count
+logger.info("mtpmark has #{count} polygons")
+polygons_count += count
-sramcore = polygons(108, 5 ).merged
-count = sramcore.count()
-logger.info("sramcore has %d polygons" % [count])
-polygons_count += count
+sramcore = get_polygons(108, 5)
+count = sramcore.count
+logger.info("sramcore has #{count} polygons")
+polygons_count += count
-lvs_rf = polygons(100, 5 ).merged
-count = lvs_rf.count()
-logger.info("lvs_rf has %d polygons" % [count])
-polygons_count += count
+lvs_rf = get_polygons(100, 5)
+count = lvs_rf.count
+logger.info("lvs_rf has #{count} polygons")
+polygons_count += count
-lvs_drain = polygons(100, 7 ).merged
-count = lvs_drain.count()
-logger.info("lvs_drain has %d polygons" % [count])
-polygons_count += count
+lvs_drain = get_polygons(100, 7)
+count = lvs_drain.count
+logger.info("lvs_drain has #{count} polygons")
+polygons_count += count
-hvpolyrs = polygons(123, 5 ).merged
-count = hvpolyrs.count()
-logger.info("hvpolyrs has %d polygons" % [count])
-polygons_count += count
+hvpolyrs = get_polygons(123, 5)
+count = hvpolyrs.count
+logger.info("hvpolyrs has #{count} polygons")
+polygons_count += count
-lvs_io = polygons(119, 5 ).merged
-count = lvs_io.count()
-logger.info("lvs_io has %d polygons" % [count])
-polygons_count += count
+lvs_io = get_polygons(119, 5)
+count = lvs_io.count
+logger.info("lvs_io has #{count} polygons")
+polygons_count += count
-mdiode = polygons(116, 5 ).merged
-count = mdiode.count()
-logger.info("mdiode has %d polygons" % [count])
-polygons_count += count
+mdiode = get_polygons(116, 5)
+count = mdiode.count
+logger.info("mdiode has #{count} polygons")
+polygons_count += count
-contact = polygons(33 , 0 ).merged
-count = contact.count()
-logger.info("contact has %d polygons" % [count])
-polygons_count += count
+contact = get_polygons(33, 0)
+count = contact.count
+logger.info("contact has #{count} polygons")
+polygons_count += count
-metal1_drawn = polygons(34, 0).merged
+metal1_drawn = get_polygons(34, 0)
count = metal1_drawn.count
logger.info("metal1_drawn has #{count} polygons")
polygons_count += count
-metal1_dummy = polygons(34, 4).merged
+metal1_dummy = get_polygons(34, 4)
count = metal1_dummy.count
logger.info("metal1_dummy has #{count} polygons")
polygons_count += count
-metal1 = metal1_drawn + metal1_dummy
+metal1 = metal1_drawn + metal1_dummy
-metal1_label = polygons(34, 10).merged
+metal1_label = labels(34, 10)
count = metal1_label.count
logger.info("metal1_label has #{count} polygons")
polygons_count += count
-metal1_slot = polygons(34, 3).merged
+metal1_slot = get_polygons(34, 3)
count = metal1_slot.count
logger.info("metal1_slot has #{count} polygons")
polygons_count += count
-metal1_blk = polygons(34, 5).merged
+metal1_blk = get_polygons(34, 5)
count = metal1_blk.count
logger.info("metal1_blk has #{count} polygons")
polygons_count += count
-via1 = polygons(35, 0).merged
+via1 = get_polygons(35, 0)
count = via1.count
logger.info("via1 has #{count} polygons")
polygons_count += count
-metal2_drawn = polygons(36, 0).merged
+metal2_drawn = get_polygons(36, 0)
count = metal2_drawn.count
logger.info("metal2_drawn has #{count} polygons")
polygons_count += count
-metal2_dummy = polygons(36, 4).merged
+metal2_dummy = get_polygons(36, 4)
count = metal2_dummy.count
logger.info("metal2_dummy has #{count} polygons")
polygons_count += count
metal2 = metal2_drawn + metal2_dummy
-metal2_label = polygons(36, 10).merged
+metal2_label = labels(36, 10)
count = metal2_label.count
logger.info("metal2_label has #{count} polygons")
polygons_count += count
-metal2_slot = polygons(36, 3).merged
+metal2_slot = get_polygons(36, 3)
count = metal2_slot.count
logger.info("metal2_slot has #{count} polygons")
polygons_count += count
-metal2_blk = polygons(36, 5).merged
+metal2_blk = get_polygons(36, 5)
count = metal2_blk.count
logger.info("metal2_blk has #{count} polygons")
polygons_count += count
-if METAL_LEVEL == '2LM'
-
- top_via = via1
- topmin1_via = contact
- top_metal = metal2
- topmin1_metal = metal1
-
-else
-
- via2 = polygons(38, 0)
+case METAL_LEVEL
+when '3LM', '4LM', '5LM', '6LM'
+ via2 = get_polygons(38, 0)
count = via2.count
logger.info("via2 has #{count} polygons")
polygons_count += count
- metal3_drawn = polygons(42, 0)
+ metal3_drawn = get_polygons(42, 0)
count = metal3_drawn.count
logger.info("metal3_drawn has #{count} polygons")
polygons_count += count
- metal3_dummy = polygons(42, 4)
+ metal3_dummy = get_polygons(42, 4)
count = metal3_dummy.count
logger.info("metal3_dummy has #{count} polygons")
polygons_count += count
metal3 = metal3_drawn + metal3_dummy
- metal3_label = polygons(42, 10)
+ metal3_label = get_polygons(42, 10)
count = metal3_label.count
logger.info("metal3_label has #{count} polygons")
polygons_count += count
- metal3_slot = polygons(42, 3)
+ metal3_slot = get_polygons(42, 3)
count = metal3_slot.count
logger.info("metal3_slot has #{count} polygons")
polygons_count += count
- metal3_blk = polygons(42, 5)
+ metal3_blk = get_polygons(42, 5)
count = metal3_blk.count
logger.info("metal3_blk has #{count} polygons")
polygons_count += count
-
- if METAL_LEVEL == '3LM'
-
- top_via = via2
- topmin1_via = via1
- top_metal = metal3
- topmin1_metal = metal2
- else
-
- via3 = polygons(40, 0)
- count = via3.count
- logger.info("via3 has #{count} polygons")
- polygons_count += count
-
- metal4_drawn = polygons(46, 0)
- count = metal4_drawn.count
- logger.info("metal4_drawn has #{count} polygons")
- polygons_count += count
-
- metal4_dummy = polygons(46, 4)
- count = metal4_dummy.count
- logger.info("metal4_dummy has #{count} polygons")
- polygons_count += count
-
- metal4 = metal4_drawn + metal4_dummy
-
- metal4_label = polygons(46, 10)
- count = metal4_label.count
- logger.info("metal4_label has #{count} polygons")
- polygons_count += count
-
- metal4_slot = polygons(46, 3)
- count = metal4_slot.count
- logger.info("metal4_slot has #{count} polygons")
- polygons_count += count
-
- metal4_blk = polygons(46, 5)
- count = metal4_blk.count
- logger.info("metal4_blk has #{count} polygons")
- polygons_count += count
-
- if METAL_LEVEL == '4LM'
-
- top_via = via3
- topmin1_via = via2
- top_metal = metal4
- topmin1_metal = metal3
- else
-
- via4 = polygons(41, 0)
- count = via4.count
- logger.info("via4 has #{count} polygons")
- polygons_count += count
-
- case METAL_LEVEL
- when '5LM'
- metal5_drawn = polygons(81, 0)
- count = metal5_drawn.count
- logger.info("metal5_drawn has #{count} polygons")
- polygons_count += count
-
- metal5_dummy = polygons(81, 4)
- count = metal5_dummy.count
- logger.info("metal5_dummy has #{count} polygons")
- polygons_count += count
-
- metal5 = metal5_drawn + metal5_dummy
-
- metal5_label = polygons(81, 10)
- count = metal5_label.count
- logger.info("metal5_label has #{count} polygons")
- polygons_count += count
-
- metal5_slot = polygons(81, 3)
- count = metal5_slot.count
- logger.info("metal5_slot has #{count} polygons")
- polygons_count += count
-
- metal5_blk = polygons(81, 5)
- count = metal5_blk.count
- logger.info("metal5_blk has #{count} polygons")
- polygons_count += count
-
- top_via = via4
- topmin1_via = via3
- top_metal = metal5
- topmin1_metal = metal4
- when '6LM'
- metal5_drawn = polygons(81, 0)
- count = metal5_drawn.count
- logger.info("metal5_drawn has #{count} polygons")
- polygons_count += count
-
- metal5_dummy = polygons(81, 4)
- count = metal5_dummy.count
- logger.info("metal5_dummy has #{count} polygons")
- polygons_count += count
-
- metal5 = metal5_drawn + metal5_dummy
-
- metal5_label = polygons(81, 10)
- count = metal5_label.count
- logger.info("metal5_label has #{count} polygons")
- polygons_count += count
-
- metal5_slot = polygons(81, 3)
- count = metal5_slot.count
- logger.info("metal5_slot has #{count} polygons")
- polygons_count += count
-
- metal5_blk = polygons(81, 5)
- count = metal5_blk.count
- logger.info("metal5_blk has #{count} polygons")
- polygons_count += count
-
- via5 = polygons(82, 0)
- count = via5.count
- logger.info("via5 has #{count} polygons")
- polygons_count += count
-
- metaltop_drawn = polygons(53, 0)
- count = metaltop_drawn.count
- logger.info("metaltop_drawn has #{count} polygons")
- polygons_count += count
-
- metaltop_dummy = polygons(53, 4)
- count = metaltop_dummy.count
- logger.info("metaltop_dummy has #{count} polygons")
- polygons_count += count
-
- metaltop = metaltop_drawn + metaltop_dummy
-
- metaltop_label = polygons(53, 10)
- count = metaltop_label.count
- logger.info("metaltop_label has #{count} polygons")
- polygons_count += count
-
- metaltop_slot = polygons(53, 3)
- count = metaltop_slot.count
- logger.info("metaltop_slot has #{count} polygons")
- polygons_count += count
-
- metaltop_blk = polygons(53, 5)
- count = metaltop_blk.count
- logger.info("metaltop_blk has #{count} polygons")
- polygons_count += count
-
- top_via = via5
- topmin1_via = via4
- top_metal = metaltop
- topmin1_metal = metal5
- else
- logger.error("Unknown metal stack #{METAL_LEVEL}")
- raise
- end
- end
- end
end
-probe_mk = polygons(13 , 17 ).merged
-count = probe_mk.count()
-logger.info("probe_mk has %d polygons" % [count])
-polygons_count += count
+case METAL_LEVEL
+when '4LM', '5LM', '6LM'
+ via3 = get_polygons(40, 0)
+ count = via3.count
+ logger.info("via3 has #{count} polygons")
+ polygons_count += count
-pad = polygons(37 , 0 ).merged
-count = pad.count()
-logger.info("pad has %d polygons" % [count])
-polygons_count += count
+ metal4_drawn = get_polygons(46, 0)
+ count = metal4_drawn.count
+ logger.info("metal4_drawn has #{count} polygons")
+ polygons_count += count
-ubmpperi = polygons(183, 0 ).merged
-count = ubmpperi.count()
-logger.info("ubmpperi has %d polygons" % [count])
-polygons_count += count
+ metal4_dummy = get_polygons(46, 4)
+ count = metal4_dummy.count
+ logger.info("metal4_dummy has #{count} polygons")
+ polygons_count += count
-ubmparray = polygons(184, 0 ).merged
-count = ubmparray.count()
-logger.info("ubmparray has %d polygons" % [count])
-polygons_count += count
+ metal4 = metal4_drawn + metal4_dummy
+ metal4_label = get_polygons(46, 10)
+ count = metal4_label.count
+ logger.info("metal4_label has #{count} polygons")
+ polygons_count += count
-ubmparray_label = polygons(33, 39 ).merged
-count = ubmparray_label.count()
-logger.info("ubmparray_label has %d polygons" % [count])
-polygons_count += count
+ metal4_slot = get_polygons(46, 3)
+ count = metal4_slot.count
+ logger.info("metal4_slot has #{count} polygons")
+ polygons_count += count
-ubmeplate = polygons(185, 0 ).merged
-count = ubmeplate.count()
-logger.info("ubmeplate has %d polygons" % [count])
-polygons_count += count
+ metal4_blk = get_polygons(46, 5)
+ count = metal4_blk.count
+ logger.info("metal4_blk has #{count} polygons")
+ polygons_count += count
+end
-pr_bndry = polygons(0 , 0 ).merged
-count = pr_bndry.count()
-logger.info("pr_bndry has %d polygons" % [count])
-polygons_count += count
+case METAL_LEVEL
+when '5LM', '6LM'
+ via4 = get_polygons(41, 0)
+ count = via4.count
+ logger.info("via4 has #{count} polygons")
+ polygons_count += count
-border = polygons(63 , 0 ).merged
-count = border.count()
-logger.info("border has %d polygons" % [count])
-polygons_count += count
+ metal5_drawn = get_polygons(81, 0)
+ count = metal5_drawn.count
+ logger.info("metal5_drawn has #{count} polygons")
+ polygons_count += count
+
+ metal5_dummy = get_polygons(81, 4)
+ count = metal5_dummy.count
+ logger.info("metal5_dummy has #{count} polygons")
+ polygons_count += count
+
+ metal5 = metal5_drawn + metal5_dummy
+
+ metal5_label = get_polygons(81, 10)
+ count = metal5_label.count
+ logger.info("metal5_label has #{count} polygons")
+ polygons_count += count
+
+ metal5_slot = get_polygons(81, 3)
+ count = metal5_slot.count
+ logger.info("metal5_slot has #{count} polygons")
+ polygons_count += count
+
+ metal5_blk = get_polygons(81, 5)
+ count = metal5_blk.count
+ logger.info("metal5_blk has #{count} polygons")
+ polygons_count += count
+
+end
+
+case METAL_LEVEL
+when '6LM'
+ via5 = get_polygons(82, 0)
+ count = via5.count
+ logger.info("via5 has #{count} polygons")
+ polygons_count += count
+
+ metaltop_drawn = get_polygons(53, 0)
+ count = metaltop_drawn.count
+ logger.info("metaltop_drawn has #{count} polygons")
+ polygons_count += count
+
+ metaltop_dummy = get_polygons(53, 4)
+ count = metaltop_dummy.count
+ logger.info("metaltop_dummy has #{count} polygons")
+ polygons_count += count
+
+ metaltop = metaltop_drawn + metaltop_dummy
+
+ metaltop_label = get_polygons(53, 10)
+ count = metaltop_label.count
+ logger.info("metaltop_label has #{count} polygons")
+ polygons_count += count
+
+ metaltop_slot = get_polygons(53, 3)
+ count = metaltop_slot.count
+ logger.info("metaltop_slot has #{count} polygons")
+ polygons_count += count
+
+ metaltop_blk = get_polygons(53, 5)
+ count = metaltop_blk.count
+ logger.info("metaltop_blk has #{count} polygons")
+ polygons_count += count
+
+end
+
+case METAL_LEVEL
+when '2LM'
+ top_via = via1
+ topmin1_via = contact
+ top_metal = metal2
+ topmin1_metal = metal1
+ top_metal_label = metal2_label
+when '3LM'
+ top_via = via2
+ topmin1_via = via1
+ top_metal = metal3
+ topmin1_metal = metal2
+ top_metal_label = metal3_label
+when '4LM'
+ top_via = via3
+ topmin1_via = via2
+ top_metal = metal4
+ topmin1_metal = metal3
+ top_metal_label = metal4_label
+when '5LM'
+ top_via = via4
+ topmin1_via = via3
+ top_metal = metal5
+ topmin1_metal = metal4
+ top_metal_label = metal5_label
+when '6LM'
+ top_via = via5
+ topmin1_via = via4
+ top_metal = metaltop
+ topmin1_metal = metal5
+ top_metal_label = metaltop_label
+else
+ logger.error("Unknown metal stack #{METAL_LEVEL}")
+ raise
+end
+
+probe_mk = get_polygons(13, 17)
+count = probe_mk.count
+logger.info("probe_mk has #{count} polygons")
+polygons_count += count
+
+pad = get_polygons(37, 0)
+count = pad.count
+logger.info("pad has #{count} polygons")
+polygons_count += count
+
+ubmpperi = get_polygons(183, 0)
+count = ubmpperi.count
+logger.info("ubmpperi has #{count} polygons")
+polygons_count += count
+
+ubmparray = get_polygons(184, 0)
+count = ubmparray.count
+logger.info("ubmparray has #{count} polygons")
+polygons_count += count
+
+ubmparray_label = labels(33, 39)
+count = ubmparray_label.count
+logger.info("ubmparray_label has #{count} polygons")
+polygons_count += count
+
+ubmeplate = get_polygons(185, 0)
+count = ubmeplate.count
+logger.info("ubmeplate has #{count} polygons")
+polygons_count += count
+
+pr_bndry = get_polygons(0, 0)
+count = pr_bndry.count
+logger.info("pr_bndry has #{count} polygons")
+polygons_count += count
+
+border = get_polygons(63, 0)
+count = border.count
+logger.info("border has #{count} polygons")
+polygons_count += count
logger.info("Total no. of polygons in the design is #{polygons_count}")
diff --git a/ULL/klayout/lvs/rule_decks/mimcap_connection.lvs b/ULL/klayout/lvs/rule_decks/mimcap_connections.lvs
similarity index 95%
rename from ULL/klayout/lvs/rule_decks/mimcap_connection.lvs
rename to ULL/klayout/lvs/rule_decks/mimcap_connections.lvs
index 886bdc9..31f0bc0 100644
--- a/ULL/klayout/lvs/rule_decks/mimcap_connection.lvs
+++ b/ULL/klayout/lvs/rule_decks/mimcap_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/mimcap_derivations.lvs b/ULL/klayout/lvs/rule_decks/mimcap_derivations.lvs
index a5e7570..b276fd3 100644
--- a/ULL/klayout/lvs/rule_decks/mimcap_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/mimcap_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/mimcap_extraction.lvs b/ULL/klayout/lvs/rule_decks/mimcap_extraction.lvs
index 54906ab..5718a4a 100644
--- a/ULL/klayout/lvs/rule_decks/mimcap_extraction.lvs
+++ b/ULL/klayout/lvs/rule_decks/mimcap_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/mos_connection.lvs b/ULL/klayout/lvs/rule_decks/mos_connections.lvs
similarity index 94%
rename from ULL/klayout/lvs/rule_decks/mos_connection.lvs
rename to ULL/klayout/lvs/rule_decks/mos_connections.lvs
index 862cda2..c9ae6e4 100644
--- a/ULL/klayout/lvs/rule_decks/mos_connection.lvs
+++ b/ULL/klayout/lvs/rule_decks/mos_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/mos_derivations.lvs b/ULL/klayout/lvs/rule_decks/mos_derivations.lvs
index e2467ca..d8e5577 100644
--- a/ULL/klayout/lvs/rule_decks/mos_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/mos_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/mos_extraction.lvs b/ULL/klayout/lvs/rule_decks/mos_extraction.lvs
index 4a2a320..6f2310c 100644
--- a/ULL/klayout/lvs/rule_decks/mos_extraction.lvs
+++ b/ULL/klayout/lvs/rule_decks/mos_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs b/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs
index 8f59869..00433fb 100644
--- a/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/moscap_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs b/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs
index 99c0318..5b0af64 100644
--- a/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs
+++ b/ULL/klayout/lvs/rule_decks/moscap_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs b/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
index 1ace25a..5ca4166 100644
--- a/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/piscap_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs b/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
index d24e852..3fab5fa 100644
--- a/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
+++ b/ULL/klayout/lvs/rule_decks/piscap_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/res_connection.lvs b/ULL/klayout/lvs/rule_decks/res_connections.lvs
similarity index 95%
rename from ULL/klayout/lvs/rule_decks/res_connection.lvs
rename to ULL/klayout/lvs/rule_decks/res_connections.lvs
index 8f716d5..b408d49 100644
--- a/ULL/klayout/lvs/rule_decks/res_connection.lvs
+++ b/ULL/klayout/lvs/rule_decks/res_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/res_derivations.lvs b/ULL/klayout/lvs/rule_decks/res_derivations.lvs
index d4a71f7..425ea0a 100644
--- a/ULL/klayout/lvs/rule_decks/res_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/res_derivations.lvs
@@ -1,6 +1,6 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/res_extraction.lvs b/ULL/klayout/lvs/rule_decks/res_extraction.lvs
index 0dfe9f9..1f723ae 100644
--- a/ULL/klayout/lvs/rule_decks/res_extraction.lvs
+++ b/ULL/klayout/lvs/rule_decks/res_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/varactor_connection.lvs b/ULL/klayout/lvs/rule_decks/varactor_connections.lvs
similarity index 95%
rename from ULL/klayout/lvs/rule_decks/varactor_connection.lvs
rename to ULL/klayout/lvs/rule_decks/varactor_connections.lvs
index 68f3f08..c001505 100644
--- a/ULL/klayout/lvs/rule_decks/varactor_connection.lvs
+++ b/ULL/klayout/lvs/rule_decks/varactor_connections.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs b/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
index b2ff75a..b67122c 100644
--- a/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
+++ b/ULL/klayout/lvs/rule_decks/varactor_derivations.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs b/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
index 1ef4ffe..f9e4e3a 100644
--- a/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
+++ b/ULL/klayout/lvs/rule_decks/varactor_extraction.lvs
@@ -1,5 +1,5 @@
################################################################################################
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/run_lvs.py b/ULL/klayout/lvs/run_lvs.py
index 968c716..f75deeb 100644
--- a/ULL/klayout/lvs/run_lvs.py
+++ b/ULL/klayout/lvs/run_lvs.py
@@ -1,195 +1,426 @@
-# Copyright 2022 GlobalFoundries PDK Authors
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
-# http://www.apache.org/licenses/LICENSE-2.0
+# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
+################################################################################################
"""Run GlobalFoundries 180nm ULL LVS.
Usage:
run_lvs.py (--help| -h)
- run_lvs.py (--design=<layout_path>) (--net=<netlist_path>) (--gf180ull=<combined_options>) [--thr=<thr>] [--run_mode=<run_mode>] [--lvs_sub=<sub_name>] [--no_net_names] [--set_spice_comments] [--set_scale] [--set_verbose] [--set_schematic_simplify] [--set_net_only] [--set_top_lvl_pins] [--set_combine] [--set_purge] [--set_purge_nets]
+ run_lvs.py (--layout=<layout_path>) (--netlist=<netlist_path>) (--variant=<combined_options>) [--thr=<thr>] [--run_dir=<run_dir_path>] [--topcell=<topcell_name>] [--run_mode=<run_mode>] [--verbose] [--lvs_sub=<sub_name>] [--no_net_names] [--spice_comments] [--scale] [--schematic_simplify] [--net_only] [--top_lvl_pins] [--combine] [--purge] [--purge_nets]
Options:
--help -h Print this help message.
- --design=<layout_path> The input GDS file path.
- --net=<netlist_path> The input netlist file path.
- --gf180ull=<combined_options> Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C).
- gf180ull=A: Select metal_top=30K mim_option=A metal_level=3LM poly_res=1K, and mim_cap=2
- gf180ull=B: Select metal_top=11K mim_option=B metal_level=4LM poly_res=1K, and mim_cap=2
- gf180ull=C: Select metal_top=9K mim_option=B metal_level=5LM poly_res=1K, and mim_cap=2
- --thr=<thr> Number of cores to be used by LVS checker
+ --layout=<layout_path> The input GDS file path.
+ --netlist=<netlist_path> The input netlist file path.
+ --variant=<combined_options> Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C).
+ variant=A: Select metal_top=30K mim_option=A metal_level=3LM poly_res=1K, and mim_cap=2
+ variant=B: Select metal_top=11K mim_option=B metal_level=4LM poly_res=1K, and mim_cap=2
+ variant=C: Select metal_top=9K mim_option=B metal_level=5LM poly_res=1K, and mim_cap=2
+ --thr=<thr> The number of threads used in run.
+ --run_dir=<run_dir_path> Run directory to save all the results [default: pwd]
+ --topcell=<topcell_name> Topcell name to use.
--run_mode=<run_mode> Select klayout mode Allowed modes (flat , deep, tiling). [default: deep]
- --lvs_sub=<sub_name> Assign the substrate name used in design.
+ --lvs_sub=<sub_name> Substrate name used in your design.
+ --verbose Detailed rule execution log for debugging.
--no_net_names Discard net names in extracted netlist.
- --set_spice_comments Set netlist comments in extracted netlist.
- --set_scale Set scale of 1e6 in extracted netlist.
- --set_verbose Set verbose mode.
- --set_schematic_simplify Set schematic simplification in input netlist.
- --set_net_only Set netlist object creation only in extracted netlist.
- --set_top_lvl_pins Set top level pins only in extracted netlist.
- --set_combine Set netlist combine only in extracted netlist.
- --set_purge Set netlist purge all only in extracted netlist.
- --set_purge_nets Set netlist purge nets only in extracted netlist.
+ --spice_comments Enable netlist comments in extracted netlist.
+ --scale Enable scale of 1e6 in extracted netlist.
+ --schematic_simplify Enable schematic simplification in input netlist.
+ --net_only Enable netlist object creation only in extracted netlist.
+ --top_lvl_pins Enable top level pins only in extracted netlist.
+ --combine Enable netlist combine only in extracted netlist.
+ --purge Enable netlist purge all only in extracted netlist.
+ --purge_nets Enable netlist purge nets only in extracted netlist.
"""
from docopt import docopt
import os
import logging
-
+import klayout.db
+from datetime import datetime
from subprocess import check_call
-def main():
+def check_klayout_version():
+ """
+ check_klayout_version checks klayout version and makes sure it would work with the LVS.
+ """
+ # ======= Checking Klayout version =======
+ klayout_v_ = os.popen("klayout -b -v").read()
+ klayout_v_ = klayout_v_.split("\n")[0]
+ klayout_v_list = []
- # Switches used in run
- switches = ""
+ if klayout_v_ == "":
+ logging.error("Klayout is not found. Please make sure klayout is installed.")
+ exit(1)
+ else:
+ klayout_v_list = [int(v) for v in klayout_v_.split(" ")[-1].split(".")]
- if args["--run_mode"] in ["flat", "deep", "tiling"]:
- switches = switches + f'-rd run_mode={args["--run_mode"]} '
+ if len(klayout_v_list) < 1 or len(klayout_v_list) > 3:
+ logging.error("Was not able to get klayout version properly.")
+ exit(1)
+ elif len(klayout_v_list) >= 2 or len(klayout_v_list) <= 3:
+ if klayout_v_list[1] < 28:
+ logging.error("Prerequisites at a minimum: KLayout 0.28.0")
+ logging.error(
+ "Using this klayout version has not been assesed in this development. Limits are unknown"
+ )
+ exit(1)
+
+ logging.info(f"Your Klayout version is: {klayout_v_}")
+
+
+def check_layout_type(layout_path):
+ """
+ check_layout_type checks if the layout provided is GDS or OAS. Otherwise, kill the process. We only support GDS or OAS now.
+
+ Parameters
+ ----------
+ layout_path : string
+ string that represent the path of the layout.
+
+ Returns
+ -------
+ string
+ string that represent full absolute layout path.
+ """
+
+ if not os.path.isfile(layout_path):
+ logging.error(
+ f"## GDS file path {layout_path} provided doesn't exist or not a file."
+ )
+ exit(1)
+
+ if ".gds" not in layout_path and ".oas" not in layout_path:
+ logging.error(
+ f"## Layout {layout_path} is not in GDSII or OASIS format. Please use gds format."
+ )
+ exit(1)
+
+ return os.path.abspath(layout_path)
+
+
+def get_top_cell_names(gds_path):
+ """
+ get_top_cell_names get the top cell names from the GDS file.
+
+ Parameters
+ ----------
+ gds_path : string
+ Path to the target GDS file.
+
+ Returns
+ -------
+ List of string
+ Names of the top cell in the layout.
+ """
+ layout = klayout.db.Layout()
+ layout.read(gds_path)
+ top_cells = [t.name for t in layout.top_cells()]
+
+ return top_cells
+
+
+def get_run_top_cell_name(arguments, layout_path):
+ """
+ get_run_top_cell_name Get the top cell name to use for running. If it's provided by the user, we use the user input.
+ If not, we get it from the GDS file.
+
+ Parameters
+ ----------
+ arguments : dict
+ Dictionary that holds the user inputs for the script generated by docopt.
+ layout_path : string
+ Path to the target layout.
+
+ Returns
+ -------
+ string
+ Name of the topcell to use in run.
+
+ """
+
+ if arguments["--topcell"]:
+ topcell = arguments["--topcell"]
+ else:
+ layout_topcells = get_top_cell_names(layout_path)
+ if len(layout_topcells) > 1:
+ logging.error(
+ "## Layout has multiple topcells. Please use --topcell to determine which topcell you want to run on."
+ )
+ exit(1)
+ else:
+ topcell = layout_topcells[0]
+
+ return topcell
+
+
+def generate_klayout_switches(arguments, layout_path, netlist_path):
+ """
+ parse_switches Function that parse all the args from input to prepare switches for LVS run.
+
+ Parameters
+ ----------
+ arguments : dict
+ Dictionary that holds the arguments used by user in the run command. This is generated by docopt library.
+ layout_path : string
+ Path to the layout file that we will run LVS on.
+ netlist_path : string
+ Path to the netlist file that we will run LVS on.
+
+ Returns
+ -------
+ dict
+ Dictionary that represent all run switches passed to klayout.
+ """
+ switches = dict()
+
+ # No. of threads
+ thrCount = 2 if arguments["--thr"] is None else int(arguments["--thr"])
+ switches["thr"] = str(int(thrCount))
+
+ if arguments["--run_mode"] in ["flat", "deep", "tiling"]:
+ switches["run_mode"] = arguments["--run_mode"]
else:
logging.error("Allowed klayout modes are (flat , deep , tiling) only")
exit()
- if args["--gf180ull"] == "A":
- switches = (
- switches
- + "-rd metal_top=30K -rd mim_option=A -rd metal_level=3LM -rd poly_res=1K -rd mim_cap=2 "
- )
- elif args["--gf180ull"] == "B":
- switches = (
- switches
- + "-rd metal_top=11K -rd mim_option=B -rd metal_level=4LM -rd poly_res=1K -rd mim_cap=2 "
- )
- elif args["--gf180ull"] == "C":
- switches = (
- switches
- + "-rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd poly_res=1K -rd mim_cap=2 "
- )
+ if arguments["--variant"] == "A":
+ switches["metal_top"] = "30K"
+ switches["mim_option"] = "A"
+ switches["metal_level"] = "3LM"
+ switches["poly_res"] = "1K"
+ switches["mim_cap"] = "2"
+ elif arguments["--variant"] == "B":
+ switches["metal_top"] = "11K"
+ switches["mim_option"] = "B"
+ switches["metal_level"] = "4LM"
+ switches["poly_res"] = "1K"
+ switches["mim_cap"] = "2"
+ elif arguments["--variant"] == "C":
+ switches["metal_top"] = "9K"
+ switches["mim_option"] = "B"
+ switches["metal_level"] = "5LM"
+ switches["poly_res"] = "1K"
+ switches["mim_cap"] = "2"
else:
- print("gf180ull switch allowed values are (A , B, C) only")
- exit()
+ logging.error("variant switch allowed values are (A , B, C) only")
+ exit(1)
- switches = (
- switches + "-rd spice_net_names=false "
- if args["--no_net_names"]
- else switches + "-rd spice_net_names=true "
- )
-
- switches = (
- switches + "-rd spice_comments=true "
- if args["--set_spice_comments"]
- else switches + "-rd spice_comments=false "
- )
-
- switches = (
- switches + "-rd scale=true "
- if args["--set_scale"]
- else switches + "-rd scale=false "
- )
-
- switches = (
- switches + "-rd verbose=true "
- if args["--set_verbose"]
- else switches + "-rd verbose=false "
- )
-
- switches = (
- switches + "-rd schematic_simplify=true "
- if args["--set_schematic_simplify"]
- else switches + "-rd schematic_simplify=false "
- )
-
- switches = (
- switches + "-rd net_only=true "
- if args["--set_net_only"]
- else switches + "-rd net_only=false "
- )
-
- switches = (
- switches + "-rd top_lvl_pins=true "
- if args["--set_top_lvl_pins"]
- else switches + "-rd top_lvl_pins=false "
- )
-
- switches = (
- switches + "-rd combine=true "
- if args["--set_combine"]
- else switches + "-rd combine=false "
- )
-
- switches = (
- switches + "-rd purge=true "
- if args["--set_purge"]
- else switches + "-rd purge=false "
- )
-
- switches = (
- switches + "-rd purge_nets=true "
- if args["--set_purge_nets"]
- else switches + "-rd purge_nets=false "
- )
-
- switches = (
- switches + f'-rd lvs_sub={args["--lvs_sub"]} '
- if args["--lvs_sub"]
- else switches
- )
-
- # Generate databases
- if args["--design"]:
- path = args["--design"]
- if args["--design"]:
- file_name = args["--net"].split(".")
- else:
- print(
- "The script must be given a netlist file or a path to be able to run LVS"
- )
- exit()
-
- check_call(
- f"klayout -b -r {run_lvs_full_path}/gf180ull.lvs -rd input={path} -rd report={file_name[0]}.lyrdb -rd schematic={args['--net']} -rd target_netlist=extracted_netlist_{file_name[0]}.cir -rd thr={workers_count} {switches}",
- shell=True,
- )
-
+ if arguments["--lvs_sub"]:
+ switches["lvs_sub"] = arguments["--lvs_sub"]
else:
- print("The script must be given a layout file or a path to be able to run LVS")
- exit()
+ switches["lvs_sub"] = "gf180ULL_gnd"
+
+ if arguments["--verbose"]:
+ switches["verbose"] = "true"
+ else:
+ switches["verbose"] = "false"
+
+ if arguments["--no_net_names"]:
+ switches["spice_net_names"] = "false"
+ else:
+ switches["spice_net_names"] = "true"
+
+ if arguments["--spice_comments"]:
+ switches["spice_comments"] = "true"
+ else:
+ switches["spice_comments"] = "false"
+
+ if arguments["--scale"]:
+ switches["scale"] = "true"
+ else:
+ switches["scale"] = "false"
+
+ if arguments["--schematic_simplify"]:
+ switches["schematic_simplify"] = "true"
+ else:
+ switches["schematic_simplify"] = "false"
+
+ if arguments["--net_only"]:
+ switches["net_only"] = "true"
+ else:
+ switches["net_only"] = "false"
+
+ if arguments["--top_lvl_pins"]:
+ switches["top_lvl_pins"] = "true"
+ else:
+ switches["top_lvl_pins"] = "false"
+
+ if arguments["--combine"]:
+ switches["combine"] = "true"
+ else:
+ switches["combine"] = "false"
+
+ if arguments["--purge"]:
+ switches["purge"] = "true"
+ else:
+ switches["purge"] = "false"
+
+ if arguments["--purge_nets"]:
+ switches["purge_nets"] = "true"
+ else:
+ switches["purge_nets"] = "false"
+
+ switches["topcell"] = get_run_top_cell_name(arguments, layout_path)
+ switches["input"] = os.path.abspath(layout_path)
+ switches["schematic"] = os.path.abspath(netlist_path)
+
+ return switches
+
+
+def build_switches_string(sws: dict):
+ """
+ build_switches_string Build swtiches string from dictionary.
+
+ Parameters
+ ----------
+ sws : dict
+ Dictionary that holds the Antenna swithces.
+ """
+ return " ".join(f"-rd {k}={v}" for k, v in sws.items())
+
+
+def check_lvs_results(results_db_files: list):
+ """
+ check_lvs_results Checks the results db generated from run and report at the end if the LVS run failed or passed.
+
+ Parameters
+ ----------
+ results_db_files : list
+ A list of strings that represent paths to results databases of all the LVS runs.
+ """
+
+ if len(results_db_files) < 1:
+ logging.error("Klayout did not generate any db results. Please check run logs")
+ exit(1)
+
+
+def run_check(lvs_file: str, path: str, run_dir: str, sws: dict):
+ """
+ run_check run LVS check.
+
+ Parameters
+ ----------
+ lvs_file : str
+ String that has the file full path to run.
+ path : str
+ String that holds the full path of the layout.
+ run_dir : str
+ String that holds the full path of the run location.
+ sws : dict
+ Dictionary that holds all switches that needs to be passed to the antenna checks.
+
+ Returns
+ -------
+ string
+ string that represent the path to the results output database for this run.
+
+ """
+
+ logging.info(f'Running Global Foundries 180nm ULL {lvs_file} checks on design {path} on cell {sws["topcell"]}')
+
+ layout_base_name = os.path.basename(path).split(".")[0]
+ new_sws = sws.copy()
+ report_path = os.path.join(run_dir, f"{layout_base_name}.lvsdb")
+ ext_net_path = os.path.join(run_dir, f"{layout_base_name}.cir")
+ new_sws["report"] = report_path
+ new_sws["target_netlist"] = ext_net_path
+
+ sws_str = build_switches_string(new_sws)
+
+ run_str = f"klayout -b -r {lvs_file} {sws_str}"
+ check_call(run_str, shell=True)
+
+ return report_path
+
+
+def main(lvs_run_dir: str, arguments: dict):
+ """
+ main function to run the LVS.
+
+ Parameters
+ ----------
+ lvs_run_dir : str
+ String with absolute path of the full run dir.
+ arguments : dict
+ Dictionary that holds the arguments used by user in the run command. This is generated by docopt library.
+ """
+
+ ## Check Klayout version
+ check_klayout_version()
+
+ ## Check layout file existance
+ layout_path = arguments["--layout"]
+ if not os.path.exists(arguments["--layout"]):
+ logging.error(
+ f"The input GDS file path {layout_path} doesn't exist, please recheck."
+ )
+ exit(1)
+
+ ## Check layout type
+ layout_path = check_layout_type(layout_path)
+
+ # Check netlist file existance
+ netlist_path = arguments["--netlist"]
+ if not os.path.exists(arguments["--netlist"]):
+ logging.error(
+ f"The input netlist file path {netlist_path} doesn't exist, please recheck."
+ )
+ exit(1)
+
+ lvs_rule_deck = os.path.join(os.path.dirname(os.path.abspath(__file__)), "gf180ULL.lvs")
+
+ ## Get run switches
+ switches = generate_klayout_switches(arguments, layout_path, netlist_path)
+
+ ## Run LVS check
+ res_db_files = run_check(lvs_rule_deck, layout_path, lvs_run_dir, switches)
+
+ ## Check run
+ check_lvs_results(res_db_files)
if __name__ == "__main__":
+ # arguments
+ arguments = docopt(__doc__, version="RUN LVS: 1.0")
+
+ # logs format
+ now_str = datetime.utcnow().strftime("lvs_run_%Y_%m_%d_%H_%M_%S")
+
+ if (
+ arguments["--run_dir"] == "pwd"
+ or arguments["--run_dir"] == ""
+ or arguments["--run_dir"] is None
+ ):
+ lvs_run_dir = os.path.join(os.path.abspath(os.getcwd()), now_str)
+ else:
+ lvs_run_dir = os.path.abspath(arguments["--run_dir"])
+
+ os.makedirs(lvs_run_dir, exist_ok=True)
+
logging.basicConfig(
level=logging.DEBUG,
+ handlers=[
+ logging.FileHandler(os.path.join(lvs_run_dir, "{}.log".format(now_str))),
+ logging.StreamHandler(),
+ ],
format="%(asctime)s | %(levelname)-7s | %(message)s",
datefmt="%d-%b-%Y %H:%M:%S",
)
- # Args
- args = docopt(__doc__, version="LVS Checker: 0.1")
- workers_count = os.cpu_count() * 2 if args["--thr"] is None else int(args["--thr"])
-
- run_lvs_full_path = os.path.dirname(os.path.abspath(__file__))
-
- # ========= Checking Klayout version =========
- klayout_v_ = os.popen("klayout -v").read()
- klayout_v_ = klayout_v_.split("\n")[0]
- klayout_v = int(klayout_v_.split(".")[-1])
-
- if klayout_v < 8:
- logging.warning(
- "Using this klayout version has not been assesed in this development. Limits are unknown"
- )
- logging.info(f"Your version is: {klayout_v_}")
- logging.info("Prerequisites at a minimum: KLayout 0.27.8")
-
# Calling main function
- main()
+ main(lvs_run_dir, arguments)
diff --git a/ULL/klayout/lvs/testing/Makefile b/ULL/klayout/lvs/testing/Makefile
index 23fd0b1..b3c1479 100644
--- a/ULL/klayout/lvs/testing/Makefile
+++ b/ULL/klayout/lvs/testing/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2022 GlobalFoundries PDK Authors
+# Copyright 2023 GlobalFoundries PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -17,7 +17,6 @@
#=========================================================================
SHELL := /bin/bash
-Testing_DIR ?= $(shell pwd)
.DEFAULT_GOAL := all
all: test-LVS
@@ -34,16 +33,3 @@
.ONESHELL:
test-LVS-%:
@ python3 run_regression.py --device_name=$*
-
-#=================================
-# -------- test-LVS-switch -------
-#=================================
-
-.ONESHELL:
-test-LVS-switch:
- @cd $(Testing_DIR)
- @cd ..
- @echo "========== LVS-Switch testing =========="
- @python3 run_lvs.py --design=testing/extraction_checking/sample_nfet_03v3.gds --net=sample_nfet_03v3.cir --gf180ull=A
- @python3 run_lvs.py --design=testing/extraction_checking/sample_nfet_03v3.gds --net=sample_nfet_03v3.cir --gf180ull=B
- @python3 run_lvs.py --design=testing/extraction_checking/sample_nfet_03v3.gds --net=sample_nfet_03v3.cir --gf180ull=C
\ No newline at end of file
diff --git a/ULL/klayout/lvs/testing/extraction_checking/sample_nfet_03v3.cir b/ULL/klayout/lvs/testing/extraction_checking/sample_nfet_03v3.cir
index 8940675..9d11097 100644
--- a/ULL/klayout/lvs/testing/extraction_checking/sample_nfet_03v3.cir
+++ b/ULL/klayout/lvs/testing/extraction_checking/sample_nfet_03v3.cir
@@ -1,4 +1,4 @@
-* Copyright 2022 GlobalFoundries PDK Authors
+* Copyright 2023 GlobalFoundries PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
diff --git a/ULL/klayout/lvs/testing/run_regression.py b/ULL/klayout/lvs/testing/run_regression.py
index b7345b3..71a5540 100644
--- a/ULL/klayout/lvs/testing/run_regression.py
+++ b/ULL/klayout/lvs/testing/run_regression.py
@@ -20,7 +20,7 @@
Options:
--help -h Print this help message.
- --device_name=<device_name> Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, MOSCAP, PISCAP, VARACTOR, EFUSE).
+ --device_name=<device_name> Name of device that we want to run regression for, Allowed values (MOS, BJT, DIODE, RES, MIMCAP, MOSCAP, MOS_SAB, EFUSE).
--mp=<num> The number of threads used in run.
--run_name=<run_name> Select your run name.
"""
@@ -70,9 +70,7 @@
logging.error("Was not able to get klayout version properly.")
exit(1)
elif len(klayout_v_list) >= 2 or len(klayout_v_list) <= 3:
- if klayout_v_list[1] < 28 or (
- klayout_v_list[1] == 28 and klayout_v_list[2] <= 3
- ):
+ if klayout_v_list[1] < 28 or (klayout_v_list[1] == 28 and klayout_v_list[2] <= 3):
logging.error("Prerequisites at a minimum: KLayout 0.28.4")
logging.error(
"Using this klayout version is not supported in this development."
@@ -85,6 +83,7 @@
def parse_existing_devices(rule_deck_path, output_path, target_device_group=None):
"""
This function collects the rule names from the existing drc rule decks.
+
Parameters
----------
rule_deck_path : string or Path object
@@ -93,6 +92,7 @@
Path of the run location to store the output analysis file.
target_device_group : string Optional
Name of the device group to be in testing
+
Returns
-------
pd.DataFrame
@@ -100,14 +100,10 @@
"""
if target_device_group is None:
- lvs_files = glob.glob(
- os.path.join(rule_deck_path, "rule_decks", "*_extraction.lvs")
- )
+ lvs_files = glob.glob(os.path.join(rule_deck_path, "rule_decks", "*_extraction.lvs"))
else:
table_device_file = os.path.join(
- rule_deck_path,
- "rule_decks",
- f"{str(target_device_group).lower()}_extraction.lvs",
+ rule_deck_path, "rule_decks", f"{str(target_device_group).lower()}_extraction.lvs"
)
if not os.path.isfile(table_device_file):
raise FileNotFoundError(
@@ -124,9 +120,9 @@
if "extract_devices" in line:
line_list = line.split("'")
rule_info = dict()
- rule_info["device_group"] = (
- os.path.basename(runset).replace("_extraction.lvs", "").upper()
- )
+ rule_info["device_group"] = os.path.basename(runset).replace(
+ "_extraction.lvs", ""
+ ).upper()
rule_info["device_name"] = line_list[1]
rule_info["in_rule_deck"] = 1
rules_data.append(rule_info)
@@ -140,12 +136,14 @@
def build_tests_dataframe(unit_test_cases_dir, target_device_group):
"""
This function is used for getting all test cases available in a formated dataframe before running.
+
Parameters
----------
unit_test_cases_dir : str
Path string to the location of unit test cases path.
target_device_group : str or None
Name of device group that we want to run regression for. If None, run all found.
+
Returns
-------
pd.DataFrame
@@ -155,37 +153,26 @@
Path(unit_test_cases_dir).rglob("*.{}".format(SUPPORTED_TC_EXT))
)
logging.info(
- "## Total number of gds files test cases found: {}".format(
- len(all_unit_test_cases_layout)
- )
+ "## Total number of gds files test cases found: {}".format(len(all_unit_test_cases_layout))
)
all_unit_test_cases_netlist = sorted(
Path(unit_test_cases_dir).rglob("*.{}".format(SUPPORTED_SPICE_EXT))
)
logging.info(
- "## Total number of spice files test cases found: {}".format(
- len(all_unit_test_cases_netlist)
- )
+ "## Total number of spice files test cases found: {}".format(len(all_unit_test_cases_netlist))
)
if len(all_unit_test_cases_netlist) != len(all_unit_test_cases_layout):
- logging.error("## Each testcase should have Layout and Netlist file")
+ logging.error(
+ "## Each testcase should have Layout and Netlist file"
+ )
exit(1)
# Get test cases df from test cases
- tc_df = pd.DataFrame(
- {
- "test_layout_path": all_unit_test_cases_layout,
- "test_netlist_path": all_unit_test_cases_netlist,
- }
- )
- tc_df["device_name"] = tc_df["test_layout_path"].apply(
- lambda x: x.name.replace(".gds", "")
- )
- tc_df["device_group"] = tc_df["test_layout_path"].apply(
- lambda x: x.parent.parent.name.replace("_devices", "").upper()
- )
+ tc_df = pd.DataFrame({"test_layout_path": all_unit_test_cases_layout , "test_netlist_path": all_unit_test_cases_netlist})
+ tc_df["device_name"] = tc_df["test_layout_path"].apply(lambda x: x.name.replace(".gds", ""))
+ tc_df["device_group"] = tc_df["test_layout_path"].apply(lambda x: x.parent.parent.name.replace("_devices", "").upper())
if target_device_group is not None:
tc_df = tc_df[tc_df["device_group"] == target_device_group]
@@ -228,6 +215,7 @@
):
"""
This function run a single test case using the correct DRC file.
+
Parameters
----------
lvs_dir : string or Path
@@ -240,6 +228,7 @@
Path to the location where is the regression run is done.
device_name : string
Device name that we are running on.
+
Returns
-------
dict
@@ -255,16 +244,12 @@
switches = " ".join(get_switches(sw_file, device_name))
else:
# Get switches
- switches = (
- " -rd lvs_sub=sub!"
- if device_name == "sample_ggnfet_06v0_dss"
- else " -rd lvs_sub=vdd!"
- ) # default switch
+ switches = " -rd lvs_sub=sub!" if device_name == "sample_ggnfet_06v0_dss" else " -rd lvs_sub=vdd!" # default switch
# Creating run folder structure and copy testcases in it
pattern_clean = ".".join(os.path.basename(layout_path).split(".")[:-1])
- output_loc = f"{run_dir}/{device_name}"
- pattern_log = f"{output_loc}/{pattern_clean}_lvs.log"
+ output_loc = os.path.join(run_dir, device_name)
+ pattern_log = os.path.join(output_loc, f"{pattern_clean}_lvs.log")
os.makedirs(output_loc, exist_ok=True)
layout_path_run = os.path.join(run_dir, device_name, f"{device_name}.gds")
netlist_path_run = os.path.join(run_dir, device_name, f"{device_name}.cdl")
@@ -272,7 +257,7 @@
shutil.copyfile(netlist_path, netlist_path_run)
# command to run drc
- call_str = f"klayout -b -r {lvs_dir}/gf180ull.lvs -rd input={layout_path_run} -rd schematic={device_name}.cdl -rd report={device_name}.lvsdb -rd target_netlist={device_name}_extracted.cir {switches} > {pattern_log} 2>&1"
+ call_str = f"klayout -b -r {lvs_dir}/gf180ULL.lvs -rd input={layout_path_run} -rd schematic={device_name}.cdl -rd report={device_name}.lvsdb -rd target_netlist={device_name}_extracted.cir {switches} > {pattern_log} 2>&1"
# Starting klayout run
try:
@@ -292,11 +277,11 @@
line = line.strip()
logging.info(f"{line}")
- # checking device status
- device_status = "Failed"
+ # checking device status
+ device_status = 'Failed'
if "Congratulations! Netlists match" in result:
logging.info(f"{device_name} testcase passed")
- device_status = "Passed"
+ device_status = 'Passed'
else:
logging.error(f"{device_name} testcase failed.")
logging.error(f"Please recheck {layout_path} file.")
@@ -310,6 +295,7 @@
def run_all_test_cases(tc_df, lvs_dir, run_dir, num_workers):
"""
This function run all test cases from the input dataframe.
+
Parameters
----------
tc_df : pd.DataFrame
@@ -320,6 +306,7 @@
Path string to the location of the testing code and output.
num_workers : int
Number of workers to use for running the regression.
+
Returns
-------
pd.DataFrame
@@ -354,15 +341,19 @@
return tc_df
-def aggregate_results(results_df: pd.DataFrame, devices_df: pd.DataFrame):
+def aggregate_results(
+ results_df: pd.DataFrame, devices_df: pd.DataFrame
+):
"""
aggregate_results Aggregate the results for all runs.
+
Parameters
----------
results_df : pd.DataFrame
Dataframe that holds the information about the unit test rules.
devices_df : pd.DataFrame
Dataframe that holds the information about all the devices implemented in the rule deck.
+
Returns
-------
pd.DataFrame
@@ -376,11 +367,9 @@
elif len(devices_df) > 0 and len(results_df) < 1:
df = devices_df
else:
- df = results_df.merge(
- devices_df, how="outer", on=["device_group", "device_name"]
- )
+ df = results_df.merge(devices_df, how="outer", on=["device_group", "device_name"])
- df.loc[(df["device_status"] != "Passed"), "device_status"] = "Failed"
+ df.loc[(df["device_status"] != 'Passed'), "device_status"] = "Failed"
return df
@@ -388,7 +377,9 @@
def run_regression(lvs_dir, output_path, target_device_group, cpu_count):
"""
Running Regression Procedure.
+
This function runs the full regression on all test cases.
+
Parameters
----------
lvs_dir : string
@@ -426,7 +417,7 @@
## Aggregate all dataframes into one
df = aggregate_results(results_df, devices_df)
df.drop_duplicates(inplace=True)
- df.drop("run_id", inplace=True, axis=1)
+ df.drop('run_id', inplace=True, axis=1)
logging.info("## Final analysis table: \n" + str(df))
## Generate error if there are any missing info or fails.
@@ -447,7 +438,9 @@
def main(lvs_dir, output_path, target_device_group):
"""
Main Procedure.
+
This function is the main execution procedure
+
Parameters
----------
lvs_dir : str
@@ -526,23 +519,11 @@
)
## selected device
- allowed_devices = [
- "MOS",
- "BJT",
- "DIODE",
- "RES",
- "MIMCAP",
- "MOSCAP",
- "PISCAP",
- "VARACTOR",
- "EFUSE",
- ]
+ allowed_devices = ["MOS", "BJT", "DIODE", "RES", "MIMCAP", "MOSCAP", "MOS_SAB", "EFUSE"]
target_device_group = args["--device_name"]
if target_device_group and target_device_group not in allowed_devices:
- logging.error(
- "Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, MOSCAP, PISCAP, VARACTOR, EFUSE) only"
- )
+ logging.error("Allowed devices are (MOS, BJT, DIODE, RES, MIMCAP, MOSCAP, MOS_SAB, EFUSE) only")
exit(1)
# Calling main function
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x2.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x02p00.gds
similarity index 98%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x2.gds
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x02p00.gds
index a46a305..9e4dfed 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x2.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x02p00.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x2_3p3.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x02p00_03v3.gds
similarity index 64%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x2_3p3.gds
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x02p00_03v3.gds
index fb7865e..10288bb 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x2_3p3.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x02p00_03v3.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x8.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x08p00.gds
similarity index 98%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x8.gds
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x08p00.gds
index 72453fe..3ccd397 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x8.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x08p00.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x8_3p3.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x08p00_03v3.gds
similarity index 73%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x8_3p3.gds
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x08p00_03v3.gds
index ddf21c2..8f8dd33 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x8_3p3.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x08p00_03v3.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x16.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x16p00.gds
similarity index 98%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x16.gds
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x16p00.gds
index 7791d22..a5be6e2 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x16.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x16p00.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x16_3p3.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x16p00_03v3.gds
similarity index 67%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x16_3p3.gds
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x16p00_03v3.gds
index b125208..73c3446 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_0p54x16_3p3.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_00p54x16p00_03v3.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_05p00x05p00.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_05p00x05p00.gds
new file mode 100644
index 0000000..cabe38c
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_05p00x05p00.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_05p00x05p00_03v3.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_05p00x05p00_03v3.gds
new file mode 100644
index 0000000..2e01328
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/npn_05p00x05p00_03v3.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x5.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_00p42x05p00_06v0.gds
similarity index 96%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x5.gds
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_00p42x05p00_06v0.gds
index 34dae7a..e549646 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x5.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_00p42x05p00_06v0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x10.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_00p42x10p00_06v0.gds
similarity index 95%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x10.gds
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_00p42x10p00_06v0.gds
index 5c9d3fa..bd815bf 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x10.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_00p42x10p00_06v0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_00p42x20p00_06v0.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_00p42x20p00_06v0.gds
new file mode 100644
index 0000000..e2ca6fe
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_00p42x20p00_06v0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_5x5.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_05p00x05p00_06v0.gds
similarity index 75%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_5x5.gds
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_05p00x05p00_06v0.gds
index 5fc9b57..fa20f0b 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_5x5.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_05p00x05p00_06v0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_10x10.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_10p00x10p00_06v0.gds
similarity index 74%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_10x10.gds
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_10p00x10p00_06v0.gds
index 5e36872..dc119c0 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_10x10.gds
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/pnp_10p00x10p00_06v0.gds
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_5x5.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_5x5.gds
deleted file mode 100644
index 940b605..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_5x5.gds
+++ /dev/null
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_5x5_3p3.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_5x5_3p3.gds
deleted file mode 100644
index 195ecaa..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vnpn_5x5_3p3.gds
+++ /dev/null
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x20.gds b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x20.gds
deleted file mode 100644
index c3715d8..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/layout/vpnp_6p0_0p42x20.gds
+++ /dev/null
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2_3p3.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x02p00.cdl
similarity index 82%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2_3p3.cdl
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x02p00.cdl
index 64d4488..1d2b22f 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2_3p3.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x02p00.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vnpn_0p54x2_3p3
+* Top Cell Name: npn_00p54x02p00
* View Name: schematic
* Netlisted on: Nov 24 10:21:29 2021
************************************************************************
@@ -22,12 +22,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vnpn_0p54x2_3p3
+* Cell Name: npn_00p54x02p00
* View Name: schematic
************************************************************************
-.SUBCKT vnpn_0p54x2_3p3 I1_default_B I1_default_C I1_default_E I1_default_S
+.SUBCKT npn_00p54x02p00 I1_default_B I1_default_C I1_default_E I1_default_S
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
-QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_0p54x2_3p3 m=1
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S npn_00p54x02p00 m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2_3p3.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x02p00_03v3.cdl
similarity index 79%
copy from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2_3p3.cdl
copy to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x02p00_03v3.cdl
index 64d4488..887e95e 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2_3p3.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x02p00_03v3.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vnpn_0p54x2_3p3
+* Top Cell Name: npn_00p54x02p00_03v3
* View Name: schematic
* Netlisted on: Nov 24 10:21:29 2021
************************************************************************
@@ -22,12 +22,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vnpn_0p54x2_3p3
+* Cell Name: npn_00p54x02p00_03v3
* View Name: schematic
************************************************************************
-.SUBCKT vnpn_0p54x2_3p3 I1_default_B I1_default_C I1_default_E I1_default_S
+.SUBCKT npn_00p54x02p00_03v3 I1_default_B I1_default_C I1_default_E I1_default_S
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
-QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_0p54x2_3p3 m=1
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S npn_00p54x02p00_03v3 m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x8_3p3.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x08p00.cdl
similarity index 82%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x8_3p3.cdl
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x08p00.cdl
index 08945b2..cb7f4fd 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x8_3p3.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x08p00.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vnpn_0p54x8_3p3
+* Top Cell Name: npn_00p54x08p00
* View Name: schematic
* Netlisted on: Nov 24 10:24:33 2021
************************************************************************
@@ -22,12 +22,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vnpn_0p54x8_3p3
+* Cell Name: npn_00p54x08p00
* View Name: schematic
************************************************************************
-.SUBCKT vnpn_0p54x8_3p3 I1_default_B I1_default_C I1_default_E I1_default_S
+.SUBCKT npn_00p54x08p00 I1_default_B I1_default_C I1_default_E I1_default_S
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
-QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_0p54x8_3p3 m=1
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S npn_00p54x08p00 m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x8.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x08p00_03v3.cdl
similarity index 79%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x8.cdl
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x08p00_03v3.cdl
index ef185ba..aa7e1f8 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x8.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x08p00_03v3.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vnpn_0p54x8
+* Top Cell Name: npn_00p54x08p00_03v3
* View Name: schematic
* Netlisted on: Nov 24 10:24:33 2021
************************************************************************
@@ -22,12 +22,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vnpn_0p54x8
+* Cell Name: npn_00p54x08p00_03v3
* View Name: schematic
************************************************************************
-.SUBCKT vnpn_0p54x8 I1_default_B I1_default_C I1_default_E I1_default_S
+.SUBCKT npn_00p54x08p00_03v3 I1_default_B I1_default_C I1_default_E I1_default_S
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
-QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_0p54x8 m=1
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S npn_00p54x08p00_03v3 m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x16p00.cdl
similarity index 81%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16.cdl
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x16p00.cdl
index 35213d6..13d3fd5 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x16p00.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vnpn_0p54x16
+* Top Cell Name: npn_00p54x16p00
* View Name: schematic
* Netlisted on: Nov 24 10:25:03 2021
************************************************************************
@@ -22,13 +22,13 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vnpn_0p54x16
+* Cell Name: npn_00p54x16p00
* View Name: schematic
************************************************************************
-.SUBCKT vnpn_0p54x16 I1_default_B I1_default_C I1_default_E I1_default_S
+.SUBCKT npn_00p54x16p00 I1_default_B I1_default_C I1_default_E I1_default_S
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
-QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_0p54x16
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S npn_00p54x16p00
+ m=1
.ENDS
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x16p00_03v3.cdl
similarity index 79%
copy from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16.cdl
copy to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x16p00_03v3.cdl
index 35213d6..47807c4 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_00p54x16p00_03v3.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vnpn_0p54x16
+* Top Cell Name: npn_00p54x16p00_03v3
* View Name: schematic
* Netlisted on: Nov 24 10:25:03 2021
************************************************************************
@@ -22,13 +22,12 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vnpn_0p54x16
+* Cell Name: npn_00p54x16p00_03v3
* View Name: schematic
************************************************************************
-.SUBCKT vnpn_0p54x16 I1_default_B I1_default_C I1_default_E I1_default_S
+.SUBCKT npn_00p54x16p00_03v3 I1_default_B I1_default_C I1_default_E I1_default_S
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
-QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_0p54x16
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S npn_00p54x16p00_03v3
+ m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_05p00x05p00.cdl
similarity index 73%
copy from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
copy to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_05p00x05p00.cdl
index 12736c4..4c2a206 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_05p00x05p00.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vpnp_6p0_0p42x5
+* Top Cell Name: npn_05p00x05p00
* View Name: schematic
* Netlisted on: Nov 24 10:34:45 2021
************************************************************************
@@ -22,12 +22,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vpnp_6p0_0p42x5
+* Cell Name: npn_05p00x05p00
* View Name: schematic
************************************************************************
-.SUBCKT vpnp_6p0_0p42x5 I1_default_B I1_default_C I1_default_E
+.SUBCKT npn_05p00x05p00 I1_default_B I1_default_C I1_default_E I1_default_S
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
-QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_0p42x5 m=1
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S npn_05p00x05p00 m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5_3p3.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_05p00x05p00_03v3.cdl
similarity index 79%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5_3p3.cdl
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_05p00x05p00_03v3.cdl
index e101ed5..514f96d 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5_3p3.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/npn_05p00x05p00_03v3.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vnpn_5x5_3p3
+* Top Cell Name: npn_05p00x05p00_03v3
* View Name: schematic
* Netlisted on: Nov 24 10:26:06 2021
************************************************************************
@@ -22,12 +22,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vnpn_5x5_3p3
+* Cell Name: npn_05p00x05p00_03v3
* View Name: schematic
************************************************************************
-.SUBCKT vnpn_5x5_3p3 I1_default_B I1_default_C I1_default_E I1_default_S
+.SUBCKT npn_05p00x05p00_03v3 I1_default_B I1_default_C I1_default_E I1_default_S
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
-QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_5x5_3p3 m=1
+QI1_default I1_default_C I1_default_B I1_default_E I1_default_S npn_05p00x05p00_03v3 m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5_3p3.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_00p42x05p00_06v0.cdl
similarity index 74%
copy from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5_3p3.cdl
copy to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_00p42x05p00_06v0.cdl
index e101ed5..7c58630 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5_3p3.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_00p42x05p00_06v0.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vnpn_5x5_3p3
+* Top Cell Name: pnp_00p42x05p00_06v0
* View Name: schematic
* Netlisted on: Nov 24 10:26:06 2021
************************************************************************
@@ -22,12 +22,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vnpn_5x5_3p3
+* Cell Name: pnp_00p42x05p00_06v0
* View Name: schematic
************************************************************************
-.SUBCKT vnpn_5x5_3p3 I1_default_B I1_default_C I1_default_E I1_default_S
+.SUBCKT pnp_00p42x05p00_06v0 I1_default_B I1_default_C I1_default_E
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
-QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_5x5_3p3 m=1
+QI1_default I1_default_C I1_default_B I1_default_E pnp_00p42x05p00_06v0 m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_00p42x10p00_06v0.cdl
similarity index 73%
copy from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
copy to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_00p42x10p00_06v0.cdl
index 12736c4..1db7fc0 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_00p42x10p00_06v0.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vpnp_6p0_0p42x5
+* Top Cell Name: pnp_00p42x10p00_06v0
* View Name: schematic
* Netlisted on: Nov 24 10:34:45 2021
************************************************************************
@@ -22,12 +22,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vpnp_6p0_0p42x5
+* Cell Name: pnp_00p42x10p00_06v0
* View Name: schematic
************************************************************************
-.SUBCKT vpnp_6p0_0p42x5 I1_default_B I1_default_C I1_default_E
+.SUBCKT pnp_00p42x10p00_06v0 I1_default_B I1_default_C I1_default_E
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
-QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_0p42x5 m=1
+QI1_default I1_default_C I1_default_B I1_default_E pnp_00p42x10p00_06v0 m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_00p42x20p00_06v0.cdl
similarity index 73%
copy from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
copy to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_00p42x20p00_06v0.cdl
index 12736c4..5cb9ba5 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_00p42x20p00_06v0.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vpnp_6p0_0p42x5
+* Top Cell Name: pnp_00p42x20p00_06v0
* View Name: schematic
* Netlisted on: Nov 24 10:34:45 2021
************************************************************************
@@ -22,12 +22,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vpnp_6p0_0p42x5
+* Cell Name: pnp_00p42x20p00_06v0
* View Name: schematic
************************************************************************
-.SUBCKT vpnp_6p0_0p42x5 I1_default_B I1_default_C I1_default_E
+.SUBCKT pnp_00p42x20p00_06v0 I1_default_B I1_default_C I1_default_E
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
-QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_0p42x5 m=1
+QI1_default I1_default_C I1_default_B I1_default_E pnp_00p42x20p00_06v0 m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_05p00x05p00_06v0.cdl
similarity index 73%
copy from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
copy to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_05p00x05p00_06v0.cdl
index 12736c4..6b5018b 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_05p00x05p00_06v0.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vpnp_6p0_0p42x5
+* Top Cell Name: pnp_05p00x05p00_06v0
* View Name: schematic
* Netlisted on: Nov 24 10:34:45 2021
************************************************************************
@@ -22,12 +22,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vpnp_6p0_0p42x5
+* Cell Name: pnp_05p00x05p00_06v0
* View Name: schematic
************************************************************************
-.SUBCKT vpnp_6p0_0p42x5 I1_default_B I1_default_C I1_default_E
+.SUBCKT pnp_05p00x05p00_06v0 I1_default_B I1_default_C I1_default_E
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
-QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_0p42x5 m=1
+QI1_default I1_default_C I1_default_B I1_default_E pnp_05p00x05p00_06v0 m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_10p00x10p00_06v0.cdl
similarity index 73%
rename from ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
rename to ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_10p00x10p00_06v0.cdl
index 12736c4..4abf268 100644
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x5.cdl
+++ b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/pnp_10p00x10p00_06v0.cdl
@@ -2,7 +2,7 @@
* auCdl Netlist:
*
* Library Name: TCG_Library
-* Top Cell Name: vpnp_6p0_0p42x5
+* Top Cell Name: pnp_10p00x10p00_06v0
* View Name: schematic
* Netlisted on: Nov 24 10:34:45 2021
************************************************************************
@@ -22,12 +22,11 @@
************************************************************************
* Library Name: TCG_Library
-* Cell Name: vpnp_6p0_0p42x5
+* Cell Name: pnp_10p00x10p00_06v0
* View Name: schematic
************************************************************************
-.SUBCKT vpnp_6p0_0p42x5 I1_default_B I1_default_C I1_default_E
+.SUBCKT pnp_10p00x10p00_06v0 I1_default_B I1_default_C I1_default_E
*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
-QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_0p42x5 m=1
+QI1_default I1_default_C I1_default_B I1_default_E pnp_10p00x10p00_06v0 m=1
.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16_3p3.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16_3p3.cdl
deleted file mode 100644
index 26629cc..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x16_3p3.cdl
+++ /dev/null
@@ -1,34 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: vnpn_0p54x16_3p3
-* View Name: schematic
-* Netlisted on: Nov 24 10:25:03 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: vnpn_0p54x16_3p3
-* View Name: schematic
-************************************************************************
-
-.SUBCKT vnpn_0p54x16_3p3 I1_default_B I1_default_C I1_default_E I1_default_S
-*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
-QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_0p54x16_3p3
-+ m=1
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2.cdl
deleted file mode 100644
index a2046bf..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_0p54x2.cdl
+++ /dev/null
@@ -1,33 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: vnpn_0p54x2
-* View Name: schematic
-* Netlisted on: Nov 24 10:21:29 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: vnpn_0p54x2
-* View Name: schematic
-************************************************************************
-
-.SUBCKT vnpn_0p54x2 I1_default_B I1_default_C I1_default_E I1_default_S
-*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
-QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_0p54x2 m=1
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5.cdl
deleted file mode 100644
index d22f81b..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vnpn_5x5.cdl
+++ /dev/null
@@ -1,33 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: vnpn_5x5
-* View Name: schematic
-* Netlisted on: Nov 24 10:26:06 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: vnpn_5x5
-* View Name: schematic
-************************************************************************
-
-.SUBCKT vnpn_5x5 I1_default_B I1_default_C I1_default_E I1_default_S
-*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I I1_default_S:I
-QI1_default I1_default_C I1_default_B I1_default_E I1_default_S vnpn_5x5 m=1
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x10.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x10.cdl
deleted file mode 100644
index 2b6a54c..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x10.cdl
+++ /dev/null
@@ -1,33 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: vpnp_6p0_0p42x10
-* View Name: schematic
-* Netlisted on: Nov 24 10:34:45 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: vpnp_6p0_0p42x10
-* View Name: schematic
-************************************************************************
-
-.SUBCKT vpnp_6p0_0p42x10 I1_default_B I1_default_C I1_default_E
-*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
-QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_0p42x10 m=1
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x20.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x20.cdl
deleted file mode 100644
index c50226a..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_0p42x20.cdl
+++ /dev/null
@@ -1,33 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: vpnp_6p0_0p42x20
-* View Name: schematic
-* Netlisted on: Nov 24 10:34:45 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: vpnp_6p0_0p42x20
-* View Name: schematic
-************************************************************************
-
-.SUBCKT vpnp_6p0_0p42x20 I1_default_B I1_default_C I1_default_E
-*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
-QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_0p42x20 m=1
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_10x10.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_10x10.cdl
deleted file mode 100644
index 5eb6971..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_10x10.cdl
+++ /dev/null
@@ -1,33 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: vpnp_6p0_10x10
-* View Name: schematic
-* Netlisted on: Nov 24 10:34:45 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: vpnp_6p0_10x10
-* View Name: schematic
-************************************************************************
-
-.SUBCKT vpnp_6p0_10x10 I1_default_B I1_default_C I1_default_E
-*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
-QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_10x10 m=1
-.ENDS
-
diff --git a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_5x5.cdl b/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_5x5.cdl
deleted file mode 100644
index 22dcf35..0000000
--- a/ULL/klayout/lvs/testing/testcases/unit/bjt_devices/netlist/vpnp_6p0_5x5.cdl
+++ /dev/null
@@ -1,33 +0,0 @@
-************************************************************************
-* auCdl Netlist:
-*
-* Library Name: TCG_Library
-* Top Cell Name: vpnp_6p0_5x5
-* View Name: schematic
-* Netlisted on: Nov 24 10:34:45 2021
-************************************************************************
-
-*.BIPOLAR
-*.RESI = 2000
-*.RESVAL
-*.CAPVAL
-*.DIOPERI
-*.DIOAREA
-*.EQUATION
-*.SCALE METER
-*.MEGA
-.PARAM
-
-
-
-************************************************************************
-* Library Name: TCG_Library
-* Cell Name: vpnp_6p0_5x5
-* View Name: schematic
-************************************************************************
-
-.SUBCKT vpnp_6p0_5x5 I1_default_B I1_default_C I1_default_E
-*.PININFO I1_default_B:I I1_default_C:I I1_default_E:I
-QI1_default I1_default_C I1_default_B I1_default_E vpnp_6p0_5x5 m=1
-.ENDS
-
