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+# LVS Documentation
+
+Explains how to use the runset.
+
+## Folder Structure
+
+```text
+📁 lvs
+ ┣ 📁testing                        Testing environment directory for GF180BCDLite LVS. 
+ ┣ 📁rule_decks                     All LVS rule decks used in GF180BCDLite.
+ ┣ 📜gf_018BCDLite.lvs                  Main LVS rule deck that call all runsets.
+ ┣ 📜README.md                      This file to document the LVS run for GF180BCDLite.
+ ┗ 📜run_lvs.py                     Main python script used for GF180BCDLite LVS.
+ ```
+
+## **Prerequisites**
+You need the following set of tools installed to be able to run GF180BCDLite LVS:
+- Python 3.6+
+- KLayout 0.28.4+
+
+## **Usage**
+
+The `run_lvs.py` script takes your input gds and netlist files to run LVS rule deck of GF180BCDLite technology on it with switches to select subsets of all checks. 
+
+```bash
+    run_lvs.py (--help| -h)
+    run_lvs.py (--layout=<layout_path>) (--netlist=<netlist_path>) (--variant=<combined_options>) [--thr=<thr>] [--run_dir=<run_dir_path>] [--topcell=<topcell_name>] [--run_mode=<run_mode>] [--verbose] [--lvs_sub=<sub_name>] [--no_net_names] [--spice_comments] [--scale] [--schematic_simplify] [--net_only] [--top_lvl_pins] [--combine] [--purge] [--purge_nets]
+```
+
+Example:
+```bash
+    python3 run_lvs.py --layout=testing/testcases/extraction_checking/nfet_01v0.gds --netlist=testing/testcases/extraction_checking/nfet_01v0.spice --variant=C --run_mode=deep --run_dir=lvs_switch_checking
+```
+
+### Options
+
+- `--help -h`                           Print this help message.
+
+- `--layout=<layout_path>`              The input GDS file path.
+
+- `--netlist=<netlist_path>`            The input netlist file path.
+
+- `--variant=<combined_options>`        Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C).
+  - gf180BCDLite=A: Select  metal_top=30K  mim_option=A  metal_level=3LM  poly_res=1K, and mim_cap=2
+  - gf180BCDLite=B: Select  metal_top=11K  mim_option=B  metal_level=4LM  poly_res=1K, and mim_cap=2
+  - gf180BCDLite=C: Select  metal_top=9K   mim_option=B  metal_level=5LM  poly_res=1K, and mim_cap=2
+
+- `--thr=<thr>`                         The number of threads used in run.
+
+- `--run_dir=<run_dir_path>`            Run directory to save all the results [default: pwd]
+
+- `--topcell=<topcell_name>`            Topcell name to use.
+
+- `--run_mode=<run_mode>`               Select klayout mode Allowed modes (flat , deep, tiling). [default: deep]
+
+- `--lvs_sub=<sub_name>`                Substrate name used in your design.
+
+- `--verbose`                           Detailed rule execution log for debugging.
+
+- `--no_net_names`                      Discard net names in extracted netlist.
+
+- `--spice_comments`                    Enable netlist comments in extracted netlist.
+
+- `--scale`                             Enable scale of 1e6 in extracted netlist.
+
+- `--schematic_simplify`                Enable schematic simplification in input netlist.
+
+- `--net_only`                          Enable netlist object creation only in extracted netlist.
+
+- `--top_lvl_pins`                      Enable top level pins only in extracted netlist.
+
+- `--combine`                           Enable netlist combine only in extracted netlist.
+
+- `--purge`                             Enable netlist purge all only in extracted netlist.
+
+- `--purge_nets`                        Enable netlist purge nets only in extracted netlist.
+
+
+## **LVS Outputs**
+
+You could find the run results at your run directory if you previously specified it through `--run_dir=<run_dir_path>`. Default path of run directory is `lvs_run_<date>_<time>` in current directory.
+
+### Folder Structure of run results
+
+```text
+📁 lvs_run_<date>_<time>
+ ┣ 📜 lvs_run_<date>_<time>.log
+ ┗ 📜 <your_design_name>.cir
+ ┗ 📜 <your_design_name>.lvsdb
+ ```
+
+The result is a database file (`<your_design_name>.lvsdb`) contains LVS extractions and comparison results. 
+You could view it on your file using: `klayout <input_gds_file> -m <resut_db_file> `, or you could view it on your gds file via netlist browser option in tools menu using klayout GUI.
+
+You could also find the extracted netlist generated from your design at (`<your_design_name>.cir`) in your run directory.
+
+
+## **Devices Status**
+
+|Device Group|Device Name               |Sim Models             |Google Standard Name|Status                       |Digital|Analog|Adv Analog|RF   |HV   |ESD  |
+|------------|--------------------------|-----------------------|--------------------|-----------------------------|-------|------|----------|-----|-----|-----|
+|MOSFET      |nmos_1p8                  |:heavy_check_mark:     |nfet_01v8           |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |nmos_1p8_dw               |:x:                    |nfet_01v8_dn        |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |nmos_1p8_nat              |:heavy_check_mark:     |nfet_01v8_nvt       |:heavy_check_mark:           |Yes    |Yes   |Maybe     |Maybe|No   |No   |
+|MOSFET      |nmos_4p2_dw               |:heavy_check_mark:     |nfet_04v2_dn        |:x:                          |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |nmos_5p0                  |:x:                    |nfet_05v0           |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |nmos_5p0_dw               |:x:                    |nfet_05v0_dn        |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |nmos_6p0                  |:heavy_check_mark:     |nfet_06v0           |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |nmos_6p0_dw               |:heavy_check_mark:     |nfet_06v0_dn        |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |nmos_6p0_nat              |:heavy_check_mark:     |nfet_06v0_nvt       |:heavy_check_mark:           |Yes    |Yes   |Maybe     |Maybe|No   |No   |
+|MOSFET      |nmos_10p0_asym            |:heavy_check_mark:     |nfet_10v0_asym      |:x:                          |No     |Yes   |Yes       |Yes  |Yes  |No   |
+|MOSFET      |nmos_10p0_asym_iso        |:heavy_check_mark:     |nfet_10v0_asym_iso  |:x:                          |No     |Yes   |Yes       |Yes  |Yes  |No   |
+|MOSFET      |nmos_10p0_sym_iso         |:heavy_check_mark:     |nfet_10v0_sym_iso   |:x:                          |No     |Yes   |Yes       |Yes  |Yes  |No   |
+|MOSFET      |nmos_30p0_asym            |:heavy_check_mark:     |nfet_30v0_asym      |:x:                          |No     |Maybe |Maybe     |Maybe|Yes  |No   |
+|MOSFET      |nmos_30p0_sym             |:heavy_check_mark:     |nfet_30v0_sym       |:x:                          |No     |Maybe |Maybe     |Maybe|Yes  |No   |
+|MOSFET      |nmos_35p0_asym            |:heavy_check_mark:     |nfet_35v0_asym      |:x:                          |No     |Maybe |Maybe     |Maybe|Yes  |No   |
+|MOSFET      |nmos_eldd                 |:heavy_check_mark:     |nfet_eldd           |:x:                          |No     |Maybe |Maybe     |Maybe|Yes  |No   |
+|MOSFET      |nmos_ddd                  |:heavy_check_mark:     |nfet_ddd            |:x:                          |No     |Maybe |Maybe     |Maybe|Yes  |No   |
+|MOSFET      |pmos_1p8                  |:heavy_check_mark:     |pfet_01v8           |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |pmos_1p8_dw               |:x:                    |pfet_01v8_dn        |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |pmos_4p2_dw               |:heavy_check_mark:     |pfet_04v2_dn        |:x:                          |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |pmos_5p0                  |:x:                    |pfet_05v0           |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |pmos_5p0_dw               |:x:                    |pfet_05v0_dn        |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |pmos_6p0                  |:heavy_check_mark:     |pfet_06v0           |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |pmos_6p0_dw               |:heavy_check_mark:     |pfet_06v0_dn        |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |pmos_6p0_nat_dw           |:heavy_check_mark:     |pfet_06v0_nvt_dn    |:heavy_check_mark:           |Yes    |Yes   |Yes       |Maybe|No   |No   |
+|MOSFET      |pmos_10p0_asym            |:heavy_check_mark:     |pfet_10v0_asym      |:x:                          |No     |Yes   |Yes       |Yes  |Yes  |No   |
+|MOSFET      |pmos_30p0_asym            |:heavy_check_mark:     |pfet_30v0_asym      |:x:                          |No     |Maybe |Maybe     |Yes  |Yes  |No   |
+|MOSFET      |pmos_30p0_sym             |:heavy_check_mark:     |pfet_30v0_sym       |:x:                          |No     |Maybe |Maybe     |Yes  |Yes  |No   |
+|MOSFET      |pmos_35p0_asym            |:heavy_check_mark:     |pfet_35v0_asym      |:x:                          |No     |Maybe |Maybe     |Yes  |Yes  |No   |
+|MOSFET      |pmos_35p0_sym             |:heavy_check_mark:     |pfet_35v0_sym       |:x:                          |No     |Maybe |Maybe     |Yes  |Yes  |No   |
+|MOSFET      |pmos_mv_dw_switch         |:x:                    |pfet_06v0_dn_sw     |:x:                          |No     |Yes   |Yes       |Maybe|No   |No   |
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|BJT         |vnpn_5x5                  |:heavy_check_mark:     |npn_05p00x05p00     |:x:                          |No     |Yes   |Yes       |Yes  |Maybe|No   |
+|BJT         |vnpn_0p54x16              |:heavy_check_mark:     |npn_00p54x16p00     |:x:                          |No     |Yes   |Yes       |Yes  |Maybe|No   |
+|BJT         |vnpn_0p54x8               |:heavy_check_mark:     |npn_00p54x08p00     |:x:                          |No     |Yes   |Yes       |Yes  |Maybe|No   |
+|BJT         |vnpn_0p54x4               |:heavy_check_mark:     |npn_00p54x04p00     |:x:                          |No     |Yes   |Yes       |Yes  |Maybe|No   |
+|BJT         |vpnp_6p0_0p42x20          |:heavy_check_mark:     |pnp_00p42x20p00_06v0|:x:                          |No     |Yes   |Yes       |Yes  |Maybe|No   |
+|BJT         |vpnp_6p0_0p42x10          |:heavy_check_mark:     |pnp_00p42x10p00_06v0|:x:                          |No     |Yes   |Yes       |Yes  |Maybe|No   |
+|BJT         |vpnp_6p0_0p42x5           |:heavy_check_mark:     |pnp_00p42x05p00_06v0|:x:                          |No     |Yes   |Yes       |Yes  |Maybe|No   |
+|BJT         |vpnp_6p0_5x5              |:heavy_check_mark:     |pnp_05p00x05p00_06v0|:x:                          |No     |Yes   |Yes       |Yes  |Maybe|No   |
+|BJT         |vpnp_6p0_10x10            |:heavy_check_mark:     |pnp_10p00x10p00_06v0|:x:                          |No     |Yes   |Yes       |Yes  |Maybe|No   |
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|DIODE       |np_1p8                    |:heavy_check_mark:     |diode_nd2ps_01v8    |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |Maybe|
+|DIODE       |np_1p8_dw                 |:x:                    |diode_nd2ps_01v8_dn |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |Maybe|
+|DIODE       |np_6p0                    |:heavy_check_mark:     |diode_nd2ps_06v0    |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |Maybe|
+|DIODE       |np_6p0_dw                 |:heavy_check_mark:     |diode_nd2ps_06v0_dn |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |Maybe|
+|DIODE       |np_30p0                   |:heavy_check_mark:     |diode_nd2ps_30v0    |:heavy_check_mark:           |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|DIODE       |pn_1p8                    |:heavy_check_mark:     |diode_pd2nw_01v8    |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |Maybe|
+|DIODE       |pn_1p8_dw                 |:x:                    |diode_pd2nw_01v8_dn |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |Maybe|
+|DIODE       |pn_6p0                    |:heavy_check_mark:     |diode_pd2nw_06v0    |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |Maybe|
+|DIODE       |pn_6p0_dw                 |:heavy_check_mark:     |diode_pd2nw_06v0_dn |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |Maybe|
+|DIODE       |pn_30p0                   |:heavy_check_mark:     |diode_pd2nw_30v0    |:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|DIODE       |nwp_6p0                   |:heavy_check_mark:     |diode_nw2ps_06v0    |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |Maybe|
+|DIODE       |dnwpw                     |:heavy_check_mark:     |diode_pw2dw         |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |Maybe|
+|DIODE       |dnwpwhv                   |:heavy_check_mark:     |diode_pw2dw_hv      |:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|DIODE       |dnwps                     |:heavy_check_mark:     |diode_dw2ps         |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |Maybe|
+|DIODE       |dpwhvdnw                  |:heavy_check_mark:     |diode_pw2dnw_hv     |:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|DIODE       |poly_diode                |:heavy_check_mark:     |diode_poly          |:x:                          |Maybe  |Yes   |Yes       |Maybe|Maybe|Maybe|
+|DIODE       |zener_diode               |:heavy_check_mark:     |diode_zener         |:x:                          |No     |Yes   |Yes       |No   |Yes  |Maybe|
+|DIODE       |zener_diode_dw            |:x:                    |diode_zener_dw      |:x:                          |No     |Yes   |Yes       |No   |Yes  |Maybe|
+|DIODE       |sc_diode                  |:heavy_check_mark:     |diode_sc            |:heavy_check_mark:           |No     |Yes   |Yes       |Maybe|No   |Maybe|
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|Res         |nplus_u                   |:heavy_check_mark:     |res_nd_3t_uns       |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |nplus_u_dw                |:x:                    |res_nd_3t_uns       |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |nplus_s                   |:heavy_check_mark:     |res_nd_3t_sal       |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |nplus_s_dw                |:x:                    |res_nd_3t_sal       |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |nwell                     |:heavy_check_mark:     |res_nw_3t           |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |nwell_6p0_LD              |:heavy_check_mark:     |res_nw_3t_06v0_hv   |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |ndrain_ext_30p0           |:heavy_check_mark:     |res_nd_3t_30v0_hv   |:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |npolyf_u                  |:heavy_check_mark:     |res_npo_3t_uns      |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |npolyf_u_dw               |:x:                    |res_npo_3t_uns      |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |npolyf_s                  |:heavy_check_mark:     |res_npo_3t_sal      |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |npolyf_s_dw               |:x:                    |res_npo_3t_sal      |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |npolyf_s_30p0             |:x:                    |res_npo_3t_sal_hv   |:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |npolyf_s_30p0_dw          |:x:                    |                    |:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |ppolyf_s_30p0_dw          |:x:                    |res_ppo_3t_sal_30v0_dn|:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |ppolyf_u_fhr_30p0_lv      |:x:                    |res_ppo_3t_uns_fhr_30v0|:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |ppolyf_u_fhr_30p0_lv_dw   |:x:                    |res_ppo_3t_uns_fhr_30v0_dn|:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |ppolyf_u_fhr_30p0_hv      |:x:                    |res_ppo_3t_uns_fhr_30v0|:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |ppolyf_u_fhr_30p0_hv_dw   |:x:                    |res_ppo_3t_uns_fhr_30v0_hv_dn|:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |npolyf_u_30p0             |:x:                    |res_npo_3t_uns_hv   |:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |npolyf_u_30p0_dw          |:x:                    |res_npo_3t_uns_hv   |:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |npolyf_u_1k               |:heavy_check_mark:     |res_npo_3t_uns_1k   |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |pplus_u                   |:heavy_check_mark:     |res_pd_3t_uns       |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |pplus_u_dw                |:x:                    |res_pd_3t_uns_dn    |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |pplus_s                   |:heavy_check_mark:     |res_pd_3t_sal       |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |pplus_s_dw                |:x:                    |res_pd_3t_sal_dn    |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |pwell                     |:heavy_check_mark:     |res_pw_3t           |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |ppolyf_u                  |:heavy_check_mark:     |res_ppo_3t_uns      |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |ppolyf_u_dw               |:x:                    |res_ppo_3t_uns_dn   |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |ppolyf_u_30p0             |:x:                    |res_ppo_3t_uns_30v0 |:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |ppolyf_u_30p0_dw          |:x:                    |res_ppo_3t_uns_30v0_dn|:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |ppolyf_s                  |:heavy_check_mark:     |res_ppo_3t_sal      |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |ppolyf_s_dw               |:x:                    |res_ppo_3t_sal_dn   |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |ppolyf_u_1k               |:heavy_check_mark:     |res_ppo_3t_uns_1k   |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |ppolyf_u_1k_dw            |:x:                    |res_ppo_3t_uns_1k_dn|:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |ppolyf_u_1k_30p0          |:x:                    |res_ppo_3t_uns_1k_30v0|:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |ppolyf_u_1k_30p0_dw       |:x:                    |res_ppo_3t_uns_1k_30v0_dn|:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |ppolyf_u_2k               |:heavy_check_mark:     |res_ppo_3t_uns_2k   |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |ppolyf_u_2k_30p0          |:x:                    |res_ppo_3t_uns_2k_30v0|:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|Res         |ppolyf_u_2k_30p0_dw       |:x:                    |res_ppo_3t_uns_2k_30v0_dn|:x:                          |No     |Yes   |Yes       |Maybe|Yes  |Maybe|
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|Res         |rm1                       |:heavy_check_mark:     |res_m1              |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |rm2                       |:heavy_check_mark:     |res_m2              |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |rm3                       |:heavy_check_mark:     |res_m3              |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |rm4                       |:heavy_check_mark:     |res_m4              |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |rm5                       |:heavy_check_mark:     |res_m5              |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |tm9k                      |:heavy_check_mark:     |res_tm_9k           |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |tm30k                     |:heavy_check_mark:     |res_tm_30k          |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |ms9k                      |:x:                    |res_tm_9k_sh        |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |ms30k                     |:x:                    |res_tm_30k_sh       |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|Maybe|
+|Res         |tanres                    |:heavy_check_mark:     |res_tan             |:x:                          |No     |Yes   |Yes       |Yes  |Maybe|Maybe|
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|MIMCAP      |mim_0p85fF                |:heavy_check_mark:     |cap_mim_0f85        |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|MIMCAP      |mim_1p0fF                 |:heavy_check_mark:     |cap_mim_1f0         |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|MIMCAP      |mim_1p5fF                 |:heavy_check_mark:     |cap_mim_1f5         |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|MIMCAP      |mim_0p85fF_tm             |:heavy_check_mark:     |cap_mim_0f85_tm     |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|MIMCAP      |mim_1p5fF_tm              |:heavy_check_mark:     |cap_mim_1f5_tm      |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|MIMCAP      |mim_1p0fF_tm              |:heavy_check_mark:     |cap_mim_1f0         |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|MOSCAP      |nmoscap_1p8               |:heavy_check_mark:     |cap_nmos_01v8       |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|MOSCAP      |nmoscap_1p8_dw            |:x:                    |cap_nmos_01v8_dn    |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|MOSCAP      |nmoscap_1p8_nwell         |:heavy_check_mark:     |cap_nmos_1p8_nwell  |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|MOSCAP      |nmoscap_1p8_dnwell        |:heavy_check_mark:     |cap_nmos_1p8_dnwell |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|MOSCAP      |nmoscap_6p0               |:heavy_check_mark:     |cap_nmos_06v0       |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|MOSCAP      |nmoscap_6p0_dw            |:heavy_check_mark:     |cap_nmos_06v0_dn    |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|MOSCAP      |nmoscap_6p0_nwell         |:heavy_check_mark:     |cap_nmos_6p0_nwell  |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|MOSCAP      |nmoscap_6p0_dnwell        |:heavy_check_mark:     |cap_nmos_06v0_dnw   |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|MOSCAP      |pmoscap_1p8               |:heavy_check_mark:     |cap_pmos_01v8       |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|MOSCAP      |pmoscap_1p8_dw            |:x:                    |cap_pmos_01v8_dn    |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|MOSCAP      |pmoscap_6p0               |:heavy_check_mark:     |cap_pmos_06v0       |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|MOSCAP      |pmoscap_6p0_dw            |:heavy_check_mark:     |cap_pmos_06v0_dn    |:heavy_check_mark:           |Maybe  |Yes   |Yes       |Maybe|No   |No   |
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|MOMCAP      |apmom                     |:heavy_check_mark:     |cap_apmom           |:x:                          |No     |Yes   |Yes       |Maybe|Maybe|No   |
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|PISCAP      |pis_1p8                   |:heavy_check_mark:     |cap_pis_01v8        |:heavy_check_mark:           |No     |Yes   |Yes       |Maybe|No   |No   |
+|PISCAP      |pis_1p8_dw                |:x:                    |cap_pis_01v8_dn     |:heavy_check_mark:           |No     |Yes   |Yes       |Maybe|No   |No   |
+|PISCAP      |pis_6p0                   |:heavy_check_mark:     |cap_pis_06v0        |:heavy_check_mark:           |No     |Yes   |Yes       |Maybe|No   |No   |
+|PISCAP      |pis_6p0_dw                |:x:                    |cap_pis_06v0_dn     |:heavy_check_mark:           |No     |Yes   |Yes       |Maybe|No   |No   |
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|VARCTOR     |pn_varactor_1p8           |:heavy_check_mark:     |cap_var_pd2nw_01v8  |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|VARCTOR     |pn_varactor_1p8_dw        |:x:                    |cap_var_pd2nw_01v8_dn|:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|VARCTOR     |pn_varactor_6p0           |:heavy_check_mark:     |cap_var_pd2nw_06v0  |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|VARCTOR     |pn_varactor_6p0_dw        |:x:                    |cap_var_pd2nw_06v0_dn|:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|VARCTOR     |mos_varactor_1p8          |:heavy_check_mark:     |cap_var_fet_01v8    |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|VARCTOR     |mos_varactor_1p8_dw       |:heavy_check_mark:     |cap_var_fet_01v8_dn |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|VARCTOR     |mos_varactor_6p0          |:heavy_check_mark:     |cap_var_fet_06v0    |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|VARCTOR     |mos_varactor_6p0_dw       |:heavy_check_mark:     |cap_var_fet_06v0_dn |:heavy_check_mark:           |No     |Yes   |Yes       |Yes  |No   |No   |
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|ESD         |nmos_1p8_sab              |:heavy_check_mark:     |nfet_01v8_dss       |:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |nmos_4p2_dw_sab           |:heavy_check_mark:     |nfet_04v2_dn_dss    |:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |nmos_6p0_sab              |:heavy_check_mark:     |nfet_06v0_dss       |:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |nmos_6p0_dw_sab           |:heavy_check_mark:     |nfet_06v0_dn_dss    |:x:                          |No     |No    |No        |No   |No   |Yes  |
+|            |                          |                       |                    |                             |       |      |          |     |     |     |
+|ESD         |esdnsh_1p8_tw             |:heavy_check_mark:     |esd_nfet_01v8_sal   |:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |ggesdnsh_1p8_tw           |:x:                    |esd_nfet_01v8_sal_gg|:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |esdnsh_6p0_tw             |:heavy_check_mark:     |esd_nfet_06v0_sal   |:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |ggesdnsh_6p0_tw           |:x:                    |esd_nfet_06v0_sal_gg|:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |esdnsh_6p0_tw_ed          |:heavy_check_mark:     |esd_nfet_06v0_sal_ed|:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |ggesdnsh_6p0_tw_ed        |:x:                    |esd_nfet_06v0_sal_ed_gg|:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |esdvnpn_1p8               |:heavy_check_mark:     |esd_npn_01v8        |:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |esdvnpn_6p0               |:heavy_check_mark:     |esd_npn_06v0        |:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |esddnwpw                  |:heavy_check_mark:     |esd_diode_pw2dnw    |:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |esddnwp                   |:heavy_check_mark:     |esd_diode_ps2dnw    |:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |esdvpnp_1p8               |:heavy_check_mark:     |esd_pnp_01v8        |:x:                          |No     |No    |No        |No   |No   |Yes  |
+|ESD         |esdvpnp_6p0               |:heavy_check_mark:     |esd_pnp_06v0        |:x:                          |No     |No    |No        |No   |No   |Yes  |
diff --git a/BCDLite/klayout/lvs/run_lvs.py b/BCDLite/klayout/lvs/run_lvs.py
new file mode 100644
index 0000000..81dc9de
--- /dev/null
+++ b/BCDLite/klayout/lvs/run_lvs.py
@@ -0,0 +1,426 @@
+################################################################################################
+# Copyright 2023 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+"""Run GlobalFoundries 180nm BCDLite LVS.
+
+Usage:
+    run_lvs.py (--help| -h)
+    run_lvs.py (--layout=<layout_path>) (--netlist=<netlist_path>) (--variant=<combined_options>) [--thr=<thr>] [--run_dir=<run_dir_path>] [--topcell=<topcell_name>] [--run_mode=<run_mode>] [--verbose] [--lvs_sub=<sub_name>] [--no_net_names] [--spice_comments] [--scale] [--schematic_simplify] [--net_only] [--top_lvl_pins] [--combine] [--purge] [--purge_nets]
+
+Options:
+    --help -h                           Print this help message.
+    --layout=<layout_path>              The input GDS file path.
+    --netlist=<netlist_path>            The input netlist file path.
+    --variant=<combined_options>        Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C).
+                                        variant=A: Select  metal_top=30K  mim_option=A  metal_level=3LM  poly_res=1K, and mim_cap=2
+                                        variant=B: Select  metal_top=11K  mim_option=B  metal_level=4LM  poly_res=1K, and mim_cap=2
+                                        variant=C: Select  metal_top=9K   mim_option=B  metal_level=5LM  poly_res=1K, and mim_cap=2
+    --thr=<thr>                         The number of threads used in run.
+    --run_dir=<run_dir_path>            Run directory to save all the results [default: pwd]
+    --topcell=<topcell_name>            Topcell name to use.
+    --run_mode=<run_mode>               Select klayout mode Allowed modes (flat , deep, tiling). [default: deep]
+    --lvs_sub=<sub_name>                Substrate name used in your design.
+    --verbose                           Detailed rule execution log for debugging.
+    --no_net_names                      Discard net names in extracted netlist.
+    --spice_comments                    Enable netlist comments in extracted netlist.
+    --scale                             Enable scale of 1e6 in extracted netlist.
+    --schematic_simplify                Enable schematic simplification in input netlist.
+    --net_only                          Enable netlist object creation only in extracted netlist.
+    --top_lvl_pins                      Enable top level pins only in extracted netlist.
+    --combine                           Enable netlist combine only in extracted netlist.
+    --purge                             Enable netlist purge all only in extracted netlist.
+    --purge_nets                        Enable netlist purge nets only in extracted netlist.
+"""
+
+from docopt import docopt
+import os
+import logging
+import klayout.db
+from datetime import datetime
+from subprocess import check_call
+
+
+def check_klayout_version():
+    """
+    check_klayout_version checks klayout version and makes sure it would work with the LVS.
+    """
+    # ======= Checking Klayout version =======
+    klayout_v_ = os.popen("klayout -b -v").read()
+    klayout_v_ = klayout_v_.split("\n")[0]
+    klayout_v_list = []
+
+    if klayout_v_ == "":
+        logging.error("Klayout is not found. Please make sure klayout is installed.")
+        exit(1)
+    else:
+        klayout_v_list = [int(v) for v in klayout_v_.split(" ")[-1].split(".")]
+
+    if len(klayout_v_list) < 1 or len(klayout_v_list) > 3:
+        logging.error("Was not able to get klayout version properly.")
+        exit(1)
+    elif len(klayout_v_list) >= 2 or len(klayout_v_list) <= 3:
+        if klayout_v_list[1] < 28:
+            logging.error("Prerequisites at a minimum: KLayout 0.28.0")
+            logging.error(
+                "Using this klayout version has not been assesed in this development. Limits are unknown"
+            )
+            exit(1)
+
+    logging.info(f"Your Klayout version is: {klayout_v_}")
+
+
+def check_layout_type(layout_path):
+    """
+    check_layout_type checks if the layout provided is GDS or OAS. Otherwise, kill the process. We only support GDS or OAS now.
+
+    Parameters
+    ----------
+    layout_path : string
+        string that represent the path of the layout.
+
+    Returns
+    -------
+    string
+        string that represent full absolute layout path.
+    """
+
+    if not os.path.isfile(layout_path):
+        logging.error(
+            f"## GDS file path {layout_path} provided doesn't exist or not a file."
+        )
+        exit(1)
+
+    if ".gds" not in layout_path and ".oas" not in layout_path:
+        logging.error(
+            f"## Layout {layout_path} is not in GDSII or OASIS format. Please use gds format."
+        )
+        exit(1)
+
+    return os.path.abspath(layout_path)
+
+
+def get_top_cell_names(gds_path):
+    """
+    get_top_cell_names get the top cell names from the GDS file.
+
+    Parameters
+    ----------
+    gds_path : string
+        Path to the target GDS file.
+
+    Returns
+    -------
+    List of string
+        Names of the top cell in the layout.
+    """
+    layout = klayout.db.Layout()
+    layout.read(gds_path)
+    top_cells = [t.name for t in layout.top_cells()]
+
+    return top_cells
+
+
+def get_run_top_cell_name(arguments, layout_path):
+    """
+    get_run_top_cell_name Get the top cell name to use for running. If it's provided by the user, we use the user input.
+    If not, we get it from the GDS file.
+
+    Parameters
+    ----------
+    arguments : dict
+        Dictionary that holds the user inputs for the script generated by docopt.
+    layout_path : string
+        Path to the target layout.
+
+    Returns
+    -------
+    string
+        Name of the topcell to use in run.
+
+    """
+
+    if arguments["--topcell"]:
+        topcell = arguments["--topcell"]
+    else:
+        layout_topcells = get_top_cell_names(layout_path)
+        if len(layout_topcells) > 1:
+            logging.error(
+                "## Layout has multiple topcells. Please use --topcell to determine which topcell you want to run on."
+            )
+            exit(1)
+        else:
+            topcell = layout_topcells[0]
+
+    return topcell
+
+
+def generate_klayout_switches(arguments, layout_path, netlist_path):
+    """
+    parse_switches Function that parse all the args from input to prepare switches for LVS run.
+
+    Parameters
+    ----------
+    arguments : dict
+        Dictionary that holds the arguments used by user in the run command. This is generated by docopt library.
+    layout_path : string
+        Path to the layout file that we will run LVS on.
+    netlist_path : string
+        Path to the netlist file that we will run LVS on.
+
+    Returns
+    -------
+    dict
+        Dictionary that represent all run switches passed to klayout.
+    """
+    switches = dict()
+
+    # No. of threads
+    thrCount = 2 if arguments["--thr"] is None else int(arguments["--thr"])
+    switches["thr"] = str(int(thrCount))
+
+    if arguments["--run_mode"] in ["flat", "deep", "tiling"]:
+        switches["run_mode"] = arguments["--run_mode"]
+    else:
+        logging.error("Allowed klayout modes are (flat , deep , tiling) only")
+        exit()
+
+    if arguments["--variant"] == "A":
+        switches["metal_top"] = "30K"
+        switches["mim_option"] = "A"
+        switches["metal_level"] = "3LM"
+        switches["poly_res"] = "1K"
+        switches["mim_cap"] = "2"
+    elif arguments["--variant"] == "B":
+        switches["metal_top"] = "11K"
+        switches["mim_option"] = "B"
+        switches["metal_level"] = "4LM"
+        switches["poly_res"] = "1K"
+        switches["mim_cap"] = "2"
+    elif arguments["--variant"] == "C":
+        switches["metal_top"] = "9K"
+        switches["mim_option"] = "B"
+        switches["metal_level"] = "5LM"
+        switches["poly_res"] = "1K"
+        switches["mim_cap"] = "2"
+    else:
+        logging.error("variant switch allowed values are (A , B, C) only")
+        exit(1)
+
+    if arguments["--lvs_sub"]:
+        switches["lvs_sub"] = arguments["--lvs_sub"]
+    else:
+        switches["lvs_sub"] = "gf180BCDLite_gnd"
+
+    if arguments["--verbose"]:
+        switches["verbose"] = "true"
+    else:
+        switches["verbose"] = "false"
+
+    if arguments["--no_net_names"]:
+        switches["spice_net_names"] = "false"
+    else:
+        switches["spice_net_names"] = "true"
+
+    if arguments["--spice_comments"]:
+        switches["spice_comments"] = "true"
+    else:
+        switches["spice_comments"] = "false"
+
+    if arguments["--scale"]:
+        switches["scale"] = "true"
+    else:
+        switches["scale"] = "false"
+
+    if arguments["--schematic_simplify"]:
+        switches["schematic_simplify"] = "true"
+    else:
+        switches["schematic_simplify"] = "false"
+
+    if arguments["--net_only"]:
+        switches["net_only"] = "true"
+    else:
+        switches["net_only"] = "false"
+
+    if arguments["--top_lvl_pins"]:
+        switches["top_lvl_pins"] = "true"
+    else:
+        switches["top_lvl_pins"] = "false"
+
+    if arguments["--combine"]:
+        switches["combine"] = "true"
+    else:
+        switches["combine"] = "false"
+
+    if arguments["--purge"]:
+        switches["purge"] = "true"
+    else:
+        switches["purge"] = "false"
+
+    if arguments["--purge_nets"]:
+        switches["purge_nets"] = "true"
+    else:
+        switches["purge_nets"] = "false"
+
+    switches["topcell"] = get_run_top_cell_name(arguments, layout_path)
+    switches["input"] = os.path.abspath(layout_path)
+    switches["schematic"] = os.path.abspath(netlist_path)
+
+    return switches
+
+
+def build_switches_string(sws: dict):
+    """
+    build_switches_string Build swtiches string from dictionary.
+
+    Parameters
+    ----------
+    sws : dict
+        Dictionary that holds the Antenna swithces.
+    """
+    return " ".join(f"-rd {k}={v}" for k, v in sws.items())
+
+
+def check_lvs_results(results_db_files: list):
+    """
+    check_lvs_results Checks the results db generated from run and report at the end if the LVS run failed or passed.
+
+    Parameters
+    ----------
+    results_db_files : list
+        A list of strings that represent paths to results databases of all the LVS runs.
+    """
+
+    if len(results_db_files) < 1:
+        logging.error("Klayout did not generate any db results. Please check run logs")
+        exit(1)
+
+
+def run_check(lvs_file: str, path: str, run_dir: str, sws: dict):
+    """
+    run_check run LVS check.
+
+    Parameters
+    ----------
+    lvs_file : str
+        String that has the file full path to run.
+    path : str
+        String that holds the full path of the layout.
+    run_dir : str
+        String that holds the full path of the run location.
+    sws : dict
+        Dictionary that holds all switches that needs to be passed to the antenna checks.
+
+    Returns
+    -------
+    string
+        string that represent the path to the results output database for this run.
+
+    """
+
+    logging.info(f'Running Global Foundries 180nm BCDLite {lvs_file} checks on design {path} on cell {sws["topcell"]}')
+
+    layout_base_name = os.path.basename(path).split(".")[0]
+    new_sws = sws.copy()
+    report_path = os.path.join(run_dir, f"{layout_base_name}.lvsdb")
+    ext_net_path = os.path.join(run_dir, f"{layout_base_name}.cir")
+    new_sws["report"] = report_path
+    new_sws["target_netlist"] = ext_net_path
+
+    sws_str = build_switches_string(new_sws)
+
+    run_str = f"klayout -b -r {lvs_file} {sws_str}"
+    check_call(run_str, shell=True)
+
+    return report_path
+
+
+def main(lvs_run_dir: str, arguments: dict):
+    """
+    main function to run the LVS.
+
+    Parameters
+    ----------
+    lvs_run_dir : str
+        String with absolute path of the full run dir.
+    arguments : dict
+        Dictionary that holds the arguments used by user in the run command. This is generated by docopt library.
+    """
+
+    ## Check Klayout version
+    check_klayout_version()
+
+    ## Check layout file existance
+    layout_path = arguments["--layout"]
+    if not os.path.exists(arguments["--layout"]):
+        logging.error(
+            f"The input GDS file path {layout_path} doesn't exist, please recheck."
+        )
+        exit(1)
+
+    ## Check layout type
+    layout_path = check_layout_type(layout_path)
+
+    # Check netlist file existance
+    netlist_path = arguments["--netlist"]
+    if not os.path.exists(arguments["--netlist"]):
+        logging.error(
+            f"The input netlist file path {netlist_path} doesn't exist, please recheck."
+        )
+        exit(1)
+
+    lvs_rule_deck = os.path.join(os.path.dirname(os.path.abspath(__file__)), "gf180BCDLite.lvs")
+
+    ## Get run switches
+    switches = generate_klayout_switches(arguments, layout_path, netlist_path)
+
+    ## Run LVS check
+    res_db_files = run_check(lvs_rule_deck, layout_path, lvs_run_dir, switches)
+
+    ## Check run
+    check_lvs_results(res_db_files)
+
+
+if __name__ == "__main__":
+
+    # arguments
+    arguments = docopt(__doc__, version="RUN LVS: 1.0")
+
+    # logs format
+    now_str = datetime.utcnow().strftime("lvs_run_%Y_%m_%d_%H_%M_%S")
+
+    if (
+        arguments["--run_dir"] == "pwd"
+        or arguments["--run_dir"] == ""
+        or arguments["--run_dir"] is None
+    ):
+        lvs_run_dir = os.path.join(os.path.abspath(os.getcwd()), now_str)
+    else:
+        lvs_run_dir = os.path.abspath(arguments["--run_dir"])
+
+    os.makedirs(lvs_run_dir, exist_ok=True)
+
+    logging.basicConfig(
+        level=logging.DEBUG,
+        handlers=[
+            logging.FileHandler(os.path.join(lvs_run_dir, "{}.log".format(now_str))),
+            logging.StreamHandler(),
+        ],
+        format="%(asctime)s | %(levelname)-7s | %(message)s",
+        datefmt="%d-%b-%Y %H:%M:%S",
+    )
+
+    # Calling main function
+    main(lvs_run_dir, arguments)
diff --git a/BCDLite/klayout/lvs/testing/Makefile b/BCDLite/klayout/lvs/testing/Makefile
index 270b923..eda6385 100644
--- a/BCDLite/klayout/lvs/testing/Makefile
+++ b/BCDLite/klayout/lvs/testing/Makefile
@@ -35,4 +35,3 @@
 .ONESHELL:
 test-LVS-%:
 	@ python3 run_regression.py --device_name=$*
-
diff --git a/BCDLite/klayout/lvs/testing/README.md b/BCDLite/klayout/lvs/testing/README.md
index 59f45c8..7b60d92 100644
--- a/BCDLite/klayout/lvs/testing/README.md
+++ b/BCDLite/klayout/lvs/testing/README.md
@@ -6,21 +6,44 @@
 
 ```text
 📁 testing
- ┣ 📜Makefile
- ┣ 📜README.md
- ┣ 📜run_regression.py
- ┗ 📜testcases
+ ┣ 📜README.md                       This file to document the regression.
+ ┣ 📜Makefile                        To make a full test for GF180nm LVS rule deck.
+ ┣ 📜run_regression.py               Main regression script used for LVS testing.
+ ┣ 📁testcases                       All testcases used in LVS regression.
  ```
 
-## Prerequisites
+## **Prerequisites**
+You need the following set of tools installed to be able to run the regression:
+- Python 3.6+
+- KLayout 0.28.4+
 
-At a minimum:
+We have tested this using the following setup:
+- Python 3.9.12
+- KLayout 0.28.5
 
-- Git 2.34.1+
-- Python 3.9.12+
-- KLayout 0.28.6+
+## **Usage**
 
-## Usage
+```bash
+    run_regression.py (--help| -h)
+    run_regression.py [--device_name=<device_name>] [--mp=<num>] [--run_name=<run_name>]
+```
+
+Example:
+
+```bash
+    python3 run_regression.py --device_name=MOS --run_name=mos_regression
+```
+
+### Options
+
+- `--help -h`                           Print this help message.
+
+- `--mp=<num>`                          The number of threads used in run.
+
+- `--run_name=<run_name>`               Select your run name.
+    
+- `--device_name=<device_name>`         Target specific device.
+
 
 To make a full test for GF180nm LVS rule deck, you could use the following command in testing directory:
 
@@ -28,6 +51,26 @@
 make all
 ```
 
-## **Regression Outputs**
+## **LVS Outputs**
 
-- Final results will appear at the end of the run logs.
+You could find the regression run results at your run directory if you previously specified it through `--run_name=<run_name>`. Default path of run directory is `unit_tests_<date>_<time>` in current directory.
+
+### Folder Structure of regression run results
+
+```text
+📁 unit_tests_<date>_<time>
+ ┣ 📜 unit_tests_<date>_<time>.log
+ ┣ 📜 all_test_cases_results.csv
+ ┗ 📜 rule_deck_rules.csv
+ ┗ 📁 <device_name>
+    ┣ 📜 <device_name>_lvs.log
+    ┣ 📜 <device_name>.gds
+    ┣ 📜 <device_name>.cdl
+    ┣ 📜 <device_name>_extracted.cir                     
+    ┣ 📜 <device_name>.lvsdb
+ ```
+
+The result is a database file for each device (`<device_name>.lvsdb`) contains LVS extractions and comparison results.
+You could view it on your file using: `klayout <device_name>.gds -mn <device_name>.lvsdb`, or you could view it on your gds file via marker browser option in tools menu using klayout GUI.
+
+You could also find the extracted netlist generated from your design at (`<device_name>.cir`) in your run directory.
diff --git a/BCDLite/klayout/lvs/testing/testcases/README.md b/BCDLite/klayout/lvs/testing/testcases/README.md
new file mode 100644
index 0000000..8ad221a
--- /dev/null
+++ b/BCDLite/klayout/lvs/testing/testcases/README.md
@@ -0,0 +1,16 @@
+# Globalfoundries 180nm BCDLite LVS Tests
+
+
+## Folder Structure
+
+```text
+📁 testcases
+ ┣ 📜README.md                       This file to document the unit tests.
+ ┣ 📁 unit                           Contains the unit test structures per device.
+    ┣ 📁layout                       Layout gds file for each device.
+    ┣ 📁netlist                      Spice netlist file for each device.
+ ┣ 📁 extraction_checking            Contains a small test case to be used for testing the LVS switches.
+ ┣ 📁 torture                        Contains a few large test cases to test the performance of the rule deck. 
+
+ ```
+ 
\ No newline at end of file