Updating metal connectivity for BCDLite
diff --git a/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs b/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs
index 4d5e90d..ea0f769 100644
--- a/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/devices_connections.lvs
@@ -44,17 +44,21 @@
connect(metal1, via1)
connect(via1, metal2_ncap)
if METAL_LEVEL != '2LM'
- connect(metal2_ncap, via2)
- connect(via2, metal3_ncap)
+ connect(metal2_ncap, via2_ncap)
+ connect(via2_ncap, metal3_ncap)
+ connect(via2_cap, fusetop)
if METAL_LEVEL != '3LM'
- connect(metal3_ncap, via3)
- connect(via3, metal4_ncap)
+ connect(metal3_ncap, via3_ncap)
+ connect(via3_ncap, metal4_ncap)
+ connect(via3_cap, fusetop)
if METAL_LEVEL != '4LM'
- connect(metal4_ncap, via4)
- connect(via4, metal5_ncap)
+ connect(metal4_ncap, via4_ncap)
+ connect(via4_ncap, metal5_ncap)
+ connect(via4_cap, fusetop)
if METAL_LEVEL != '5LM'
- connect(metal5_ncap, via5)
- connect(via5, metaltop)
+ connect(metal5_ncap, via5_ncap)
+ connect(via5_ncap, metaltop)
+ connect(via5_cap, fusetop)
end
end
end
diff --git a/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs b/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs
index d6b0ec6..5626997 100644
--- a/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs
+++ b/BCDLite/klayout/lvs/rule_decks/general_derivations.lvs
@@ -54,13 +54,24 @@
# metal layers derivation
-metal2_ncap = metal2.not(cap_mk).not(mom_m2_mk)
+metal2_ncap = metal2.not(mom_m2_mk)
if METAL_LEVEL != '2LM'
- metal3_ncap = metal3.not(cap_mk).not(mom_m3_mk)
+ metal3_ncap = metal3.not(mom_m3_mk)
if METAL_LEVEL != '3LM'
- metal4_ncap = metal4.not(cap_mk).not(mom_m4_mk)
- metal5_ncap = metal5.not(cap_mk).not(mom_m5_mk) if METAL_LEVEL != '4LM'
+ metal4_ncap = metal4.not(mom_m4_mk)
+ metal5_ncap = metal5.not(mom_m5_mk) if METAL_LEVEL != '4LM'
end
end
+
+
+# Splitting vias into cap-vias(connected to fusetop), ncap-vias(connected to metals)
+via2_ncap = via2.not(fusetop)
+via2_cap = via2.and(fusetop)
+via3_ncap = via3.not(fusetop)
+via3_cap = via3.and(fusetop)
+via4_ncap = via4.not(fusetop)
+via4_cap = via4.and(fusetop)
+via5_ncap = via5.not(fusetop)
+via5_cap = via5.and(fusetop)
\ No newline at end of file
