diff --git a/.github/workflows/linting.yml b/.github/workflows/linting.yml
index 9996112..7dd3c9b 100644
--- a/.github/workflows/linting.yml
+++ b/.github/workflows/linting.yml
@@ -14,8 +14,8 @@
 
 name: code linting
 on:
-  pull_request:
-  push:
+#  push:
+#  pull_request:
   workflow_dispatch:
 
 jobs:
diff --git a/.github/workflows/lvs_regression.yml b/.github/workflows/lvs_regression.yml
index 3b26c9f..2335586 100644
--- a/.github/workflows/lvs_regression.yml
+++ b/.github/workflows/lvs_regression.yml
@@ -21,8 +21,8 @@
   cancel-in-progress: true
 
 on:
-  push:
-  pull_request:
+#  push:
+#  pull_request:
   workflow_dispatch:
 
 jobs:
diff --git a/IC/klayout/lvs/README.md b/IC/klayout/lvs/README.md
new file mode 100644
index 0000000..b3a832c
--- /dev/null
+++ b/IC/klayout/lvs/README.md
@@ -0,0 +1,165 @@
+# LVS Documentation
+
+Explains how to use the runset.
+
+## Folder Structure
+
+```text
+📁 lvs
+ ┣ 📁testing                        Testing environment directory for GF180IC LVS. 
+ ┣ 📁rule_decks                     All LVS rule decks used in GF180IC.
+ ┣ 📜gf_018IC.lvs                  Main LVS rule deck that call all runsets.
+ ┣ 📜README.md                      This file to document the LVS run for GF180IC.
+ ┗ 📜run_lvs.py                     Main python script used for GF180IC LVS.
+ ```
+
+## **Prerequisites**
+You need the following set of tools installed to be able to run GF180IC LVS:
+- Python 3.6+
+- KLayout 0.28.4+
+
+## **Usage**
+
+The `run_lvs.py` script takes your input gds and netlist files to run LVS rule deck of GF180IC technology on it with switches to select subsets of all checks. 
+
+```bash
+    run_lvs.py (--help| -h)
+    run_lvs.py (--layout=<layout_path>) (--netlist=<netlist_path>) (--variant=<combined_options>) [--thr=<thr>] [--run_dir=<run_dir_path>] [--topcell=<topcell_name>] [--run_mode=<run_mode>] [--verbose] [--lvs_sub=<sub_name>] [--no_net_names] [--spice_comments] [--scale] [--schematic_simplify] [--net_only] [--top_lvl_pins] [--combine] [--purge] [--purge_nets]
+```
+
+Example:
+```bash
+    python3 run_lvs.py --layout=testing/testcases/extraction_checking/nfet_01v0.gds --netlist=testing/testcases/extraction_checking/nfet_01v0.spice --variant=C --run_mode=deep --run_dir=lvs_switch_checking
+```
+
+### Options
+
+- `--help -h`                           Print this help message.
+
+- `--layout=<layout_path>`              The input GDS file path.
+
+- `--netlist=<netlist_path>`            The input netlist file path.
+
+- `--variant=<combined_options>`        Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C).
+  - gf180IC=A: Select  metal_top=30K  mim_option=A  metal_level=3LM  poly_res=1K, and mim_cap=2
+  - gf180IC=B: Select  metal_top=11K  mim_option=B  metal_level=4LM  poly_res=1K, and mim_cap=2
+  - gf180IC=C: Select  metal_top=9K   mim_option=B  metal_level=5LM  poly_res=1K, and mim_cap=2
+
+- `--thr=<thr>`                         The number of threads used in run.
+
+- `--run_dir=<run_dir_path>`            Run directory to save all the results [default: pwd]
+
+- `--topcell=<topcell_name>`            Topcell name to use.
+
+- `--run_mode=<run_mode>`               Select klayout mode Allowed modes (flat , deep, tiling). [default: deep]
+
+- `--lvs_sub=<sub_name>`                Substrate name used in your design.
+
+- `--verbose`                           Detailed rule execution log for debugging.
+
+- `--no_net_names`                      Discard net names in extracted netlist.
+
+- `--spice_comments`                    Enable netlist comments in extracted netlist.
+
+- `--scale`                             Enable scale of 1e6 in extracted netlist.
+
+- `--schematic_simplify`                Enable schematic simplification in input netlist.
+
+- `--net_only`                          Enable netlist object creation only in extracted netlist.
+
+- `--top_lvl_pins`                      Enable top level pins only in extracted netlist.
+
+- `--combine`                           Enable netlist combine only in extracted netlist.
+
+- `--purge`                             Enable netlist purge all only in extracted netlist.
+
+- `--purge_nets`                        Enable netlist purge nets only in extracted netlist.
+
+
+## **LVS Outputs**
+
+You could find the run results at your run directory if you previously specified it through `--run_dir=<run_dir_path>`. Default path of run directory is `lvs_run_<date>_<time>` in current directory.
+
+### Folder Structure of run results
+
+```text
+📁 lvs_run_<date>_<time>
+ ┣ 📜 lvs_run_<date>_<time>.log
+ ┗ 📜 <your_design_name>.cir
+ ┗ 📜 <your_design_name>.lvsdb
+ ```
+
+The result is a database file (`<your_design_name>.lvsdb`) contains LVS extractions and comparison results. 
+You could view it on your file using: `klayout <input_gds_file> -m <resut_db_file> `, or you could view it on your gds file via netlist browser option in tools menu using klayout GUI.
+
+You could also find the extracted netlist generated from your design at (`<your_design_name>.cir`) in your run directory.
+
+
+## **Devices Status**
+
+|Device Group|Device Name            |Sim Models        |Google Standard Name      |Status            |Standard Digital|Analog|Advanced Analog|RF   |HV   |ESD  |
+|------------|-----------------------|------------------|--------------------------|------------------|----------------|------|---------------|-----|-----|-----|
+|MOSFET      |nmos_1p8               |:heavy_check_mark:|nfet_01v8                 |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_1p8_nat           |:heavy_check_mark:|nfet_01v8_nvt             |:heavy_check_mark:|Yes             |Yes   |Maybe          |Maybe|No   |No   |
+|MOSFET      |nmos_1p8_mvt           |:heavy_check_mark:|nfet_01v8_mvt             |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_3p3               |:heavy_check_mark:|nfet_03v3                 |:heavy_check_mark:|Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_3p3_mvt           |:heavy_check_mark:|nfet_03v3_mvt             |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_3p3_nat           |:heavy_check_mark:|nfet_03v3_nvt             |:x:               |Yes             |Yes   |Maybe          |Maybe|No   |No   |
+|MOSFET      |pmos_1p8               |:heavy_check_mark:|pfet_01v8                 |:heavy_check_mark:|Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |pmos_1p8_mvt           |:heavy_check_mark:|pfet_01v8_mvt             |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |pmos_3p3               |:heavy_check_mark:|pfet_03v3                 |:heavy_check_mark:|Yes             |Yes   |Yes            |Maybe|No   |No   |
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|BJT         |vnpn_10x10             |:heavy_check_mark:|npn_10p00x10p00           |                  |No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vnpn_5x5               |:heavy_check_mark:|npn_05p00x05p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vnpn_2x2               |:heavy_check_mark:|npn_02p00x02p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vpnp_10x10             |:heavy_check_mark:|pnp_10p00x10p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vpnp_5x5               |:heavy_check_mark:|pnp_05p00x05p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vpnp_0p46x0p46         |:heavy_check_mark:|pnp_00p46x00p46           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vpnp_0p46x1p2          |:heavy_check_mark:|pnp_00p46x01p20           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vpnp_1p2x2p5           |:heavy_check_mark:|pnp_01p20x02p50           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |lpnp_1p8_0p54x0p54     |:heavy_check_mark:|pnp_00p54x00p54_01v8      |:x:               |No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |lpnp_1p8_0p54x1p2      |:heavy_check_mark:|pnp_00p54x01p20_01v8      |:x:               |No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |lpnp_1p8_1p2x2p5       |:heavy_check_mark:|pnp_01p20x02p50_01v8      |:x:               |No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |lpnp_1p8_5x5           |:heavy_check_mark:|pnp_05p00x05p00_01v8      |:x:               |No              |Yes   |Yes            |Yes  |Maybe|No   |
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|DIODE       |np_1p8                 |:heavy_check_mark:|diode_nd2ps_01v8          |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |np_1p8_nat             |:heavy_check_mark:|diode_nd2ps_01v8_nvt      |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |np_3p3                 |:heavy_check_mark:|diode_nd2ps_03v3          |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |np_3p3_nat             |:heavy_check_mark:|diode_nd2ps_03v3_nvt      |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |pn_1p8                 |:heavy_check_mark:|diode_pd2nw_01v8          |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |pn_3p3                 |:heavy_check_mark:|diode_pd2nw_03v3          |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |nwp                    |:heavy_check_mark:|diode_nw2ps               |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |dnwpw                  |:heavy_check_mark:|diode_pw2dw               |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |dnwps                  |:heavy_check_mark:|diode_dw2ps               |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|RES         |nplus_u                |:heavy_check_mark:|res_nd_3t_uns             |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |nplus_s                |:heavy_check_mark:|res_nd_3t_sal             |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |nwell                  |:heavy_check_mark:|res_nw_3t                 |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |npolyf_u               |:heavy_check_mark:|res_npo_3t_uns            |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |npolyf_s               |:heavy_check_mark:|res_npo_3t_sal            |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |npolyf_u_1k            |:heavy_check_mark:|res_npo_3t_uns_1k         |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |pplus_u                |:heavy_check_mark:|res_pd_3t_uns             |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |pplus_s                |:heavy_check_mark:|res_pd_3t_sal             |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_u               |:heavy_check_mark:|res_ppo_3t_uns            |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_s               |:heavy_check_mark:|res_ppo_3t_sal            |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_u_1k            |:heavy_check_mark:|res_ppo_3t_uns_1k         |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_u_2k            |:heavy_check_mark:|res_ppo_3t_uns_2k         |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|RES         |rm1                    |:heavy_check_mark:|res_m1                    |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |rm2                    |:heavy_check_mark:|res_m2                    |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |rm3                    |:heavy_check_mark:|res_m3                    |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |rm4                    |:heavy_check_mark:|res_m4                    |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |rm5                    |:heavy_check_mark:|res_m5                    |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |tm9k                   |:heavy_check_mark:|res_tm_9k                 |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |tm25k                  |:heavy_check_mark:|res_tm_25k                |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|MIMCAP      |mim_0p85fF             |:heavy_check_mark:|cap_mim_0f85              |                  |No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_1p0fF              |:heavy_check_mark:|cap_mim_1f0               |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_1p5fF              |:heavy_check_mark:|cap_mim_1f5               |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_2p0fF              |:heavy_check_mark:|cap_mim_2f0               |:x:               |No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_single_2p0fF       |:heavy_check_mark:|cap_mim_2f0               |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_3p0fF              |:heavy_check_mark:|cap_mim_3f0               |:x:               |No              |Yes   |Yes            |Yes  |No   |No   |
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|VARACTOR    |pnvar_1p8              |:heavy_check_mark:|cap_var_pd2nw_01v8        |:x:               |No              |Yes   |Yes            |Yes  |No   |No   |
+|VARACTOR    |nmosvar_1p8            |:heavy_check_mark:|cap_var_01v8              |:x:               |No              |Yes   |Yes            |Yes  |No   |No   |
+|VARACTOR    |nmosvar_3p3            |:heavy_check_mark:|cap_var_03v3              |:x:               |No              |Yes   |Yes            |Yes  |No   |No   |
diff --git a/IC/klayout/lvs/testing/README.md b/IC/klayout/lvs/testing/README.md
new file mode 100644
index 0000000..2f473a8
--- /dev/null
+++ b/IC/klayout/lvs/testing/README.md
@@ -0,0 +1,76 @@
+# Globalfoundries 180nm IC LVS Testing
+
+Explains how to test GF180nm LVS rule decks.
+
+## Folder Structure
+
+```text
+📁 testing
+ ┣ 📜README.md                       This file to document the regression.
+ ┣ 📜Makefile                        To make a full test for GF180nm LVS rule deck.
+ ┣ 📜run_regression.py               Main regression script used for LVS testing.
+ ┣ 📁testcases                       All testcases used in LVS regression.
+ ```
+
+## **Prerequisites**
+You need the following set of tools installed to be able to run the regression:
+- Python 3.6+
+- KLayout 0.28.4+
+
+We have tested this using the following setup:
+- Python 3.9.12
+- KLayout 0.28.5
+
+## **Usage**
+
+```bash
+    run_regression.py (--help| -h)
+    run_regression.py [--device_name=<device_name>] [--mp=<num>] [--run_name=<run_name>]
+```
+
+Example:
+
+```bash
+    python3 run_regression.py --device_name=MOS --run_name=mos_regression
+```
+
+### Options
+
+- `--help -h`                           Print this help message.
+
+- `--mp=<num>`                          The number of threads used in run.
+
+- `--run_name=<run_name>`               Select your run name.
+    
+- `--device_name=<device_name>`         Target specific device.
+
+
+To make a full test for GF180nm LVS rule deck, you could use the following command in testing directory:
+
+```bash
+make all
+```
+
+## **LVS Outputs**
+
+You could find the regression run results at your run directory if you previously specified it through `--run_name=<run_name>`. Default path of run directory is `unit_tests_<date>_<time>` in current directory.
+
+### Folder Structure of regression run results
+
+```text
+📁 unit_tests_<date>_<time>
+ ┣ 📜 unit_tests_<date>_<time>.log
+ ┣ 📜 all_test_cases_results.csv
+ ┗ 📜 rule_deck_rules.csv
+ ┗ 📁 <device_name>
+    ┣ 📜 <device_name>_lvs.log
+    ┣ 📜 <device_name>.gds
+    ┣ 📜 <device_name>.cdl
+    ┣ 📜 <device_name>_extracted.cir                     
+    ┣ 📜 <device_name>.lvsdb
+ ```
+
+The result is a database file for each device (`<device_name>.lvsdb`) contains LVS extractions and comparison results.
+You could view it on your file using: `klayout <device_name>.gds -mn <device_name>.lvsdb`, or you could view it on your gds file via marker browser option in tools menu using klayout GUI.
+
+You could also find the extracted netlist generated from your design at (`<device_name>.cir`) in your run directory.
diff --git a/IC/klayout/lvs/testing/testcases/README.md b/IC/klayout/lvs/testing/testcases/README.md
new file mode 100644
index 0000000..c90220e
--- /dev/null
+++ b/IC/klayout/lvs/testing/testcases/README.md
@@ -0,0 +1,16 @@
+# Globalfoundries 180nm IC LVS Tests
+
+
+## Folder Structure
+
+```text
+📁 testcases
+ ┣ 📜README.md                       This file to document the unit tests.
+ ┣ 📁 unit                           Contains the unit test structures per device.
+    ┣ 📁layout                       Layout gds file for each device.
+    ┣ 📁netlist                      Spice netlist file for each device.
+ ┣ 📁 extraction_checking            Contains a small test case to be used for testing the LVS switches.
+ ┣ 📁 torture                        Contains a few large test cases to test the performance of the rule deck. 
+
+ ```
+ 
\ No newline at end of file
diff --git a/ULL/klayout/lvs/README.md b/ULL/klayout/lvs/README.md
new file mode 100644
index 0000000..7d64fad
--- /dev/null
+++ b/ULL/klayout/lvs/README.md
@@ -0,0 +1,221 @@
+# LVS Documentation
+
+Explains how to use the runset.
+
+## Folder Structure
+
+```text
+📁 lvs
+ ┣ 📁testing                        Testing environment directory for GF180ULL LVS. 
+ ┣ 📁rule_decks                     All LVS rule decks used in GF180ULL.
+ ┣ 📜gf_018ULL.lvs                  Main LVS rule deck that call all runsets.
+ ┣ 📜README.md                      This file to document the LVS run for GF180ULL.
+ ┗ 📜run_lvs.py                     Main python script used for GF180ULL LVS.
+ ```
+
+## **Prerequisites**
+You need the following set of tools installed to be able to run GF180ULL LVS:
+- Python 3.6+
+- KLayout 0.28.4+
+
+## **Usage**
+
+The `run_lvs.py` script takes your input gds and netlist files to run LVS rule deck of GF180ULL technology on it with switches to select subsets of all checks. 
+
+```bash
+    run_lvs.py (--help| -h)
+    run_lvs.py (--layout=<layout_path>) (--netlist=<netlist_path>) (--variant=<combined_options>) [--thr=<thr>] [--run_dir=<run_dir_path>] [--topcell=<topcell_name>] [--run_mode=<run_mode>] [--verbose] [--lvs_sub=<sub_name>] [--no_net_names] [--spice_comments] [--scale] [--schematic_simplify] [--net_only] [--top_lvl_pins] [--combine] [--purge] [--purge_nets]
+```
+
+Example:
+```bash
+    python3 run_lvs.py --layout=testing/testcases/extraction_checking/nfet_01v0.gds --netlist=testing/testcases/extraction_checking/nfet_01v0.spice --variant=C --run_mode=deep --run_dir=lvs_switch_checking
+```
+
+### Options
+
+- `--help -h`                           Print this help message.
+
+- `--layout=<layout_path>`              The input GDS file path.
+
+- `--netlist=<netlist_path>`            The input netlist file path.
+
+- `--variant=<combined_options>`        Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C).
+  - variant=A: Select  metal_top=30K  mim_option=A  metal_level=3LM  poly_res=1K, and mim_cap=2
+  - variant=B: Select  metal_top=11K  mim_option=B  metal_level=4LM  poly_res=1K, and mim_cap=2
+  - variant=C: Select  metal_top=9K   mim_option=B  metal_level=5LM  poly_res=1K, and mim_cap=2
+
+- `--thr=<thr>`                         The number of threads used in run.
+
+- `--run_dir=<run_dir_path>`            Run directory to save all the results [default: pwd]
+
+- `--topcell=<topcell_name>`            Topcell name to use.
+
+- `--run_mode=<run_mode>`               Select klayout mode Allowed modes (flat , deep, tiling). [default: deep]
+
+- `--lvs_sub=<sub_name>`                Substrate name used in your design.
+
+- `--verbose`                           Detailed rule execution log for debugging.
+
+- `--no_net_names`                      Discard net names in extracted netlist.
+
+- `--spice_comments`                    Enable netlist comments in extracted netlist.
+
+- `--scale`                             Enable scale of 1e6 in extracted netlist.
+
+- `--schematic_simplify`                Enable schematic simplification in input netlist.
+
+- `--net_only`                          Enable netlist object creation only in extracted netlist.
+
+- `--top_lvl_pins`                      Enable top level pins only in extracted netlist.
+
+- `--combine`                           Enable netlist combine only in extracted netlist.
+
+- `--purge`                             Enable netlist purge all only in extracted netlist.
+
+- `--purge_nets`                        Enable netlist purge nets only in extracted netlist.
+
+
+## **LVS Outputs**
+
+You could find the run results at your run directory if you previously specified it through `--run_dir=<run_dir_path>`. Default path of run directory is `lvs_run_<date>_<time>` in current directory.
+
+### Folder Structure of run results
+
+```text
+📁 lvs_run_<date>_<time>
+ ┣ 📜 lvs_run_<date>_<time>.log
+ ┗ 📜 <your_design_name>.cir
+ ┗ 📜 <your_design_name>.lvsdb
+ ```
+
+The result is a database file (`<your_design_name>.lvsdb`) contains LVS extractions and comparison results. 
+You could view it on your file using: `klayout <input_gds_file> -m <resut_db_file> `, or you could view it on your gds file via netlist browser option in tools menu using klayout GUI.
+
+You could also find the extracted netlist generated from your design at (`<your_design_name>.cir`) in your run directory.
+
+
+## **Devices Status**
+
+|Device Group|Device Name            |Sim Models        |Google Standard Name      |Status            |Standard Digital|Analog|Advanced Analog|RF   |HV   |ESD  |
+|------------|-----------------------|------------------|--------------------------|------------------|----------------|------|---------------|-----|-----|-----|
+|MOSFET      |nmos_1p8               |:heavy_check_mark:|nfet_01v8                 |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_1p8_dw            |:x:               |nfet_01v8_dn              |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_1p8_nat           |:heavy_check_mark:|nfet_01v8_nvt             |:x:               |Yes             |Yes   |Maybe          |Maybe|No   |No   |
+|MOSFET      |nmos_3p3               |:heavy_check_mark:|nfet_03v3                 |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_3p3_dw            |:heavy_check_mark:|nfet_03v3_dn              |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_3p3_nat           |:heavy_check_mark:|nfet_03v3_nvt             |:x:               |Yes             |Yes   |Maybe          |Maybe|No   |No   |
+|MOSFET      |nmos_5p0               |:x:               |nfet_05v0                 |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_5p0_dw            |:x:               |nfet_05v0_dn              |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_6p0               |:heavy_check_mark:|nfet_06v0                 |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_6p0_dw            |:heavy_check_mark:|nfet_06v0_dn              |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |nmos_6p0_nat           |:heavy_check_mark:|nfet_06v0_nvt             |:x:               |Yes             |Yes   |Maybe          |Maybe|No   |No   |
+|MOSFET      |pmos_1p8               |:heavy_check_mark:|pfet_01v8                 |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |pmos_1p8_dw            |:x:               |pfet_01v8_dn              |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |pmos_3p3               |:heavy_check_mark:|pfet_03v3                 |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |pmos_3p3_dw            |:heavy_check_mark:|pfet_03v3_dn              |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |pmos_5p0               |:x:               |pfet_05v0                 |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |pmos_5p0_dw            |:x:               |pfet_05v0_dn              |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |pmos_6p0               |:heavy_check_mark:|pfet_06v0                 |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|MOSFET      |pmos_6p0_dw            |:heavy_check_mark:|pfet_06v0_dn              |:x:               |Yes             |Yes   |Yes            |Maybe|No   |No   |
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|BJT         |vnpn_10x10             |:heavy_check_mark:|npn_10p00x10p00           |                  |No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vnpn_5x5               |:heavy_check_mark:|npn_05p00x05p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vnpn_0p54x16           |:heavy_check_mark:|npn_00p54x16p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vnpn_0p54x8            |:heavy_check_mark:|npn_00p54x08p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vnpn_0p54x2            |:heavy_check_mark:|npn_00p54x02p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vnpn_0p54x16_3p3       |:x:               |npn_00p54x16p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vnpn_0p54x8_3p3        |:x:               |npn_00p54x08p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vnpn_0p54x2_3p3        |:x:               |npn_00p54x02p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vnpn_5x5_3p3           |:x:               |npn_05p00x05p00           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vpnp_6p0_0p42x20       |:heavy_check_mark:|pnp_00p42x20p00_06v0      |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vpnp_6p0_0p42x10       |:heavy_check_mark:|pnp_00p42x10p00_06v0      |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vpnp_6p0_0p42x5        |:heavy_check_mark:|pnp_00p42x05p00_06v0      |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vpnp_6p0_5x5           |:heavy_check_mark:|pnp_05p00x05p00_06v0      |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|BJT         |vpnp_6p0_10x10         |:heavy_check_mark:|pnp_10p00x10p00_06v0      |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |Maybe|No   |
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|DIODE       |np_1p8                 |:heavy_check_mark:|diode_nd2ps_01v8          |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |np_1p8_dw              |:x:               |diode_nd2ps_01v8_dn       |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |np_3p3                 |:heavy_check_mark:|diode_nd2ps_03v3          |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |np_3p3_dw              |:heavy_check_mark:|diode_nd2ps_03v3_dn       |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |np_6p0                 |:heavy_check_mark:|diode_nd2ps_06v0          |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |np_6p0_dw              |:heavy_check_mark:|diode_nd2ps_06v0_dn       |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |pn_1p8                 |:heavy_check_mark:|diode_pd2nw_01v8          |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |pn_1p8_dw              |:x:               |diode_pd2nw_01v8_dn       |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |pn_3p3                 |:heavy_check_mark:|diode_pd2nw_03v3          |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |pn_3p3_dw              |:heavy_check_mark:|diode_pd2nw_03v3_dn       |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |pn_6p0                 |:heavy_check_mark:|diode_pd2nw_06v0          |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |pn_6p0_dw              |:heavy_check_mark:|diode_pd2nw_06v0_dn       |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |nwp_6p0                |:heavy_check_mark:|diode_nw2ps_06v0          |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |dnwpw                  |:heavy_check_mark:|diode_pw2dw               |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|DIODE       |dnwps                  |:heavy_check_mark:|diode_dw2ps               |:x:               |Maybe           |Yes   |Yes            |Maybe|No   |Maybe|
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|RES         |nplus_u                |:heavy_check_mark:|res_nd_3t_uns             |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |nplus_u_dw             |:x:               |res_nd_3t_uns             |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |nplus_s                |:heavy_check_mark:|res_nd_3t_sal             |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |nplus_s_dw             |:x:               |res_nd_3t_sal             |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |npolyf_u               |:heavy_check_mark:|res_npo_3t_uns            |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |npolyf_u_dw            |:x:               |res_npo_3t_uns            |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |npolyf_s               |:heavy_check_mark:|res_npo_3t_sal            |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |npolyf_s_dw            |:x:               |res_npo_3t_sal            |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |pplus_u                |:heavy_check_mark:|res_pd_3t_uns             |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |pplus_u_dw             |:x:               |res_pd_3t_uns_dn          |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |pplus_s                |:heavy_check_mark:|res_pd_3t_sal             |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |pplus_s_dw             |:x:               |res_pd_3t_sal_dn          |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |pwell                  |:heavy_check_mark:|res_pw_3t                 |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_u               |:heavy_check_mark:|res_ppo_3t_uns            |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_u_dw            |:x:               |res_ppo_3t_uns_dn         |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_s               |:heavy_check_mark:|res_ppo_3t_sal            |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_s_dw            |:x:               |res_ppo_3t_sal_dn         |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_u_1k            |:heavy_check_mark:|res_ppo_3t_uns_1k         |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_u_1k_dw         |:x:               |res_ppo_3t_uns_1k_dn      |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_u_2k            |:heavy_check_mark:|res_ppo_3t_uns_2k         |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_u_2k_dw         |:x:               |res_ppo_3t_uns_2k_dn      |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |ppolyf_u_fhr_16p0_lv   |:heavy_check_mark:|res_ppo_3t_uns_fhr_16v0   |:x:               |No              |Yes   |Yes            |Maybe|Yes  |Maybe|
+|RES         |ppolyf_u_fhr_16p0_lv_dw|:x:               |res_ppo_3t_uns_fhr_16v0_dw|:x:               |No              |Yes   |Yes            |Maybe|Yes  |Maybe|
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|RES         |rm1                    |:heavy_check_mark:|res_m1                    |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |rm2                    |:heavy_check_mark:|res_m2                    |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |rm3                    |:heavy_check_mark:|res_m3                    |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |rm4                    |:heavy_check_mark:|res_m4                    |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |rm5                    |:heavy_check_mark:|res_m5                    |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|RES         |tm9k                   |:heavy_check_mark:|res_tm_9k                 |:x:               |No              |Yes   |Yes            |Maybe|Maybe|Maybe|
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|MIMCAP      |mim_0p85fF             |:heavy_check_mark:|cap_mim_0f85              |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_1p0fF              |:heavy_check_mark:|cap_mim_1f0               |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_1p5fF              |:heavy_check_mark:|cap_mim_1f5               |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_2p0fF              |:heavy_check_mark:|cap_mim_2f0               |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_0p85fF_tm          |:heavy_check_mark:|cap_mim_0f85_tm           |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_1p5fF_tm           |:heavy_check_mark:|cap_mim_1f5_tm            |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_1p0fF_tm           |:heavy_check_mark:|cap_mim_1f0               |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_2p0fF_tm           |:heavy_check_mark:|cap_mim_2f0_tm            |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|MIMCAP      |mim_1p5fF_stk          |:heavy_check_mark:|cap_mim_1f5_stk           |:x:               |No              |Yes   |Yes            |Yes  |No   |No   |
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|MOSCAP      |nmoscap_1p8            |:heavy_check_mark:|cap_nmos_01v8             |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|MOSCAP      |nmoscap_1p8_dw         |:x:               |cap_nmos_01v8_dn          |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|MOSCAP      |nmoscap_1p8_nwell      |:heavy_check_mark:|cap_nmos_1p8_nwell        |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|MOSCAP      |nmoscap_1p8_dnwell     |:heavy_check_mark:|cap_nmos_1p8_dnwell       |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|MOSCAP      |nmoscap_6p0            |:heavy_check_mark:|cap_nmos_06v0             |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|MOSCAP      |nmoscap_6p0_dw         |:heavy_check_mark:|cap_nmos_06v0_dn          |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|MOSCAP      |nmoscap_6p0_nwell      |:heavy_check_mark:|cap_nmos_6p0_nwell        |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|MOSCAP      |nmoscap_6p0_dnwell     |:heavy_check_mark:|cap_nmos_06v0_dnw         |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|MOSCAP      |pmoscap_1p8            |:heavy_check_mark:|cap_pmos_01v8             |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|MOSCAP      |pmoscap_1p8_dw         |:x:               |cap_pmos_01v8_dn          |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|MOSCAP      |pmoscap_6p0            |:heavy_check_mark:|cap_pmos_06v0             |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|MOSCAP      |pmoscap_6p0_dw         |:heavy_check_mark:|cap_pmos_06v0_dn          |:heavy_check_mark:|Maybe           |Yes   |Yes            |Maybe|No   |No   |
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|PISCAP      |pis_1p8                |:heavy_check_mark:|cap_pis_01v8              |:heavy_check_mark:|No              |Yes   |Yes            |Maybe|No   |No   |
+|PISCAP      |pis_1p8_dw             |:x:               |cap_pis_01v8_dn           |:heavy_check_mark:|No              |Yes   |Yes            |Maybe|No   |No   |
+|PISCAP      |pis_6p0                |:heavy_check_mark:|cap_pis_06v0              |:heavy_check_mark:|No              |Yes   |Yes            |Maybe|No   |No   |
+|PISCAP      |pis_6p0_dw             |:x:               |cap_pis_06v0_dn           |:heavy_check_mark:|No              |Yes   |Yes            |Maybe|No   |No   |
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|VARACTOR    |pn_varactor_1p8        |:heavy_check_mark:|cap_var_pd2nw_01v8        |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|VARACTOR    |pn_varactor_1p8_dw     |:x:               |cap_var_pd2nw_01v8_dn     |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|VARACTOR    |pn_varactor_6p0        |:heavy_check_mark:|cap_var_pd2nw_06v0        |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|VARACTOR    |pn_varactor_6p0_dw     |:x:               |cap_var_pd2nw_06v0_dn     |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|VARACTOR    |mos_varactor_1p8       |:heavy_check_mark:|cap_var_fet_01v8          |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|VARACTOR    |mos_varactor_1p8_dw    |:heavy_check_mark:|cap_var_fet_01v8_dn       |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|VARACTOR    |mos_varactor_6p0       |:heavy_check_mark:|cap_var_fet_06v0          |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|VARACTOR    |mos_varactor_6p0_dw    |:heavy_check_mark:|cap_var_fet_06v0_dn       |:heavy_check_mark:|No              |Yes   |Yes            |Yes  |No   |No   |
+|            |                       |                  |                          |                  |                |      |               |     |     |     |
+|eFuse       |eFuse                  |:heavy_check_mark:|efuse                     |:x:               |Maybe           |Yes   |Yes            |No   |Maybe|No   |
diff --git a/ULL/klayout/lvs/testing/README.md b/ULL/klayout/lvs/testing/README.md
new file mode 100644
index 0000000..2f27c91
--- /dev/null
+++ b/ULL/klayout/lvs/testing/README.md
@@ -0,0 +1,76 @@
+# Globalfoundries 180nm ULL LVS Testing
+
+Explains how to test GF180nm LVS rule decks.
+
+## Folder Structure
+
+```text
+📁 testing
+ ┣ 📜README.md                       This file to document the regression.
+ ┣ 📜Makefile                        To make a full test for GF180nm LVS rule deck.
+ ┣ 📜run_regression.py               Main regression script used for LVS testing.
+ ┣ 📁testcases                       All testcases used in LVS regression.
+ ```
+
+## **Prerequisites**
+You need the following set of tools installed to be able to run the regression:
+- Python 3.6+
+- KLayout 0.28.4+
+
+We have tested this using the following setup:
+- Python 3.9.12
+- KLayout 0.28.5
+
+## **Usage**
+
+```bash
+    run_regression.py (--help| -h)
+    run_regression.py [--device_name=<device_name>] [--mp=<num>] [--run_name=<run_name>]
+```
+
+Example:
+
+```bash
+    python3 run_regression.py --device_name=MOS --run_name=mos_regression
+```
+
+### Options
+
+- `--help -h`                           Print this help message.
+
+- `--mp=<num>`                          The number of threads used in run.
+
+- `--run_name=<run_name>`               Select your run name.
+    
+- `--device_name=<device_name>`         Target specific device.
+
+
+To make a full test for GF180nm LVS rule deck, you could use the following command in testing directory:
+
+```bash
+make all
+```
+
+## **LVS Outputs**
+
+You could find the regression run results at your run directory if you previously specified it through `--run_name=<run_name>`. Default path of run directory is `unit_tests_<date>_<time>` in current directory.
+
+### Folder Structure of regression run results
+
+```text
+📁 unit_tests_<date>_<time>
+ ┣ 📜 unit_tests_<date>_<time>.log
+ ┣ 📜 all_test_cases_results.csv
+ ┗ 📜 rule_deck_rules.csv
+ ┗ 📁 <device_name>
+    ┣ 📜 <device_name>_lvs.log
+    ┣ 📜 <device_name>.gds
+    ┣ 📜 <device_name>.cdl
+    ┣ 📜 <device_name>_extracted.cir                     
+    ┣ 📜 <device_name>.lvsdb
+ ```
+
+The result is a database file for each device (`<device_name>.lvsdb`) contains LVS extractions and comparison results.
+You could view it on your file using: `klayout <device_name>.gds -mn <device_name>.lvsdb`, or you could view it on your gds file via marker browser option in tools menu using klayout GUI.
+
+You could also find the extracted netlist generated from your design at (`<device_name>.cir`) in your run directory.
diff --git a/ULL/klayout/lvs/testing/extraction_checking/extracted_netlist_sample_nfet_03v3.cir b/ULL/klayout/lvs/testing/extraction_checking/extracted_netlist_sample_nfet_03v3.cir
deleted file mode 100644
index e69de29..0000000
--- a/ULL/klayout/lvs/testing/extraction_checking/extracted_netlist_sample_nfet_03v3.cir
+++ /dev/null
diff --git a/ULL/klayout/lvs/testing/extraction_checking/sample_nfet_03v3.cir b/ULL/klayout/lvs/testing/extraction_checking/sample_nfet_03v3.cir
deleted file mode 100644
index 9d11097..0000000
--- a/ULL/klayout/lvs/testing/extraction_checking/sample_nfet_03v3.cir
+++ /dev/null
@@ -1,23 +0,0 @@
-* Copyright 2023 GlobalFoundries PDK Authors
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     https://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-
-** Circuit sample_nfet_03v3
-
-.subckt sample_nfet_03v3 I1_default_D I1_default_G I1_default_S vdd!
-MI1_default I1_default_D I1_default_G I1_default_S vdd! nfet_03v3 m=1 w=360e-9
-+ l=280n nf=1 as=158.4e-15 ad=158.4e-15 ps=1.6e-6 pd=1.6e-6 nrd=1.222222
-+ nrs=1.222222 sa=0.440u sb=0.440u sd=0u dtemp=0 par=1
-.ends
-
-.end
\ No newline at end of file
diff --git a/ULL/klayout/lvs/testing/extraction_checking/sample_nfet_03v3.gds b/ULL/klayout/lvs/testing/extraction_checking/sample_nfet_03v3.gds
deleted file mode 100644
index 6fe0c18..0000000
--- a/ULL/klayout/lvs/testing/extraction_checking/sample_nfet_03v3.gds
+++ /dev/null
Binary files differ
diff --git a/ULL/klayout/lvs/testing/testcases/README.md b/ULL/klayout/lvs/testing/testcases/README.md
new file mode 100644
index 0000000..705d5fc
--- /dev/null
+++ b/ULL/klayout/lvs/testing/testcases/README.md
@@ -0,0 +1,16 @@
+# Globalfoundries 180nm ULL LVS Tests
+
+
+## Folder Structure
+
+```text
+📁 testcases
+ ┣ 📜README.md                       This file to document the unit tests.
+ ┣ 📁 unit                           Contains the unit test structures per device.
+    ┣ 📁layout                       Layout gds file for each device.
+    ┣ 📁netlist                      Spice netlist file for each device.
+ ┣ 📁 extraction_checking            Contains a small test case to be used for testing the LVS switches.
+ ┣ 📁 torture                        Contains a few large test cases to test the performance of the rule deck. 
+
+ ```
+ 
\ No newline at end of file