add mgmt core wrapper block level sta
diff --git a/logs/mgmt_core_wrapper-sta.log b/logs/mgmt_core_wrapper-sta.log
new file mode 100644
index 0000000..e220f01
--- /dev/null
+++ b/logs/mgmt_core_wrapper-sta.log
@@ -0,0 +1,17656 @@
+OpenSTA 2.3.1 79a46b62da Copyright (c) 2021, Parallax Software, Inc.
+License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
+
+This is free software, and you are free to change and redistribute it
+under certain conditions; type `show_copying' for details.
+This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
+ignoring /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/__user_analog_project_wrapper.v
+ignoring /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/__user_project_wrapper.v
+ignoring /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/caravel.v.orig
+ignoring /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/gpio_defaults_block.v
+ignoring /home/kareem_farid/gf180.new/caravel/caravel/verilog/gl/user_project_wrapper.v
+read_spef /home/kareem_farid/gf180.new/caravel/mgmt_soc_litex/spef/mgmt_core_wrapper_nom.spef
+report_checks -fields {capacitance slew input_pins nets fanout} -path_delay min_max -group_count 5
+Startpoint: _43032_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: _44478_ (rising edge-triggered flip-flop clocked by core_clk)
+Path Group: core_clk
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 3.90 3.90 clock network delay (propagated)
+ 0.12 0.00 3.90 ^ _43032_/CLK (DFFQ_X1_7T5P0)
+ 0.23 0.71 4.61 v _43032_/Q (DFFQ_X1_7T5P0)
+ 2 0.02 core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[29] (net)
+ 0.23 0.00 4.61 v _34607_/A1 (NAND2_X1_7T5P0)
+ 0.18 0.16 4.77 ^ _34607_/ZN (NAND2_X1_7T5P0)
+ 1 0.01 _14586_ (net)
+ 0.18 0.00 4.77 ^ _34609_/B1 (AOI22_X1_7T5P0)
+ 0.17 0.14 4.92 v _34609_/ZN (AOI22_X1_7T5P0)
+ 1 0.00 _02548_ (net)
+ 0.17 0.00 4.92 v _44478_/D (DFFQ_X1_7T5P0)
+ 4.92 data arrival time
+
+ 0.00 0.00 clock core_clk (rise edge)
+ 5.66 5.66 clock network delay (propagated)
+ 0.25 5.91 clock uncertainty
+ -0.22 5.68 clock reconvergence pessimism
+ 5.68 ^ _44478_/CLK (DFFQ_X1_7T5P0)
+ 0.08 5.76 library hold time
+ 5.76 data required time
+-----------------------------------------------------------------------------
+ 5.76 data required time
+ -4.92 data arrival time
+-----------------------------------------------------------------------------
+ -0.85 slack (VIOLATED)
+
+
+Startpoint: _43643_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: _43879_ (rising edge-triggered flip-flop clocked by core_clk)
+Path Group: core_clk
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 3.83 3.83 clock network delay (propagated)
+ 0.13 0.00 3.83 ^ _43643_/CLK (DFFQ_X1_7T5P0)
+ 0.17 0.67 4.50 v _43643_/Q (DFFQ_X1_7T5P0)
+ 2 0.01 core.VexRiscv.lastStagePc[6] (net)
+ 0.17 0.00 4.50 v _22234_/A1 (OAI211_X1_7T5P0)
+ 0.45 0.33 4.83 ^ _22234_/ZN (OAI211_X1_7T5P0)
+ 1 0.01 _04904_ (net)
+ 0.45 0.00 4.83 ^ _22235_/B (OAI21_X1_7T5P0)
+ 0.19 0.14 4.97 v _22235_/ZN (OAI21_X1_7T5P0)
+ 1 0.00 _04905_ (net)
+ 0.19 0.00 4.97 v _22236_/I (CLKBUF_X1_7T5P0)
+ 0.10 0.20 5.17 v _22236_/Z (CLKBUF_X1_7T5P0)
+ 1 0.00 _00125_ (net)
+ 0.10 0.00 5.17 v _43879_/D (DFFQ_X1_7T5P0)
+ 5.17 data arrival time
+
+ 0.00 0.00 clock core_clk (rise edge)
+ 5.60 5.60 clock network delay (propagated)
+ 0.25 5.85 clock uncertainty
+ -0.07 5.77 clock reconvergence pessimism
+ 5.77 ^ _43879_/CLK (DFFQ_X1_7T5P0)
+ 0.09 5.86 library hold time
+ 5.86 data required time
+-----------------------------------------------------------------------------
+ 5.86 data required time
+ -5.17 data arrival time
+-----------------------------------------------------------------------------
+ -0.70 slack (VIOLATED)
+
+
+Startpoint: _45852_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: _44479_ (rising edge-triggered flip-flop clocked by core_clk)
+Path Group: core_clk
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.06 4.06 clock network delay (propagated)
+ 0.17 0.00 4.06 ^ _45852_/CLK (DFFQ_X1_7T5P0)
+ 0.16 0.67 4.73 v _45852_/Q (DFFQ_X1_7T5P0)
+ 2 0.01 core.mgmtsoc_vexriscv_i_cmd_payload_data[30] (net)
+ 0.16 0.00 4.73 v _34610_/I (CLKINV_X1_7T5P0)
+ 0.34 0.23 4.96 ^ _34610_/ZN (CLKINV_X1_7T5P0)
+ 1 0.02 _14588_ (net)
+ 0.34 0.00 4.96 ^ _34613_/A1 (AOI22_X1_7T5P0)
+ 0.18 0.14 5.09 v _34613_/ZN (AOI22_X1_7T5P0)
+ 1 0.01 _02549_ (net)
+ 0.18 0.00 5.09 v _44479_/D (DFFQ_X1_7T5P0)
+ 5.09 data arrival time
+
+ 0.00 0.00 clock core_clk (rise edge)
+ 5.65 5.65 clock network delay (propagated)
+ 0.25 5.90 clock uncertainty
+ -0.22 5.68 clock reconvergence pessimism
+ 5.68 ^ _44479_/CLK (DFFQ_X1_7T5P0)
+ 0.08 5.76 library hold time
+ 5.76 data required time
+-----------------------------------------------------------------------------
+ 5.76 data required time
+ -5.09 data arrival time
+-----------------------------------------------------------------------------
+ -0.67 slack (VIOLATED)
+
+
+Startpoint: _43029_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: _44475_ (rising edge-triggered flip-flop clocked by core_clk)
+Path Group: core_clk
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.05 4.05 clock network delay (propagated)
+ 0.11 0.00 4.05 ^ _43029_/CLK (DFFQ_X1_7T5P0)
+ 0.19 0.68 4.73 v _43029_/Q (DFFQ_X1_7T5P0)
+ 2 0.01 core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[26] (net)
+ 0.19 0.00 4.73 v _34595_/A1 (NAND2_X1_7T5P0)
+ 0.23 0.19 4.92 ^ _34595_/ZN (NAND2_X1_7T5P0)
+ 1 0.01 _14577_ (net)
+ 0.23 0.00 4.92 ^ _34597_/B1 (AOI22_X1_7T5P0)
+ 0.15 0.15 5.07 v _34597_/ZN (AOI22_X1_7T5P0)
+ 1 0.00 _02545_ (net)
+ 0.15 0.00 5.07 v _44475_/D (DFFQ_X1_7T5P0)
+ 5.07 data arrival time
+
+ 0.00 0.00 clock core_clk (rise edge)
+ 5.47 5.47 clock network delay (propagated)
+ 0.25 5.72 clock uncertainty
+ -0.22 5.50 clock reconvergence pessimism
+ 5.50 ^ _44475_/CLK (DFFQ_X1_7T5P0)
+ 0.08 5.58 library hold time
+ 5.58 data required time
+-----------------------------------------------------------------------------
+ 5.58 data required time
+ -5.07 data arrival time
+-----------------------------------------------------------------------------
+ -0.51 slack (VIOLATED)
+
+
+Startpoint: _44952_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: _44956_ (rising edge-triggered flip-flop clocked by core_clk)
+Path Group: core_clk
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 3.66 3.66 clock network delay (propagated)
+ 0.17 0.00 3.66 ^ _44952_/CLK (DFFQ_X1_7T5P0)
+ 0.16 0.72 4.37 ^ _44952_/Q (DFFQ_X1_7T5P0)
+ 1 0.01 core.gpioin1_gpioin1_trigger_d (net)
+ 0.16 0.00 4.37 ^ _36438_/A2 (OAI31_X1_7T5P0)
+ 0.19 0.17 4.54 v _36438_/ZN (OAI31_X1_7T5P0)
+ 1 0.01 _02885_ (net)
+ 0.19 0.00 4.54 v _44956_/D (DFFQ_X1_7T5P0)
+ 4.54 data arrival time
+
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.72 4.72 clock network delay (propagated)
+ 0.25 4.97 clock uncertainty
+ -0.18 4.79 clock reconvergence pessimism
+ 4.79 ^ _44956_/CLK (DFFQ_X1_7T5P0)
+ 0.07 4.87 library hold time
+ 4.87 data required time
+-----------------------------------------------------------------------------
+ 4.87 data required time
+ -4.54 data arrival time
+-----------------------------------------------------------------------------
+ -0.33 slack (VIOLATED)
+
+
+Startpoint: mprj_ack_i (input port clocked by core_clk)
+Endpoint: _44447_ (rising edge-triggered flip-flop clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 9.00 9.00 ^ input external delay
+ 0.16 0.07 9.07 ^ mprj_ack_i (in)
+ 2 0.01 mprj_ack_i (net)
+ 0.16 0.00 9.07 ^ input108/I (CLKBUF_X1_7T5P0)
+ 9.02 5.54 14.61 ^ input108/Z (CLKBUF_X1_7T5P0)
+ 2 0.56 net108 (net)
+ 9.04 0.23 14.84 ^ _21137_/A3 (NOR4_X2_7T5P0)
+ 2.43 0.28 15.12 v _21137_/ZN (NOR4_X2_7T5P0)
+ 1 0.02 _20349_ (net)
+ 2.43 0.00 15.12 v _21138_/A4 (NAND4_X4_7T5P0)
+ 1.80 1.78 16.90 ^ _21138_/ZN (NAND4_X4_7T5P0)
+ 10 0.23 _20350_ (net)
+ 1.80 0.01 16.91 ^ _21139_/A2 (NAND2_X1_7T5P0)
+ 1.00 0.69 17.60 v _21139_/ZN (NAND2_X1_7T5P0)
+ 4 0.05 _20351_ (net)
+ 1.00 0.00 17.61 v _21140_/A3 (NOR3_X2_7T5P0)
+ 15.90 9.51 27.12 ^ _21140_/ZN (NOR3_X2_7T5P0)
+ 6 0.74 _20352_ (net)
+ 15.90 0.09 27.21 ^ _21141_/A3 (OR3_X1_7T5P0)
+ 0.62 -0.94 26.28 ^ _21141_/Z (OR3_X1_7T5P0)
+ 2 0.02 _20353_ (net)
+ 0.62 0.00 26.28 ^ _21142_/A2 (NAND2_X2_7T5P0)
+ 1.66 0.81 27.08 v _21142_/ZN (NAND2_X2_7T5P0)
+ 14 0.15 _20354_ (net)
+ 1.66 0.01 27.09 v _21218_/A1 (OR2_X1_7T5P0)
+ 3.05 2.88 29.97 v _21218_/Z (OR2_X1_7T5P0)
+ 8 0.32 _20430_ (net)
+ 3.06 0.07 30.04 v _21328_/A1 (OR3_X1_7T5P0)
+ 1.04 2.39 32.43 v _21328_/Z (OR3_X1_7T5P0)
+ 6 0.09 _20540_ (net)
+ 1.04 0.01 32.44 v _21329_/I (CLKBUF_X2_7T5P0)
+ 0.52 0.74 33.18 v _21329_/Z (CLKBUF_X2_7T5P0)
+ 8 0.06 _20541_ (net)
+ 0.52 0.00 33.19 v _21336_/I (CLKBUF_X2_7T5P0)
+ 1.94 1.55 34.74 v _21336_/Z (CLKBUF_X2_7T5P0)
+ 16 0.25 _20548_ (net)
+ 1.95 0.02 34.76 v _26778_/A1 (NOR2_X2_7T5P0)
+ 12.01 7.55 42.31 ^ _26778_/ZN (NOR2_X2_7T5P0)
+ 14 0.83 _08573_ (net)
+ 12.03 0.25 42.56 ^ _34438_/I (CLKBUF_X2_7T5P0)
+ 5.26 4.17 46.72 ^ _34438_/Z (CLKBUF_X2_7T5P0)
+ 16 0.69 _14448_ (net)
+ 5.26 0.01 46.73 ^ _34473_/A1 (NAND4_X1_7T5P0)
+ 11.30 8.29 55.02 v _34473_/ZN (NAND4_X1_7T5P0)
+ 2 0.46 _14483_ (net)
+ 11.30 0.11 55.14 v _34474_/B (OAI21_X1_7T5P0)
+ 2.03 2.49 57.62 ^ _34474_/ZN (OAI21_X1_7T5P0)
+ 1 0.01 _14484_ (net)
+ 2.03 0.00 57.62 ^ _34475_/I (CLKBUF_X1_7T5P0)
+ 0.16 0.39 58.01 ^ _34475_/Z (CLKBUF_X1_7T5P0)
+ 1 0.00 _02517_ (net)
+ 0.16 0.00 58.01 ^ _44447_/D (DFFQ_X1_7T5P0)
+ 58.01 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 4.75 49.75 clock network delay (propagated)
+ -0.25 49.50 clock uncertainty
+ 0.00 49.50 clock reconvergence pessimism
+ 49.50 ^ _44447_/CLK (DFFQ_X1_7T5P0)
+ -0.21 49.29 library setup time
+ 49.29 data required time
+-----------------------------------------------------------------------------
+ 49.29 data required time
+ -58.01 data arrival time
+-----------------------------------------------------------------------------
+ -8.72 slack (VIOLATED)
+
+
+Startpoint: mprj_ack_i (input port clocked by core_clk)
+Endpoint: _43707_ (rising edge-triggered flip-flop clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 9.00 9.00 ^ input external delay
+ 0.16 0.07 9.07 ^ mprj_ack_i (in)
+ 2 0.01 mprj_ack_i (net)
+ 0.16 0.00 9.07 ^ input108/I (CLKBUF_X1_7T5P0)
+ 9.02 5.54 14.61 ^ input108/Z (CLKBUF_X1_7T5P0)
+ 2 0.56 net108 (net)
+ 9.04 0.23 14.84 ^ _21137_/A3 (NOR4_X2_7T5P0)
+ 2.43 0.28 15.12 v _21137_/ZN (NOR4_X2_7T5P0)
+ 1 0.02 _20349_ (net)
+ 2.43 0.00 15.12 v _21138_/A4 (NAND4_X4_7T5P0)
+ 1.80 1.78 16.90 ^ _21138_/ZN (NAND4_X4_7T5P0)
+ 10 0.23 _20350_ (net)
+ 1.80 0.01 16.91 ^ _21139_/A2 (NAND2_X1_7T5P0)
+ 1.00 0.69 17.60 v _21139_/ZN (NAND2_X1_7T5P0)
+ 4 0.05 _20351_ (net)
+ 1.00 0.00 17.61 v _21140_/A3 (NOR3_X2_7T5P0)
+ 15.90 9.51 27.12 ^ _21140_/ZN (NOR3_X2_7T5P0)
+ 6 0.74 _20352_ (net)
+ 15.90 0.09 27.21 ^ _21141_/A3 (OR3_X1_7T5P0)
+ 0.62 -0.94 26.28 ^ _21141_/Z (OR3_X1_7T5P0)
+ 2 0.02 _20353_ (net)
+ 0.62 0.00 26.28 ^ _21142_/A2 (NAND2_X2_7T5P0)
+ 1.66 0.81 27.08 v _21142_/ZN (NAND2_X2_7T5P0)
+ 14 0.15 _20354_ (net)
+ 1.66 0.01 27.09 v _21218_/A1 (OR2_X1_7T5P0)
+ 3.05 2.88 29.97 v _21218_/Z (OR2_X1_7T5P0)
+ 8 0.32 _20430_ (net)
+ 3.06 0.07 30.04 v _21328_/A1 (OR3_X1_7T5P0)
+ 1.04 2.39 32.43 v _21328_/Z (OR3_X1_7T5P0)
+ 6 0.09 _20540_ (net)
+ 1.04 0.01 32.44 v _21329_/I (CLKBUF_X2_7T5P0)
+ 0.52 0.74 33.18 v _21329_/Z (CLKBUF_X2_7T5P0)
+ 8 0.06 _20541_ (net)
+ 0.52 0.00 33.19 v _21336_/I (CLKBUF_X2_7T5P0)
+ 1.94 1.55 34.74 v _21336_/Z (CLKBUF_X2_7T5P0)
+ 16 0.25 _20548_ (net)
+ 1.95 0.02 34.76 v _26778_/A1 (NOR2_X2_7T5P0)
+ 12.01 7.55 42.31 ^ _26778_/ZN (NOR2_X2_7T5P0)
+ 14 0.83 _08573_ (net)
+ 12.03 0.23 42.54 ^ _26799_/I (CLKBUF_X2_7T5P0)
+ 6.38 4.97 47.51 ^ _26799_/Z (CLKBUF_X2_7T5P0)
+ 16 0.85 _08591_ (net)
+ 6.38 0.13 47.64 ^ _31491_/A1 (NAND4_X2_7T5P0)
+ 5.68 4.61 52.25 v _31491_/ZN (NAND4_X2_7T5P0)
+ 4 0.43 _12337_ (net)
+ 5.69 0.07 52.33 v _31907_/A1 (AOI21_X1_7T5P0)
+ 1.33 1.52 53.85 ^ _31907_/ZN (AOI21_X1_7T5P0)
+ 1 0.01 _12617_ (net)
+ 1.33 0.00 53.85 ^ _31908_/I (CLKBUF_X1_7T5P0)
+ 0.14 0.34 54.19 ^ _31908_/Z (CLKBUF_X1_7T5P0)
+ 1 0.00 _01817_ (net)
+ 0.14 0.00 54.19 ^ _43707_/D (DFFQ_X1_7T5P0)
+ 54.19 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 3.80 48.80 clock network delay (propagated)
+ -0.25 48.55 clock uncertainty
+ 0.00 48.55 clock reconvergence pessimism
+ 48.55 ^ _43707_/CLK (DFFQ_X1_7T5P0)
+ -0.22 48.33 library setup time
+ 48.33 data required time
+-----------------------------------------------------------------------------
+ 48.33 data required time
+ -54.19 data arrival time
+-----------------------------------------------------------------------------
+ -5.86 slack (VIOLATED)
+
+
+Startpoint: _43085_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: _43005_ (rising edge-triggered flip-flop clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 5.23 5.23 clock network delay (propagated)
+ 0.13 0.00 5.23 ^ _43085_/CLK (DFFQ_X1_7T5P0)
+ 4.96 3.82 9.04 v _43085_/Q (DFFQ_X1_7T5P0)
+ 10 0.52 core.VexRiscv.CsrPlugin_exceptionPendings_3 (net)
+ 4.96 0.02 9.06 v _22139_/A4 (NOR4_X1_7T5P0)
+ 1.62 1.12 10.18 ^ _22139_/ZN (NOR4_X1_7T5P0)
+ 1 0.01 _04815_ (net)
+ 1.62 0.00 10.18 ^ _22140_/A4 (AND4_X1_7T5P0)
+ 3.90 2.84 13.02 ^ _22140_/Z (AND4_X1_7T5P0)
+ 10 0.24 _04816_ (net)
+ 3.90 0.04 13.06 ^ _22172_/A2 (OR2_X1_7T5P0)
+ 6.86 4.24 17.30 ^ _22172_/Z (OR2_X1_7T5P0)
+ 12 0.43 _04846_ (net)
+ 6.86 0.01 17.31 ^ _26755_/A2 (NOR2_X2_7T5P0)
+ 2.89 1.95 19.25 v _26755_/ZN (NOR2_X2_7T5P0)
+ 14 0.20 _08550_ (net)
+ 2.89 0.00 19.25 v _26756_/A2 (NAND2_X1_7T5P0)
+ 8.32 5.85 25.10 ^ _26756_/ZN (NAND2_X1_7T5P0)
+ 6 0.48 _08551_ (net)
+ 8.32 0.10 25.20 ^ _26763_/A1 (NOR2_X1_7T5P0)
+ 4.06 2.98 28.17 v _26763_/ZN (NOR2_X1_7T5P0)
+ 4 0.16 _08558_ (net)
+ 4.06 0.02 28.19 v _26773_/A1 (NOR3_X1_7T5P0)
+ 17.39 11.14 39.33 ^ _26773_/ZN (NOR3_X1_7T5P0)
+ 6 0.41 _08568_ (net)
+ 17.39 0.07 39.40 ^ _26774_/I (BUF_X1_7T5P0)
+ 10.30 5.99 45.38 ^ _26774_/Z (BUF_X1_7T5P0)
+ 16 0.70 _08569_ (net)
+ 10.30 0.01 45.39 ^ _26881_/I (BUF_X1_7T5P0)
+ 10.14 6.08 51.47 ^ _26881_/Z (BUF_X1_7T5P0)
+ 16 0.66 _08656_ (net)
+ 10.15 0.14 51.61 ^ _28767_/B (AOI21_X1_7T5P0)
+ 2.53 0.78 52.39 v _28767_/ZN (AOI21_X1_7T5P0)
+ 1 0.02 _10096_ (net)
+ 2.53 0.00 52.39 v _28768_/B2 (AOI221_X1_7T5P0)
+ 3.17 2.38 54.77 ^ _28768_/ZN (AOI221_X1_7T5P0)
+ 2 0.06 _10097_ (net)
+ 3.17 0.00 54.78 ^ _28769_/B (AOI21_X1_7T5P0)
+ 0.90 0.37 55.14 v _28769_/ZN (AOI21_X1_7T5P0)
+ 1 0.01 _10098_ (net)
+ 0.90 0.00 55.14 v _28770_/I (CLKINV_X1_7T5P0)
+ 0.31 0.29 55.44 ^ _28770_/ZN (CLKINV_X1_7T5P0)
+ 1 0.01 _01198_ (net)
+ 0.31 0.00 55.44 ^ _43005_/D (DFFQ_X1_7T5P0)
+ 55.44 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 4.85 49.85 clock network delay (propagated)
+ -0.25 49.60 clock uncertainty
+ 0.36 49.96 clock reconvergence pessimism
+ 49.96 ^ _43005_/CLK (DFFQ_X1_7T5P0)
+ -0.22 49.74 library setup time
+ 49.74 data required time
+-----------------------------------------------------------------------------
+ 49.74 data required time
+ -55.44 data arrival time
+-----------------------------------------------------------------------------
+ -5.70 slack (VIOLATED)
+
+
+Startpoint: _43085_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: _43004_ (rising edge-triggered flip-flop clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 5.23 5.23 clock network delay (propagated)
+ 0.13 0.00 5.23 ^ _43085_/CLK (DFFQ_X1_7T5P0)
+ 4.96 3.82 9.04 v _43085_/Q (DFFQ_X1_7T5P0)
+ 10 0.52 core.VexRiscv.CsrPlugin_exceptionPendings_3 (net)
+ 4.96 0.02 9.06 v _22139_/A4 (NOR4_X1_7T5P0)
+ 1.62 1.12 10.18 ^ _22139_/ZN (NOR4_X1_7T5P0)
+ 1 0.01 _04815_ (net)
+ 1.62 0.00 10.18 ^ _22140_/A4 (AND4_X1_7T5P0)
+ 3.90 2.84 13.02 ^ _22140_/Z (AND4_X1_7T5P0)
+ 10 0.24 _04816_ (net)
+ 3.90 0.04 13.06 ^ _22172_/A2 (OR2_X1_7T5P0)
+ 6.86 4.24 17.30 ^ _22172_/Z (OR2_X1_7T5P0)
+ 12 0.43 _04846_ (net)
+ 6.86 0.01 17.31 ^ _26755_/A2 (NOR2_X2_7T5P0)
+ 2.89 1.95 19.25 v _26755_/ZN (NOR2_X2_7T5P0)
+ 14 0.20 _08550_ (net)
+ 2.89 0.00 19.25 v _26756_/A2 (NAND2_X1_7T5P0)
+ 8.32 5.85 25.10 ^ _26756_/ZN (NAND2_X1_7T5P0)
+ 6 0.48 _08551_ (net)
+ 8.32 0.10 25.20 ^ _26763_/A1 (NOR2_X1_7T5P0)
+ 4.06 2.98 28.17 v _26763_/ZN (NOR2_X1_7T5P0)
+ 4 0.16 _08558_ (net)
+ 4.06 0.02 28.19 v _26773_/A1 (NOR3_X1_7T5P0)
+ 17.39 11.14 39.33 ^ _26773_/ZN (NOR3_X1_7T5P0)
+ 6 0.41 _08568_ (net)
+ 17.39 0.07 39.40 ^ _26774_/I (BUF_X1_7T5P0)
+ 10.30 5.99 45.38 ^ _26774_/Z (BUF_X1_7T5P0)
+ 16 0.70 _08569_ (net)
+ 10.30 0.01 45.39 ^ _26881_/I (BUF_X1_7T5P0)
+ 10.14 6.08 51.47 ^ _26881_/Z (BUF_X1_7T5P0)
+ 16 0.66 _08656_ (net)
+ 10.15 0.14 51.61 ^ _28755_/B (AOI21_X1_7T5P0)
+ 2.18 0.41 52.02 v _28755_/ZN (AOI21_X1_7T5P0)
+ 1 0.01 _10085_ (net)
+ 2.18 0.00 52.02 v _28756_/B2 (AOI221_X1_7T5P0)
+ 3.96 2.78 54.80 ^ _28756_/ZN (AOI221_X1_7T5P0)
+ 2 0.08 _10086_ (net)
+ 3.96 0.00 54.81 ^ _28757_/B (AOI21_X1_7T5P0)
+ 1.05 0.38 55.19 v _28757_/ZN (AOI21_X1_7T5P0)
+ 1 0.01 _10087_ (net)
+ 1.05 0.00 55.19 v _28758_/I (CLKINV_X1_7T5P0)
+ 0.27 0.24 55.43 ^ _28758_/ZN (CLKINV_X1_7T5P0)
+ 1 0.00 _01197_ (net)
+ 0.27 0.00 55.43 ^ _43004_/D (DFFQ_X1_7T5P0)
+ 55.43 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 4.75 49.75 clock network delay (propagated)
+ -0.25 49.50 clock uncertainty
+ 0.46 49.96 clock reconvergence pessimism
+ 49.96 ^ _43004_/CLK (DFFQ_X1_7T5P0)
+ -0.22 49.73 library setup time
+ 49.73 data required time
+-----------------------------------------------------------------------------
+ 49.73 data required time
+ -55.43 data arrival time
+-----------------------------------------------------------------------------
+ -5.70 slack (VIOLATED)
+
+
+Startpoint: _43085_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: _43007_ (rising edge-triggered flip-flop clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 5.23 5.23 clock network delay (propagated)
+ 0.13 0.00 5.23 ^ _43085_/CLK (DFFQ_X1_7T5P0)
+ 4.96 3.82 9.04 v _43085_/Q (DFFQ_X1_7T5P0)
+ 10 0.52 core.VexRiscv.CsrPlugin_exceptionPendings_3 (net)
+ 4.96 0.02 9.06 v _22139_/A4 (NOR4_X1_7T5P0)
+ 1.62 1.12 10.18 ^ _22139_/ZN (NOR4_X1_7T5P0)
+ 1 0.01 _04815_ (net)
+ 1.62 0.00 10.18 ^ _22140_/A4 (AND4_X1_7T5P0)
+ 3.90 2.84 13.02 ^ _22140_/Z (AND4_X1_7T5P0)
+ 10 0.24 _04816_ (net)
+ 3.90 0.04 13.06 ^ _22172_/A2 (OR2_X1_7T5P0)
+ 6.86 4.24 17.30 ^ _22172_/Z (OR2_X1_7T5P0)
+ 12 0.43 _04846_ (net)
+ 6.86 0.01 17.31 ^ _26755_/A2 (NOR2_X2_7T5P0)
+ 2.89 1.95 19.25 v _26755_/ZN (NOR2_X2_7T5P0)
+ 14 0.20 _08550_ (net)
+ 2.89 0.00 19.25 v _26756_/A2 (NAND2_X1_7T5P0)
+ 8.32 5.85 25.10 ^ _26756_/ZN (NAND2_X1_7T5P0)
+ 6 0.48 _08551_ (net)
+ 8.32 0.10 25.20 ^ _26763_/A1 (NOR2_X1_7T5P0)
+ 4.06 2.98 28.17 v _26763_/ZN (NOR2_X1_7T5P0)
+ 4 0.16 _08558_ (net)
+ 4.06 0.02 28.19 v _26773_/A1 (NOR3_X1_7T5P0)
+ 17.39 11.14 39.33 ^ _26773_/ZN (NOR3_X1_7T5P0)
+ 6 0.41 _08568_ (net)
+ 17.39 0.07 39.40 ^ _26774_/I (BUF_X1_7T5P0)
+ 10.30 5.99 45.38 ^ _26774_/Z (BUF_X1_7T5P0)
+ 16 0.70 _08569_ (net)
+ 10.30 0.01 45.39 ^ _26881_/I (BUF_X1_7T5P0)
+ 10.14 6.08 51.47 ^ _26881_/Z (BUF_X1_7T5P0)
+ 16 0.66 _08656_ (net)
+ 10.15 0.14 51.61 ^ _28789_/B (AOI21_X1_7T5P0)
+ 2.22 0.45 52.07 v _28789_/ZN (AOI21_X1_7T5P0)
+ 1 0.01 _10116_ (net)
+ 2.22 0.00 52.07 v _28790_/B2 (AOI221_X1_7T5P0)
+ 3.75 2.66 54.73 ^ _28790_/ZN (AOI221_X1_7T5P0)
+ 2 0.08 _10117_ (net)
+ 3.75 0.00 54.73 ^ _28791_/B (AOI21_X1_7T5P0)
+ 1.04 0.41 55.14 v _28791_/ZN (AOI21_X1_7T5P0)
+ 1 0.01 _10118_ (net)
+ 1.04 0.00 55.14 v _28792_/I (CLKINV_X1_7T5P0)
+ 0.30 0.28 55.42 ^ _28792_/ZN (CLKINV_X1_7T5P0)
+ 1 0.01 _01200_ (net)
+ 0.30 0.00 55.42 ^ _43007_/D (DFFQ_X1_7T5P0)
+ 55.42 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 4.89 49.89 clock network delay (propagated)
+ -0.25 49.64 clock uncertainty
+ 0.36 50.00 clock reconvergence pessimism
+ 50.00 ^ _43007_/CLK (DFFQ_X1_7T5P0)
+ -0.23 49.77 library setup time
+ 49.77 data required time
+-----------------------------------------------------------------------------
+ 49.77 data required time
+ -55.42 data arrival time
+-----------------------------------------------------------------------------
+ -5.65 slack (VIOLATED)
+
+
+report_check_types -max_slew -max_capacitance -max_fanout -violators
+max slew
+
+Pin Limit Slew Slack
+------------------------------------------------------------
+ANTENNA__22798__A3/I 4.00 26.17 -22.17 (VIOLATED)
+_22798_/A3 4.00 26.17 -22.17 (VIOLATED)
+_22796_/ZN 4.00 26.16 -22.16 (VIOLATED)
+ANTENNA__22654__A2/I 4.00 21.53 -17.53 (VIOLATED)
+_22654_/A2 4.00 21.53 -17.53 (VIOLATED)
+_22652_/ZN 4.00 21.53 -17.53 (VIOLATED)
+ANTENNA__39746__I/I 4.00 20.80 -16.80 (VIOLATED)
+ANTENNA__39764__I/I 4.00 20.80 -16.80 (VIOLATED)
+_39746_/I 4.00 20.80 -16.80 (VIOLATED)
+_39764_/I 4.00 20.80 -16.80 (VIOLATED)
+ANTENNA__39728__I/I 4.00 20.80 -16.80 (VIOLATED)
+_39728_/I 4.00 20.80 -16.80 (VIOLATED)
+ANTENNA__39709__I/I 4.00 20.79 -16.79 (VIOLATED)
+_39708_/ZN 4.00 20.79 -16.79 (VIOLATED)
+_39709_/I 4.00 20.79 -16.79 (VIOLATED)
+ANTENNA__31111__A1/I 4.00 20.26 -16.26 (VIOLATED)
+ANTENNA__30469__I1/I 4.00 20.26 -16.26 (VIOLATED)
+_30469_/I1 4.00 20.26 -16.26 (VIOLATED)
+_31111_/A1 4.00 20.26 -16.26 (VIOLATED)
+ANTENNA__32911__A2/I 4.00 20.26 -16.26 (VIOLATED)
+_30468_/ZN 4.00 20.26 -16.26 (VIOLATED)
+_32911_/A2 4.00 20.26 -16.26 (VIOLATED)
+_32807_/A2 4.00 20.07 -16.07 (VIOLATED)
+ANTENNA__32807__A2/I 4.00 20.07 -16.07 (VIOLATED)
+_32806_/ZN 4.00 20.07 -16.07 (VIOLATED)
+ANTENNA__22707__A2/I 4.00 19.25 -15.25 (VIOLATED)
+_22707_/A2 4.00 19.25 -15.25 (VIOLATED)
+_22705_/ZN 4.00 19.24 -15.24 (VIOLATED)
+ANTENNA__31630__A2/I 4.00 18.44 -14.44 (VIOLATED)
+ANTENNA__31891__I/I 4.00 18.44 -14.44 (VIOLATED)
+ANTENNA__39457__A3/I 4.00 18.44 -14.44 (VIOLATED)
+_31630_/A2 4.00 18.44 -14.44 (VIOLATED)
+_31891_/I 4.00 18.44 -14.44 (VIOLATED)
+_39457_/A3 4.00 18.44 -14.44 (VIOLATED)
+_31627_/ZN 4.00 18.43 -14.43 (VIOLATED)
+ANTENNA__39745__I/I 4.00 17.87 -13.87 (VIOLATED)
+ANTENNA__39763__I/I 4.00 17.87 -13.87 (VIOLATED)
+_39745_/I 4.00 17.87 -13.87 (VIOLATED)
+_39763_/I 4.00 17.87 -13.87 (VIOLATED)
+ANTENNA__39727__I/I 4.00 17.87 -13.87 (VIOLATED)
+_39727_/I 4.00 17.87 -13.87 (VIOLATED)
+ANTENNA__39461__I/I 4.00 17.86 -13.86 (VIOLATED)
+_39460_/ZN 4.00 17.86 -13.86 (VIOLATED)
+_39461_/I 4.00 17.86 -13.86 (VIOLATED)
+ANTENNA__22742__A3/I 4.00 17.54 -13.54 (VIOLATED)
+_22742_/A3 4.00 17.54 -13.54 (VIOLATED)
+_22740_/ZN 4.00 17.54 -13.54 (VIOLATED)
+ANTENNA__26797__I/I 4.00 17.39 -13.39 (VIOLATED)
+ANTENNA__26810__I/I 4.00 17.39 -13.39 (VIOLATED)
+_26797_/I 4.00 17.39 -13.39 (VIOLATED)
+_26810_/I 4.00 17.39 -13.39 (VIOLATED)
+ANTENNA__26774__I/I 4.00 17.39 -13.39 (VIOLATED)
+_26774_/I 4.00 17.39 -13.39 (VIOLATED)
+_26773_/ZN 4.00 17.39 -13.39 (VIOLATED)
+_22766_/A2 4.00 17.29 -13.29 (VIOLATED)
+ANTENNA__22766__A2/I 4.00 17.29 -13.29 (VIOLATED)
+_22762_/ZN 4.00 17.28 -13.28 (VIOLATED)
+ANTENNA__24371__I/I 4.00 16.73 -12.73 (VIOLATED)
+_24371_/I 4.00 16.73 -12.73 (VIOLATED)
+_24370_/ZN 4.00 16.72 -12.72 (VIOLATED)
+ANTENNA__21141__A3/I 4.00 15.90 -11.90 (VIOLATED)
+ANTENNA__29325__A3/I 4.00 15.90 -11.90 (VIOLATED)
+ANTENNA__31124__A2/I 4.00 15.90 -11.90 (VIOLATED)
+_21141_/A3 4.00 15.90 -11.90 (VIOLATED)
+_29325_/A3 4.00 15.90 -11.90 (VIOLATED)
+_31124_/A2 4.00 15.90 -11.90 (VIOLATED)
+_21140_/ZN 4.00 15.90 -11.90 (VIOLATED)
+ANTENNA__34394__C/I 4.00 15.77 -11.77 (VIOLATED)
+ANTENNA__32773__C/I 4.00 15.77 -11.77 (VIOLATED)
+_32773_/C 4.00 15.77 -11.77 (VIOLATED)
+_34394_/C 4.00 15.77 -11.77 (VIOLATED)
+ANTENNA__34411__C/I 4.00 15.77 -11.77 (VIOLATED)
+_34411_/C 4.00 15.77 -11.77 (VIOLATED)
+_28548_/C 4.00 15.74 -11.74 (VIOLATED)
+_28545_/C 4.00 15.74 -11.74 (VIOLATED)
+_28542_/C 4.00 15.74 -11.74 (VIOLATED)
+_28539_/C 4.00 15.74 -11.74 (VIOLATED)
+ANTENNA__28545__C/I 4.00 15.74 -11.74 (VIOLATED)
+ANTENNA__28548__C/I 4.00 15.74 -11.74 (VIOLATED)
+ANTENNA__28542__C/I 4.00 15.74 -11.74 (VIOLATED)
+ANTENNA__28539__C/I 4.00 15.74 -11.74 (VIOLATED)
+ANTENNA__35965__C/I 4.00 15.74 -11.74 (VIOLATED)
+_35965_/C 4.00 15.74 -11.74 (VIOLATED)
+_28538_/Z 4.00 15.74 -11.74 (VIOLATED)
+ANTENNA_output394_I/I 4.00 15.71 -11.71 (VIOLATED)
+output394/I 4.00 15.71 -11.71 (VIOLATED)
+ANTENNA__39775__A1/I 4.00 15.71 -11.71 (VIOLATED)
+_39775_/A1 4.00 15.71 -11.71 (VIOLATED)
+ANTENNA_core.sram.ram512x32.RAM02_D[7]/I 4.00 15.69 -11.69 (VIOLATED)
+ANTENNA__27556__A2/I 4.00 15.69 -11.69 (VIOLATED)
+_27556_/A2 4.00 15.69 -11.69 (VIOLATED)
+_20875_/Z 4.00 15.69 -11.69 (VIOLATED)
+ANTENNA__22608__A2/I 4.00 15.17 -11.17 (VIOLATED)
+_22608_/A2 4.00 15.17 -11.17 (VIOLATED)
+_22607_/ZN 4.00 15.16 -11.16 (VIOLATED)
+ANTENNA__28700__B/I 4.00 15.07 -11.07 (VIOLATED)
+_28700_/B 4.00 15.07 -11.07 (VIOLATED)
+_28699_/ZN 4.00 15.07 -11.07 (VIOLATED)
+ANTENNA__22525__I/I 4.00 15.07 -11.07 (VIOLATED)
+_22525_/I 4.00 15.07 -11.07 (VIOLATED)
+_22524_/ZN 4.00 15.07 -11.07 (VIOLATED)
+ANTENNA__31912__B2/I 4.00 14.85 -10.85 (VIOLATED)
+_31912_/B2 4.00 14.85 -10.85 (VIOLATED)
+_31911_/ZN 4.00 14.85 -10.85 (VIOLATED)
+ANTENNA__22754__A3/I 4.00 14.80 -10.80 (VIOLATED)
+_22754_/A3 4.00 14.80 -10.80 (VIOLATED)
+_22752_/ZN 4.00 14.80 -10.80 (VIOLATED)
+_22644_/A2 4.00 14.78 -10.78 (VIOLATED)
+ANTENNA__22644__A2/I 4.00 14.78 -10.78 (VIOLATED)
+_22642_/ZN 4.00 14.78 -10.78 (VIOLATED)
+_22597_/A2 4.00 14.72 -10.72 (VIOLATED)
+ANTENNA__22597__A2/I 4.00 14.72 -10.72 (VIOLATED)
+_22596_/ZN 4.00 14.71 -10.71 (VIOLATED)
+_44089_/D 4.00 14.63 -10.63 (VIOLATED)
+ANTENNA__44089__D/I 4.00 14.63 -10.63 (VIOLATED)
+_33048_/ZN 4.00 14.63 -10.63 (VIOLATED)
+ANTENNA__22784__C/I 4.00 14.61 -10.61 (VIOLATED)
+_22784_/C 4.00 14.61 -10.61 (VIOLATED)
+_22783_/ZN 4.00 14.61 -10.61 (VIOLATED)
+ANTENNA__22669__A3/I 4.00 14.49 -10.49 (VIOLATED)
+_22669_/A3 4.00 14.49 -10.49 (VIOLATED)
+_22668_/ZN 4.00 14.48 -10.48 (VIOLATED)
+ANTENNA__34476__A2/I 4.00 14.39 -10.39 (VIOLATED)
+ANTENNA__34719__A1/I 4.00 14.39 -10.39 (VIOLATED)
+_34476_/A2 4.00 14.39 -10.39 (VIOLATED)
+_34719_/A1 4.00 14.39 -10.39 (VIOLATED)
+ANTENNA__34434__A2/I 4.00 14.39 -10.39 (VIOLATED)
+_34433_/ZN 4.00 14.39 -10.39 (VIOLATED)
+_34434_/A2 4.00 14.39 -10.39 (VIOLATED)
+ANTENNA__39463__A1/I 4.00 14.16 -10.16 (VIOLATED)
+ANTENNA__39704__A2/I 4.00 14.16 -10.16 (VIOLATED)
+ANTENNA__39795__A2/I 4.00 14.16 -10.16 (VIOLATED)
+_39463_/A1 4.00 14.16 -10.16 (VIOLATED)
+_39704_/A2 4.00 14.16 -10.16 (VIOLATED)
+_39795_/A2 4.00 14.16 -10.16 (VIOLATED)
+_39457_/ZN 4.00 14.14 -10.14 (VIOLATED)
+_24940_/A2 4.00 14.08 -10.08 (VIOLATED)
+_25081_/I 4.00 14.08 -10.08 (VIOLATED)
+ANTENNA__25081__I/I 4.00 14.08 -10.08 (VIOLATED)
+ANTENNA__24940__A2/I 4.00 14.08 -10.08 (VIOLATED)
+_24939_/ZN 4.00 14.07 -10.07 (VIOLATED)
+_22804_/A2 4.00 14.07 -10.07 (VIOLATED)
+ANTENNA__22804__A2/I 4.00 14.07 -10.07 (VIOLATED)
+_22800_/ZN 4.00 14.06 -10.06 (VIOLATED)
+ANTENNA__22524__A1/I 4.00 14.03 -10.03 (VIOLATED)
+_22524_/A1 4.00 14.01 -10.01 (VIOLATED)
+ANTENNA__34410__A2/I 4.00 14.01 -10.01 (VIOLATED)
+_22522_/ZN 4.00 14.01 -10.01 (VIOLATED)
+_34410_/A2 4.00 14.01 -10.01 (VIOLATED)
+ANTENNA__32830__A2/I 4.00 13.97 -9.97 (VIOLATED)
+_32830_/A2 4.00 13.97 -9.97 (VIOLATED)
+ANTENNA__30599__A2/I 4.00 13.97 -9.97 (VIOLATED)
+_30592_/ZN 4.00 13.97 -9.97 (VIOLATED)
+_30599_/A2 4.00 13.97 -9.97 (VIOLATED)
+ANTENNA__22874__A2/I 4.00 13.79 -9.79 (VIOLATED)
+_22874_/A2 4.00 13.79 -9.79 (VIOLATED)
+_39034_/I 4.00 13.79 -9.79 (VIOLATED)
+ANTENNA__39034__I/I 4.00 13.79 -9.79 (VIOLATED)
+_22873_/ZN 4.00 13.79 -9.79 (VIOLATED)
+ANTENNA__22617__A2/I 4.00 13.72 -9.72 (VIOLATED)
+_22617_/A2 4.00 13.72 -9.72 (VIOLATED)
+_22616_/ZN 4.00 13.71 -9.71 (VIOLATED)
+ANTENNA__24787__A1/I 4.00 13.66 -9.66 (VIOLATED)
+_24787_/A1 4.00 13.66 -9.66 (VIOLATED)
+ANTENNA__24698__A1/I 4.00 13.66 -9.66 (VIOLATED)
+_24698_/A1 4.00 13.66 -9.66 (VIOLATED)
+_24559_/I 4.00 13.66 -9.66 (VIOLATED)
+_29792_/I 4.00 13.66 -9.66 (VIOLATED)
+ANTENNA__24559__I/I 4.00 13.66 -9.66 (VIOLATED)
+ANTENNA__29792__I/I 4.00 13.66 -9.66 (VIOLATED)
+output389/I 4.00 13.64 -9.64 (VIOLATED)
+ANTENNA_output389_I/I 4.00 13.64 -9.64 (VIOLATED)
+ANTENNA__39767__A1/I 4.00 13.64 -9.64 (VIOLATED)
+_39767_/A1 4.00 13.64 -9.64 (VIOLATED)
+ANTENNA_core.sram.ram512x32.RAM02_D[3]/I 4.00 13.62 -9.62 (VIOLATED)
+ANTENNA__27538__A2/I 4.00 13.61 -9.61 (VIOLATED)
+_27538_/A2 4.00 13.61 -9.61 (VIOLATED)
+_20883_/Z 4.00 13.61 -9.61 (VIOLATED)
+_43682_/Q 4.00 13.60 -9.60 (VIOLATED)
+ANTENNA__22635__B/I 4.00 13.50 -9.50 (VIOLATED)
+_22635_/B 4.00 13.50 -9.50 (VIOLATED)
+_22633_/ZN 4.00 13.50 -9.50 (VIOLATED)
+ANTENNA__24518__I/I 4.00 13.31 -9.31 (VIOLATED)
+ANTENNA__29754__I/I 4.00 13.31 -9.31 (VIOLATED)
+_24518_/I 4.00 13.31 -9.31 (VIOLATED)
+_29754_/I 4.00 13.31 -9.31 (VIOLATED)
+_24659_/A1 4.00 13.31 -9.31 (VIOLATED)
+ANTENNA__24659__A1/I 4.00 13.31 -9.31 (VIOLATED)
+_43671_/Q 4.00 13.29 -9.29 (VIOLATED)
+ANTENNA__22677__A2/I 4.00 13.23 -9.23 (VIOLATED)
+_22677_/A2 4.00 13.23 -9.23 (VIOLATED)
+_22675_/ZN 4.00 13.23 -9.23 (VIOLATED)
+ANTENNA__24537__I/I 4.00 13.08 -9.08 (VIOLATED)
+ANTENNA__29770__I/I 4.00 13.08 -9.08 (VIOLATED)
+_24537_/I 4.00 13.08 -9.08 (VIOLATED)
+_29770_/I 4.00 13.08 -9.08 (VIOLATED)
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+_35119_/ZN 0.12 0.13 -0.00 (VIOLATED)
+_35386_/ZN 0.16 0.17 -0.00 (VIOLATED)
+_43516_/Q 0.24 0.24 -0.00 (VIOLATED)
+_21189_/ZN 0.22 0.22 -0.00 (VIOLATED)
+_35454_/ZN 0.16 0.17 -0.00 (VIOLATED)
+_30474_/Z 0.24 0.24 -0.00 (VIOLATED)
+_22140_/Z 0.24 0.24 -0.00 (VIOLATED)
+_35429_/ZN 0.16 0.17 -0.00 (VIOLATED)
+_35477_/ZN 0.16 0.17 -0.00 (VIOLATED)
+_22970_/ZN 0.07 0.08 -0.00 (VIOLATED)
+_44281_/Q 0.24 0.24 -0.00 (VIOLATED)
+_28556_/Z 0.24 0.24 -0.00 (VIOLATED)
+_35280_/ZN 0.10 0.10 -0.00 (VIOLATED)
+_32072_/Z 0.24 0.24 -0.00 (VIOLATED)
+_28081_/ZN 0.25 0.25 -0.00 (VIOLATED)
+_31119_/Z 0.48 0.48 -0.00 (VIOLATED)
+_31125_/Z 0.48 0.48 -0.00 (VIOLATED)
+_35358_/ZN 0.16 0.16 -0.00 (VIOLATED)
+_21552_/ZN 0.08 0.08 -0.00 (VIOLATED)
+_42777_/Q 0.24 0.24 -0.00 (VIOLATED)
+_23984_/ZN 0.08 0.08 -0.00 (VIOLATED)
+_35371_/ZN 0.10 0.10 -0.00 (VIOLATED)
+_45154_/Q 0.24 0.24 -0.00 (VIOLATED)
+_22612_/ZN 0.08 0.08 -0.00 (VIOLATED)
+
+report_checks -unconstrained -fields {slew cap input nets fanout} -format full_clock_expanded
+Startpoint: mprj_ack_i (input port clocked by core_clk)
+Endpoint: _44447_ (rising edge-triggered flip-flop clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 9.00 9.00 ^ input external delay
+ 0.16 0.07 9.07 ^ mprj_ack_i (in)
+ 2 0.01 mprj_ack_i (net)
+ 0.16 0.00 9.07 ^ input108/I (CLKBUF_X1_7T5P0)
+ 9.02 5.54 14.61 ^ input108/Z (CLKBUF_X1_7T5P0)
+ 2 0.56 net108 (net)
+ 9.04 0.23 14.84 ^ _21137_/A3 (NOR4_X2_7T5P0)
+ 2.43 0.28 15.12 v _21137_/ZN (NOR4_X2_7T5P0)
+ 1 0.02 _20349_ (net)
+ 2.43 0.00 15.12 v _21138_/A4 (NAND4_X4_7T5P0)
+ 1.80 1.78 16.90 ^ _21138_/ZN (NAND4_X4_7T5P0)
+ 10 0.23 _20350_ (net)
+ 1.80 0.01 16.91 ^ _21139_/A2 (NAND2_X1_7T5P0)
+ 1.00 0.69 17.60 v _21139_/ZN (NAND2_X1_7T5P0)
+ 4 0.05 _20351_ (net)
+ 1.00 0.00 17.61 v _21140_/A3 (NOR3_X2_7T5P0)
+ 15.90 9.51 27.12 ^ _21140_/ZN (NOR3_X2_7T5P0)
+ 6 0.74 _20352_ (net)
+ 15.90 0.09 27.21 ^ _21141_/A3 (OR3_X1_7T5P0)
+ 0.62 -0.94 26.28 ^ _21141_/Z (OR3_X1_7T5P0)
+ 2 0.02 _20353_ (net)
+ 0.62 0.00 26.28 ^ _21142_/A2 (NAND2_X2_7T5P0)
+ 1.66 0.81 27.08 v _21142_/ZN (NAND2_X2_7T5P0)
+ 14 0.15 _20354_ (net)
+ 1.66 0.01 27.09 v _21218_/A1 (OR2_X1_7T5P0)
+ 3.05 2.88 29.97 v _21218_/Z (OR2_X1_7T5P0)
+ 8 0.32 _20430_ (net)
+ 3.06 0.07 30.04 v _21328_/A1 (OR3_X1_7T5P0)
+ 1.04 2.39 32.43 v _21328_/Z (OR3_X1_7T5P0)
+ 6 0.09 _20540_ (net)
+ 1.04 0.01 32.44 v _21329_/I (CLKBUF_X2_7T5P0)
+ 0.52 0.74 33.18 v _21329_/Z (CLKBUF_X2_7T5P0)
+ 8 0.06 _20541_ (net)
+ 0.52 0.00 33.19 v _21336_/I (CLKBUF_X2_7T5P0)
+ 1.94 1.55 34.74 v _21336_/Z (CLKBUF_X2_7T5P0)
+ 16 0.25 _20548_ (net)
+ 1.95 0.02 34.76 v _26778_/A1 (NOR2_X2_7T5P0)
+ 12.01 7.55 42.31 ^ _26778_/ZN (NOR2_X2_7T5P0)
+ 14 0.83 _08573_ (net)
+ 12.03 0.25 42.56 ^ _34438_/I (CLKBUF_X2_7T5P0)
+ 5.26 4.17 46.72 ^ _34438_/Z (CLKBUF_X2_7T5P0)
+ 16 0.69 _14448_ (net)
+ 5.26 0.01 46.73 ^ _34473_/A1 (NAND4_X1_7T5P0)
+ 11.30 8.29 55.02 v _34473_/ZN (NAND4_X1_7T5P0)
+ 2 0.46 _14483_ (net)
+ 11.30 0.11 55.14 v _34474_/B (OAI21_X1_7T5P0)
+ 2.03 2.49 57.62 ^ _34474_/ZN (OAI21_X1_7T5P0)
+ 1 0.01 _14484_ (net)
+ 2.03 0.00 57.62 ^ _34475_/I (CLKBUF_X1_7T5P0)
+ 0.16 0.39 58.01 ^ _34475_/Z (CLKBUF_X1_7T5P0)
+ 1 0.00 _02517_ (net)
+ 0.16 0.00 58.01 ^ _44447_/D (DFFQ_X1_7T5P0)
+ 58.01 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock source latency
+ 0.66 0.36 45.36 ^ core_clk (in)
+ 2 0.16 core_clk (net)
+ 0.66 0.00 45.36 ^ clkbuf_0_core_clk/I (CLKBUF_X16_7T5P0)
+ 0.13 0.33 45.69 ^ clkbuf_0_core_clk/Z (CLKBUF_X16_7T5P0)
+ 2 0.05 clknet_0_core_clk (net)
+ 0.13 0.00 45.69 ^ clkbuf_1_1_0_core_clk/I (CLKBUF_X8_7T5P0)
+ 0.95 0.68 46.37 ^ clkbuf_1_1_0_core_clk/Z (CLKBUF_X8_7T5P0)
+ 4 0.47 clknet_1_1_0_core_clk (net)
+ 0.96 0.07 46.43 ^ clkbuf_2_2_0_core_clk/I (CLKBUF_X8_7T5P0)
+ 0.14 0.36 46.80 ^ clkbuf_2_2_0_core_clk/Z (CLKBUF_X8_7T5P0)
+ 1 0.03 clknet_2_2_0_core_clk (net)
+ 0.14 0.00 46.80 ^ clkbuf_2_2_1_core_clk/I (CLKBUF_X8_7T5P0)
+ 0.26 0.33 47.12 ^ clkbuf_2_2_1_core_clk/Z (CLKBUF_X8_7T5P0)
+ 4 0.11 clknet_2_2_1_core_clk (net)
+ 0.26 0.00 47.13 ^ clkbuf_3_4_0_core_clk/I (CLKBUF_X8_7T5P0)
+ 0.11 0.25 47.38 ^ clkbuf_3_4_0_core_clk/Z (CLKBUF_X8_7T5P0)
+ 1 0.02 clknet_3_4_0_core_clk (net)
+ 0.11 0.00 47.38 ^ clkbuf_3_4_1_core_clk/I (CLKBUF_X8_7T5P0)
+ 0.68 0.54 47.92 ^ clkbuf_3_4_1_core_clk/Z (CLKBUF_X8_7T5P0)
+ 4 0.33 clknet_3_4_1_core_clk (net)
+ 0.69 0.05 47.97 ^ clkbuf_4_8_0_core_clk/I (CLKBUF_X8_7T5P0)
+ 0.27 0.42 48.39 ^ clkbuf_4_8_0_core_clk/Z (CLKBUF_X8_7T5P0)
+ 4 0.11 clknet_4_8_0_core_clk (net)
+ 0.27 0.01 48.40 ^ clkbuf_5_16_0_core_clk/I (CLKBUF_X8_7T5P0)
+ 0.30 0.38 48.78 ^ clkbuf_5_16_0_core_clk/Z (CLKBUF_X8_7T5P0)
+ 4 0.13 clknet_5_16_0_core_clk (net)
+ 0.30 0.01 48.79 ^ clkbuf_6_32_0_core_clk/I (CLKBUF_X8_7T5P0)
+ 0.68 0.59 49.38 ^ clkbuf_6_32_0_core_clk/Z (CLKBUF_X8_7T5P0)
+ 14 0.32 clknet_6_32_0_core_clk (net)
+ 0.68 0.01 49.39 ^ clkbuf_leaf_439_core_clk/I (CLKBUF_X16_7T5P0)
+ 0.16 0.36 49.75 ^ clkbuf_leaf_439_core_clk/Z (CLKBUF_X16_7T5P0)
+ 14 0.09 clknet_leaf_439_core_clk (net)
+ 0.16 0.00 49.75 ^ _44447_/CLK (DFFQ_X1_7T5P0)
+ -0.25 49.50 clock uncertainty
+ 0.00 49.50 clock reconvergence pessimism
+ -0.21 49.29 library setup time
+ 49.29 data required time
+-----------------------------------------------------------------------------
+ 49.29 data required time
+ -58.01 data arrival time
+-----------------------------------------------------------------------------
+ -8.72 slack (VIOLATED)
+
+
+report_checks -to _b053240900000000_p_Port _8054240900000000_p_Port _5055240900000000_p_Port _2056240900000000_p_Port _4053240900000000_p_Port _d058240900000000_p_Port _a059240900000000_p_Port _405b240900000000_p_Port _105c240900000000_p_Port _f056240900000000_p_Port _005f240900000000_p_Port _a060240900000000_p_Port _7061240900000000_p_Port _1063240900000000_p_Port _e063240900000000_p_Port _b064240900000000_p_Port _8065240900000000_p_Port _5066240900000000_p_Port _f067240900000000_p_Port _c068240900000000_p_Port _606a240900000000_p_Port _b05d240900000000_p_Port _206d240900000000_p_Port _d06d240900000000_p_Port _a06e240900000000_p_Port _4070240900000000_p_Port _1071240900000000_p_Port _e071240900000000_p_Port _b072240900000000_p_Port _5074240900000000_p_Port _2075240900000000_p_Port _f075240900000000_p_Port _c076240900000000_p_Port _c095240900000000_p_Port _9096240900000000_p_Port _6097240900000000_p_Port _f097240900000000_p_Port _8098240900000000_p_Port _8099240900000000_p_Port _309a240900000000_p_Port _e09a240900000000_p_Port _909b240900000000_p_Port _3099240900000000_p_Port _309d240900000000_p_Port _e09d240900000000_p_Port _909e240900000000_p_Port _409f240900000000_p_Port _f09f240900000000_p_Port _a0a0240900000000_p_Port _50a1240900000000_p_Port _409c240900000000_p_Port _50a3240900000000_p_Port _e0a3240900000000_p_Port _90a4240900000000_p_Port _40a5240900000000_p_Port _f0a5240900000000_p_Port _a0a6240900000000_p_Port _50a7240900000000_p_Port _00a8240900000000_p_Port _b0a8240900000000_p_Port _60a9240900000000_p_Port _10aa240900000000_p_Port _c0aa240900000000_p_Port _70ab240900000000_p_Port _20ac240900000000_p_Port _d0ac240900000000_p_Port _00a2240900000000_p_Port _b0a2240900000000_p_Port _f0af240900000000_p_Port _a0b0240900000000_p_Port _50b1240900000000_p_Port _00b2240900000000_p_Port _b0b2240900000000_p_Port _60b3240900000000_p_Port _10b4240900000000_p_Port _c0b4240900000000_p_Port _70b5240900000000_p_Port _20b6240900000000_p_Port _d0b6240900000000_p_Port _80b7240900000000_p_Port _30b8240900000000_p_Port _e0b8240900000000_p_Port _90b9240900000000_p_Port _40ba240900000000_p_Port _f0ba240900000000_p_Port _a0bb240900000000_p_Port _50bc240900000000_p_Port _00bd240900000000_p_Port _b0bd240900000000_p_Port _60be240900000000_p_Port _10bf240900000000_p_Port _c0bf240900000000_p_Port _70c0240900000000_p_Port _20c1240900000000_p_Port _d0c1240900000000_p_Port _80c2240900000000_p_Port _30c3240900000000_p_Port _e0f3240900000000_p_Port _b0f4240900000000_p_Port _80f5240900000000_p_Port _10f6240900000000_p_Port _a0f6240900000000_p_Port _a0f7240900000000_p_Port _50f8240900000000_p_Port _00f9240900000000_p_Port _b0f9240900000000_p_Port _50f7240900000000_p_Port _50fb240900000000_p_Port _00fc240900000000_p_Port _b0fc240900000000_p_Port _60fd240900000000_p_Port _10fe240900000000_p_Port _c0fe240900000000_p_Port _70ff240900000000_p_Port _60fa240900000000_p_Port _7001250900000000_p_Port _0002250900000000_p_Port _b002250900000000_p_Port _6003250900000000_p_Port _1004250900000000_p_Port _c004250900000000_p_Port _7005250900000000_p_Port _2006250900000000_p_Port _d006250900000000_p_Port _8007250900000000_p_Port _3008250900000000_p_Port _e008250900000000_p_Port _9009250900000000_p_Port _400a250900000000_p_Port _f00a250900000000_p_Port _2000250900000000_p_Port _d000250900000000_p_Port _100e250900000000_p_Port _c00e250900000000_p_Port _700f250900000000_p_Port _2010250900000000_p_Port _d010250900000000_p_Port _8011250900000000_p_Port _3012250900000000_p_Port _e012250900000000_p_Port _9013250900000000_p_Port _4014250900000000_p_Port _f014250900000000_p_Port _a015250900000000_p_Port _5016250900000000_p_Port _0017250900000000_p_Port _b017250900000000_p_Port _6018250900000000_p_Port _1019250900000000_p_Port _c019250900000000_p_Port _701a250900000000_p_Port _201b250900000000_p_Port _d01b250900000000_p_Port _801c250900000000_p_Port _301d250900000000_p_Port _e01d250900000000_p_Port _901e250900000000_p_Port _401f250900000000_p_Port _f01f250900000000_p_Port _a020250900000000_p_Port _5021250900000000_p_Port _f022250900000000_p_Port _c023250900000000_p_Port _9024250900000000_p_Port _2025250900000000_p_Port _b025250900000000_p_Port _b026250900000000_p_Port _6027250900000000_p_Port _1028250900000000_p_Port _c028250900000000_p_Port _6026250900000000_p_Port _602a250900000000_p_Port _102b250900000000_p_Port _c02b250900000000_p_Port _702c250900000000_p_Port _202d250900000000_p_Port _d02d250900000000_p_Port _802e250900000000_p_Port _7029250900000000_p_Port _8030250900000000_p_Port _1031250900000000_p_Port _c031250900000000_p_Port _7032250900000000_p_Port _2033250900000000_p_Port _d033250900000000_p_Port _8034250900000000_p_Port _3035250900000000_p_Port _e035250900000000_p_Port _9036250900000000_p_Port _4037250900000000_p_Port _f037250900000000_p_Port _a038250900000000_p_Port _5039250900000000_p_Port _003a250900000000_p_Port _302f250900000000_p_Port _e02f250900000000_p_Port _203d250900000000_p_Port _d03d250900000000_p_Port _803e250900000000_p_Port _303f250900000000_p_Port _e03f250900000000_p_Port _9040250900000000_p_Port _4041250900000000_p_Port _f041250900000000_p_Port _a042250900000000_p_Port _5043250900000000_p_Port _0044250900000000_p_Port _b044250900000000_p_Port _6045250900000000_p_Port _1046250900000000_p_Port _c046250900000000_p_Port _7047250900000000_p_Port _2048250900000000_p_Port _d048250900000000_p_Port _8049250900000000_p_Port _304a250900000000_p_Port _e04a250900000000_p_Port _904b250900000000_p_Port _404c250900000000_p_Port _f04c250900000000_p_Port _a04d250900000000_p_Port _504e250900000000_p_Port _004f250900000000_p_Port _b04f250900000000_p_Port _6050250900000000_p_Port _0052250900000000_p_Port _d052250900000000_p_Port _a053250900000000_p_Port _3054250900000000_p_Port _c054250900000000_p_Port _c055250900000000_p_Port _7056250900000000_p_Port _2057250900000000_p_Port _d057250900000000_p_Port _7055250900000000_p_Port _7059250900000000_p_Port _205a250900000000_p_Port _d05a250900000000_p_Port _805b250900000000_p_Port _305c250900000000_p_Port _e05c250900000000_p_Port _905d250900000000_p_Port _8058250900000000_p_Port _905f250900000000_p_Port _2060250900000000_p_Port _d060250900000000_p_Port _8061250900000000_p_Port _3062250900000000_p_Port _e062250900000000_p_Port _9063250900000000_p_Port _4064250900000000_p_Port _f064250900000000_p_Port _a065250900000000_p_Port _5066250900000000_p_Port _0067250900000000_p_Port _b067250900000000_p_Port _6068250900000000_p_Port _0082250900000000_p_Port _d082250900000000_p_Port _a083250900000000_p_Port _3084250900000000_p_Port _c084250900000000_p_Port _c085250900000000_p_Port _7086250900000000_p_Port _2087250900000000_p_Port _d087250900000000_p_Port _7085250900000000_p_Port _7089250900000000_p_Port _208a250900000000_p_Port _d08a250900000000_p_Port _808b250900000000_p_Port _308c250900000000_p_Port _e08c250900000000_p_Port _908d250900000000_p_Port _8088250900000000_p_Port _908f250900000000_p_Port _2090250900000000_p_Port _d090250900000000_p_Port _8091250900000000_p_Port _3092250900000000_p_Port _e092250900000000_p_Port _9093250900000000_p_Port _4094250900000000_p_Port _f094250900000000_p_Port _a095250900000000_p_Port _5096250900000000_p_Port _0097250900000000_p_Port _b097250900000000_p_Port _6098250900000000_p_Port _009a250900000000_p_Port _d09a250900000000_p_Port _a09b250900000000_p_Port _309c250900000000_p_Port _b09d250900000000_p_Port _809e250900000000_p_Port _509f250900000000_p_Port -group_count 1000
+Startpoint: _44446_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_cyc_o (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.31 4.31 clock network delay (propagated)
+ 0.00 4.31 ^ _44446_/CLK (DFFQ_X1_7T5P0)
+ 7.18 11.49 ^ _44446_/Q (DFFQ_X1_7T5P0)
+ 9.20 20.68 v _21076_/ZN (CLKINV_X1_7T5P0)
+ 3.91 24.59 ^ _21078_/ZN (OAI21_X1_7T5P0)
+ 0.49 25.08 v _21079_/ZN (AOI22_X1_7T5P0)
+ 0.59 25.68 ^ _21080_/ZN (NOR2_X1_7T5P0)
+ 0.97 26.64 v _21081_/ZN (AOI21_X4_7T5P0)
+ 10.27 36.91 ^ _24370_/ZN (NOR2_X1_7T5P0)
+ 1.07 37.99 ^ _24371_/Z (CLKBUF_X1_7T5P0)
+ 0.43 38.42 ^ output378/Z (CLKBUF_X4_7T5P0)
+ 0.00 38.42 ^ mprj_cyc_o (out)
+ 38.42 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -38.42 data arrival time
+---------------------------------------------------------
+ -2.67 slack (VIOLATED)
+
+
+Startpoint: _44446_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_stb_o (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.31 4.31 clock network delay (propagated)
+ 0.00 4.31 ^ _44446_/CLK (DFFQ_X1_7T5P0)
+ 7.18 11.49 ^ _44446_/Q (DFFQ_X1_7T5P0)
+ 9.20 20.68 v _21076_/ZN (CLKINV_X1_7T5P0)
+ 3.91 24.59 ^ _21078_/ZN (OAI21_X1_7T5P0)
+ 0.49 25.08 v _21079_/ZN (AOI22_X1_7T5P0)
+ 0.59 25.68 ^ _21080_/ZN (NOR2_X1_7T5P0)
+ 0.97 26.64 v _21081_/ZN (AOI21_X4_7T5P0)
+ 5.18 31.82 ^ _21082_/ZN (INV_X2_7T5P0)
+ 1.32 33.14 ^ _46517_/Z (CLKBUF_X1_7T5P0)
+ 0.47 33.62 ^ output415/Z (CLKBUF_X4_7T5P0)
+ 0.00 33.62 ^ mprj_stb_o (out)
+ 33.62 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -33.62 data arrival time
+---------------------------------------------------------
+ 2.13 slack (MET)
+
+
+Startpoint: _44446_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: hk_stb_o (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.31 4.31 clock network delay (propagated)
+ 0.00 4.31 ^ _44446_/CLK (DFFQ_X1_7T5P0)
+ 7.18 11.49 ^ _44446_/Q (DFFQ_X1_7T5P0)
+ 9.20 20.68 v _21076_/ZN (CLKINV_X1_7T5P0)
+ 3.91 24.59 ^ _21078_/ZN (OAI21_X1_7T5P0)
+ 0.49 25.08 v _21079_/ZN (AOI22_X1_7T5P0)
+ 0.59 25.68 ^ _21080_/ZN (NOR2_X1_7T5P0)
+ 0.97 26.64 v _21081_/ZN (AOI21_X4_7T5P0)
+ 5.18 31.82 ^ _21082_/ZN (INV_X2_7T5P0)
+ 1.43 33.25 ^ output155/Z (CLKBUF_X4_7T5P0)
+ 0.00 33.25 ^ hk_stb_o (out)
+ 33.25 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -33.25 data arrival time
+---------------------------------------------------------
+ 2.50 slack (MET)
+
+
+Startpoint: _44446_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: hk_cyc_o (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.31 4.31 clock network delay (propagated)
+ 0.00 4.31 ^ _44446_/CLK (DFFQ_X1_7T5P0)
+ 7.18 11.49 ^ _44446_/Q (DFFQ_X1_7T5P0)
+ 9.20 20.68 v _21076_/ZN (CLKINV_X1_7T5P0)
+ 3.91 24.59 ^ _21078_/ZN (OAI21_X1_7T5P0)
+ 0.49 25.08 v _21079_/ZN (AOI22_X1_7T5P0)
+ 0.59 25.68 ^ _21080_/ZN (NOR2_X1_7T5P0)
+ 0.97 26.64 v _21081_/ZN (AOI21_X4_7T5P0)
+ 4.17 30.82 ^ _24364_/ZN (NOR2_X1_7T5P0)
+ 0.57 31.39 ^ _24365_/Z (CLKBUF_X1_7T5P0)
+ 0.39 31.77 ^ output154/Z (CLKBUF_X4_7T5P0)
+ 0.00 31.78 ^ hk_cyc_o (out)
+ 31.78 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -31.78 data arrival time
+---------------------------------------------------------
+ 3.97 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[23] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.07 12.53 ^ _20873_/Z (CLKBUF_X4_7T5P0)
+ 0.36 12.89 ^ _20874_/Z (MUX2_X2_7T5P0)
+ 9.66 22.55 ^ _20875_/Z (BUF_X1_7T5P0)
+ 1.69 24.24 ^ output394/Z (CLKBUF_X4_7T5P0)
+ 0.00 24.24 ^ mprj_dat_o[23] (out)
+ 24.24 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -24.24 data arrival time
+---------------------------------------------------------
+ 11.51 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[29] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 1.21 13.97 ^ _20844_/Z (CLKBUF_X2_7T5P0)
+ 0.13 14.11 v _20849_/ZN (NAND2_X1_7T5P0)
+ 0.27 14.37 ^ _20850_/ZN (OAI21_X1_7T5P0)
+ 7.91 22.29 ^ _20851_/Z (BUF_X1_7T5P0)
+ 1.59 23.88 ^ output400/Z (CLKBUF_X4_7T5P0)
+ 0.00 23.88 ^ mprj_dat_o[29] (out)
+ 23.88 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -23.88 data arrival time
+---------------------------------------------------------
+ 11.87 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[27] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.65 13.13 ^ _20853_/Z (CLKBUF_X2_7T5P0)
+ 0.19 13.32 v _20858_/ZN (NAND2_X1_7T5P0)
+ 0.36 13.68 ^ _20859_/ZN (OAI21_X1_7T5P0)
+ 7.96 21.64 ^ _20860_/Z (BUF_X1_7T5P0)
+ 1.58 23.22 ^ output398/Z (CLKBUF_X4_7T5P0)
+ 0.00 23.22 ^ mprj_dat_o[27] (out)
+ 23.22 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -23.22 data arrival time
+---------------------------------------------------------
+ 12.53 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[19] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.07 12.53 ^ _20873_/Z (CLKBUF_X4_7T5P0)
+ 0.35 12.87 ^ _20882_/Z (MUX2_X2_7T5P0)
+ 8.32 21.19 ^ _20883_/Z (BUF_X1_7T5P0)
+ 1.65 22.84 ^ output389/Z (CLKBUF_X4_7T5P0)
+ 0.00 22.85 ^ mprj_dat_o[19] (out)
+ 22.85 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -22.85 data arrival time
+---------------------------------------------------------
+ 12.90 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[25] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.65 13.13 ^ _20853_/Z (CLKBUF_X2_7T5P0)
+ 0.28 13.42 v _20866_/ZN (NAND2_X1_7T5P0)
+ 0.52 13.94 ^ _20867_/ZN (OAI21_X1_7T5P0)
+ 7.36 21.30 ^ _20868_/Z (BUF_X1_7T5P0)
+ 1.47 22.77 ^ output396/Z (CLKBUF_X4_7T5P0)
+ 0.00 22.77 ^ mprj_dat_o[25] (out)
+ 22.77 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -22.77 data arrival time
+---------------------------------------------------------
+ 12.98 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[24] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 1.21 13.97 ^ _20844_/Z (CLKBUF_X2_7T5P0)
+ 0.13 14.10 v _20870_/ZN (NAND2_X1_7T5P0)
+ 0.28 14.37 ^ _20871_/ZN (OAI21_X1_7T5P0)
+ 6.95 21.32 ^ _20872_/Z (BUF_X1_7T5P0)
+ 1.40 22.72 ^ output395/Z (CLKBUF_X4_7T5P0)
+ 0.00 22.72 ^ mprj_dat_o[24] (out)
+ 22.72 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -22.72 data arrival time
+---------------------------------------------------------
+ 13.03 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[15] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 0.26 11.72 v _21033_/ZN (AOI22_X1_7T5P0)
+ 0.67 12.38 v _21034_/Z (AND2_X1_7T5P0)
+ 1.64 14.02 v _21035_/Z (CLKBUF_X2_7T5P0)
+ 7.27 21.30 ^ _21036_/ZN (INV_X1_7T5P0)
+ 1.41 22.71 ^ output353/Z (CLKBUF_X4_7T5P0)
+ 0.00 22.71 ^ mprj_adr_o[15] (out)
+ 22.71 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -22.71 data arrival time
+---------------------------------------------------------
+ 13.04 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_we_o (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.63 v _44899_/Q (DFFQ_X1_7T5P0)
+ 0.62 6.25 ^ _20837_/ZN (INV_X1_7T5P0)
+ 0.50 6.75 v _20838_/ZN (NOR2_X4_7T5P0)
+ 0.87 7.61 v _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.30 8.91 v _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.86 9.77 v _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.18 10.95 v _20842_/Z (BUF_X2_7T5P0)
+ 2.18 13.13 ^ _21052_/ZN (AOI22_X4_7T5P0)
+ 7.66 20.79 v _21053_/ZN (CLKINV_X1_7T5P0)
+ 1.84 22.63 v output417/Z (CLKBUF_X4_7T5P0)
+ 0.00 22.63 v mprj_we_o (out)
+ 22.63 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -22.63 data arrival time
+---------------------------------------------------------
+ 13.12 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[30] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 1.21 13.97 ^ _20844_/Z (CLKBUF_X2_7T5P0)
+ 0.15 14.12 v _20845_/ZN (NAND2_X1_7T5P0)
+ 0.27 14.39 ^ _20846_/ZN (OAI21_X1_7T5P0)
+ 6.90 21.30 ^ _20847_/Z (BUF_X1_7T5P0)
+ 1.33 22.63 ^ output402/Z (CLKBUF_X4_7T5P0)
+ 0.00 22.63 ^ mprj_dat_o[30] (out)
+ 22.63 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -22.63 data arrival time
+---------------------------------------------------------
+ 13.12 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[26] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.65 13.13 ^ _20853_/Z (CLKBUF_X2_7T5P0)
+ 0.24 13.37 v _20862_/ZN (NAND2_X1_7T5P0)
+ 0.38 13.76 ^ _20863_/ZN (OAI21_X1_7T5P0)
+ 7.28 21.04 ^ _20864_/Z (BUF_X1_7T5P0)
+ 1.47 22.51 ^ output397/Z (CLKBUF_X4_7T5P0)
+ 0.00 22.51 ^ mprj_dat_o[26] (out)
+ 22.51 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -22.51 data arrival time
+---------------------------------------------------------
+ 13.24 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[31] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.66 13.15 ^ _20832_/Z (CLKBUF_X2_7T5P0)
+ 0.15 13.29 v _20833_/ZN (NAND2_X1_7T5P0)
+ 0.44 13.74 ^ _20834_/ZN (OAI21_X1_7T5P0)
+ 7.22 20.96 ^ _20835_/Z (BUF_X1_7T5P0)
+ 1.46 22.42 ^ output403/Z (CLKBUF_X4_7T5P0)
+ 0.00 22.42 ^ mprj_dat_o[31] (out)
+ 22.42 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -22.42 data arrival time
+---------------------------------------------------------
+ 13.33 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[22] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.07 12.53 ^ _20873_/Z (CLKBUF_X4_7T5P0)
+ 0.37 12.89 ^ _20876_/Z (MUX2_X2_7T5P0)
+ 7.84 20.73 ^ _20877_/Z (BUF_X1_7T5P0)
+ 1.51 22.25 ^ output393/Z (CLKBUF_X4_7T5P0)
+ 0.00 22.25 ^ mprj_dat_o[22] (out)
+ 22.25 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -22.25 data arrival time
+---------------------------------------------------------
+ 13.50 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[17] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.07 12.53 ^ _20873_/Z (CLKBUF_X4_7T5P0)
+ 0.35 12.88 ^ _20886_/Z (MUX2_X2_7T5P0)
+ 7.59 20.47 ^ _20887_/Z (BUF_X1_7T5P0)
+ 1.50 21.97 ^ output387/Z (CLKBUF_X4_7T5P0)
+ 0.00 21.97 ^ mprj_dat_o[17] (out)
+ 21.97 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -21.97 data arrival time
+---------------------------------------------------------
+ 13.78 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[28] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.65 13.13 ^ _20853_/Z (CLKBUF_X2_7T5P0)
+ 0.26 13.39 v _20854_/ZN (NAND2_X1_7T5P0)
+ 0.39 13.78 ^ _20855_/ZN (OAI21_X1_7T5P0)
+ 6.92 20.70 ^ _20856_/Z (BUF_X1_7T5P0)
+ 1.26 21.96 ^ output399/Z (CLKBUF_X4_7T5P0)
+ 0.00 21.96 ^ mprj_dat_o[28] (out)
+ 21.96 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -21.96 data arrival time
+---------------------------------------------------------
+ 13.79 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[21] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.07 12.53 ^ _20873_/Z (CLKBUF_X4_7T5P0)
+ 0.36 12.88 ^ _20878_/Z (MUX2_X2_7T5P0)
+ 7.26 20.14 ^ _20879_/Z (BUF_X1_7T5P0)
+ 1.48 21.63 ^ output392/Z (CLKBUF_X4_7T5P0)
+ 0.00 21.63 ^ mprj_dat_o[21] (out)
+ 21.63 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -21.63 data arrival time
+---------------------------------------------------------
+ 14.12 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[18] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.07 12.53 ^ _20873_/Z (CLKBUF_X4_7T5P0)
+ 0.34 12.87 ^ _20884_/Z (MUX2_X2_7T5P0)
+ 6.96 19.83 ^ _20885_/Z (BUF_X1_7T5P0)
+ 1.40 21.23 ^ output388/Z (CLKBUF_X4_7T5P0)
+ 0.00 21.23 ^ mprj_dat_o[18] (out)
+ 21.23 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -21.23 data arrival time
+---------------------------------------------------------
+ 14.52 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[16] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.07 12.53 ^ _20873_/Z (CLKBUF_X4_7T5P0)
+ 0.34 12.87 ^ _20888_/Z (MUX2_X2_7T5P0)
+ 6.90 19.77 ^ _20889_/Z (BUF_X1_7T5P0)
+ 1.32 21.09 ^ output386/Z (CLKBUF_X4_7T5P0)
+ 0.00 21.09 ^ mprj_dat_o[16] (out)
+ 21.09 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -21.09 data arrival time
+---------------------------------------------------------
+ 14.66 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[20] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.07 12.53 ^ _20873_/Z (CLKBUF_X4_7T5P0)
+ 0.35 12.88 ^ _20880_/Z (MUX2_X2_7T5P0)
+ 6.83 19.71 ^ _20881_/Z (BUF_X1_7T5P0)
+ 1.38 21.09 ^ output391/Z (CLKBUF_X4_7T5P0)
+ 0.00 21.09 ^ mprj_dat_o[20] (out)
+ 21.09 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -21.09 data arrival time
+---------------------------------------------------------
+ 14.66 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[17] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20938_/ZN (NOR2_X1_7T5P0)
+ 0.80 7.11 v _20939_/Z (BUF_X3_7T5P0)
+ 1.31 8.42 v _20940_/Z (CLKBUF_X2_7T5P0)
+ 2.68 11.10 ^ _20984_/ZN (AOI22_X1_7T5P0)
+ 1.38 12.48 ^ _20985_/Z (AND2_X1_7T5P0)
+ 6.83 19.31 v _20986_/ZN (CLKINV_X1_7T5P0)
+ 1.70 21.00 v output355/Z (CLKBUF_X4_7T5P0)
+ 0.00 21.00 v mprj_adr_o[17] (out)
+ 21.00 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -21.00 data arrival time
+---------------------------------------------------------
+ 14.75 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[19] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20938_/ZN (NOR2_X1_7T5P0)
+ 0.80 7.11 v _20939_/Z (BUF_X3_7T5P0)
+ 1.31 8.42 v _20940_/Z (CLKBUF_X2_7T5P0)
+ 0.88 9.31 v _20941_/Z (CLKBUF_X2_7T5P0)
+ 0.33 9.64 ^ _20975_/ZN (NAND2_X1_7T5P0)
+ 2.79 12.43 ^ _20977_/Z (AND2_X1_7T5P0)
+ 6.89 19.32 v _20978_/ZN (CLKINV_X1_7T5P0)
+ 1.66 20.98 v output357/Z (CLKBUF_X4_7T5P0)
+ 0.00 20.98 v mprj_adr_o[19] (out)
+ 20.98 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -20.98 data arrival time
+---------------------------------------------------------
+ 14.77 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_sel_o[3] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 1.21 13.97 ^ _20844_/Z (CLKBUF_X2_7T5P0)
+ 1.05 15.02 v _21054_/ZN (NAND2_X1_7T5P0)
+ 1.07 16.09 v _21071_/Z (OR2_X1_7T5P0)
+ 3.02 19.11 v _21072_/Z (CLKBUF_X2_7T5P0)
+ 1.06 20.17 v output414/Z (CLKBUF_X4_7T5P0)
+ 0.00 20.17 v mprj_sel_o[3] (out)
+ 20.17 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -20.17 data arrival time
+---------------------------------------------------------
+ 15.58 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[1] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 0.45 13.21 v _20934_/Z (MUX2_X2_7T5P0)
+ 4.67 17.88 v _20935_/Z (CLKBUF_X2_7T5P0)
+ 1.50 19.37 v output390/Z (CLKBUF_X4_7T5P0)
+ 0.00 19.38 v mprj_dat_o[1] (out)
+ 19.38 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -19.38 data arrival time
+---------------------------------------------------------
+ 16.37 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[7] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 0.37 13.13 ^ _20922_/Z (MUX2_X2_7T5P0)
+ 4.95 18.08 ^ _20923_/Z (BUF_X2_7T5P0)
+ 1.26 19.34 ^ output408/Z (CLKBUF_X4_7T5P0)
+ 0.00 19.34 ^ mprj_dat_o[7] (out)
+ 19.34 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -19.34 data arrival time
+---------------------------------------------------------
+ 16.41 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[8] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 1.06 13.54 ^ _20831_/Z (CLKBUF_X2_7T5P0)
+ 0.29 13.83 v _20920_/ZN (OAI21_X1_7T5P0)
+ 4.19 18.02 v _20921_/Z (CLKBUF_X2_7T5P0)
+ 1.25 19.27 v output409/Z (CLKBUF_X4_7T5P0)
+ 0.00 19.27 v mprj_dat_o[8] (out)
+ 19.27 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -19.27 data arrival time
+---------------------------------------------------------
+ 16.48 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_sel_o[0] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 1.21 13.97 ^ _20844_/Z (CLKBUF_X2_7T5P0)
+ 1.05 15.02 v _21054_/ZN (NAND2_X1_7T5P0)
+ 1.04 16.06 v _21056_/Z (OR2_X1_7T5P0)
+ 2.22 18.29 v _21057_/Z (CLKBUF_X2_7T5P0)
+ 0.93 19.21 v output411/Z (CLKBUF_X4_7T5P0)
+ 0.00 19.21 v mprj_sel_o[0] (out)
+ 19.21 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -19.21 data arrival time
+---------------------------------------------------------
+ 16.54 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[6] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 0.43 13.19 v _20924_/Z (MUX2_X2_7T5P0)
+ 4.54 17.73 v _20925_/Z (CLKBUF_X2_7T5P0)
+ 1.44 19.17 v output407/Z (CLKBUF_X4_7T5P0)
+ 0.00 19.17 v mprj_dat_o[6] (out)
+ 19.17 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -19.17 data arrival time
+---------------------------------------------------------
+ 16.58 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[5] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 0.43 13.19 v _20926_/Z (MUX2_X2_7T5P0)
+ 4.51 17.70 v _20927_/Z (CLKBUF_X2_7T5P0)
+ 1.47 19.17 v output406/Z (CLKBUF_X4_7T5P0)
+ 0.00 19.17 v mprj_dat_o[5] (out)
+ 19.17 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -19.17 data arrival time
+---------------------------------------------------------
+ 16.58 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_sel_o[1] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 1.21 13.97 ^ _20844_/Z (CLKBUF_X2_7T5P0)
+ 1.05 15.02 v _21054_/ZN (NAND2_X1_7T5P0)
+ 1.05 16.07 v _21061_/Z (OR2_X1_7T5P0)
+ 2.17 18.24 v _21062_/Z (CLKBUF_X2_7T5P0)
+ 0.90 19.14 v output412/Z (CLKBUF_X4_7T5P0)
+ 0.00 19.14 v mprj_sel_o[1] (out)
+ 19.14 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -19.14 data arrival time
+---------------------------------------------------------
+ 16.61 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[2] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 0.44 13.19 v _20932_/Z (MUX2_X2_7T5P0)
+ 4.47 17.67 v _20933_/Z (CLKBUF_X2_7T5P0)
+ 1.44 19.10 v output401/Z (CLKBUF_X4_7T5P0)
+ 0.00 19.11 v mprj_dat_o[2] (out)
+ 19.11 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -19.11 data arrival time
+---------------------------------------------------------
+ 16.64 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[10] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.66 13.15 ^ _20832_/Z (CLKBUF_X2_7T5P0)
+ 0.19 13.34 v _20912_/ZN (OAI21_X1_7T5P0)
+ 4.38 17.72 v _20913_/Z (CLKBUF_X2_7T5P0)
+ 1.35 19.07 v output380/Z (CLKBUF_X4_7T5P0)
+ 0.00 19.07 v mprj_dat_o[10] (out)
+ 19.07 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -19.07 data arrival time
+---------------------------------------------------------
+ 16.68 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_sel_o[2] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 1.21 13.97 ^ _20844_/Z (CLKBUF_X2_7T5P0)
+ 1.05 15.02 v _21054_/ZN (NAND2_X1_7T5P0)
+ 1.08 16.10 v _21067_/Z (OR2_X1_7T5P0)
+ 1.97 18.08 v _21068_/Z (CLKBUF_X2_7T5P0)
+ 0.87 18.95 v output413/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.95 v mprj_sel_o[2] (out)
+ 18.95 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.95 data arrival time
+---------------------------------------------------------
+ 16.80 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[4] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 0.39 13.15 ^ _20928_/Z (MUX2_X2_7T5P0)
+ 4.56 17.71 ^ _20929_/Z (BUF_X2_7T5P0)
+ 1.17 18.87 ^ output405/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.88 ^ mprj_dat_o[4] (out)
+ 18.88 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.88 data arrival time
+---------------------------------------------------------
+ 16.87 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[13] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.65 13.13 ^ _20853_/Z (CLKBUF_X2_7T5P0)
+ 0.29 13.43 v _20899_/ZN (NAND2_X1_7T5P0)
+ 0.42 13.85 ^ _20900_/ZN (OAI21_X1_7T5P0)
+ 3.86 17.71 ^ _20901_/Z (CLKBUF_X2_7T5P0)
+ 1.15 18.86 ^ output383/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.86 ^ mprj_dat_o[13] (out)
+ 18.86 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.86 data arrival time
+---------------------------------------------------------
+ 16.89 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[3] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 1.30 12.76 ^ _20843_/Z (BUF_X3_7T5P0)
+ 0.37 13.12 ^ _20930_/Z (MUX2_X2_7T5P0)
+ 4.58 17.70 ^ _20931_/Z (BUF_X2_7T5P0)
+ 1.10 18.80 ^ output404/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.81 ^ mprj_dat_o[3] (out)
+ 18.81 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.81 data arrival time
+---------------------------------------------------------
+ 16.94 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[9] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.66 13.15 ^ _20832_/Z (CLKBUF_X2_7T5P0)
+ 0.18 13.33 v _20916_/ZN (OAI21_X1_7T5P0)
+ 4.02 17.35 v _20917_/Z (CLKBUF_X2_7T5P0)
+ 1.34 18.69 v output410/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.69 v mprj_dat_o[9] (out)
+ 18.69 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.69 data arrival time
+---------------------------------------------------------
+ 17.06 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[12] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.66 13.15 ^ _20832_/Z (CLKBUF_X2_7T5P0)
+ 0.19 13.34 v _20904_/ZN (OAI21_X1_7T5P0)
+ 3.94 17.28 v _20905_/Z (CLKBUF_X2_7T5P0)
+ 1.39 18.67 v output382/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.67 v mprj_dat_o[12] (out)
+ 18.67 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.67 data arrival time
+---------------------------------------------------------
+ 17.08 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[11] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.65 13.13 ^ _20853_/Z (CLKBUF_X2_7T5P0)
+ 0.41 13.54 v _20907_/ZN (NAND2_X1_7T5P0)
+ 0.50 14.04 ^ _20908_/ZN (OAI21_X1_7T5P0)
+ 3.58 17.63 ^ _20909_/Z (CLKBUF_X2_7T5P0)
+ 1.00 18.63 ^ output381/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.63 ^ mprj_dat_o[11] (out)
+ 18.63 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.63 data arrival time
+---------------------------------------------------------
+ 17.12 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[15] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.65 13.13 ^ _20853_/Z (CLKBUF_X2_7T5P0)
+ 0.30 13.43 v _20891_/ZN (NAND2_X1_7T5P0)
+ 0.43 13.86 ^ _20892_/ZN (OAI21_X1_7T5P0)
+ 3.64 17.49 ^ _20893_/Z (CLKBUF_X2_7T5P0)
+ 1.05 18.55 ^ output385/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.55 ^ mprj_dat_o[15] (out)
+ 18.55 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.55 data arrival time
+---------------------------------------------------------
+ 17.20 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[14] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.86 ^ _44900_/Q (DFFQ_X1_7T5P0)
+ 1.14 7.00 ^ _20825_/Z (BUF_X3_7T5P0)
+ 1.10 8.10 ^ _20826_/Z (CLKBUF_X2_7T5P0)
+ 1.16 9.26 ^ _20827_/Z (BUF_X2_7T5P0)
+ 1.69 10.95 ^ _20828_/Z (BUF_X2_7T5P0)
+ 0.59 11.54 v _20829_/ZN (CLKINV_X1_7T5P0)
+ 0.94 12.49 ^ _20830_/ZN (NAND2_X2_7T5P0)
+ 0.66 13.15 ^ _20832_/Z (CLKBUF_X2_7T5P0)
+ 0.20 13.35 v _20896_/ZN (OAI21_X1_7T5P0)
+ 3.89 17.25 v _20897_/Z (CLKBUF_X2_7T5P0)
+ 1.27 18.52 v output384/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.52 v mprj_dat_o[14] (out)
+ 18.52 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.52 data arrival time
+---------------------------------------------------------
+ 17.23 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_dat_o[0] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.52 11.46 ^ _20842_/Z (BUF_X2_7T5P0)
+ 0.44 11.90 v _20936_/Z (MUX2_X2_7T5P0)
+ 4.97 16.87 v _20937_/Z (CLKBUF_X2_7T5P0)
+ 1.58 18.44 v output379/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.45 v mprj_dat_o[0] (out)
+ 18.45 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.45 data arrival time
+---------------------------------------------------------
+ 17.30 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[13] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.63 v _44899_/Q (DFFQ_X1_7T5P0)
+ 0.62 6.25 ^ _20837_/ZN (INV_X1_7T5P0)
+ 0.50 6.75 v _20838_/ZN (NOR2_X4_7T5P0)
+ 0.87 7.61 v _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.30 8.91 v _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.86 9.77 v _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.40 11.18 ^ _21024_/ZN (NAND2_X1_7T5P0)
+ 1.52 12.69 ^ _21026_/Z (AND2_X2_7T5P0)
+ 4.17 16.86 v _21027_/ZN (CLKINV_X2_7T5P0)
+ 1.42 18.28 v output351/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.28 v mprj_adr_o[13] (out)
+ 18.28 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.28 data arrival time
+---------------------------------------------------------
+ 17.47 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[12] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.63 v _44899_/Q (DFFQ_X1_7T5P0)
+ 0.62 6.25 ^ _20837_/ZN (INV_X1_7T5P0)
+ 0.50 6.75 v _20838_/ZN (NOR2_X4_7T5P0)
+ 0.87 7.61 v _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.30 8.91 v _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.86 9.77 v _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.18 10.95 v _20842_/Z (BUF_X2_7T5P0)
+ 0.68 11.63 ^ _21021_/ZN (AOI22_X1_7T5P0)
+ 1.58 13.21 ^ _21022_/Z (AND2_X2_7T5P0)
+ 3.81 17.02 v _21023_/ZN (CLKINV_X2_7T5P0)
+ 1.23 18.25 v output350/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.25 v mprj_adr_o[12] (out)
+ 18.25 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.25 data arrival time
+---------------------------------------------------------
+ 17.50 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[14] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.63 v _44899_/Q (DFFQ_X1_7T5P0)
+ 0.62 6.25 ^ _20837_/ZN (INV_X1_7T5P0)
+ 0.50 6.75 v _20838_/ZN (NOR2_X4_7T5P0)
+ 0.87 7.61 v _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.30 8.91 v _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.86 9.77 v _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.18 10.95 v _20842_/Z (BUF_X2_7T5P0)
+ 0.62 11.57 ^ _21029_/ZN (AOI22_X1_7T5P0)
+ 1.76 13.34 ^ _21030_/Z (AND2_X2_7T5P0)
+ 3.70 17.04 v _21031_/ZN (CLKINV_X2_7T5P0)
+ 1.19 18.23 v output352/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.23 v mprj_adr_o[14] (out)
+ 18.23 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.23 data arrival time
+---------------------------------------------------------
+ 17.52 slack (MET)
+
+
+Startpoint: _44900_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[28] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _44900_/CLK (DFFQ_X1_7T5P0)
+ 1.01 5.64 v _44900_/Q (DFFQ_X1_7T5P0)
+ 0.67 6.31 ^ _20938_/ZN (NOR2_X1_7T5P0)
+ 0.90 7.21 ^ _20939_/Z (BUF_X3_7T5P0)
+ 1.31 8.52 ^ _20940_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.27 v _20999_/ZN (NAND2_X1_7T5P0)
+ 0.99 10.26 v _21001_/Z (AND2_X1_7T5P0)
+ 6.66 16.93 ^ _21002_/ZN (INV_X1_7T5P0)
+ 1.24 18.17 ^ output366/Z (CLKBUF_X4_7T5P0)
+ 0.00 18.17 ^ mprj_adr_o[28] (out)
+ 18.17 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -18.17 data arrival time
+---------------------------------------------------------
+ 17.58 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[11] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.63 v _44899_/Q (DFFQ_X1_7T5P0)
+ 0.62 6.25 ^ _20837_/ZN (INV_X1_7T5P0)
+ 0.50 6.75 v _20838_/ZN (NOR2_X4_7T5P0)
+ 0.87 7.61 v _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.30 8.91 v _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.86 9.77 v _20841_/Z (CLKBUF_X2_7T5P0)
+ 1.18 10.95 v _20842_/Z (BUF_X2_7T5P0)
+ 0.65 11.60 ^ _21014_/ZN (AOI22_X1_7T5P0)
+ 0.87 12.47 ^ _21015_/Z (AND2_X1_7T5P0)
+ 3.94 16.40 v _21016_/ZN (CLKINV_X2_7T5P0)
+ 1.37 17.77 v output349/Z (CLKBUF_X4_7T5P0)
+ 0.00 17.77 v mprj_adr_o[11] (out)
+ 17.77 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -17.77 data arrival time
+---------------------------------------------------------
+ 17.98 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[5] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.63 v _44899_/Q (DFFQ_X1_7T5P0)
+ 0.62 6.25 ^ _20837_/ZN (INV_X1_7T5P0)
+ 0.50 6.75 v _20838_/ZN (NOR2_X4_7T5P0)
+ 0.87 7.61 v _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.30 8.91 v _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.86 9.77 v _20841_/Z (CLKBUF_X2_7T5P0)
+ 0.30 10.07 ^ _20950_/ZN (NAND2_X1_7T5P0)
+ 2.98 13.05 ^ _20952_/Z (AND2_X1_7T5P0)
+ 1.87 14.92 v _20953_/ZN (INV_X1_7T5P0)
+ 1.63 16.54 v _20954_/Z (BUF_X8_7T5P0)
+ 0.89 17.43 v output373/Z (CLKBUF_X4_7T5P0)
+ 0.00 17.43 v mprj_adr_o[5] (out)
+ 17.43 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -17.43 data arrival time
+---------------------------------------------------------
+ 18.32 slack (MET)
+
+
+Startpoint: _43729_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[20] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.34 4.34 clock network delay (propagated)
+ 0.00 4.34 ^ _43729_/CLK (DFFQ_X1_7T5P0)
+ 1.88 6.21 v _43729_/Q (DFFQ_X1_7T5P0)
+ 0.82 7.03 v _21101_/Z (AND2_X1_7T5P0)
+ 1.31 8.35 ^ _21102_/ZN (AOI221_X4_7T5P0)
+ 7.00 15.35 v _21103_/ZN (CLKINV_X1_7T5P0)
+ 1.81 17.15 v output358/Z (CLKBUF_X4_7T5P0)
+ 0.00 17.15 v mprj_adr_o[20] (out)
+ 17.15 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -17.15 data arrival time
+---------------------------------------------------------
+ 18.60 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[2] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20938_/ZN (NOR2_X1_7T5P0)
+ 0.80 7.11 v _20939_/Z (BUF_X3_7T5P0)
+ 1.31 8.42 v _20940_/Z (CLKBUF_X2_7T5P0)
+ 0.88 9.31 v _20941_/Z (CLKBUF_X2_7T5P0)
+ 1.11 10.41 v _20965_/Z (CLKBUF_X2_7T5P0)
+ 0.60 11.02 ^ _20966_/ZN (NAND2_X1_7T5P0)
+ 2.96 13.97 ^ _20968_/Z (AND2_X1_7T5P0)
+ 0.75 14.72 v _20969_/ZN (CLKINV_X2_7T5P0)
+ 1.33 16.05 v _20970_/Z (CLKBUF_X12_7T5P0)
+ 1.08 17.13 v output368/Z (CLKBUF_X4_7T5P0)
+ 0.00 17.13 v mprj_adr_o[2] (out)
+ 17.13 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -17.13 data arrival time
+---------------------------------------------------------
+ 18.62 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[27] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.63 v _44899_/Q (DFFQ_X1_7T5P0)
+ 0.62 6.25 ^ _20837_/ZN (INV_X1_7T5P0)
+ 0.50 6.75 v _20838_/ZN (NOR2_X4_7T5P0)
+ 0.87 7.61 v _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.97 9.59 ^ _21097_/ZN (AOI222_X2_7T5P0)
+ 5.79 15.38 v _21098_/ZN (CLKINV_X1_7T5P0)
+ 1.47 16.85 v output365/Z (CLKBUF_X4_7T5P0)
+ 0.00 16.85 v mprj_adr_o[27] (out)
+ 16.85 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -16.85 data arrival time
+---------------------------------------------------------
+ 18.90 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[24] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20938_/ZN (NOR2_X1_7T5P0)
+ 0.58 6.88 v _21004_/Z (AND2_X1_7T5P0)
+ 1.59 8.47 ^ _21005_/ZN (AOI221_X4_7T5P0)
+ 6.43 14.90 v _21006_/ZN (CLKINV_X1_7T5P0)
+ 1.54 16.45 v output362/Z (CLKBUF_X4_7T5P0)
+ 0.00 16.45 v mprj_adr_o[24] (out)
+ 16.45 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -16.45 data arrival time
+---------------------------------------------------------
+ 19.30 slack (MET)
+
+
+Startpoint: _45158_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[25] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.37 4.37 clock network delay (propagated)
+ 0.00 4.37 ^ _45158_/CLK (DFFQ_X1_7T5P0)
+ 2.11 6.48 v _45158_/Q (DFFQ_X1_7T5P0)
+ 1.73 8.21 ^ _21011_/ZN (AOI221_X4_7T5P0)
+ 6.55 14.76 v _21012_/ZN (CLKINV_X1_7T5P0)
+ 1.58 16.34 v output363/Z (CLKBUF_X4_7T5P0)
+ 0.00 16.34 v mprj_adr_o[25] (out)
+ 16.34 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -16.34 data arrival time
+---------------------------------------------------------
+ 19.41 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[18] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20938_/ZN (NOR2_X1_7T5P0)
+ 0.80 7.11 v _20939_/Z (BUF_X3_7T5P0)
+ 1.31 8.42 v _20940_/Z (CLKBUF_X2_7T5P0)
+ 2.79 11.22 ^ _20980_/ZN (AOI22_X1_7T5P0)
+ 0.31 11.52 v _20981_/ZN (NAND2_X1_7T5P0)
+ 3.50 15.02 v _20982_/Z (CLKBUF_X2_7T5P0)
+ 1.29 16.31 v output356/Z (CLKBUF_X4_7T5P0)
+ 0.00 16.31 v mprj_adr_o[18] (out)
+ 16.31 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -16.31 data arrival time
+---------------------------------------------------------
+ 19.44 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[23] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20938_/ZN (NOR2_X1_7T5P0)
+ 0.80 7.11 v _20939_/Z (BUF_X3_7T5P0)
+ 1.49 8.60 ^ _21099_/ZN (AOI222_X4_7T5P0)
+ 5.77 14.37 v _21100_/ZN (CLKINV_X1_7T5P0)
+ 1.50 15.87 v output361/Z (CLKBUF_X4_7T5P0)
+ 0.00 15.87 v mprj_adr_o[23] (out)
+ 15.87 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -15.87 data arrival time
+---------------------------------------------------------
+ 19.88 slack (MET)
+
+
+Startpoint: debug_in (input port clocked by core_clk)
+Endpoint: ser_tx (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 9.00 9.00 v input external delay
+ 0.04 9.04 v debug_in (in)
+ 3.00 12.04 v input2/Z (CLKBUF_X1_7T5P0)
+ 2.28 14.32 v _22536_/Z (MUX2_X2_7T5P0)
+ 0.94 15.26 v _22537_/Z (CLKBUF_X1_7T5P0)
+ 0.55 15.82 v output418/Z (CLKBUF_X4_7T5P0)
+ 0.00 15.82 v ser_tx (out)
+ 15.82 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -15.82 data arrival time
+---------------------------------------------------------
+ 19.93 slack (MET)
+
+
+Startpoint: debug_in (input port clocked by core_clk)
+Endpoint: uart_enabled (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 9.00 9.00 v input external delay
+ 0.04 9.04 v debug_in (in)
+ 3.00 12.04 v input2/Z (CLKBUF_X1_7T5P0)
+ 2.81 14.85 v _24388_/Z (OR2_X1_7T5P0)
+ 0.51 15.35 v _24389_/Z (CLKBUF_X1_7T5P0)
+ 0.38 15.73 v output424/Z (CLKBUF_X4_7T5P0)
+ 0.00 15.73 v uart_enabled (out)
+ 15.73 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -15.73 data arrival time
+---------------------------------------------------------
+ 20.02 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[26] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.63 v _44899_/Q (DFFQ_X1_7T5P0)
+ 0.62 6.25 ^ _20837_/ZN (INV_X1_7T5P0)
+ 0.50 6.75 v _20838_/ZN (NOR2_X4_7T5P0)
+ 0.87 7.61 v _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.25 8.87 ^ _21008_/ZN (AOI221_X4_7T5P0)
+ 5.37 14.24 v _21009_/ZN (CLKINV_X1_7T5P0)
+ 1.46 15.70 v output364/Z (CLKBUF_X4_7T5P0)
+ 0.00 15.71 v mprj_adr_o[26] (out)
+ 15.71 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -15.71 data arrival time
+---------------------------------------------------------
+ 20.04 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[30] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.63 v _44899_/Q (DFFQ_X1_7T5P0)
+ 0.62 6.25 ^ _20837_/ZN (INV_X1_7T5P0)
+ 0.50 6.75 v _20838_/ZN (NOR2_X4_7T5P0)
+ 0.87 7.61 v _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.84 9.45 ^ _20994_/ZN (AOI221_X2_7T5P0)
+ 4.92 14.37 v _20995_/ZN (CLKINV_X1_7T5P0)
+ 1.32 15.69 v output369/Z (CLKBUF_X4_7T5P0)
+ 0.00 15.69 v mprj_adr_o[30] (out)
+ 15.69 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -15.69 data arrival time
+---------------------------------------------------------
+ 20.06 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[16] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20938_/ZN (NOR2_X1_7T5P0)
+ 0.80 7.11 v _20939_/Z (BUF_X3_7T5P0)
+ 1.31 8.42 v _20940_/Z (CLKBUF_X2_7T5P0)
+ 2.61 11.04 ^ _20988_/ZN (AOI22_X1_7T5P0)
+ 0.30 11.34 v _20989_/ZN (NAND2_X1_7T5P0)
+ 3.17 14.51 v _20990_/Z (CLKBUF_X2_7T5P0)
+ 1.14 15.65 v output354/Z (CLKBUF_X4_7T5P0)
+ 0.00 15.65 v mprj_adr_o[16] (out)
+ 15.65 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -15.65 data arrival time
+---------------------------------------------------------
+ 20.10 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[31] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.63 v _44899_/Q (DFFQ_X1_7T5P0)
+ 0.62 6.25 ^ _20837_/ZN (INV_X1_7T5P0)
+ 0.50 6.75 v _20838_/ZN (NOR2_X4_7T5P0)
+ 0.87 7.61 v _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.21 8.83 ^ _20991_/ZN (AOI222_X4_7T5P0)
+ 5.41 14.24 v _20992_/ZN (CLKINV_X1_7T5P0)
+ 1.39 15.63 v output370/Z (CLKBUF_X4_7T5P0)
+ 0.00 15.63 v mprj_adr_o[31] (out)
+ 15.63 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -15.63 data arrival time
+---------------------------------------------------------
+ 20.12 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[4] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 0.22 10.15 v _20956_/ZN (AOI22_X1_7T5P0)
+ 0.69 10.84 v _20957_/Z (AND2_X1_7T5P0)
+ 1.42 12.26 v _20958_/Z (CLKBUF_X4_7T5P0)
+ 2.03 14.29 ^ _20959_/ZN (INV_X8_7T5P0)
+ 1.04 15.33 ^ output372/Z (CLKBUF_X4_7T5P0)
+ 0.00 15.33 ^ mprj_adr_o[4] (out)
+ 15.33 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -15.33 data arrival time
+---------------------------------------------------------
+ 20.42 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[29] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 0.54 8.48 v _20997_/ZN (AOI221_X4_7T5P0)
+ 5.69 14.17 ^ _20998_/ZN (INV_X1_7T5P0)
+ 1.11 15.28 ^ output367/Z (CLKBUF_X4_7T5P0)
+ 0.00 15.28 ^ mprj_adr_o[29] (out)
+ 15.28 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -15.28 data arrival time
+---------------------------------------------------------
+ 20.47 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[22] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20938_/ZN (NOR2_X1_7T5P0)
+ 0.80 7.11 v _20939_/Z (BUF_X3_7T5P0)
+ 1.36 8.47 ^ _21104_/ZN (AOI222_X4_7T5P0)
+ 5.39 13.87 v _21105_/ZN (CLKINV_X1_7T5P0)
+ 1.41 15.28 v output360/Z (CLKBUF_X4_7T5P0)
+ 0.00 15.28 v mprj_adr_o[22] (out)
+ 15.28 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -15.28 data arrival time
+---------------------------------------------------------
+ 20.47 slack (MET)
+
+
+Startpoint: _45154_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[21] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _45154_/CLK (DFFQ_X1_7T5P0)
+ 2.16 6.57 v _45154_/Q (DFFQ_X1_7T5P0)
+ 2.00 8.57 ^ _21018_/ZN (AOI221_X4_7T5P0)
+ 4.83 13.39 v _21019_/ZN (CLKINV_X1_7T5P0)
+ 1.28 14.67 v output359/Z (CLKBUF_X4_7T5P0)
+ 0.00 14.67 v mprj_adr_o[21] (out)
+ 14.67 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -14.67 data arrival time
+---------------------------------------------------------
+ 21.08 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[3] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 0.23 10.16 v _20961_/ZN (AOI22_X1_7T5P0)
+ 0.54 10.71 v _20962_/Z (AND2_X1_7T5P0)
+ 0.98 11.69 v _20963_/Z (BUF_X3_7T5P0)
+ 1.82 13.52 ^ _20964_/ZN (INV_X8_7T5P0)
+ 1.03 14.54 ^ output371/Z (CLKBUF_X4_7T5P0)
+ 0.00 14.54 ^ mprj_adr_o[3] (out)
+ 14.54 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -14.54 data arrival time
+---------------------------------------------------------
+ 21.21 slack (MET)
+
+
+Startpoint: _45619_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: flash_csb (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.39 4.39 clock network delay (propagated)
+ 0.00 4.39 ^ _45619_/CLK (DFFQ_X1_7T5P0)
+ 0.91 5.30 v _45619_/Q (DFFQ_X1_7T5P0)
+ 0.71 6.01 ^ _20972_/ZN (NOR3_X1_7T5P0)
+ 0.63 6.64 ^ _20973_/Z (AND2_X1_7T5P0)
+ 6.18 12.82 v _20974_/ZN (CLKINV_X1_7T5P0)
+ 1.71 14.54 v output146/Z (CLKBUF_X4_7T5P0)
+ 0.00 14.54 v flash_csb (out)
+ 14.54 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -14.54 data arrival time
+---------------------------------------------------------
+ 21.21 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[9] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20938_/ZN (NOR2_X1_7T5P0)
+ 0.80 7.11 v _20939_/Z (BUF_X3_7T5P0)
+ 1.31 8.42 v _20940_/Z (CLKBUF_X2_7T5P0)
+ 1.48 9.91 ^ _21042_/ZN (AOI22_X1_7T5P0)
+ 1.43 11.34 ^ _21043_/Z (AND2_X2_7T5P0)
+ 1.34 12.68 v _21044_/ZN (INV_X8_7T5P0)
+ 1.04 13.71 v output377/Z (CLKBUF_X4_7T5P0)
+ 0.00 13.71 v mprj_adr_o[9] (out)
+ 13.71 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -13.71 data arrival time
+---------------------------------------------------------
+ 22.04 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[7] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 0.30 10.24 v _20943_/ZN (AOI22_X1_7T5P0)
+ 0.99 11.22 v _20944_/Z (AND2_X2_7T5P0)
+ 1.44 12.66 ^ _20945_/ZN (INV_X8_7T5P0)
+ 0.89 13.55 ^ output375/Z (CLKBUF_X4_7T5P0)
+ 0.00 13.55 ^ mprj_adr_o[7] (out)
+ 13.55 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -13.55 data arrival time
+---------------------------------------------------------
+ 22.20 slack (MET)
+
+
+Startpoint: _45072_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: debug_oeb (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _45072_/CLK (DFFQ_X1_7T5P0)
+ 7.69 12.10 ^ _45072_/Q (DFFQ_X1_7T5P0)
+ 1.42 13.52 ^ output144/Z (CLKBUF_X4_7T5P0)
+ 0.00 13.52 ^ debug_oeb (out)
+ 13.52 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -13.52 data arrival time
+---------------------------------------------------------
+ 22.23 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[10] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 1.17 10.35 v _21045_/ZN (NAND2_X1_7T5P0)
+ 0.70 11.05 ^ _21047_/ZN (NAND2_X1_7T5P0)
+ 1.26 12.31 ^ _21048_/Z (BUF_X8_7T5P0)
+ 1.08 13.39 ^ output348/Z (CLKBUF_X4_7T5P0)
+ 0.00 13.39 ^ mprj_adr_o[10] (out)
+ 13.39 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -13.39 data arrival time
+---------------------------------------------------------
+ 22.36 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[8] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.76 9.94 ^ _20841_/Z (CLKBUF_X2_7T5P0)
+ 0.33 10.26 v _21038_/ZN (AOI22_X1_7T5P0)
+ 0.70 10.96 ^ _21039_/ZN (NAND2_X1_7T5P0)
+ 1.33 12.29 ^ _21040_/Z (BUF_X8_7T5P0)
+ 1.00 13.29 ^ output376/Z (CLKBUF_X4_7T5P0)
+ 0.00 13.29 ^ mprj_adr_o[8] (out)
+ 13.29 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -13.29 data arrival time
+---------------------------------------------------------
+ 22.46 slack (MET)
+
+
+Startpoint: _45338_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_wb_iena (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _45338_/CLK (DFFQ_X1_7T5P0)
+ 7.24 11.67 ^ _45338_/Q (DFFQ_X1_7T5P0)
+ 1.30 12.96 ^ output416/Z (CLKBUF_X4_7T5P0)
+ 0.00 12.96 ^ mprj_wb_iena (out)
+ 12.96 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -12.96 data arrival time
+---------------------------------------------------------
+ 22.79 slack (MET)
+
+
+Startpoint: _44899_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: mprj_adr_o[6] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.62 4.62 clock network delay (propagated)
+ 0.00 4.62 ^ _44899_/CLK (DFFQ_X1_7T5P0)
+ 1.23 5.85 ^ _44899_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.31 v _20837_/ZN (INV_X1_7T5P0)
+ 0.76 7.07 ^ _20838_/ZN (NOR2_X4_7T5P0)
+ 0.88 7.94 ^ _20839_/Z (CLKBUF_X4_7T5P0)
+ 1.23 9.18 ^ _20840_/Z (CLKBUF_X2_7T5P0)
+ 0.27 9.45 v _20947_/ZN (AOI22_X1_7T5P0)
+ 1.03 10.48 v _20948_/Z (AND2_X2_7T5P0)
+ 1.41 11.89 ^ _20949_/ZN (INV_X8_7T5P0)
+ 0.88 12.77 ^ output374/Z (CLKBUF_X4_7T5P0)
+ 0.00 12.77 ^ mprj_adr_o[6] (out)
+ 12.77 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -12.77 data arrival time
+---------------------------------------------------------
+ 22.98 slack (MET)
+
+
+Startpoint: _45066_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: gpio_outenb_pad (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _45066_/CLK (DFFQ_X1_7T5P0)
+ 1.03 5.44 ^ _45066_/Q (DFFQ_X1_7T5P0)
+ 5.39 10.83 v _24345_/ZN (CLKINV_X1_7T5P0)
+ 1.54 12.37 v output153/Z (CLKBUF_X4_7T5P0)
+ 0.00 12.37 v gpio_outenb_pad (out)
+ 12.37 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -12.37 data arrival time
+---------------------------------------------------------
+ 23.38 slack (MET)
+
+
+Startpoint: _44968_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: spi_enabled (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _44968_/CLK (DFFQ_X1_7T5P0)
+ 6.35 10.78 ^ _44968_/Q (DFFQ_X1_7T5P0)
+ 1.22 11.99 ^ output420/Z (CLKBUF_X4_7T5P0)
+ 0.00 11.99 ^ spi_enabled (out)
+ 11.99 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -11.99 data arrival time
+---------------------------------------------------------
+ 23.76 slack (MET)
+
+
+Startpoint: _44965_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: user_irq_ena[0] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.37 4.37 clock network delay (propagated)
+ 0.00 4.37 ^ _44965_/CLK (DFFQ_X1_7T5P0)
+ 6.35 10.72 ^ _44965_/Q (DFFQ_X1_7T5P0)
+ 1.13 11.84 ^ output425/Z (CLKBUF_X4_7T5P0)
+ 0.00 11.85 ^ user_irq_ena[0] (out)
+ 11.85 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -11.85 data arrival time
+---------------------------------------------------------
+ 23.90 slack (MET)
+
+
+Startpoint: _44966_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: user_irq_ena[1] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.37 4.37 clock network delay (propagated)
+ 0.00 4.37 ^ _44966_/CLK (DFFQ_X1_7T5P0)
+ 5.90 10.27 ^ _44966_/Q (DFFQ_X1_7T5P0)
+ 1.19 11.46 ^ output426/Z (CLKBUF_X4_7T5P0)
+ 0.00 11.46 ^ user_irq_ena[1] (out)
+ 11.46 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -11.46 data arrival time
+---------------------------------------------------------
+ 24.29 slack (MET)
+
+
+Startpoint: _44967_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: user_irq_ena[2] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _44967_/CLK (DFFQ_X1_7T5P0)
+ 5.69 10.11 ^ _44967_/Q (DFFQ_X1_7T5P0)
+ 1.13 11.24 ^ output427/Z (CLKBUF_X4_7T5P0)
+ 0.00 11.24 ^ user_irq_ena[2] (out)
+ 11.24 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -11.24 data arrival time
+---------------------------------------------------------
+ 24.51 slack (MET)
+
+
+Startpoint: _42765_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[38] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _42765_/CLK (DFFQ_X1_7T5P0)
+ 1.09 5.65 ^ _42765_/Q (DFFQ_X1_7T5P0)
+ 4.18 9.83 v _24306_/ZN (CLKINV_X1_7T5P0)
+ 1.20 11.03 v output187/Z (CLKBUF_X4_7T5P0)
+ 0.00 11.03 v la_iena[38] (out)
+ 11.03 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -11.03 data arrival time
+---------------------------------------------------------
+ 24.72 slack (MET)
+
+
+Startpoint: _42787_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[60] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42787_/CLK (DFFQ_X1_7T5P0)
+ 2.72 7.16 ^ _42787_/Q (DFFQ_X1_7T5P0)
+ 2.97 10.13 v _24284_/ZN (CLKINV_X1_7T5P0)
+ 0.90 11.03 v output212/Z (CLKBUF_X4_7T5P0)
+ 0.00 11.03 v la_iena[60] (out)
+ 11.03 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -11.03 data arrival time
+---------------------------------------------------------
+ 24.72 slack (MET)
+
+
+Startpoint: _45065_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: gpio_out_pad (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _45065_/CLK (DFFQ_X1_7T5P0)
+ 5.49 9.90 ^ _45065_/Q (DFFQ_X1_7T5P0)
+ 1.11 11.01 ^ output152/Z (CLKBUF_X4_7T5P0)
+ 0.00 11.01 ^ gpio_out_pad (out)
+ 11.01 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -11.01 data arrival time
+---------------------------------------------------------
+ 24.74 slack (MET)
+
+
+Startpoint: _42762_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[35] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.59 4.59 clock network delay (propagated)
+ 0.00 4.59 ^ _42762_/CLK (DFFQ_X1_7T5P0)
+ 1.46 6.05 ^ _42762_/Q (DFFQ_X1_7T5P0)
+ 3.68 9.73 v _24309_/ZN (CLKINV_X1_7T5P0)
+ 1.13 10.86 v output184/Z (CLKBUF_X4_7T5P0)
+ 0.00 10.87 v la_iena[35] (out)
+ 10.87 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -10.87 data arrival time
+---------------------------------------------------------
+ 24.88 slack (MET)
+
+
+Startpoint: _46499_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: flash_clk (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.24 4.24 clock network delay (propagated)
+ 0.00 4.24 ^ _46499_/CLK (DFFQ_X1_7T5P0)
+ 5.06 9.30 ^ _46499_/Q (DFFQ_X1_7T5P0)
+ 1.11 10.41 ^ output145/Z (CLKBUF_X4_7T5P0)
+ 0.00 10.41 ^ flash_clk (out)
+ 10.41 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -10.41 data arrival time
+---------------------------------------------------------
+ 25.34 slack (MET)
+
+
+Startpoint: _42766_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[39] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _42766_/CLK (DFFQ_X1_7T5P0)
+ 1.13 5.70 ^ _42766_/Q (DFFQ_X1_7T5P0)
+ 3.58 9.28 v _24305_/ZN (CLKINV_X1_7T5P0)
+ 1.10 10.38 v output188/Z (CLKBUF_X4_7T5P0)
+ 0.00 10.38 v la_iena[39] (out)
+ 10.38 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -10.38 data arrival time
+---------------------------------------------------------
+ 25.37 slack (MET)
+
+
+Startpoint: _45038_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[5] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _45038_/CLK (DFFQ_X1_7T5P0)
+ 2.74 7.16 ^ _45038_/Q (DFFQ_X1_7T5P0)
+ 2.25 9.41 v _24339_/ZN (CLKINV_X1_7T5P0)
+ 0.80 10.21 v output211/Z (CLKBUF_X4_7T5P0)
+ 0.00 10.21 v la_iena[5] (out)
+ 10.21 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -10.21 data arrival time
+---------------------------------------------------------
+ 25.54 slack (MET)
+
+
+Startpoint: _42761_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[34] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.61 4.61 clock network delay (propagated)
+ 0.00 4.61 ^ _42761_/CLK (DFFQ_X1_7T5P0)
+ 1.38 5.99 ^ _42761_/Q (DFFQ_X1_7T5P0)
+ 3.04 9.03 v _24310_/ZN (CLKINV_X1_7T5P0)
+ 1.03 10.06 v output183/Z (CLKBUF_X4_7T5P0)
+ 0.00 10.06 v la_iena[34] (out)
+ 10.06 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -10.06 data arrival time
+---------------------------------------------------------
+ 25.69 slack (MET)
+
+
+Startpoint: _45036_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[3] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _45036_/CLK (DFFQ_X1_7T5P0)
+ 2.59 7.02 ^ _45036_/Q (DFFQ_X1_7T5P0)
+ 2.25 9.27 v _24341_/ZN (CLKINV_X1_7T5P0)
+ 0.79 10.06 v output189/Z (CLKBUF_X4_7T5P0)
+ 0.00 10.06 v la_iena[3] (out)
+ 10.06 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -10.06 data arrival time
+---------------------------------------------------------
+ 25.69 slack (MET)
+
+
+Startpoint: _42759_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[32] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.61 4.61 clock network delay (propagated)
+ 0.00 4.61 ^ _42759_/CLK (DFFQ_X1_7T5P0)
+ 1.13 5.74 ^ _42759_/Q (DFFQ_X1_7T5P0)
+ 3.20 8.94 v _24312_/ZN (CLKINV_X1_7T5P0)
+ 1.09 10.04 v output181/Z (CLKBUF_X4_7T5P0)
+ 0.00 10.04 v la_iena[32] (out)
+ 10.04 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -10.04 data arrival time
+---------------------------------------------------------
+ 25.71 slack (MET)
+
+
+Startpoint: _42770_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[43] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42770_/CLK (DFFQ_X1_7T5P0)
+ 1.58 6.01 ^ _42770_/Q (DFFQ_X1_7T5P0)
+ 3.00 9.01 v _24301_/ZN (CLKINV_X1_7T5P0)
+ 0.97 9.99 v output193/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.99 v la_iena[43] (out)
+ 9.99 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.99 data arrival time
+---------------------------------------------------------
+ 25.76 slack (MET)
+
+
+Startpoint: _42780_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[53] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _42780_/CLK (DFFQ_X1_7T5P0)
+ 2.86 7.30 ^ _42780_/Q (DFFQ_X1_7T5P0)
+ 1.88 9.18 v _24291_/ZN (CLKINV_X1_7T5P0)
+ 0.75 9.93 v output204/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.93 v la_iena[53] (out)
+ 9.93 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.93 data arrival time
+---------------------------------------------------------
+ 25.82 slack (MET)
+
+
+Startpoint: _42768_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[41] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42768_/CLK (DFFQ_X1_7T5P0)
+ 1.03 5.47 ^ _42768_/Q (DFFQ_X1_7T5P0)
+ 3.35 8.82 v _24303_/ZN (CLKINV_X1_7T5P0)
+ 1.07 9.89 v output191/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.89 v la_iena[41] (out)
+ 9.89 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.89 data arrival time
+---------------------------------------------------------
+ 25.86 slack (MET)
+
+
+Startpoint: _42760_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[33] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.61 4.61 clock network delay (propagated)
+ 0.00 4.61 ^ _42760_/CLK (DFFQ_X1_7T5P0)
+ 1.17 5.77 ^ _42760_/Q (DFFQ_X1_7T5P0)
+ 3.06 8.83 v _24311_/ZN (CLKINV_X1_7T5P0)
+ 1.02 9.86 v output182/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.86 v la_iena[33] (out)
+ 9.86 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.86 data arrival time
+---------------------------------------------------------
+ 25.89 slack (MET)
+
+
+Startpoint: _42776_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[49] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _42776_/CLK (DFFQ_X1_7T5P0)
+ 3.96 8.38 ^ _42776_/Q (DFFQ_X1_7T5P0)
+ 0.84 9.21 v _24295_/ZN (CLKINV_X1_7T5P0)
+ 0.64 9.86 v output199/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.86 v la_iena[49] (out)
+ 9.86 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.86 data arrival time
+---------------------------------------------------------
+ 25.89 slack (MET)
+
+
+Startpoint: _42764_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[37] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _42764_/CLK (DFFQ_X1_7T5P0)
+ 1.33 5.89 ^ _42764_/Q (DFFQ_X1_7T5P0)
+ 2.96 8.85 v _24307_/ZN (CLKINV_X1_7T5P0)
+ 1.00 9.85 v output186/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.85 v la_iena[37] (out)
+ 9.85 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.85 data arrival time
+---------------------------------------------------------
+ 25.90 slack (MET)
+
+
+Startpoint: _42782_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[55] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _42782_/CLK (DFFQ_X1_7T5P0)
+ 2.75 7.17 ^ _42782_/Q (DFFQ_X1_7T5P0)
+ 1.84 9.01 v _24289_/ZN (CLKINV_X1_7T5P0)
+ 0.75 9.76 v output206/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.76 v la_iena[55] (out)
+ 9.76 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.76 data arrival time
+---------------------------------------------------------
+ 25.99 slack (MET)
+
+
+Startpoint: _42775_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[48] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _42775_/CLK (DFFQ_X1_7T5P0)
+ 4.26 8.67 ^ _42775_/Q (DFFQ_X1_7T5P0)
+ 0.46 9.13 v _24296_/ZN (CLKINV_X1_7T5P0)
+ 0.58 9.71 v output198/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.71 v la_iena[48] (out)
+ 9.71 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.71 data arrival time
+---------------------------------------------------------
+ 26.04 slack (MET)
+
+
+Startpoint: _45048_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[15] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.49 4.49 clock network delay (propagated)
+ 0.00 4.49 ^ _45048_/CLK (DFFQ_X1_7T5P0)
+ 4.33 8.82 ^ _45048_/Q (DFFQ_X1_7T5P0)
+ 0.31 9.13 v _24329_/ZN (CLKINV_X1_7T5P0)
+ 0.56 9.69 v output162/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.69 v la_iena[15] (out)
+ 9.69 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.69 data arrival time
+---------------------------------------------------------
+ 26.06 slack (MET)
+
+
+Startpoint: _42777_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[50] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _42777_/CLK (DFFQ_X1_7T5P0)
+ 3.06 7.50 ^ _42777_/Q (DFFQ_X1_7T5P0)
+ 1.47 8.97 v _24294_/ZN (CLKINV_X1_7T5P0)
+ 0.70 9.67 v output201/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.67 v la_iena[50] (out)
+ 9.67 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.67 data arrival time
+---------------------------------------------------------
+ 26.08 slack (MET)
+
+
+Startpoint: _45068_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: gpio_mode0_pad (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _45068_/CLK (DFFQ_X1_7T5P0)
+ 4.26 8.67 ^ _45068_/Q (DFFQ_X1_7T5P0)
+ 0.98 9.66 ^ output150/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.66 ^ gpio_mode0_pad (out)
+ 9.66 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.66 data arrival time
+---------------------------------------------------------
+ 26.09 slack (MET)
+
+
+Startpoint: _45045_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[12] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _45045_/CLK (DFFQ_X1_7T5P0)
+ 4.00 8.50 ^ _45045_/Q (DFFQ_X1_7T5P0)
+ 0.53 9.03 v _24332_/ZN (CLKINV_X1_7T5P0)
+ 0.59 9.62 v output159/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.62 v la_iena[12] (out)
+ 9.62 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.62 data arrival time
+---------------------------------------------------------
+ 26.13 slack (MET)
+
+
+Startpoint: _45054_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[21] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.84 4.84 clock network delay (propagated)
+ 0.00 4.84 ^ _45054_/CLK (DFFQ_X1_7T5P0)
+ 3.92 8.76 ^ _45054_/Q (DFFQ_X1_7T5P0)
+ 0.30 9.06 v _24323_/ZN (CLKINV_X1_7T5P0)
+ 0.55 9.61 v output169/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.61 v la_iena[21] (out)
+ 9.61 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.61 data arrival time
+---------------------------------------------------------
+ 26.14 slack (MET)
+
+
+Startpoint: _45926_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: spi_sck (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.74 4.74 clock network delay (propagated)
+ 0.00 4.74 ^ _45926_/CLK (DFFQ_X1_7T5P0)
+ 3.95 8.69 ^ _45926_/Q (DFFQ_X1_7T5P0)
+ 0.90 9.59 ^ output421/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.59 ^ spi_sck (out)
+ 9.59 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.59 data arrival time
+---------------------------------------------------------
+ 26.16 slack (MET)
+
+
+Startpoint: _42788_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[61] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42788_/CLK (DFFQ_X1_7T5P0)
+ 1.12 5.55 ^ _42788_/Q (DFFQ_X1_7T5P0)
+ 3.01 8.56 v _24283_/ZN (CLKINV_X1_7T5P0)
+ 1.01 9.58 v output213/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.58 v la_iena[61] (out)
+ 9.58 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.58 data arrival time
+---------------------------------------------------------
+ 26.17 slack (MET)
+
+
+Startpoint: _42857_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[34] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.66 4.66 clock network delay (propagated)
+ 0.00 4.66 ^ _42857_/CLK (DFFQ_X1_7T5P0)
+ 3.68 8.35 ^ _42857_/Q (DFFQ_X1_7T5P0)
+ 0.63 8.98 v _24246_/ZN (CLKINV_X1_7T5P0)
+ 0.60 9.57 v output247/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.57 v la_oenb[34] (out)
+ 9.57 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.57 data arrival time
+---------------------------------------------------------
+ 26.18 slack (MET)
+
+
+Startpoint: _45039_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[6] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _45039_/CLK (DFFQ_X1_7T5P0)
+ 2.45 6.88 ^ _45039_/Q (DFFQ_X1_7T5P0)
+ 1.92 8.80 v _24338_/ZN (CLKINV_X1_7T5P0)
+ 0.76 9.56 v output216/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.56 v la_iena[6] (out)
+ 9.56 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.56 data arrival time
+---------------------------------------------------------
+ 26.19 slack (MET)
+
+
+Startpoint: _45051_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[18] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.87 4.87 clock network delay (propagated)
+ 0.00 4.87 ^ _45051_/CLK (DFFQ_X1_7T5P0)
+ 3.75 8.62 ^ _45051_/Q (DFFQ_X1_7T5P0)
+ 0.37 8.99 v _24326_/ZN (CLKINV_X1_7T5P0)
+ 0.56 9.55 v output165/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.55 v la_iena[18] (out)
+ 9.55 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.55 data arrival time
+---------------------------------------------------------
+ 26.20 slack (MET)
+
+
+Startpoint: _42763_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[36] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _42763_/CLK (DFFQ_X1_7T5P0)
+ 1.10 5.67 ^ _42763_/Q (DFFQ_X1_7T5P0)
+ 2.85 8.52 v _24308_/ZN (CLKINV_X1_7T5P0)
+ 1.02 9.54 v output185/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.54 v la_iena[36] (out)
+ 9.54 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.54 data arrival time
+---------------------------------------------------------
+ 26.21 slack (MET)
+
+
+Startpoint: _45055_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[22] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.84 4.84 clock network delay (propagated)
+ 0.00 4.84 ^ _45055_/CLK (DFFQ_X1_7T5P0)
+ 3.77 8.61 ^ _45055_/Q (DFFQ_X1_7T5P0)
+ 0.37 8.98 v _24322_/ZN (CLKINV_X1_7T5P0)
+ 0.55 9.54 v output170/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.54 v la_iena[22] (out)
+ 9.54 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.54 data arrival time
+---------------------------------------------------------
+ 26.21 slack (MET)
+
+
+Startpoint: _45060_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[27] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.87 4.87 clock network delay (propagated)
+ 0.00 4.87 ^ _45060_/CLK (DFFQ_X1_7T5P0)
+ 2.93 7.79 ^ _45060_/Q (DFFQ_X1_7T5P0)
+ 1.09 8.89 v _24317_/ZN (CLKINV_X1_7T5P0)
+ 0.65 9.54 v output175/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.54 v la_iena[27] (out)
+ 9.54 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.54 data arrival time
+---------------------------------------------------------
+ 26.21 slack (MET)
+
+
+Startpoint: _45042_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[9] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _45042_/CLK (DFFQ_X1_7T5P0)
+ 3.09 7.53 ^ _45042_/Q (DFFQ_X1_7T5P0)
+ 1.32 8.85 v _24335_/ZN (CLKINV_X1_7T5P0)
+ 0.68 9.53 v output219/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.54 v la_iena[9] (out)
+ 9.54 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.54 data arrival time
+---------------------------------------------------------
+ 26.21 slack (MET)
+
+
+Startpoint: _42790_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[63] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42790_/CLK (DFFQ_X1_7T5P0)
+ 1.38 5.82 ^ _42790_/Q (DFFQ_X1_7T5P0)
+ 2.77 8.59 v _24281_/ZN (CLKINV_X1_7T5P0)
+ 0.95 9.53 v output215/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.53 v la_iena[63] (out)
+ 9.53 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.53 data arrival time
+---------------------------------------------------------
+ 26.22 slack (MET)
+
+
+Startpoint: _42785_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[58] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42785_/CLK (DFFQ_X1_7T5P0)
+ 3.93 8.36 ^ _42785_/Q (DFFQ_X1_7T5P0)
+ 0.58 8.93 v _24286_/ZN (CLKINV_X1_7T5P0)
+ 0.59 9.52 v output209/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.52 v la_iena[58] (out)
+ 9.52 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.52 data arrival time
+---------------------------------------------------------
+ 26.23 slack (MET)
+
+
+Startpoint: _45047_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[14] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.49 4.49 clock network delay (propagated)
+ 0.00 4.49 ^ _45047_/CLK (DFFQ_X1_7T5P0)
+ 4.10 8.60 ^ _45047_/Q (DFFQ_X1_7T5P0)
+ 0.35 8.95 v _24330_/ZN (CLKINV_X1_7T5P0)
+ 0.56 9.51 v output161/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.51 v la_iena[14] (out)
+ 9.51 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.51 data arrival time
+---------------------------------------------------------
+ 26.24 slack (MET)
+
+
+Startpoint: _42774_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[47] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _42774_/CLK (DFFQ_X1_7T5P0)
+ 1.56 5.97 ^ _42774_/Q (DFFQ_X1_7T5P0)
+ 2.61 8.58 v _24297_/ZN (CLKINV_X1_7T5P0)
+ 0.92 9.50 v output197/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.50 v la_iena[47] (out)
+ 9.50 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.50 data arrival time
+---------------------------------------------------------
+ 26.25 slack (MET)
+
+
+Startpoint: _42773_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[46] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42773_/CLK (DFFQ_X1_7T5P0)
+ 1.09 5.52 ^ _42773_/Q (DFFQ_X1_7T5P0)
+ 2.94 8.46 v _24298_/ZN (CLKINV_X1_7T5P0)
+ 1.03 9.49 v output196/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.50 v la_iena[46] (out)
+ 9.50 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.50 data arrival time
+---------------------------------------------------------
+ 26.25 slack (MET)
+
+
+Startpoint: _42779_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[52] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _42779_/CLK (DFFQ_X1_7T5P0)
+ 2.34 6.78 ^ _42779_/Q (DFFQ_X1_7T5P0)
+ 1.93 8.72 v _24292_/ZN (CLKINV_X1_7T5P0)
+ 0.75 9.47 v output203/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.47 v la_iena[52] (out)
+ 9.47 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.47 data arrival time
+---------------------------------------------------------
+ 26.28 slack (MET)
+
+
+Startpoint: _42772_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[45] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _42772_/CLK (DFFQ_X1_7T5P0)
+ 1.76 6.16 ^ _42772_/Q (DFFQ_X1_7T5P0)
+ 2.43 8.59 v _24299_/ZN (CLKINV_X1_7T5P0)
+ 0.87 9.46 v output195/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.46 v la_iena[45] (out)
+ 9.46 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.46 data arrival time
+---------------------------------------------------------
+ 26.29 slack (MET)
+
+
+Startpoint: _45056_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[23] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.87 4.87 clock network delay (propagated)
+ 0.00 4.87 ^ _45056_/CLK (DFFQ_X1_7T5P0)
+ 3.61 8.48 ^ _45056_/Q (DFFQ_X1_7T5P0)
+ 0.42 8.90 v _24321_/ZN (CLKINV_X1_7T5P0)
+ 0.56 9.46 v output171/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.46 v la_iena[23] (out)
+ 9.46 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.46 data arrival time
+---------------------------------------------------------
+ 26.29 slack (MET)
+
+
+Startpoint: _45041_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[8] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _45041_/CLK (DFFQ_X1_7T5P0)
+ 3.46 7.89 ^ _45041_/Q (DFFQ_X1_7T5P0)
+ 0.91 8.81 v _24336_/ZN (CLKINV_X1_7T5P0)
+ 0.63 9.44 v output218/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.44 v la_iena[8] (out)
+ 9.44 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.44 data arrival time
+---------------------------------------------------------
+ 26.31 slack (MET)
+
+
+Startpoint: _45061_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[28] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.46 4.46 clock network delay (propagated)
+ 0.00 4.46 ^ _45061_/CLK (DFFQ_X1_7T5P0)
+ 2.99 7.45 ^ _45061_/Q (DFFQ_X1_7T5P0)
+ 1.26 8.71 v _24316_/ZN (CLKINV_X1_7T5P0)
+ 0.67 9.38 v output176/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.38 v la_iena[28] (out)
+ 9.38 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.38 data arrival time
+---------------------------------------------------------
+ 26.37 slack (MET)
+
+
+Startpoint: _45035_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[2] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _45035_/CLK (DFFQ_X1_7T5P0)
+ 2.09 6.52 ^ _45035_/Q (DFFQ_X1_7T5P0)
+ 2.08 8.60 v _24342_/ZN (CLKINV_X1_7T5P0)
+ 0.78 9.38 v output178/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.38 v la_iena[2] (out)
+ 9.38 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.38 data arrival time
+---------------------------------------------------------
+ 26.37 slack (MET)
+
+
+Startpoint: _42860_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[37] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _42860_/CLK (DFFQ_X1_7T5P0)
+ 3.76 8.33 ^ _42860_/Q (DFFQ_X1_7T5P0)
+ 0.45 8.78 v _24243_/ZN (CLKINV_X1_7T5P0)
+ 0.57 9.34 v output250/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.34 v la_oenb[37] (out)
+ 9.34 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.34 data arrival time
+---------------------------------------------------------
+ 26.41 slack (MET)
+
+
+Startpoint: _45044_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[11] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _45044_/CLK (DFFQ_X1_7T5P0)
+ 3.67 8.16 ^ _45044_/Q (DFFQ_X1_7T5P0)
+ 0.59 8.75 v _24333_/ZN (CLKINV_X1_7T5P0)
+ 0.59 9.34 v output158/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.34 v la_iena[11] (out)
+ 9.34 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.34 data arrival time
+---------------------------------------------------------
+ 26.41 slack (MET)
+
+
+Startpoint: _45069_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: gpio_mode1_pad (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _45069_/CLK (DFFQ_X1_7T5P0)
+ 3.94 8.35 ^ _45069_/Q (DFFQ_X1_7T5P0)
+ 0.96 9.31 ^ output151/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.31 ^ gpio_mode1_pad (out)
+ 9.31 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.31 data arrival time
+---------------------------------------------------------
+ 26.44 slack (MET)
+
+
+Startpoint: _42861_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[38] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.66 4.66 clock network delay (propagated)
+ 0.00 4.66 ^ _42861_/CLK (DFFQ_X1_7T5P0)
+ 3.81 8.47 ^ _42861_/Q (DFFQ_X1_7T5P0)
+ 0.30 8.76 v _24242_/ZN (CLKINV_X1_7T5P0)
+ 0.54 9.30 v output251/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.30 v la_oenb[38] (out)
+ 9.30 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.30 data arrival time
+---------------------------------------------------------
+ 26.45 slack (MET)
+
+
+Startpoint: _42771_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[44] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _42771_/CLK (DFFQ_X1_7T5P0)
+ 1.26 5.67 ^ _42771_/Q (DFFQ_X1_7T5P0)
+ 2.67 8.34 v _24300_/ZN (CLKINV_X1_7T5P0)
+ 0.96 9.29 v output194/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.30 v la_iena[44] (out)
+ 9.30 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.30 data arrival time
+---------------------------------------------------------
+ 26.45 slack (MET)
+
+
+Startpoint: _45033_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[0] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _45033_/CLK (DFFQ_X1_7T5P0)
+ 3.74 8.17 ^ _45033_/Q (DFFQ_X1_7T5P0)
+ 0.52 8.69 v _24344_/ZN (CLKINV_X1_7T5P0)
+ 0.58 9.27 v output156/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.27 v la_iena[0] (out)
+ 9.27 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.27 data arrival time
+---------------------------------------------------------
+ 26.48 slack (MET)
+
+
+Startpoint: _42767_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[40] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.38 4.38 clock network delay (propagated)
+ 0.00 4.38 ^ _42767_/CLK (DFFQ_X1_7T5P0)
+ 1.15 5.52 ^ _42767_/Q (DFFQ_X1_7T5P0)
+ 2.75 8.27 v _24304_/ZN (CLKINV_X1_7T5P0)
+ 0.98 9.26 v output190/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.26 v la_iena[40] (out)
+ 9.26 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.26 data arrival time
+---------------------------------------------------------
+ 26.49 slack (MET)
+
+
+Startpoint: _42855_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[32] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _42855_/CLK (DFFQ_X1_7T5P0)
+ 3.43 7.99 ^ _42855_/Q (DFFQ_X1_7T5P0)
+ 0.66 8.65 v _24248_/ZN (CLKINV_X1_7T5P0)
+ 0.60 9.25 v output245/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.25 v la_oenb[32] (out)
+ 9.25 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.25 data arrival time
+---------------------------------------------------------
+ 26.50 slack (MET)
+
+
+Startpoint: _45059_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[26] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _45059_/CLK (DFFQ_X1_7T5P0)
+ 2.61 7.03 ^ _45059_/Q (DFFQ_X1_7T5P0)
+ 1.50 8.54 v _24318_/ZN (CLKINV_X1_7T5P0)
+ 0.70 9.24 v output174/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.24 v la_iena[26] (out)
+ 9.24 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.24 data arrival time
+---------------------------------------------------------
+ 26.51 slack (MET)
+
+
+Startpoint: _45037_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[4] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _45037_/CLK (DFFQ_X1_7T5P0)
+ 2.24 6.67 ^ _45037_/Q (DFFQ_X1_7T5P0)
+ 1.81 8.48 v _24340_/ZN (CLKINV_X1_7T5P0)
+ 0.74 9.22 v output200/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.22 v la_iena[4] (out)
+ 9.22 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.22 data arrival time
+---------------------------------------------------------
+ 26.53 slack (MET)
+
+
+Startpoint: _45064_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[31] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.87 4.87 clock network delay (propagated)
+ 0.00 4.87 ^ _45064_/CLK (DFFQ_X1_7T5P0)
+ 3.39 8.26 ^ _45064_/Q (DFFQ_X1_7T5P0)
+ 0.41 8.66 v _24313_/ZN (CLKINV_X1_7T5P0)
+ 0.55 9.21 v output180/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.21 v la_iena[31] (out)
+ 9.21 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.21 data arrival time
+---------------------------------------------------------
+ 26.54 slack (MET)
+
+
+Startpoint: _45043_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[10] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.49 4.49 clock network delay (propagated)
+ 0.00 4.49 ^ _45043_/CLK (DFFQ_X1_7T5P0)
+ 3.40 7.89 ^ _45043_/Q (DFFQ_X1_7T5P0)
+ 0.72 8.61 v _24334_/ZN (CLKINV_X1_7T5P0)
+ 0.61 9.21 v output157/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.21 v la_iena[10] (out)
+ 9.21 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.21 data arrival time
+---------------------------------------------------------
+ 26.54 slack (MET)
+
+
+Startpoint: _45052_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[19] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.87 4.87 clock network delay (propagated)
+ 0.00 4.87 ^ _45052_/CLK (DFFQ_X1_7T5P0)
+ 3.41 8.27 ^ _45052_/Q (DFFQ_X1_7T5P0)
+ 0.34 8.62 v _24325_/ZN (CLKINV_X1_7T5P0)
+ 0.54 9.16 v output166/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.16 v la_iena[19] (out)
+ 9.16 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.16 data arrival time
+---------------------------------------------------------
+ 26.59 slack (MET)
+
+
+Startpoint: _42789_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[62] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42789_/CLK (DFFQ_X1_7T5P0)
+ 1.32 5.75 ^ _42789_/Q (DFFQ_X1_7T5P0)
+ 2.47 8.22 v _24282_/ZN (CLKINV_X1_7T5P0)
+ 0.92 9.14 v output214/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.15 v la_iena[62] (out)
+ 9.15 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.15 data arrival time
+---------------------------------------------------------
+ 26.60 slack (MET)
+
+
+Startpoint: _42864_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[41] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42864_/CLK (DFFQ_X1_7T5P0)
+ 3.75 8.17 ^ _42864_/Q (DFFQ_X1_7T5P0)
+ 0.41 8.58 v _24239_/ZN (CLKINV_X1_7T5P0)
+ 0.56 9.14 v output255/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.14 v la_oenb[41] (out)
+ 9.14 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.14 data arrival time
+---------------------------------------------------------
+ 26.61 slack (MET)
+
+
+Startpoint: _45040_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[7] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _45040_/CLK (DFFQ_X1_7T5P0)
+ 3.55 7.98 ^ _45040_/Q (DFFQ_X1_7T5P0)
+ 0.56 8.54 v _24337_/ZN (CLKINV_X1_7T5P0)
+ 0.58 9.12 v output217/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.12 v la_iena[7] (out)
+ 9.12 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.12 data arrival time
+---------------------------------------------------------
+ 26.63 slack (MET)
+
+
+Startpoint: _42786_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[59] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42786_/CLK (DFFQ_X1_7T5P0)
+ 3.54 7.98 ^ _42786_/Q (DFFQ_X1_7T5P0)
+ 0.56 8.54 v _24285_/ZN (CLKINV_X1_7T5P0)
+ 0.58 9.11 v output210/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.11 v la_iena[59] (out)
+ 9.11 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.11 data arrival time
+---------------------------------------------------------
+ 26.64 slack (MET)
+
+
+Startpoint: _42885_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[62] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _42885_/CLK (DFFQ_X1_7T5P0)
+ 3.46 7.87 ^ _42885_/Q (DFFQ_X1_7T5P0)
+ 0.63 8.50 v _24218_/ZN (CLKINV_X1_7T5P0)
+ 0.59 9.09 v output278/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.09 v la_oenb[62] (out)
+ 9.09 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.09 data arrival time
+---------------------------------------------------------
+ 26.66 slack (MET)
+
+
+Startpoint: _42783_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[56] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _42783_/CLK (DFFQ_X1_7T5P0)
+ 1.44 5.86 ^ _42783_/Q (DFFQ_X1_7T5P0)
+ 2.33 8.19 v _24288_/ZN (CLKINV_X1_7T5P0)
+ 0.89 9.08 v output207/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.08 v la_iena[56] (out)
+ 9.08 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.08 data arrival time
+---------------------------------------------------------
+ 26.67 slack (MET)
+
+
+Startpoint: _42883_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[60] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _42883_/CLK (DFFQ_X1_7T5P0)
+ 3.37 7.81 ^ _42883_/Q (DFFQ_X1_7T5P0)
+ 0.65 8.46 v _24220_/ZN (CLKINV_X1_7T5P0)
+ 0.59 9.05 v output276/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.06 v la_oenb[60] (out)
+ 9.06 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.06 data arrival time
+---------------------------------------------------------
+ 26.69 slack (MET)
+
+
+Startpoint: _42856_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[33] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.60 4.60 clock network delay (propagated)
+ 0.00 4.60 ^ _42856_/CLK (DFFQ_X1_7T5P0)
+ 3.34 7.93 ^ _42856_/Q (DFFQ_X1_7T5P0)
+ 0.55 8.48 v _24247_/ZN (CLKINV_X1_7T5P0)
+ 0.57 9.05 v output246/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.05 v la_oenb[33] (out)
+ 9.05 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.05 data arrival time
+---------------------------------------------------------
+ 26.70 slack (MET)
+
+
+Startpoint: _45050_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[17] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _45050_/CLK (DFFQ_X1_7T5P0)
+ 3.62 8.04 ^ _45050_/Q (DFFQ_X1_7T5P0)
+ 0.42 8.46 v _24327_/ZN (CLKINV_X1_7T5P0)
+ 0.56 9.02 v output164/Z (CLKBUF_X4_7T5P0)
+ 0.00 9.02 v la_iena[17] (out)
+ 9.02 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -9.02 data arrival time
+---------------------------------------------------------
+ 26.73 slack (MET)
+
+
+Startpoint: _42862_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[39] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.66 4.66 clock network delay (propagated)
+ 0.00 4.66 ^ _42862_/CLK (DFFQ_X1_7T5P0)
+ 3.45 8.11 ^ _42862_/Q (DFFQ_X1_7T5P0)
+ 0.33 8.44 v _24241_/ZN (CLKINV_X1_7T5P0)
+ 0.53 8.97 v output252/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.97 v la_oenb[39] (out)
+ 8.97 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.97 data arrival time
+---------------------------------------------------------
+ 26.78 slack (MET)
+
+
+Startpoint: _42866_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[43] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42866_/CLK (DFFQ_X1_7T5P0)
+ 3.67 8.11 ^ _42866_/Q (DFFQ_X1_7T5P0)
+ 0.32 8.43 v _24237_/ZN (CLKINV_X1_7T5P0)
+ 0.54 8.97 v output257/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.97 v la_oenb[43] (out)
+ 8.97 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.97 data arrival time
+---------------------------------------------------------
+ 26.78 slack (MET)
+
+
+Startpoint: _45063_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[30] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.87 4.87 clock network delay (propagated)
+ 0.00 4.87 ^ _45063_/CLK (DFFQ_X1_7T5P0)
+ 3.23 8.10 ^ _45063_/Q (DFFQ_X1_7T5P0)
+ 0.33 8.43 v _24314_/ZN (CLKINV_X1_7T5P0)
+ 0.53 8.96 v output179/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.96 v la_iena[30] (out)
+ 8.96 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.96 data arrival time
+---------------------------------------------------------
+ 26.79 slack (MET)
+
+
+Startpoint: _42870_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[47] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42870_/CLK (DFFQ_X1_7T5P0)
+ 3.66 8.08 ^ _42870_/Q (DFFQ_X1_7T5P0)
+ 0.34 8.42 v _24233_/ZN (CLKINV_X1_7T5P0)
+ 0.54 8.96 v output261/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.96 v la_oenb[47] (out)
+ 8.96 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.96 data arrival time
+---------------------------------------------------------
+ 26.79 slack (MET)
+
+
+Startpoint: _45046_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[13] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.49 4.49 clock network delay (propagated)
+ 0.00 4.49 ^ _45046_/CLK (DFFQ_X1_7T5P0)
+ 3.60 8.09 ^ _45046_/Q (DFFQ_X1_7T5P0)
+ 0.31 8.40 v _24331_/ZN (CLKINV_X1_7T5P0)
+ 0.55 8.95 v output160/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.95 v la_iena[13] (out)
+ 8.95 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.95 data arrival time
+---------------------------------------------------------
+ 26.80 slack (MET)
+
+
+Startpoint: _42871_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[48] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _42871_/CLK (DFFQ_X1_7T5P0)
+ 3.56 7.97 ^ _42871_/Q (DFFQ_X1_7T5P0)
+ 0.41 8.38 v _24232_/ZN (CLKINV_X1_7T5P0)
+ 0.55 8.93 v output262/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.93 v la_oenb[48] (out)
+ 8.93 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.93 data arrival time
+---------------------------------------------------------
+ 26.82 slack (MET)
+
+
+Startpoint: _42863_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[40] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42863_/CLK (DFFQ_X1_7T5P0)
+ 3.61 8.04 ^ _42863_/Q (DFFQ_X1_7T5P0)
+ 0.33 8.37 v _24240_/ZN (CLKINV_X1_7T5P0)
+ 0.54 8.90 v output254/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.90 v la_oenb[40] (out)
+ 8.90 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.90 data arrival time
+---------------------------------------------------------
+ 26.85 slack (MET)
+
+
+Startpoint: _42859_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[36] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.66 4.66 clock network delay (propagated)
+ 0.00 4.66 ^ _42859_/CLK (DFFQ_X1_7T5P0)
+ 3.32 7.98 ^ _42859_/Q (DFFQ_X1_7T5P0)
+ 0.37 8.35 v _24244_/ZN (CLKINV_X1_7T5P0)
+ 0.54 8.88 v output249/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.89 v la_oenb[36] (out)
+ 8.89 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.89 data arrival time
+---------------------------------------------------------
+ 26.86 slack (MET)
+
+
+Startpoint: _42778_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[51] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _42778_/CLK (DFFQ_X1_7T5P0)
+ 2.44 6.86 ^ _42778_/Q (DFFQ_X1_7T5P0)
+ 1.34 8.20 v _24293_/ZN (CLKINV_X1_7T5P0)
+ 0.67 8.87 v output202/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.87 v la_iena[51] (out)
+ 8.87 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.87 data arrival time
+---------------------------------------------------------
+ 26.88 slack (MET)
+
+
+Startpoint: _42858_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[35] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.65 4.65 clock network delay (propagated)
+ 0.00 4.65 ^ _42858_/CLK (DFFQ_X1_7T5P0)
+ 3.24 7.89 ^ _42858_/Q (DFFQ_X1_7T5P0)
+ 0.42 8.31 v _24245_/ZN (CLKINV_X1_7T5P0)
+ 0.54 8.85 v output248/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.85 v la_oenb[35] (out)
+ 8.85 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.85 data arrival time
+---------------------------------------------------------
+ 26.90 slack (MET)
+
+
+Startpoint: _45034_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[1] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _45034_/CLK (DFFQ_X1_7T5P0)
+ 3.23 7.65 ^ _45034_/Q (DFFQ_X1_7T5P0)
+ 0.58 8.24 v _24343_/ZN (CLKINV_X1_7T5P0)
+ 0.58 8.81 v output167/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.81 v la_iena[1] (out)
+ 8.81 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.81 data arrival time
+---------------------------------------------------------
+ 26.94 slack (MET)
+
+
+Startpoint: _42781_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[54] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _42781_/CLK (DFFQ_X1_7T5P0)
+ 2.17 6.61 ^ _42781_/Q (DFFQ_X1_7T5P0)
+ 1.49 8.10 v _24290_/ZN (CLKINV_X1_7T5P0)
+ 0.68 8.78 v output205/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.78 v la_iena[54] (out)
+ 8.78 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.78 data arrival time
+---------------------------------------------------------
+ 26.97 slack (MET)
+
+
+Startpoint: _42865_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[42] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42865_/CLK (DFFQ_X1_7T5P0)
+ 3.35 7.78 ^ _42865_/Q (DFFQ_X1_7T5P0)
+ 0.43 8.21 v _24238_/ZN (CLKINV_X1_7T5P0)
+ 0.55 8.77 v output256/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.77 v la_oenb[42] (out)
+ 8.77 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.77 data arrival time
+---------------------------------------------------------
+ 26.98 slack (MET)
+
+
+Startpoint: _42872_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[49] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _42872_/CLK (DFFQ_X1_7T5P0)
+ 3.19 7.63 ^ _42872_/Q (DFFQ_X1_7T5P0)
+ 0.50 8.13 v _24231_/ZN (CLKINV_X1_7T5P0)
+ 0.56 8.69 v output263/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.69 v la_oenb[49] (out)
+ 8.69 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.69 data arrival time
+---------------------------------------------------------
+ 27.06 slack (MET)
+
+
+Startpoint: _42868_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[45] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42868_/CLK (DFFQ_X1_7T5P0)
+ 3.41 7.83 ^ _42868_/Q (DFFQ_X1_7T5P0)
+ 0.31 8.15 v _24235_/ZN (CLKINV_X1_7T5P0)
+ 0.53 8.67 v output259/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.67 v la_oenb[45] (out)
+ 8.67 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.67 data arrival time
+---------------------------------------------------------
+ 27.08 slack (MET)
+
+
+Startpoint: _42880_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[57] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _42880_/CLK (DFFQ_X1_7T5P0)
+ 3.22 7.66 ^ _42880_/Q (DFFQ_X1_7T5P0)
+ 0.45 8.11 v _24223_/ZN (CLKINV_X1_7T5P0)
+ 0.55 8.66 v output272/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.66 v la_oenb[57] (out)
+ 8.66 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.66 data arrival time
+---------------------------------------------------------
+ 27.09 slack (MET)
+
+
+Startpoint: _42886_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[63] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _42886_/CLK (DFFQ_X1_7T5P0)
+ 3.26 7.67 ^ _42886_/Q (DFFQ_X1_7T5P0)
+ 0.43 8.10 v _24217_/ZN (CLKINV_X1_7T5P0)
+ 0.55 8.65 v output279/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.65 v la_oenb[63] (out)
+ 8.65 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.65 data arrival time
+---------------------------------------------------------
+ 27.10 slack (MET)
+
+
+Startpoint: _42784_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[57] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42784_/CLK (DFFQ_X1_7T5P0)
+ 1.35 5.78 ^ _42784_/Q (DFFQ_X1_7T5P0)
+ 2.03 7.81 v _24287_/ZN (CLKINV_X1_7T5P0)
+ 0.84 8.65 v output208/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.65 v la_iena[57] (out)
+ 8.65 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.65 data arrival time
+---------------------------------------------------------
+ 27.10 slack (MET)
+
+
+Startpoint: _45058_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[25] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _45058_/CLK (DFFQ_X1_7T5P0)
+ 3.30 7.72 ^ _45058_/Q (DFFQ_X1_7T5P0)
+ 0.38 8.10 v _24319_/ZN (CLKINV_X1_7T5P0)
+ 0.54 8.64 v output173/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.64 v la_iena[25] (out)
+ 8.64 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.64 data arrival time
+---------------------------------------------------------
+ 27.11 slack (MET)
+
+
+Startpoint: _42769_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[42] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.32 4.32 clock network delay (propagated)
+ 0.00 4.32 ^ _42769_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.32 ^ _42769_/Q (DFFQ_X1_7T5P0)
+ 2.36 7.67 v _24302_/ZN (CLKINV_X1_7T5P0)
+ 0.93 8.61 v output192/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.61 v la_iena[42] (out)
+ 8.61 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.61 data arrival time
+---------------------------------------------------------
+ 27.14 slack (MET)
+
+
+Startpoint: _42869_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[46] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42869_/CLK (DFFQ_X1_7T5P0)
+ 3.27 7.70 ^ _42869_/Q (DFFQ_X1_7T5P0)
+ 0.35 8.04 v _24234_/ZN (CLKINV_X1_7T5P0)
+ 0.53 8.58 v output260/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.58 v la_oenb[46] (out)
+ 8.58 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.58 data arrival time
+---------------------------------------------------------
+ 27.17 slack (MET)
+
+
+Startpoint: _45053_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[20] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _45053_/CLK (DFFQ_X1_7T5P0)
+ 3.20 7.62 ^ _45053_/Q (DFFQ_X1_7T5P0)
+ 0.39 8.01 v _24324_/ZN (CLKINV_X1_7T5P0)
+ 0.54 8.55 v output168/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.55 v la_iena[20] (out)
+ 8.55 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.55 data arrival time
+---------------------------------------------------------
+ 27.20 slack (MET)
+
+
+Startpoint: _42884_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[61] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _42884_/CLK (DFFQ_X1_7T5P0)
+ 2.87 7.31 ^ _42884_/Q (DFFQ_X1_7T5P0)
+ 0.64 7.95 v _24219_/ZN (CLKINV_X1_7T5P0)
+ 0.57 8.52 v output277/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.52 v la_oenb[61] (out)
+ 8.52 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.52 data arrival time
+---------------------------------------------------------
+ 27.23 slack (MET)
+
+
+Startpoint: _42867_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[44] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42867_/CLK (DFFQ_X1_7T5P0)
+ 3.26 7.69 ^ _42867_/Q (DFFQ_X1_7T5P0)
+ 0.31 8.00 v _24236_/ZN (CLKINV_X1_7T5P0)
+ 0.52 8.52 v output258/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.52 v la_oenb[44] (out)
+ 8.52 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.52 data arrival time
+---------------------------------------------------------
+ 27.23 slack (MET)
+
+
+Startpoint: _42879_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[56] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _42879_/CLK (DFFQ_X1_7T5P0)
+ 2.94 7.38 ^ _42879_/Q (DFFQ_X1_7T5P0)
+ 0.54 7.92 v _24224_/ZN (CLKINV_X1_7T5P0)
+ 0.55 8.48 v output271/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.48 v la_oenb[56] (out)
+ 8.48 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.48 data arrival time
+---------------------------------------------------------
+ 27.27 slack (MET)
+
+
+Startpoint: _45062_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[29] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.46 4.46 clock network delay (propagated)
+ 0.00 4.46 ^ _45062_/CLK (DFFQ_X1_7T5P0)
+ 3.00 7.46 ^ _45062_/Q (DFFQ_X1_7T5P0)
+ 0.45 7.92 v _24315_/ZN (CLKINV_X1_7T5P0)
+ 0.55 8.46 v output177/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.46 v la_iena[29] (out)
+ 8.46 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.46 data arrival time
+---------------------------------------------------------
+ 27.29 slack (MET)
+
+
+Startpoint: _45049_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[16] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _45049_/CLK (DFFQ_X1_7T5P0)
+ 3.02 7.44 ^ _45049_/Q (DFFQ_X1_7T5P0)
+ 0.40 7.84 v _24328_/ZN (CLKINV_X1_7T5P0)
+ 0.54 8.38 v output163/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.38 v la_iena[16] (out)
+ 8.38 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.38 data arrival time
+---------------------------------------------------------
+ 27.37 slack (MET)
+
+
+Startpoint: _42875_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[52] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _42875_/CLK (DFFQ_X1_7T5P0)
+ 2.80 7.22 ^ _42875_/Q (DFFQ_X1_7T5P0)
+ 0.58 7.80 v _24228_/ZN (CLKINV_X1_7T5P0)
+ 0.56 8.36 v output267/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.36 v la_oenb[52] (out)
+ 8.36 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.36 data arrival time
+---------------------------------------------------------
+ 27.39 slack (MET)
+
+
+Startpoint: _42881_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[58] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _42881_/CLK (DFFQ_X1_7T5P0)
+ 2.90 7.32 ^ _42881_/Q (DFFQ_X1_7T5P0)
+ 0.43 7.74 v _24222_/ZN (CLKINV_X1_7T5P0)
+ 0.53 8.27 v output273/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.28 v la_oenb[58] (out)
+ 8.28 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.28 data arrival time
+---------------------------------------------------------
+ 27.47 slack (MET)
+
+
+Startpoint: _42882_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[59] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.44 4.44 clock network delay (propagated)
+ 0.00 4.44 ^ _42882_/CLK (DFFQ_X1_7T5P0)
+ 2.83 7.27 ^ _42882_/Q (DFFQ_X1_7T5P0)
+ 0.40 7.67 v _24221_/ZN (CLKINV_X1_7T5P0)
+ 0.53 8.20 v output274/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.20 v la_oenb[59] (out)
+ 8.20 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.20 data arrival time
+---------------------------------------------------------
+ 27.55 slack (MET)
+
+
+Startpoint: _45925_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: spi_sdo (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.13 4.13 clock network delay (propagated)
+ 0.00 4.13 ^ _45925_/CLK (DFFQ_X1_7T5P0)
+ 3.20 7.33 ^ _45925_/Q (DFFQ_X1_7T5P0)
+ 0.81 8.15 ^ output422/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.15 ^ spi_sdo (out)
+ 8.15 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.15 data arrival time
+---------------------------------------------------------
+ 27.60 slack (MET)
+
+
+Startpoint: _42877_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[54] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _42877_/CLK (DFFQ_X1_7T5P0)
+ 2.90 7.32 ^ _42877_/Q (DFFQ_X1_7T5P0)
+ 0.30 7.63 v _24226_/ZN (CLKINV_X1_7T5P0)
+ 0.51 8.13 v output269/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.13 v la_oenb[54] (out)
+ 8.13 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.13 data arrival time
+---------------------------------------------------------
+ 27.62 slack (MET)
+
+
+Startpoint: _42878_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[55] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _42878_/CLK (DFFQ_X1_7T5P0)
+ 2.88 7.30 ^ _42878_/Q (DFFQ_X1_7T5P0)
+ 0.29 7.60 v _24225_/ZN (CLKINV_X1_7T5P0)
+ 0.50 8.10 v output270/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.10 v la_oenb[55] (out)
+ 8.10 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.10 data arrival time
+---------------------------------------------------------
+ 27.65 slack (MET)
+
+
+Startpoint: _45057_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_iena[24] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _45057_/CLK (DFFQ_X1_7T5P0)
+ 2.76 7.18 ^ _45057_/Q (DFFQ_X1_7T5P0)
+ 0.37 7.54 v _24320_/ZN (CLKINV_X1_7T5P0)
+ 0.53 8.07 v output172/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.07 v la_iena[24] (out)
+ 8.07 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.07 data arrival time
+---------------------------------------------------------
+ 27.68 slack (MET)
+
+
+Startpoint: _45071_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: debug_mode (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _45071_/CLK (DFFQ_X1_7T5P0)
+ 2.84 7.25 ^ _45071_/Q (DFFQ_X1_7T5P0)
+ 0.80 8.04 ^ output143/Z (CLKBUF_X4_7T5P0)
+ 0.00 8.04 ^ debug_mode (out)
+ 8.04 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -8.04 data arrival time
+---------------------------------------------------------
+ 27.71 slack (MET)
+
+
+Startpoint: _42874_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[51] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _42874_/CLK (DFFQ_X1_7T5P0)
+ 2.52 6.93 ^ _42874_/Q (DFFQ_X1_7T5P0)
+ 0.49 7.42 v _24229_/ZN (CLKINV_X1_7T5P0)
+ 0.53 7.95 v output266/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.95 v la_oenb[51] (out)
+ 7.95 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.95 data arrival time
+---------------------------------------------------------
+ 27.80 slack (MET)
+
+
+Startpoint: _45067_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: gpio_inenb_pad (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _45067_/CLK (DFFQ_X1_7T5P0)
+ 1.06 5.47 ^ _45067_/Q (DFFQ_X1_7T5P0)
+ 1.49 6.96 v _24346_/ZN (CLKINV_X1_7T5P0)
+ 0.76 7.71 v output149/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.71 v gpio_inenb_pad (out)
+ 7.71 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.71 data arrival time
+---------------------------------------------------------
+ 28.04 slack (MET)
+
+
+Startpoint: _44990_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[21] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _44990_/CLK (DFFQ_X1_7T5P0)
+ 2.41 6.98 ^ _44990_/Q (DFFQ_X1_7T5P0)
+ 0.68 7.66 ^ output297/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.66 ^ la_output[21] (out)
+ 7.66 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.66 data arrival time
+---------------------------------------------------------
+ 28.09 slack (MET)
+
+
+Startpoint: _44991_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[22] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.56 4.56 clock network delay (propagated)
+ 0.00 4.56 ^ _44991_/CLK (DFFQ_X1_7T5P0)
+ 2.38 6.94 ^ _44991_/Q (DFFQ_X1_7T5P0)
+ 0.68 7.62 ^ output298/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.62 ^ la_output[22] (out)
+ 7.62 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.62 data arrival time
+---------------------------------------------------------
+ 28.13 slack (MET)
+
+
+Startpoint: _44992_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[23] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _44992_/CLK (DFFQ_X1_7T5P0)
+ 2.36 6.93 ^ _44992_/Q (DFFQ_X1_7T5P0)
+ 0.68 7.60 ^ output299/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.60 ^ la_output[23] (out)
+ 7.60 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.60 data arrival time
+---------------------------------------------------------
+ 28.15 slack (MET)
+
+
+Startpoint: _42876_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[53] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _42876_/CLK (DFFQ_X1_7T5P0)
+ 2.19 6.61 ^ _42876_/Q (DFFQ_X1_7T5P0)
+ 0.42 7.03 v _24227_/ZN (CLKINV_X1_7T5P0)
+ 0.50 7.54 v output268/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.54 v la_oenb[53] (out)
+ 7.54 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.54 data arrival time
+---------------------------------------------------------
+ 28.21 slack (MET)
+
+
+Startpoint: _42965_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[46] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42965_/CLK (DFFQ_X1_7T5P0)
+ 2.17 6.85 ^ _42965_/Q (DFFQ_X1_7T5P0)
+ 0.65 7.51 ^ output324/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.51 ^ la_output[46] (out)
+ 7.51 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.51 data arrival time
+---------------------------------------------------------
+ 28.24 slack (MET)
+
+
+Startpoint: _44995_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[26] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _44995_/CLK (DFFQ_X1_7T5P0)
+ 2.25 6.82 ^ _44995_/Q (DFFQ_X1_7T5P0)
+ 0.67 7.49 ^ output302/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.49 ^ la_output[26] (out)
+ 7.49 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.49 data arrival time
+---------------------------------------------------------
+ 28.26 slack (MET)
+
+
+Startpoint: _45002_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[1] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _45002_/CLK (DFFQ_X1_7T5P0)
+ 2.06 6.63 ^ _45002_/Q (DFFQ_X1_7T5P0)
+ 0.35 6.98 v _24279_/ZN (CLKINV_X1_7T5P0)
+ 0.49 7.47 v output231/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.47 v la_oenb[1] (out)
+ 7.47 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.47 data arrival time
+---------------------------------------------------------
+ 28.28 slack (MET)
+
+
+Startpoint: _44987_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[18] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.56 4.56 clock network delay (propagated)
+ 0.00 4.56 ^ _44987_/CLK (DFFQ_X1_7T5P0)
+ 2.23 6.78 ^ _44987_/Q (DFFQ_X1_7T5P0)
+ 0.66 7.45 ^ output293/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.45 ^ la_output[18] (out)
+ 7.45 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.45 data arrival time
+---------------------------------------------------------
+ 28.30 slack (MET)
+
+
+Startpoint: _44993_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[24] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.56 4.56 clock network delay (propagated)
+ 0.00 4.56 ^ _44993_/CLK (DFFQ_X1_7T5P0)
+ 2.18 6.74 ^ _44993_/Q (DFFQ_X1_7T5P0)
+ 0.66 7.40 ^ output300/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.40 ^ la_output[24] (out)
+ 7.40 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.40 data arrival time
+---------------------------------------------------------
+ 28.35 slack (MET)
+
+
+Startpoint: _42873_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[50] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _42873_/CLK (DFFQ_X1_7T5P0)
+ 2.03 6.45 ^ _42873_/Q (DFFQ_X1_7T5P0)
+ 0.44 6.89 v _24230_/ZN (CLKINV_X1_7T5P0)
+ 0.50 7.39 v output265/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.39 v la_oenb[50] (out)
+ 7.39 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.39 data arrival time
+---------------------------------------------------------
+ 28.36 slack (MET)
+
+
+Startpoint: _44989_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[20] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.56 4.56 clock network delay (propagated)
+ 0.00 4.56 ^ _44989_/CLK (DFFQ_X1_7T5P0)
+ 2.17 6.73 ^ _44989_/Q (DFFQ_X1_7T5P0)
+ 0.66 7.39 ^ output296/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.39 ^ la_output[20] (out)
+ 7.39 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.39 data arrival time
+---------------------------------------------------------
+ 28.36 slack (MET)
+
+
+Startpoint: _44988_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[19] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.56 4.56 clock network delay (propagated)
+ 0.00 4.56 ^ _44988_/CLK (DFFQ_X1_7T5P0)
+ 2.17 6.72 ^ _44988_/Q (DFFQ_X1_7T5P0)
+ 0.66 7.39 ^ output294/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.39 ^ la_output[19] (out)
+ 7.39 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.39 data arrival time
+---------------------------------------------------------
+ 28.36 slack (MET)
+
+
+Startpoint: _42964_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[45] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42964_/CLK (DFFQ_X1_7T5P0)
+ 2.01 6.69 ^ _42964_/Q (DFFQ_X1_7T5P0)
+ 0.64 7.33 ^ output323/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.33 ^ la_output[45] (out)
+ 7.33 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.33 data arrival time
+---------------------------------------------------------
+ 28.42 slack (MET)
+
+
+Startpoint: _45005_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[4] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _45005_/CLK (DFFQ_X1_7T5P0)
+ 1.83 6.26 ^ _45005_/Q (DFFQ_X1_7T5P0)
+ 0.52 6.79 v _24276_/ZN (CLKINV_X1_7T5P0)
+ 0.52 7.30 v output264/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.31 v la_oenb[4] (out)
+ 7.31 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.31 data arrival time
+---------------------------------------------------------
+ 28.44 slack (MET)
+
+
+Startpoint: _45001_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[0] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _45001_/CLK (DFFQ_X1_7T5P0)
+ 1.95 6.52 ^ _45001_/Q (DFFQ_X1_7T5P0)
+ 0.26 6.79 v _24280_/ZN (CLKINV_X1_7T5P0)
+ 0.46 7.25 v output220/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.26 v la_oenb[0] (out)
+ 7.26 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.26 data arrival time
+---------------------------------------------------------
+ 28.49 slack (MET)
+
+
+Startpoint: _45000_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[31] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.66 4.66 clock network delay (propagated)
+ 0.00 4.66 ^ _45000_/CLK (DFFQ_X1_7T5P0)
+ 1.95 6.61 ^ _45000_/Q (DFFQ_X1_7T5P0)
+ 0.63 7.24 ^ output308/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.24 ^ la_output[31] (out)
+ 7.24 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.24 data arrival time
+---------------------------------------------------------
+ 28.51 slack (MET)
+
+
+Startpoint: _44998_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[29] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.66 4.66 clock network delay (propagated)
+ 0.00 4.66 ^ _44998_/CLK (DFFQ_X1_7T5P0)
+ 1.95 6.60 ^ _44998_/Q (DFFQ_X1_7T5P0)
+ 0.63 7.23 ^ output305/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.23 ^ la_output[29] (out)
+ 7.23 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.23 data arrival time
+---------------------------------------------------------
+ 28.52 slack (MET)
+
+
+Startpoint: _45004_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[3] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _45004_/CLK (DFFQ_X1_7T5P0)
+ 1.90 6.32 ^ _45004_/Q (DFFQ_X1_7T5P0)
+ 0.41 6.73 v _24277_/ZN (CLKINV_X1_7T5P0)
+ 0.49 7.21 v output253/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.21 v la_oenb[3] (out)
+ 7.21 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.21 data arrival time
+---------------------------------------------------------
+ 28.54 slack (MET)
+
+
+Startpoint: _44994_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[25] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.66 4.66 clock network delay (propagated)
+ 0.00 4.66 ^ _44994_/CLK (DFFQ_X1_7T5P0)
+ 1.90 6.56 ^ _44994_/Q (DFFQ_X1_7T5P0)
+ 0.62 7.18 ^ output301/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.18 ^ la_output[25] (out)
+ 7.18 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.18 data arrival time
+---------------------------------------------------------
+ 28.57 slack (MET)
+
+
+Startpoint: _45003_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[2] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _45003_/CLK (DFFQ_X1_7T5P0)
+ 1.16 5.57 ^ _45003_/Q (DFFQ_X1_7T5P0)
+ 0.98 6.55 v _24278_/ZN (CLKINV_X1_7T5P0)
+ 0.62 7.17 v output242/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.17 v la_oenb[2] (out)
+ 7.17 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.17 data arrival time
+---------------------------------------------------------
+ 28.58 slack (MET)
+
+
+Startpoint: _45008_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[7] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _45008_/CLK (DFFQ_X1_7T5P0)
+ 1.88 6.31 ^ _45008_/Q (DFFQ_X1_7T5P0)
+ 0.37 6.68 v _24273_/ZN (CLKINV_X1_7T5P0)
+ 0.48 7.16 v output281/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.17 v la_oenb[7] (out)
+ 7.17 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.17 data arrival time
+---------------------------------------------------------
+ 28.58 slack (MET)
+
+
+Startpoint: _42961_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[42] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _42961_/CLK (DFFQ_X1_7T5P0)
+ 1.96 6.52 ^ _42961_/Q (DFFQ_X1_7T5P0)
+ 0.63 7.15 ^ output320/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.15 ^ la_output[42] (out)
+ 7.15 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.15 data arrival time
+---------------------------------------------------------
+ 28.60 slack (MET)
+
+
+Startpoint: _45021_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[20] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.47 4.47 clock network delay (propagated)
+ 0.00 4.47 ^ _45021_/CLK (DFFQ_X1_7T5P0)
+ 1.80 6.27 ^ _45021_/Q (DFFQ_X1_7T5P0)
+ 0.35 6.63 v _24260_/ZN (CLKINV_X1_7T5P0)
+ 0.47 7.10 v output232/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.10 v la_oenb[20] (out)
+ 7.10 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.10 data arrival time
+---------------------------------------------------------
+ 28.65 slack (MET)
+
+
+Startpoint: _42962_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[43] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _42962_/CLK (DFFQ_X1_7T5P0)
+ 1.88 6.45 ^ _42962_/Q (DFFQ_X1_7T5P0)
+ 0.62 7.06 ^ output321/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.07 ^ la_output[43] (out)
+ 7.07 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.07 data arrival time
+---------------------------------------------------------
+ 28.68 slack (MET)
+
+
+Startpoint: _45018_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[17] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _45018_/CLK (DFFQ_X1_7T5P0)
+ 1.63 6.04 ^ _45018_/Q (DFFQ_X1_7T5P0)
+ 0.48 6.52 v _24263_/ZN (CLKINV_X1_7T5P0)
+ 0.49 7.02 v output228/Z (CLKBUF_X4_7T5P0)
+ 0.00 7.02 v la_oenb[17] (out)
+ 7.02 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -7.02 data arrival time
+---------------------------------------------------------
+ 28.73 slack (MET)
+
+
+Startpoint: _44997_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[28] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.66 4.66 clock network delay (propagated)
+ 0.00 4.66 ^ _44997_/CLK (DFFQ_X1_7T5P0)
+ 1.73 6.40 ^ _44997_/Q (DFFQ_X1_7T5P0)
+ 0.60 6.99 ^ output304/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.99 ^ la_output[28] (out)
+ 6.99 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.99 data arrival time
+---------------------------------------------------------
+ 28.76 slack (MET)
+
+
+Startpoint: _44986_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[17] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.35 4.35 clock network delay (propagated)
+ 0.00 4.35 ^ _44986_/CLK (DFFQ_X1_7T5P0)
+ 2.00 6.35 ^ _44986_/Q (DFFQ_X1_7T5P0)
+ 0.63 6.99 ^ output292/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.99 ^ la_output[17] (out)
+ 6.99 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.99 data arrival time
+---------------------------------------------------------
+ 28.76 slack (MET)
+
+
+Startpoint: _45029_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[28] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.46 4.46 clock network delay (propagated)
+ 0.00 4.46 ^ _45029_/CLK (DFFQ_X1_7T5P0)
+ 1.78 6.24 ^ _45029_/Q (DFFQ_X1_7T5P0)
+ 0.27 6.51 v _24252_/ZN (CLKINV_X1_7T5P0)
+ 0.45 6.97 v output240/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.97 v la_oenb[28] (out)
+ 6.97 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.97 data arrival time
+---------------------------------------------------------
+ 28.78 slack (MET)
+
+
+Startpoint: _44999_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[30] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _44999_/CLK (DFFQ_X1_7T5P0)
+ 1.78 6.34 ^ _44999_/Q (DFFQ_X1_7T5P0)
+ 0.60 6.95 ^ output307/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.95 ^ la_output[30] (out)
+ 6.95 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.95 data arrival time
+---------------------------------------------------------
+ 28.80 slack (MET)
+
+
+Startpoint: _45023_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[22] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.47 4.47 clock network delay (propagated)
+ 0.00 4.47 ^ _45023_/CLK (DFFQ_X1_7T5P0)
+ 1.68 6.15 ^ _45023_/Q (DFFQ_X1_7T5P0)
+ 0.32 6.48 v _24258_/ZN (CLKINV_X1_7T5P0)
+ 0.46 6.94 v output234/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.94 v la_oenb[22] (out)
+ 6.94 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.94 data arrival time
+---------------------------------------------------------
+ 28.81 slack (MET)
+
+
+Startpoint: _45020_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[19] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.47 4.47 clock network delay (propagated)
+ 0.00 4.47 ^ _45020_/CLK (DFFQ_X1_7T5P0)
+ 1.61 6.08 ^ _45020_/Q (DFFQ_X1_7T5P0)
+ 0.35 6.43 v _24261_/ZN (CLKINV_X1_7T5P0)
+ 0.46 6.89 v output230/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.89 v la_oenb[19] (out)
+ 6.89 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.89 data arrival time
+---------------------------------------------------------
+ 28.86 slack (MET)
+
+
+Startpoint: _45024_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[23] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.47 4.47 clock network delay (propagated)
+ 0.00 4.47 ^ _45024_/CLK (DFFQ_X1_7T5P0)
+ 1.64 6.11 ^ _45024_/Q (DFFQ_X1_7T5P0)
+ 0.28 6.40 v _24257_/ZN (CLKINV_X1_7T5P0)
+ 0.45 6.85 v output235/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.85 v la_oenb[23] (out)
+ 6.85 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.85 data arrival time
+---------------------------------------------------------
+ 28.90 slack (MET)
+
+
+Startpoint: _44971_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[2] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.66 4.66 clock network delay (propagated)
+ 0.00 4.66 ^ _44971_/CLK (DFFQ_X1_7T5P0)
+ 1.58 6.25 ^ _44971_/Q (DFFQ_X1_7T5P0)
+ 0.59 6.83 ^ output306/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.83 ^ la_output[2] (out)
+ 6.83 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.83 data arrival time
+---------------------------------------------------------
+ 28.92 slack (MET)
+
+
+Startpoint: _45019_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[18] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.47 4.47 clock network delay (propagated)
+ 0.00 4.47 ^ _45019_/CLK (DFFQ_X1_7T5P0)
+ 1.58 6.06 ^ _45019_/Q (DFFQ_X1_7T5P0)
+ 0.31 6.37 v _24262_/ZN (CLKINV_X1_7T5P0)
+ 0.45 6.82 v output229/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.83 v la_oenb[18] (out)
+ 6.83 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.83 data arrival time
+---------------------------------------------------------
+ 28.92 slack (MET)
+
+
+Startpoint: _44970_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[1] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.60 4.60 clock network delay (propagated)
+ 0.00 4.60 ^ _44970_/CLK (DFFQ_X1_7T5P0)
+ 1.62 6.21 ^ _44970_/Q (DFFQ_X1_7T5P0)
+ 0.59 6.81 ^ output295/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.81 ^ la_output[1] (out)
+ 6.81 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.81 data arrival time
+---------------------------------------------------------
+ 28.94 slack (MET)
+
+
+Startpoint: _45017_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[16] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.47 4.47 clock network delay (propagated)
+ 0.00 4.47 ^ _45017_/CLK (DFFQ_X1_7T5P0)
+ 1.53 6.00 ^ _45017_/Q (DFFQ_X1_7T5P0)
+ 0.34 6.34 v _24264_/ZN (CLKINV_X1_7T5P0)
+ 0.46 6.80 v output227/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.80 v la_oenb[16] (out)
+ 6.80 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.80 data arrival time
+---------------------------------------------------------
+ 28.95 slack (MET)
+
+
+Startpoint: _45025_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[24] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _45025_/CLK (DFFQ_X1_7T5P0)
+ 1.57 5.99 ^ _45025_/Q (DFFQ_X1_7T5P0)
+ 0.34 6.33 v _24256_/ZN (CLKINV_X1_7T5P0)
+ 0.46 6.79 v output236/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.79 v la_oenb[24] (out)
+ 6.79 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.79 data arrival time
+---------------------------------------------------------
+ 28.96 slack (MET)
+
+
+Startpoint: _45026_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[25] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.47 4.47 clock network delay (propagated)
+ 0.00 4.47 ^ _45026_/CLK (DFFQ_X1_7T5P0)
+ 1.48 5.95 ^ _45026_/Q (DFFQ_X1_7T5P0)
+ 0.35 6.29 v _24255_/ZN (CLKINV_X1_7T5P0)
+ 0.45 6.75 v output237/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.75 v la_oenb[25] (out)
+ 6.75 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.75 data arrival time
+---------------------------------------------------------
+ 29.00 slack (MET)
+
+
+Startpoint: _45022_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[21] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.47 4.47 clock network delay (propagated)
+ 0.00 4.47 ^ _45022_/CLK (DFFQ_X1_7T5P0)
+ 1.48 5.96 ^ _45022_/Q (DFFQ_X1_7T5P0)
+ 0.30 6.25 v _24259_/ZN (CLKINV_X1_7T5P0)
+ 0.45 6.70 v output233/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.70 v la_oenb[21] (out)
+ 6.70 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.70 data arrival time
+---------------------------------------------------------
+ 29.05 slack (MET)
+
+
+Startpoint: _44979_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[10] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.35 4.35 clock network delay (propagated)
+ 0.00 4.35 ^ _44979_/CLK (DFFQ_X1_7T5P0)
+ 1.63 5.98 ^ _44979_/Q (DFFQ_X1_7T5P0)
+ 0.59 6.57 ^ output285/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.57 ^ la_output[10] (out)
+ 6.57 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.57 data arrival time
+---------------------------------------------------------
+ 29.18 slack (MET)
+
+
+Startpoint: _44969_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[0] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.38 4.38 clock network delay (propagated)
+ 0.00 4.38 ^ _44969_/CLK (DFFQ_X1_7T5P0)
+ 1.61 5.99 ^ _44969_/Q (DFFQ_X1_7T5P0)
+ 0.58 6.56 ^ output284/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.57 ^ la_output[0] (out)
+ 6.57 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.57 data arrival time
+---------------------------------------------------------
+ 29.18 slack (MET)
+
+
+Startpoint: _45006_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[5] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _45006_/CLK (DFFQ_X1_7T5P0)
+ 0.98 5.40 ^ _45006_/Q (DFFQ_X1_7T5P0)
+ 0.63 6.03 v _24275_/ZN (CLKINV_X1_7T5P0)
+ 0.53 6.56 v output275/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.56 v la_oenb[5] (out)
+ 6.56 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.56 data arrival time
+---------------------------------------------------------
+ 29.19 slack (MET)
+
+
+Startpoint: _45007_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[6] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _45007_/CLK (DFFQ_X1_7T5P0)
+ 1.04 5.46 ^ _45007_/Q (DFFQ_X1_7T5P0)
+ 0.58 6.04 v _24274_/ZN (CLKINV_X1_7T5P0)
+ 0.52 6.56 v output280/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.56 v la_oenb[6] (out)
+ 6.56 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.56 data arrival time
+---------------------------------------------------------
+ 29.19 slack (MET)
+
+
+Startpoint: _45922_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: spi_sdoenb (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _45922_/CLK (DFFQ_X1_7T5P0)
+ 1.29 5.92 ^ _45922_/Q (DFFQ_X1_7T5P0)
+ 0.22 6.14 v _24359_/ZN (CLKINV_X1_7T5P0)
+ 0.41 6.56 v output423/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.56 v spi_sdoenb (out)
+ 6.56 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.56 data arrival time
+---------------------------------------------------------
+ 29.19 slack (MET)
+
+
+Startpoint: _44972_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[3] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.38 4.38 clock network delay (propagated)
+ 0.00 4.38 ^ _44972_/CLK (DFFQ_X1_7T5P0)
+ 1.57 5.95 ^ _44972_/Q (DFFQ_X1_7T5P0)
+ 0.57 6.52 ^ output317/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.52 ^ la_output[3] (out)
+ 6.52 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.52 data arrival time
+---------------------------------------------------------
+ 29.23 slack (MET)
+
+
+Startpoint: _45028_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[27] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.47 4.47 clock network delay (propagated)
+ 0.00 4.47 ^ _45028_/CLK (DFFQ_X1_7T5P0)
+ 1.31 5.78 ^ _45028_/Q (DFFQ_X1_7T5P0)
+ 0.28 6.06 v _24253_/ZN (CLKINV_X1_7T5P0)
+ 0.43 6.49 v output239/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.49 v la_oenb[27] (out)
+ 6.49 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.49 data arrival time
+---------------------------------------------------------
+ 29.26 slack (MET)
+
+
+Startpoint: _45027_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[26] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.41 4.41 clock network delay (propagated)
+ 0.00 4.41 ^ _45027_/CLK (DFFQ_X1_7T5P0)
+ 1.34 5.75 ^ _45027_/Q (DFFQ_X1_7T5P0)
+ 0.28 6.03 v _24254_/ZN (CLKINV_X1_7T5P0)
+ 0.44 6.47 v output238/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.47 v la_oenb[26] (out)
+ 6.47 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.47 data arrival time
+---------------------------------------------------------
+ 29.28 slack (MET)
+
+
+Startpoint: _45032_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[31] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.47 4.47 clock network delay (propagated)
+ 0.00 4.47 ^ _45032_/CLK (DFFQ_X1_7T5P0)
+ 1.33 5.80 ^ _45032_/Q (DFFQ_X1_7T5P0)
+ 0.23 6.03 v _24249_/ZN (CLKINV_X1_7T5P0)
+ 0.42 6.45 v output244/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.45 v la_oenb[31] (out)
+ 6.45 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.45 data arrival time
+---------------------------------------------------------
+ 29.30 slack (MET)
+
+
+Startpoint: _45922_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: spi_csb (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.63 4.63 clock network delay (propagated)
+ 0.00 4.63 ^ _45922_/CLK (DFFQ_X1_7T5P0)
+ 1.29 5.92 ^ _45922_/Q (DFFQ_X1_7T5P0)
+ 0.52 6.44 ^ output419/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.44 ^ spi_csb (out)
+ 6.44 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.44 data arrival time
+---------------------------------------------------------
+ 29.31 slack (MET)
+
+
+Startpoint: _44973_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[4] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.38 4.38 clock network delay (propagated)
+ 0.00 4.38 ^ _44973_/CLK (DFFQ_X1_7T5P0)
+ 1.50 5.87 ^ _44973_/Q (DFFQ_X1_7T5P0)
+ 0.55 6.43 ^ output328/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.43 ^ la_output[4] (out)
+ 6.43 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.43 data arrival time
+---------------------------------------------------------
+ 29.32 slack (MET)
+
+
+Startpoint: _45030_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[29] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.46 4.46 clock network delay (propagated)
+ 0.00 4.46 ^ _45030_/CLK (DFFQ_X1_7T5P0)
+ 1.24 5.70 ^ _45030_/Q (DFFQ_X1_7T5P0)
+ 0.28 5.99 v _24251_/ZN (CLKINV_X1_7T5P0)
+ 0.43 6.42 v output241/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.42 v la_oenb[29] (out)
+ 6.42 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.42 data arrival time
+---------------------------------------------------------
+ 29.33 slack (MET)
+
+
+Startpoint: _45031_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[30] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.47 4.47 clock network delay (propagated)
+ 0.00 4.47 ^ _45031_/CLK (DFFQ_X1_7T5P0)
+ 1.25 5.72 ^ _45031_/Q (DFFQ_X1_7T5P0)
+ 0.24 5.96 v _24250_/ZN (CLKINV_X1_7T5P0)
+ 0.42 6.37 v output243/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.37 v la_oenb[30] (out)
+ 6.37 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.37 data arrival time
+---------------------------------------------------------
+ 29.38 slack (MET)
+
+
+Startpoint: _42966_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[47] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42966_/CLK (DFFQ_X1_7T5P0)
+ 1.20 5.88 ^ _42966_/Q (DFFQ_X1_7T5P0)
+ 0.49 6.37 ^ output325/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.37 ^ la_output[47] (out)
+ 6.37 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.37 data arrival time
+---------------------------------------------------------
+ 29.38 slack (MET)
+
+
+Startpoint: _42959_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[40] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42959_/CLK (DFFQ_X1_7T5P0)
+ 1.19 5.87 ^ _42959_/Q (DFFQ_X1_7T5P0)
+ 0.50 6.37 ^ output318/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.37 ^ la_output[40] (out)
+ 6.37 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.37 data arrival time
+---------------------------------------------------------
+ 29.38 slack (MET)
+
+
+Startpoint: _42960_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[41] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42960_/CLK (DFFQ_X1_7T5P0)
+ 1.15 5.83 ^ _42960_/Q (DFFQ_X1_7T5P0)
+ 0.47 6.30 ^ output319/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.30 ^ la_output[41] (out)
+ 6.30 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.30 data arrival time
+---------------------------------------------------------
+ 29.45 slack (MET)
+
+
+Startpoint: _42955_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[36] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42955_/CLK (DFFQ_X1_7T5P0)
+ 1.13 5.81 ^ _42955_/Q (DFFQ_X1_7T5P0)
+ 0.48 6.29 ^ output313/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.29 ^ la_output[36] (out)
+ 6.29 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.29 data arrival time
+---------------------------------------------------------
+ 29.46 slack (MET)
+
+
+Startpoint: _42952_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[33] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.65 4.65 clock network delay (propagated)
+ 0.00 4.65 ^ _42952_/CLK (DFFQ_X1_7T5P0)
+ 1.15 5.81 ^ _42952_/Q (DFFQ_X1_7T5P0)
+ 0.48 6.29 ^ output310/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.29 ^ la_output[33] (out)
+ 6.29 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.29 data arrival time
+---------------------------------------------------------
+ 29.46 slack (MET)
+
+
+Startpoint: _42956_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[37] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42956_/CLK (DFFQ_X1_7T5P0)
+ 1.12 5.79 ^ _42956_/Q (DFFQ_X1_7T5P0)
+ 0.47 6.27 ^ output314/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.27 ^ la_output[37] (out)
+ 6.27 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.27 data arrival time
+---------------------------------------------------------
+ 29.48 slack (MET)
+
+
+Startpoint: _42957_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[38] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42957_/CLK (DFFQ_X1_7T5P0)
+ 1.11 5.79 ^ _42957_/Q (DFFQ_X1_7T5P0)
+ 0.47 6.26 ^ output315/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.26 ^ la_output[38] (out)
+ 6.26 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.26 data arrival time
+---------------------------------------------------------
+ 29.49 slack (MET)
+
+
+Startpoint: _42963_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[44] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42963_/CLK (DFFQ_X1_7T5P0)
+ 1.11 5.79 ^ _42963_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.25 ^ output322/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.25 ^ la_output[44] (out)
+ 6.25 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.25 data arrival time
+---------------------------------------------------------
+ 29.50 slack (MET)
+
+
+Startpoint: _42969_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[50] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42969_/CLK (DFFQ_X1_7T5P0)
+ 1.10 5.78 ^ _42969_/Q (DFFQ_X1_7T5P0)
+ 0.47 6.24 ^ output329/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.24 ^ la_output[50] (out)
+ 6.24 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.24 data arrival time
+---------------------------------------------------------
+ 29.51 slack (MET)
+
+
+Startpoint: _42958_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[39] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42958_/CLK (DFFQ_X1_7T5P0)
+ 1.08 5.75 ^ _42958_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.21 ^ output316/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.21 ^ la_output[39] (out)
+ 6.21 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.21 data arrival time
+---------------------------------------------------------
+ 29.54 slack (MET)
+
+
+Startpoint: _45012_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[11] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _45012_/CLK (DFFQ_X1_7T5P0)
+ 0.97 5.47 ^ _45012_/Q (DFFQ_X1_7T5P0)
+ 0.29 5.77 v _24269_/ZN (CLKINV_X1_7T5P0)
+ 0.42 6.19 v output222/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.19 v la_oenb[11] (out)
+ 6.19 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.19 data arrival time
+---------------------------------------------------------
+ 29.56 slack (MET)
+
+
+Startpoint: _42953_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[34] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.68 4.68 clock network delay (propagated)
+ 0.00 4.68 ^ _42953_/CLK (DFFQ_X1_7T5P0)
+ 1.03 5.72 ^ _42953_/Q (DFFQ_X1_7T5P0)
+ 0.44 6.16 ^ output311/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.16 ^ la_output[34] (out)
+ 6.16 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.16 data arrival time
+---------------------------------------------------------
+ 29.59 slack (MET)
+
+
+Startpoint: _42951_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[32] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.65 4.65 clock network delay (propagated)
+ 0.00 4.65 ^ _42951_/CLK (DFFQ_X1_7T5P0)
+ 1.05 5.71 ^ _42951_/Q (DFFQ_X1_7T5P0)
+ 0.45 6.16 ^ output309/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.16 ^ la_output[32] (out)
+ 6.16 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.16 data arrival time
+---------------------------------------------------------
+ 29.59 slack (MET)
+
+
+Startpoint: _45009_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[8] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _45009_/CLK (DFFQ_X1_7T5P0)
+ 1.04 5.54 ^ _45009_/Q (DFFQ_X1_7T5P0)
+ 0.21 5.76 v _24272_/ZN (CLKINV_X1_7T5P0)
+ 0.40 6.15 v output282/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.15 v la_oenb[8] (out)
+ 6.15 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.15 data arrival time
+---------------------------------------------------------
+ 29.60 slack (MET)
+
+
+Startpoint: _45010_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[9] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _45010_/CLK (DFFQ_X1_7T5P0)
+ 1.04 5.54 ^ _45010_/Q (DFFQ_X1_7T5P0)
+ 0.20 5.74 v _24271_/ZN (CLKINV_X1_7T5P0)
+ 0.40 6.14 v output283/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.14 v la_oenb[9] (out)
+ 6.14 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.14 data arrival time
+---------------------------------------------------------
+ 29.61 slack (MET)
+
+
+Startpoint: _45016_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[15] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _45016_/CLK (DFFQ_X1_7T5P0)
+ 1.03 5.52 ^ _45016_/Q (DFFQ_X1_7T5P0)
+ 0.21 5.73 v _24265_/ZN (CLKINV_X1_7T5P0)
+ 0.40 6.13 v output226/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.13 v la_oenb[15] (out)
+ 6.13 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.13 data arrival time
+---------------------------------------------------------
+ 29.62 slack (MET)
+
+
+Startpoint: _44996_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[27] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _44996_/CLK (DFFQ_X1_7T5P0)
+ 1.09 5.66 ^ _44996_/Q (DFFQ_X1_7T5P0)
+ 0.47 6.13 ^ output303/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.13 ^ la_output[27] (out)
+ 6.13 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.13 data arrival time
+---------------------------------------------------------
+ 29.62 slack (MET)
+
+
+Startpoint: _42954_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[35] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.57 4.57 clock network delay (propagated)
+ 0.00 4.57 ^ _42954_/CLK (DFFQ_X1_7T5P0)
+ 1.09 5.66 ^ _42954_/Q (DFFQ_X1_7T5P0)
+ 0.47 6.13 ^ output312/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.13 ^ la_output[35] (out)
+ 6.13 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.13 data arrival time
+---------------------------------------------------------
+ 29.62 slack (MET)
+
+
+Startpoint: _45013_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[12] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _45013_/CLK (DFFQ_X1_7T5P0)
+ 0.98 5.48 ^ _45013_/Q (DFFQ_X1_7T5P0)
+ 0.24 5.72 v _24268_/ZN (CLKINV_X1_7T5P0)
+ 0.41 6.13 v output223/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.13 v la_oenb[12] (out)
+ 6.13 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.13 data arrival time
+---------------------------------------------------------
+ 29.62 slack (MET)
+
+
+Startpoint: _45011_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[10] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _45011_/CLK (DFFQ_X1_7T5P0)
+ 0.93 5.43 ^ _45011_/Q (DFFQ_X1_7T5P0)
+ 0.28 5.70 v _24270_/ZN (CLKINV_X1_7T5P0)
+ 0.42 6.12 v output221/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.12 v la_oenb[10] (out)
+ 6.12 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.12 data arrival time
+---------------------------------------------------------
+ 29.63 slack (MET)
+
+
+Startpoint: _46500_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: flash_io0_oeb (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.89 4.89 clock network delay (propagated)
+ 0.00 4.89 ^ _46500_/CLK (DFFQ_X1_7T5P0)
+ 0.83 5.72 ^ _46500_/Q (DFFQ_X1_7T5P0)
+ 0.38 6.10 ^ output148/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.10 ^ flash_io0_oeb (out)
+ 6.10 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.10 data arrival time
+---------------------------------------------------------
+ 29.65 slack (MET)
+
+
+Startpoint: _46501_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: flash_io0_do (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.89 4.89 clock network delay (propagated)
+ 0.00 4.89 ^ _46501_/CLK (DFFQ_X1_7T5P0)
+ 0.81 5.70 ^ _46501_/Q (DFFQ_X1_7T5P0)
+ 0.37 6.06 ^ output147/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.06 ^ flash_io0_do (out)
+ 6.06 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.06 data arrival time
+---------------------------------------------------------
+ 29.69 slack (MET)
+
+
+Startpoint: _45014_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[13] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _45014_/CLK (DFFQ_X1_7T5P0)
+ 0.96 5.46 ^ _45014_/Q (DFFQ_X1_7T5P0)
+ 0.19 5.65 v _24267_/ZN (CLKINV_X1_7T5P0)
+ 0.39 6.04 v output224/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.04 v la_oenb[13] (out)
+ 6.04 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.04 data arrival time
+---------------------------------------------------------
+ 29.71 slack (MET)
+
+
+Startpoint: _42970_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[51] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42970_/CLK (DFFQ_X1_7T5P0)
+ 1.12 5.55 ^ _42970_/Q (DFFQ_X1_7T5P0)
+ 0.48 6.04 ^ output330/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.04 ^ la_output[51] (out)
+ 6.04 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.04 data arrival time
+---------------------------------------------------------
+ 29.71 slack (MET)
+
+
+Startpoint: _44980_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[11] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.35 4.35 clock network delay (propagated)
+ 0.00 4.35 ^ _44980_/CLK (DFFQ_X1_7T5P0)
+ 1.18 5.53 ^ _44980_/Q (DFFQ_X1_7T5P0)
+ 0.50 6.03 ^ output286/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.03 ^ la_output[11] (out)
+ 6.03 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.03 data arrival time
+---------------------------------------------------------
+ 29.72 slack (MET)
+
+
+Startpoint: _42975_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[56] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.51 4.51 clock network delay (propagated)
+ 0.00 4.51 ^ _42975_/CLK (DFFQ_X1_7T5P0)
+ 1.06 5.57 ^ _42975_/Q (DFFQ_X1_7T5P0)
+ 0.46 6.02 ^ output335/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.02 ^ la_output[56] (out)
+ 6.02 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.02 data arrival time
+---------------------------------------------------------
+ 29.73 slack (MET)
+
+
+Startpoint: _45015_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_oenb[14] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _45015_/CLK (DFFQ_X1_7T5P0)
+ 0.95 5.44 ^ _45015_/Q (DFFQ_X1_7T5P0)
+ 0.19 5.64 v _24266_/ZN (CLKINV_X1_7T5P0)
+ 0.39 6.02 v output225/Z (CLKBUF_X4_7T5P0)
+ 0.00 6.02 v la_oenb[14] (out)
+ 6.02 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -6.02 data arrival time
+---------------------------------------------------------
+ 29.73 slack (MET)
+
+
+Startpoint: _44982_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[13] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.35 4.35 clock network delay (propagated)
+ 0.00 4.35 ^ _44982_/CLK (DFFQ_X1_7T5P0)
+ 1.16 5.51 ^ _44982_/Q (DFFQ_X1_7T5P0)
+ 0.48 5.99 ^ output288/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.99 ^ la_output[13] (out)
+ 5.99 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.99 data arrival time
+---------------------------------------------------------
+ 29.76 slack (MET)
+
+
+Startpoint: _44981_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[12] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.35 4.35 clock network delay (propagated)
+ 0.00 4.35 ^ _44981_/CLK (DFFQ_X1_7T5P0)
+ 1.12 5.47 ^ _44981_/Q (DFFQ_X1_7T5P0)
+ 0.48 5.95 ^ output287/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.95 ^ la_output[12] (out)
+ 5.95 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.95 data arrival time
+---------------------------------------------------------
+ 29.80 slack (MET)
+
+
+Startpoint: _42977_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[58] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.51 4.51 clock network delay (propagated)
+ 0.00 4.51 ^ _42977_/CLK (DFFQ_X1_7T5P0)
+ 1.00 5.51 ^ _42977_/Q (DFFQ_X1_7T5P0)
+ 0.44 5.95 ^ output337/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.95 ^ la_output[58] (out)
+ 5.95 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.95 data arrival time
+---------------------------------------------------------
+ 29.80 slack (MET)
+
+
+Startpoint: _42972_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[53] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.51 4.51 clock network delay (propagated)
+ 0.00 4.51 ^ _42972_/CLK (DFFQ_X1_7T5P0)
+ 0.99 5.50 ^ _42972_/Q (DFFQ_X1_7T5P0)
+ 0.43 5.94 ^ output332/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.94 ^ la_output[53] (out)
+ 5.94 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.94 data arrival time
+---------------------------------------------------------
+ 29.81 slack (MET)
+
+
+Startpoint: _42968_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[49] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42968_/CLK (DFFQ_X1_7T5P0)
+ 1.05 5.48 ^ _42968_/Q (DFFQ_X1_7T5P0)
+ 0.45 5.93 ^ output327/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.93 ^ la_output[49] (out)
+ 5.93 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.93 data arrival time
+---------------------------------------------------------
+ 29.82 slack (MET)
+
+
+Startpoint: _42981_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[62] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.51 4.51 clock network delay (propagated)
+ 0.00 4.51 ^ _42981_/CLK (DFFQ_X1_7T5P0)
+ 0.99 5.49 ^ _42981_/Q (DFFQ_X1_7T5P0)
+ 0.43 5.92 ^ output342/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.93 ^ la_output[62] (out)
+ 5.93 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.93 data arrival time
+---------------------------------------------------------
+ 29.82 slack (MET)
+
+
+Startpoint: _42982_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[63] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.51 4.51 clock network delay (propagated)
+ 0.00 4.51 ^ _42982_/CLK (DFFQ_X1_7T5P0)
+ 0.98 5.49 ^ _42982_/Q (DFFQ_X1_7T5P0)
+ 0.43 5.92 ^ output343/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.92 ^ la_output[63] (out)
+ 5.92 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.92 data arrival time
+---------------------------------------------------------
+ 29.83 slack (MET)
+
+
+Startpoint: _42979_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[60] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _42979_/CLK (DFFQ_X1_7T5P0)
+ 1.03 5.45 ^ _42979_/Q (DFFQ_X1_7T5P0)
+ 0.46 5.91 ^ output340/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.91 ^ la_output[60] (out)
+ 5.91 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.91 data arrival time
+---------------------------------------------------------
+ 29.84 slack (MET)
+
+
+Startpoint: _42980_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[61] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _42980_/CLK (DFFQ_X1_7T5P0)
+ 0.98 5.48 ^ _42980_/Q (DFFQ_X1_7T5P0)
+ 0.43 5.91 ^ output341/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.91 ^ la_output[61] (out)
+ 5.91 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.91 data arrival time
+---------------------------------------------------------
+ 29.84 slack (MET)
+
+
+Startpoint: _42978_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[59] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.50 4.50 clock network delay (propagated)
+ 0.00 4.50 ^ _42978_/CLK (DFFQ_X1_7T5P0)
+ 0.97 5.47 ^ _42978_/Q (DFFQ_X1_7T5P0)
+ 0.43 5.90 ^ output338/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.90 ^ la_output[59] (out)
+ 5.90 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.90 data arrival time
+---------------------------------------------------------
+ 29.85 slack (MET)
+
+
+Startpoint: _42976_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[57] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.51 4.51 clock network delay (propagated)
+ 0.00 4.51 ^ _42976_/CLK (DFFQ_X1_7T5P0)
+ 0.96 5.47 ^ _42976_/Q (DFFQ_X1_7T5P0)
+ 0.42 5.89 ^ output336/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.89 ^ la_output[57] (out)
+ 5.89 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.89 data arrival time
+---------------------------------------------------------
+ 29.86 slack (MET)
+
+
+Startpoint: _44983_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[14] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.38 4.38 clock network delay (propagated)
+ 0.00 4.38 ^ _44983_/CLK (DFFQ_X1_7T5P0)
+ 1.05 5.42 ^ _44983_/Q (DFFQ_X1_7T5P0)
+ 0.46 5.88 ^ output289/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.89 ^ la_output[14] (out)
+ 5.89 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.89 data arrival time
+---------------------------------------------------------
+ 29.86 slack (MET)
+
+
+Startpoint: _44974_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[5] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.38 4.38 clock network delay (propagated)
+ 0.00 4.38 ^ _44974_/CLK (DFFQ_X1_7T5P0)
+ 1.05 5.43 ^ _44974_/Q (DFFQ_X1_7T5P0)
+ 0.45 5.88 ^ output339/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.88 ^ la_output[5] (out)
+ 5.88 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.88 data arrival time
+---------------------------------------------------------
+ 29.87 slack (MET)
+
+
+Startpoint: _42971_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[52] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42971_/CLK (DFFQ_X1_7T5P0)
+ 0.99 5.42 ^ _42971_/Q (DFFQ_X1_7T5P0)
+ 0.44 5.86 ^ output331/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.86 ^ la_output[52] (out)
+ 5.86 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.86 data arrival time
+---------------------------------------------------------
+ 29.89 slack (MET)
+
+
+Startpoint: _44975_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[6] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.38 4.38 clock network delay (propagated)
+ 0.00 4.38 ^ _44975_/CLK (DFFQ_X1_7T5P0)
+ 1.03 5.40 ^ _44975_/Q (DFFQ_X1_7T5P0)
+ 0.45 5.86 ^ output344/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.86 ^ la_output[6] (out)
+ 5.86 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.86 data arrival time
+---------------------------------------------------------
+ 29.89 slack (MET)
+
+
+Startpoint: _44985_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[16] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.35 4.35 clock network delay (propagated)
+ 0.00 4.35 ^ _44985_/CLK (DFFQ_X1_7T5P0)
+ 1.04 5.39 ^ _44985_/Q (DFFQ_X1_7T5P0)
+ 0.46 5.85 ^ output291/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.85 ^ la_output[16] (out)
+ 5.85 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.85 data arrival time
+---------------------------------------------------------
+ 29.90 slack (MET)
+
+
+Startpoint: _44984_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[15] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.35 4.35 clock network delay (propagated)
+ 0.00 4.35 ^ _44984_/CLK (DFFQ_X1_7T5P0)
+ 1.05 5.40 ^ _44984_/Q (DFFQ_X1_7T5P0)
+ 0.45 5.85 ^ output290/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.85 ^ la_output[15] (out)
+ 5.85 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.85 data arrival time
+---------------------------------------------------------
+ 29.90 slack (MET)
+
+
+Startpoint: _42974_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[55] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42974_/CLK (DFFQ_X1_7T5P0)
+ 0.97 5.40 ^ _42974_/Q (DFFQ_X1_7T5P0)
+ 0.43 5.83 ^ output334/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.83 ^ la_output[55] (out)
+ 5.83 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.83 data arrival time
+---------------------------------------------------------
+ 29.92 slack (MET)
+
+
+Startpoint: _42973_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[54] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.42 4.42 clock network delay (propagated)
+ 0.00 4.42 ^ _42973_/CLK (DFFQ_X1_7T5P0)
+ 0.96 5.38 ^ _42973_/Q (DFFQ_X1_7T5P0)
+ 0.43 5.81 ^ output333/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.81 ^ la_output[54] (out)
+ 5.81 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.81 data arrival time
+---------------------------------------------------------
+ 29.94 slack (MET)
+
+
+Startpoint: _42967_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[48] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.43 4.43 clock network delay (propagated)
+ 0.00 4.43 ^ _42967_/CLK (DFFQ_X1_7T5P0)
+ 0.92 5.35 ^ _42967_/Q (DFFQ_X1_7T5P0)
+ 0.42 5.77 ^ output326/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.77 ^ la_output[48] (out)
+ 5.77 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.77 data arrival time
+---------------------------------------------------------
+ 29.98 slack (MET)
+
+
+Startpoint: _44978_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[9] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.35 4.35 clock network delay (propagated)
+ 0.00 4.35 ^ _44978_/CLK (DFFQ_X1_7T5P0)
+ 0.98 5.33 ^ _44978_/Q (DFFQ_X1_7T5P0)
+ 0.43 5.76 ^ output347/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.76 ^ la_output[9] (out)
+ 5.76 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.76 data arrival time
+---------------------------------------------------------
+ 29.99 slack (MET)
+
+
+Startpoint: _44977_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[8] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.35 4.35 clock network delay (propagated)
+ 0.00 4.35 ^ _44977_/CLK (DFFQ_X1_7T5P0)
+ 0.94 5.30 ^ _44977_/Q (DFFQ_X1_7T5P0)
+ 0.42 5.72 ^ output346/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.72 ^ la_output[8] (out)
+ 5.72 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.72 data arrival time
+---------------------------------------------------------
+ 30.03 slack (MET)
+
+
+Startpoint: _44976_ (rising edge-triggered flip-flop clocked by core_clk)
+Endpoint: la_output[7] (output port clocked by core_clk)
+Path Group: core_clk
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock core_clk (rise edge)
+ 4.35 4.35 clock network delay (propagated)
+ 0.00 4.35 ^ _44976_/CLK (DFFQ_X1_7T5P0)
+ 0.94 5.29 ^ _44976_/Q (DFFQ_X1_7T5P0)
+ 0.42 5.71 ^ output345/Z (CLKBUF_X4_7T5P0)
+ 0.00 5.71 ^ la_output[7] (out)
+ 5.71 data arrival time
+
+ 45.00 45.00 clock core_clk (rise edge)
+ 0.00 45.00 clock network delay (propagated)
+ -0.25 44.75 clock uncertainty
+ 0.00 44.75 clock reconvergence pessimism
+ -9.00 35.75 output external delay
+ 35.75 data required time
+---------------------------------------------------------
+ 35.75 data required time
+ -5.71 data arrival time
+---------------------------------------------------------
+ 30.04 slack (MET)
+
+
+setup:
+worst slack -8.72
+hold:
+worst slack -0.85
+
+block: mgmt_core_wrapper
+spef: /home/kareem_farid/gf180.new/caravel/mgmt_soc_litex/spef/mgmt_core_wrapper_nom.spef
+def: /home/kareem_farid/gf180.new/caravel/mgmt_soc_litex/def/mgmt_core_wrapper.def
+sdc: /home/kareem_farid/gf180.new/caravel/mgmt_soc_litex/sdc/mgmt_core_wrapper.sdc
