Added a to-do list for things that need to be done before the
first MPW tapeout.
diff --git a/TODO b/TODO
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+NOTES on GF180MCU implementation of Caravel
+---------------------------------------------
+
+Items that remain to be addressed for a version that can
+be used with an Open MPW tapeout:
+
+(1) The DLL should be redesigned to operate around the
+ nominal frequency of the ring oscillator; the ring
+ oscillator may need to be redesigned to a different
+ number of stages (as it was originally designed for
+ 1.8V logic, the existing version is probably slower
+ than optimal for this process).
+
+(2) User project wrapper needs to be expanded to the
+ largest extent possible, since it is already less
+ than the preferred 10um^2. There is room on all
+ sides to expand. With the recommendations below,
+ the user project area should be able to be
+ 3100um x 3200um. If the managment SoC can be made
+ slightly wider and shorter, then it should be
+ possible to make the user area 3100um x 3226um,
+ which reclaims the preferred 10um^2.
+
+(3) Along with (2), the GPIO control blocks could be
+ designed with the main power buses overlapping, so
+ that the main power buses pass over top the GPIO
+ control blocks, saving area. Make them as narrow as
+ possible (no more than 25um is preferred).
+
+(4) The power bus should be redesigned with the main
+ power always on top level (thick) metal. Power
+ supply stubs should be on metal4. The main two power
+ buses should be at least 10um wide each.
+
+(5) GPIO control blocks need layout in which the output
+ signals exactly align with the input signals. The
+ current arrangement requires the routes between them
+ to cross over one another, when they could be simply a
+ straight one-line route from instance to instance.
+
+(6) GPIO defaults block power routing should match
+ the GPIO control block power routing as defined above
+ (which will be the case if the GPIO control block
+ power stripe directions are reversed, meaning that
+ the GPIO control block should be synthesized in a
+ narrow vertical aspect ratio, not horizontal.
+
+(7) GPIO control block needs same treatment as the
+ original sky130 caravel, to clock the last shift
+ register output on the clock negative edge to obtain
+ the maximum margin against hold violations.
+
+(8) Move housekeeping and other nearby top-level blocks
+ as close to the padframe as possible. Expand the
+ management SoC area to take up all remaining available
+ space.
+
+(9) Swap gpio_control_in_1[4] and gpio_control_in_1[5],
+ which are out of order ([4] should connect to
+ mprj_io[12] and [5] should connect to mprj_io[13];
+ is this wrong in the verilog?).
+
+(10) Need scripts to generate user-defined GPIO defaults
+ blocks.
+
+(11) Need scripts to generate the user ID
+
+(12) Schmitt trigger inverter on the POR needs to be checked,
+ as this is a custom design.
+
+(13) Need script to run fill generation
+
+(14) Need script to run seal ring generation
+
+(15) Need to fix the management SoC to handle the full user
+ project area wishbone address space
+
+(16) Need to fix the management SoC to handle the full
+ houskeeping wishbone address space
+
+(17) Need hexidecimal large digit cell layouts for user project
+ ID number.
+
+(18) Restore the open source icon block (layout exists).
+
+Other recommendations/requests:
+
+(1) No power supply route between top level blocks will be less
+ than 10um wide
+
+(2) Power routing inside synthesized blocks will cover at least
+ 10% of the total layout area with top level power routing
+
+(3) User project area pins will align (within reason) with the
+ location of the destination, not spread evenly. They will
+ always align with a multiple of the standard cell route
+ pitch.
