| 7.2 Dnwell | |
| ---------- | |
| This layer is defined to put 3.3V and 5V/6V CMOS devices inside deep Nwell for better isolation from substrate noise. | |
| .. csv-table:: DNWELL RULES | |
| :file: tables_clear/11_DNWELL28.csv | |
| :widths: 200, 700 , 100 | |
| :align: center | |
| .. image:: images/dnwell.png | |
| :width: 800 | |
| :align: center | |
| :alt: DNWELL | |