diff --git a/.readthedocs.yaml b/.readthedocs.yaml
new file mode 100644
index 0000000..55c224e
--- /dev/null
+++ b/.readthedocs.yaml
@@ -0,0 +1,23 @@
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+name: gf180mu-pdk-docs
+channels:
+- defaults
+dependencies:
+- python>=3.8
+- pip:
+  - -r docs/requirements.txt
diff --git a/docs/IPs/IO/gf180mcu_fd_io/gf180mcu_fd_io__1.rst b/docs/IPs/IO/gf180mcu_fd_io/gf180mcu_fd_io__1.rst
index 4728b87..409db95 100644
--- a/docs/IPs/IO/gf180mcu_fd_io/gf180mcu_fd_io__1.rst
+++ b/docs/IPs/IO/gf180mcu_fd_io/gf180mcu_fd_io__1.rst
@@ -17,7 +17,7 @@
 1.2 Device List
 ---------------
 
-nmos_6p0, pmos_6p0, pn_6p0, np_6p0, ppolyf_u, nmoscap_6p0, nmos_6p0_sab, pmos_6p0_sab.
+nfet_06v0, pfet_06v0, diode_pd2nw_06v0, diode_nd2ps_06v0, ppolyf_u, cap_nmos_06v0, nfet_06v0_dss, pfet_06v0_dss.
 
 1.3 Design Manual
 -----------------
diff --git a/docs/analog/model_parameters/HV/HV_4_1.rst b/docs/analog/model_parameters/HV/HV_4_1.rst
index ca996f5..97ee519 100644
--- a/docs/analog/model_parameters/HV/HV_4_1.rst
+++ b/docs/analog/model_parameters/HV/HV_4_1.rst
@@ -40,7 +40,7 @@
 
 The value of the fet_mc_skew parameter can be any real number greater than 0. When simulating MC parallel device, in order to get consistent mismatch results, both “m” and “par” multiplicity factors parameters are needed. It must instantiated as follows:
 
-- Xm11 2 0 0nmos_10p0_asymw=10u l=10u m=10
+- Xm11 2 0 0nfet_10v0_asymw=10u l=10u m=10
 
-- Xm21 2 0 0pmos_10p0_asymw=10u l=10u m=10
+- Xm21 2 0 0pfet_10v0_asymw=10u l=10u m=10
 
diff --git a/docs/analog/model_parameters/HV/tables_clear/1_MOSFETs.csv b/docs/analog/model_parameters/HV/tables_clear/1_MOSFETs.csv
index b88063f..3b9c67a 100644
--- a/docs/analog/model_parameters/HV/tables_clear/1_MOSFETs.csv
+++ b/docs/analog/model_parameters/HV/tables_clear/1_MOSFETs.csv
@@ -3,5 +3,5 @@
 Available","Global
 
 Statistical",NF scaling
-nmos_10p0_asym,Asymmetrical LDNMOS (10V),4.6,Y,Y,Y,N
-pmos_10p0_asym,Asymmetrical LDPMOS (10V),4.6,Y,Y,Y,N
+nfet_10v0_asym,Asymmetrical LDNMOS (10V),4.6,Y,Y,Y,N
+pfet_10v0_asym,Asymmetrical LDPMOS (10V),4.6,Y,Y,Y,N
diff --git a/docs/analog/model_parameters/HV/tables_clear/3_Instance_Parameter_Range.csv b/docs/analog/model_parameters/HV/tables_clear/3_Instance_Parameter_Range.csv
index 7512337..8e28b78 100644
--- a/docs/analog/model_parameters/HV/tables_clear/3_Instance_Parameter_Range.csv
+++ b/docs/analog/model_parameters/HV/tables_clear/3_Instance_Parameter_Range.csv
@@ -3,12 +3,12 @@
 (BSIM Version)","Parameter
 
 Value",W (um),L (um),M,as (m^2),ad (m^2),ps(m),pd (m)
-"nmos_10p0_asym
+"nfet_10v0_asym
 
 (BSIM 4.6)",Min,4,0.6,1,-,-,-,-
 ,Max,50,20,100,-,-,-,-
 ,Default,25,0.6,1,1.2E-11,3.7E-11,5.10E-05,5.30E-05
-"pmos_10p0_asym
+"pfet_10v0_asym
 
 (BSIM 4.6)",Min,4,0.6,1,-,-,-,-
 ,Max,50,20,100,-,-,-,-
diff --git a/docs/analog/model_parameters/HV/tables_clear/5_Nominal1.csv b/docs/analog/model_parameters/HV/tables_clear/5_Nominal1.csv
index 1f41a9f..9618fa6 100644
--- a/docs/analog/model_parameters/HV/tables_clear/5_Nominal1.csv
+++ b/docs/analog/model_parameters/HV/tables_clear/5_Nominal1.csv
@@ -1,11 +1,11 @@
 EP Specification,,,,Measurement,
 Device (W/L), Model,Idsat (uA/um),Vtlin,Idsat (uA/um),Vtlin (V)
-"nmos_10p0_asym
+"nfet_10v0_asym
 
  (25/0.6),nf=1",slow,444,0.97,\-,\-
 ,typical ,535,0.84,543,0.83
 , fast ,626,0.71,\-,\-
-"pmos_10p0_asym
+"pfet_10v0_asym
 
  (25/0.6),nf=1",slow ,-200,-0.88,\-,\-
 ,typical ,-260,-1.02,-268,-1.02
diff --git a/docs/analog/model_parameters/HV/tables_clear/6_Statistical_Models.csv b/docs/analog/model_parameters/HV/tables_clear/6_Statistical_Models.csv
index 2b0d1cf..05b2a54 100644
--- a/docs/analog/model_parameters/HV/tables_clear/6_Statistical_Models.csv
+++ b/docs/analog/model_parameters/HV/tables_clear/6_Statistical_Models.csv
@@ -1,5 +1,5 @@
 MOSFET Model,"Both Local
 
 and Global",Description
-nmos_10p0_asym,global only,Statistical BSIM4 model for Asym 10 V LDNMOS
-pmos_10p0_asym,global only,Statistical BSIM4 model for Asym 10V LDPMOS
+nfet_10v0_asym,global only,Statistical BSIM4 model for Asym 10 V LDNMOS
+pfet_10v0_asym,global only,Statistical BSIM4 model for Asym 10V LDPMOS
diff --git a/docs/analog/model_parameters/LV/LV_2_5.rst b/docs/analog/model_parameters/LV/LV_2_5.rst
index c1a78b2..bc490d2 100644
--- a/docs/analog/model_parameters/LV/LV_2_5.rst
+++ b/docs/analog/model_parameters/LV/LV_2_5.rst
@@ -7,20 +7,20 @@
 
 where
 
-- Vdd = 3.3V for nmos_3p3
+- Vdd = 3.3V for nfet_03v3
 
-- Vdd =-3.3V for pmos_3p3
+- Vdd =-3.3V for pfet_03v3
 
-- Vdd = 6V for nmos_6p0
+- Vdd = 6V for nfet_06v0
 
-- Vdd =-6V for pmos_6p0
+- Vdd =-6V for pfet_06v0
 
-- Vdd = 6V for nmos_6p0_nat
+- Vdd = 6V for nfet_06v0_nvt
 
 .. note::
    Vth0 is the measured or simulated threshold voltage obtained using the max Gm method at Vd = 0.05V. For 6.0V native NMOS, Vth0 is measured and simulated at Vd=0.1V. Vth1 is the simulated threshold voltage obtained using the BSIM equation. These two values may have a difference.
 
-2.5.1 nmos_3p3 and pmos_3p3 (3.3V)
+2.5.1 nfet_03v3 and pfet_03v3 (3.3V)
 ..................................
 
 .. csv-table::
@@ -35,11 +35,11 @@
 
 .. note::
 
-   - nmos_3p3_sab SAB Length on Drain side SAB DOP: 1.78um , Source Side SAB SOP: 0.48um
+   - nfet_03v3_dss SAB Length on Drain side SAB DOP: 1.78um , Source Side SAB SOP: 0.48um
 
-   - pmos_3p3_sab SAB Length on Drain side SAB DOP: 1.78um, Source Side SAB SOP: 0.48um
+   - pfet_03v3_dss SAB Length on Drain side SAB DOP: 1.78um, Source Side SAB SOP: 0.48um
 
-2.5.3 nmos_6p0 and pmos_6p0 (6V)
+2.5.3 nfet_06v0 and pfet_06v0 (6V)
 ................................
 
 .. csv-table::
@@ -47,11 +47,11 @@
 
 .. note::
 
-   - nmos_6p0_sab Length of SAB on Drain side : 3.78um, Length of SAB on Source side: 0.28um
+   - nfet_06v0_dss Length of SAB on Drain side : 3.78um, Length of SAB on Source side: 0.28um
 
-   - pmos_6p0_sab Length of SAB on Drain side : 2.78um, Length of SAB on Source side: 0.28um
+   - pfet_06v0_dss Length of SAB on Drain side : 2.78um, Length of SAB on Source side: 0.28um
 
-2.5.4 nmos_6p0 and pmos_6p0 (5V)
+2.5.4 nfet_06v0 and pfet_06v0 (5V)
 ................................
 
 .. csv-table::
diff --git a/docs/analog/model_parameters/LV/LV_6.rst b/docs/analog/model_parameters/LV/LV_6.rst
index 773d92d..ab19485 100644
--- a/docs/analog/model_parameters/LV/LV_6.rst
+++ b/docs/analog/model_parameters/LV/LV_6.rst
@@ -21,7 +21,7 @@
 
 **Examples:**
 
-Xc1 1 2 nmoscap_3p3 w=50u l=50u
+Xc1 1 2 cap_nmos_03v3 w=50u l=50u
 
 6.2 How to use the Models
 -------------------------
diff --git a/docs/analog/model_parameters/LV/LV_8_1.rst b/docs/analog/model_parameters/LV/LV_8_1.rst
index 1fb81b2..7a57403 100644
--- a/docs/analog/model_parameters/LV/LV_8_1.rst
+++ b/docs/analog/model_parameters/LV/LV_8_1.rst
@@ -1,7 +1,7 @@
 8.1 MOSFETs
 ===========
 
-8.1.1 nmos_3p3 (3.3V)
+8.1.1 nfet_03v3 (3.3V)
 .....................
 
 8.1.1.1 CV - Characteristics
@@ -88,7 +88,7 @@
    :align: center
    :alt: I/f Noise - Characteristics
 
-8.1.2 pmos_3p3 (3.3V)
+8.1.2 pfet_03v3 (3.3V)
 .....................
 
 8.1.2.1 CV - Characteristics
@@ -175,7 +175,7 @@
    :align: center
    :alt: I/f Noise - Characteristics
 
-8.1.3 nmos_6p0 (6.0V)
+8.1.3 nfet_06v0 (6.0V)
 .....................
 
 8.1.3.1 CV - Characteristics
@@ -216,7 +216,7 @@
    :align: center
    :alt: I/f Noise - Characteristics
 
-8.1.4 pmos_6p0 (6.0V)
+8.1.4 pfet_06v0 (6.0V)
 .....................
 
 8.1.4.1 CV - Characteristics
@@ -263,7 +263,7 @@
    :align: center
    :alt: I/f Noise - Characteristics
 
-8.1.5 nmos_6p0_nat (6.0V)
+8.1.5 nfet_06v0_nvt (6.0V)
 .........................
 
 8.1.5.1 IV - Characteristics
diff --git a/docs/analog/model_parameters/LV/tables_clear/00_rev.csv b/docs/analog/model_parameters/LV/tables_clear/00_rev.csv
index 0e980a4..e8fab9c 100644
--- a/docs/analog/model_parameters/LV/tables_clear/00_rev.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/00_rev.csv
@@ -124,9 +124,9 @@
 
 1. Updated leakage current for 6V PMOS
 
-2. Added paper model SAB devices nmos_3p3_sab, pmos_3p3_sab, nmos_6p0_sab,
+2. Added paper model SAB devices nfet_03v3_dss, pfet_03v3_dss, nfet_06v0_dss,
 
-pmos_6p0_sab for 3.3V NMOS/PMOS and 6V NMOS/PMOS
+pfet_06v0_dss for 3.3V NMOS/PMOS and 6V NMOS/PMOS
 
 3. Added instance parameter ""s"" to allow defining resistors in series connection
 "
@@ -173,11 +173,11 @@
 
 4. Added mismatch model for pplus_u/npolyf_u/ppolyf_u/nplus_u
 
-5. Added global statistical model for mim_1p0fF/mim_1p5fF/mim_2p0fF
+5. Added global statistical model for cap_mim_1p0fF/cap_mim_1p5fF/cap_mim_2p0fF
 
-6. Added global & mismatch model for vpnp_5x5/ vpnp_0p42x10/ vpnp_0p42x5/
+6. Added global & mismatch model for pnp_05p00x05p00/ pnp_10p00x00p42/ pnp_05p00x00p42/
 
-vpnp_10x10
+pnp_10p00x10p00
 
 7. Added global statistical model for VNPN
 "
diff --git a/docs/analog/model_parameters/LV/tables_clear/03_MOSFETs.csv b/docs/analog/model_parameters/LV/tables_clear/03_MOSFETs.csv
index 89cd711..a44822e 100644
--- a/docs/analog/model_parameters/LV/tables_clear/03_MOSFETs.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/03_MOSFETs.csv
@@ -5,12 +5,12 @@
 Statistical","Local
 
 Statistical"
-nmos_3p3,BSIM4 model for 0.18um 3.3V NMOS,Y,Y,Y,Y
-pmos_3p3,BSIM4 model for 0.18um 3.3V PMOS,Y,Y,Y,Y
-nmos_6p0,BSIM4 model for 0.18um 6V NMOS,Y,Y,Y,Y
-pmos_6p0,BSIM4 model for 0.18um 6V PMOS,Y,Y,Y,Y
-nmos_3p3_sab,Subcircuit model for 3.3V NMOS with SAB,Y,Y,Y,Y
-pmos_3p3_sab,Subcircuit model for 3.3V PMOS with SAB,Y,Y,Y,Y
-nmos_6p0_sab,Subcircuit model for 6.0V NMOS with SAB,Y,Y,Y,Y
-pmos_6p0_sab,Subcircuit model for 6.0V PMOS with SAB,Y,Y,Y,Y
-nmos_6p0_nat,BSIM4 model for 0.18um 6V native NMOS,Y,Y,Y,N
+nfet_03v3,BSIM4 model for 0.18um 3.3V NMOS,Y,Y,Y,Y
+pfet_03v3,BSIM4 model for 0.18um 3.3V PMOS,Y,Y,Y,Y
+nfet_06v0,BSIM4 model for 0.18um 6V NMOS,Y,Y,Y,Y
+pfet_06v0,BSIM4 model for 0.18um 6V PMOS,Y,Y,Y,Y
+nfet_03v3_dss,Subcircuit model for 3.3V NMOS with SAB,Y,Y,Y,Y
+pfet_03v3_dss,Subcircuit model for 3.3V PMOS with SAB,Y,Y,Y,Y
+nfet_06v0_dss,Subcircuit model for 6.0V NMOS with SAB,Y,Y,Y,Y
+pfet_06v0_dss,Subcircuit model for 6.0V PMOS with SAB,Y,Y,Y,Y
+nfet_06v0_nvt,BSIM4 model for 0.18um 6V native NMOS,Y,Y,Y,N
diff --git a/docs/analog/model_parameters/LV/tables_clear/04_Diodes.csv b/docs/analog/model_parameters/LV/tables_clear/04_Diodes.csv
index e401a69..7d92cb4 100644
--- a/docs/analog/model_parameters/LV/tables_clear/04_Diodes.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/04_Diodes.csv
@@ -3,12 +3,12 @@
 Model","Global
 
 Statistical"
-np_3p3,Model for thin gate N+/Psub diode,Y,Y,N
-pn_3p3,Model for thin gate P+/Nwell diode,Y,Y,N
-np_6p0,Model for thin gate N+/Psub diode,Y,Y,N
-pn_6p0,Model for thin gate P+/Nwell diode,Y,Y,N
-nwp_3p3,Model for 3.3V Nwell/Psub diode,Y,Y,N
-nwp_6p0,Model for 6V Nwell/Psub diode,Y,Y,N
-dnwpw,Model for PWELL/DNWELL diode,Y,Y,N
-dnwps,Model for DNWELL/Psub diode,Y,Y,N
+diode_nd2ps_03v3,Model for thin gate N+/Psub diode,Y,Y,N
+diode_pd2nw_03v3,Model for thin gate P+/Nwell diode,Y,Y,N
+diode_nd2ps_06v0,Model for thin gate N+/Psub diode,Y,Y,N
+diode_pd2nw_06v0,Model for thin gate P+/Nwell diode,Y,Y,N
+diode_nw2ps_03v3,Model for 3.3V Nwell/Psub diode,Y,Y,N
+diode_nw2ps_06v0,Model for 6V Nwell/Psub diode,Y,Y,N
+diode_pw2dw,Model for PWELL/DNWELL diode,Y,Y,N
+diode_dw2ps,Model for DNWELL/Psub diode,Y,Y,N
 sc_diode,Model for Schottky diode,Y,Y,N
diff --git a/docs/analog/model_parameters/LV/tables_clear/05_BJTs.csv b/docs/analog/model_parameters/LV/tables_clear/05_BJTs.csv
index f71976f..ec0030d 100644
--- a/docs/analog/model_parameters/LV/tables_clear/05_BJTs.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/05_BJTs.csv
@@ -5,10 +5,10 @@
 Statistical","Local
 
 Statistical"
-vpnp_10x10,"GP model for vertical PNP with
+pnp_10p00x10p00,"GP model for vertical PNP with
 
 emitter size of 10um x 10um",N,Y,Y,Y
-vpnp_5x5,"GP model for vertical PNP with
+pnp_05p00x05p00,"GP model for vertical PNP with
 
 emitter size of 5um x 5um",N,Y,Y,Y
 vpnp_0.42x10,"GP model for vertical PNP with
@@ -17,21 +17,21 @@
 vpnp_0.42x5,"GP model for vertical PNP with
 
 Emitter size of 0.42um x 5um",N,Y,Y,Y
-vnpn_10x10,"GP model for vertical NPN with
+npn_10p00x10p00,"GP model for vertical NPN with
 
 emitter size of 10umx10um",N,Y,Y,N
-vnpn_5x5,"GP model for vertical NPN with
+npn_05p00x05p00,"GP model for vertical NPN with
 
 emitter size of 5umx5um",N,Y,Y,N
-vnpn_0p54x16,"GP model for VNPN with
+npn_00p54x16p00,"GP model for VNPN with
 
 emitter size of 0.54umx16um",N,Y,Y,N
-vnpn_0p54x8,"GP model for VNPN with
+npn_00p54x08p00,"GP model for VNPN with
 
 emitter size of 0.54umx8um",N,Y,Y,N
-vnpn_0p54x4,"GP model for VNPN with
+npn_00p54x04p00,"GP model for VNPN with
 
 emitter size of 0.54umx4um",N,Y,Y,N
-vnpn_0p54x2,"GP model for VNPN with
+npn_00p54x02p00,"GP model for VNPN with
 
 emitter size of 0.54umx2um",N,Y,Y,N
diff --git a/docs/analog/model_parameters/LV/tables_clear/07_MOSCAP.csv b/docs/analog/model_parameters/LV/tables_clear/07_MOSCAP.csv
index dfb12f5..e24436b 100644
--- a/docs/analog/model_parameters/LV/tables_clear/07_MOSCAP.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/07_MOSCAP.csv
@@ -3,11 +3,11 @@
 Model","Statistical
 
 Model"
-nmoscap_3p3,Model for nominal IO 3.3V inversion-mode NMOS capacitor,Y,Y,N
-pmoscap_3p3,Model for nominal IO 3.3V inversion-mode PMOS capacitor,Y,Y,N
-nmoscap_6p0,Model for nominal IO 6V inversion -mode NMOS capacitor,Y,Y,N
-pmoscap_6p0,Model for nominal IO 6V inversion -mode PMOS capacitor,Y,Y,N
-nmoscap_3p3_b,Model for nominal IO 3.3V NMOS in Nwell capacitor,Y,Y,N
-pmoscap_3p3_b,Model for nominal IO 3.3V PMOS in Pwell capacitor,Y,Y,N
-nmoscap_6p0_b,Model for nominal IO 6V NMOS in Nwell capacitor,Y,Y,N
-pmoscap_6p0_b,Model for nominal IO 6V PMOS in Pwell capacitor,Y,Y,N
+cap_nmos_03v3,Model for nominal IO 3.3V inversion-mode NMOS capacitor,Y,Y,N
+cap_pmos_03v3,Model for nominal IO 3.3V inversion-mode PMOS capacitor,Y,Y,N
+cap_nmos_06v0,Model for nominal IO 6V inversion -mode NMOS capacitor,Y,Y,N
+cap_pmos_06v0,Model for nominal IO 6V inversion -mode PMOS capacitor,Y,Y,N
+cap_nmos_03v3_b,Model for nominal IO 3.3V NMOS in Nwell capacitor,Y,Y,N
+cap_pmos_03v3_b,Model for nominal IO 3.3V PMOS in Pwell capacitor,Y,Y,N
+cap_nmos_06v0_b,Model for nominal IO 6V NMOS in Nwell capacitor,Y,Y,N
+cap_pmos_06v0_b,Model for nominal IO 6V PMOS in Pwell capacitor,Y,Y,N
diff --git a/docs/analog/model_parameters/LV/tables_clear/08_MIM.csv b/docs/analog/model_parameters/LV/tables_clear/08_MIM.csv
index 7b838e0..ed50570 100644
--- a/docs/analog/model_parameters/LV/tables_clear/08_MIM.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/08_MIM.csv
@@ -5,17 +5,17 @@
 Statistical","Local
 
 Statistical"
-nmoscap_3p3,"Model for 1.5fF/um2 MIM
+cap_nmos_03v3,"Model for 1.5fF/um2 MIM
 
 (*)-usable for Volt <=6V
 
 across capacitor",Y,Y,Y,N
-pmoscap_3p3,"Model for 1.0fF/um2 MIM
+cap_pmos_03v3,"Model for 1.0fF/um2 MIM
 
 (*)-usable for Volt <=6V
 
 across capacitor",Y,Y,Y,N
-nmoscap_6p0,"Model for 2.0fF/um2 MIM
+cap_nmos_06v0,"Model for 2.0fF/um2 MIM
 
 (*)-usable for Volt <=6V
 
diff --git a/docs/analog/model_parameters/LV/tables_clear/10_LV_NMOS.csv b/docs/analog/model_parameters/LV/tables_clear/10_LV_NMOS.csv
index 2f27eaf..220861a 100644
--- a/docs/analog/model_parameters/LV/tables_clear/10_LV_NMOS.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/10_LV_NMOS.csv
@@ -3,12 +3,12 @@
 (BSIM Version)","Parameter
 
 Value",W,L,nf,as,ad,ps,pd,nrs,nrd,dtemp
-"nmos_3p3
+"nfet_03v3
 
 (BSIM 4.5)",Min,0.22,0.28,1,-,-,-,-,-,-,-
 ,Max,100,50,-,-,-,-,-,-,-,-
 ,Default,0,0,1,0,0,0,0,0,0,0
-"pmos_3p3
+"pfet_03v3
 
 (BSIM 4.5)",Min,0.22,0.28,1,-,-,-,-,-,-,-
 ,Max,50,100,-,-,-,-,-,-,-,-
diff --git a/docs/analog/model_parameters/LV/tables_clear/11_MV_NMOS.csv b/docs/analog/model_parameters/LV/tables_clear/11_MV_NMOS.csv
index 9c7fb2f..f1b0b7f 100644
--- a/docs/analog/model_parameters/LV/tables_clear/11_MV_NMOS.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/11_MV_NMOS.csv
@@ -3,17 +3,17 @@
 (BSIM Version)","Parameter
 
 Value",W,L,nf,as,ad,ps,pd,nrs,nrd,dtemp
-"nmos_6p0
+"nfet_06v0
 
 (BSIM 4.5)",Min,0.3,0.6,1,-,-,-,-,-,-,-
 ,Max,100,50,-,-,-,-,-,-,-,-
 ,Default,0,0,1,0,0,0,0,0,0,0
-"pmos_6p0
+"pfet_06v0
 
 (BSIM 4.5)",Min,0.3,0.5,1,-,-,-,-,-,-,-
 ,Max,100,50,-,-,-,-,-,-,-,-
 ,Default,0,0,1,0,0,0,0,0,0,0
-"nmos_6p0_nat
+"nfet_06v0_nvt
 
 (BSIM 4.6)",Min,0.8,1.8,1,-,-,-,-,-,-,-
 ,Max,100,50,-,-,-,-,-,-,-,-
diff --git a/docs/analog/model_parameters/LV/tables_clear/17_Noise.csv b/docs/analog/model_parameters/LV/tables_clear/17_Noise.csv
index 7b5f7aa..a97314b 100644
--- a/docs/analog/model_parameters/LV/tables_clear/17_Noise.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/17_Noise.csv
@@ -1,6 +1,6 @@
 Device,Vds (V),Vgs (V),W x L (um x um)
-nmos_3p3,"0.1, 1.8, 3.3","0.8, 1.8, 3.3",10x0.28
-pmos_3p3,"-0.1, -1.8, -3.3","-0.8, -1.8, -3.3",10x0.28
-nmos_6p0,"0.1, 3, 6","1, 3, 6",10x0.7
-pmos_6p0,"-0.1, -3, -6","-1, -3, -6",10x0.55
-nmos_6p0_nat,"0.1, 3, 6","0.3, 3, 6",10x1.8
+nfet_03v3,"0.1, 1.8, 3.3","0.8, 1.8, 3.3",10x0.28
+pfet_03v3,"-0.1, -1.8, -3.3","-0.8, -1.8, -3.3",10x0.28
+nfet_06v0,"0.1, 3, 6","1, 3, 6",10x0.7
+pfet_06v0,"-0.1, -3, -6","-1, -3, -6",10x0.55
+nfet_06v0_nvt,"0.1, 3, 6","0.3, 3, 6",10x1.8
diff --git a/docs/analog/model_parameters/LV/tables_clear/19_mos_3p3.csv b/docs/analog/model_parameters/LV/tables_clear/19_mos_3p3.csv
index 383f999..ac7b132 100644
--- a/docs/analog/model_parameters/LV/tables_clear/19_mos_3p3.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/19_mos_3p3.csv
@@ -1,11 +1,11 @@
 EP Specification,,,,Measurement,
 Device (W/L) ,Model,Idsat (uA/um),Vth0 (V),Idsat (uA/um),Vth0  (V)
-"nmos_3p3
+"nfet_03v3
 
 (10/0.28)",slow ,430,0.73,\-,\-
 ,typical,510,0.63,508,0.644
 ,fast ,590,0.53,\-,\-
-"pmos_3p3
+"pfet_03v3
 
 (10/0.28)",slow,-210,-0.85,\-,\-
 ,typical,-250,-0.73,-254.1,-0.733
diff --git a/docs/analog/model_parameters/LV/tables_clear/20_MOS_3p3_SAB.csv b/docs/analog/model_parameters/LV/tables_clear/20_MOS_3p3_SAB.csv
index c3f2011..275bf38 100644
--- a/docs/analog/model_parameters/LV/tables_clear/20_MOS_3p3_SAB.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/20_MOS_3p3_SAB.csv
@@ -1,11 +1,11 @@
 EP Specification,,,,
 Device (W/L) ,Model,Idsat (uA/um),Vth0 (V),Idlin (uA/um)
-"nmos_3p3_sab \*
+"nfet_03v3_dss \*
 
 (10/0.28)",slow,426,0.73,52
 ,typical ,505,0.63,57
 ,fast ,586,0.53,63
-"pmos_3p3_sab
+"pfet_03v3_dss
 
 (10/0.28)",slow ,-206,-0.84,-18
 ,typical ,-245,-0.72,-20
diff --git a/docs/analog/model_parameters/LV/tables_clear/21_mos_6p0.csv b/docs/analog/model_parameters/LV/tables_clear/21_mos_6p0.csv
index e34866b..2aeed51 100644
--- a/docs/analog/model_parameters/LV/tables_clear/21_mos_6p0.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/21_mos_6p0.csv
@@ -1,16 +1,16 @@
 EP Specification,,,,Measurement,
 Device (W/L) ,Model,Idsat (uA/um),Vth0 (V),Idsat (uA/um),Vth0  (V)
-"nmos_6p0
+"nfet_06v0
 
 (10/0.7)",slow ,480,0.85,\-,\-
 ,typical,570,0.73,579.6,0.738
 ,fast,660,0.61,\-,\-
-"nmos_6p0_nat
+"nfet_06v0_nvt
 
 (10/1.8)",slow ,430,0.08,\-,\-
 ,typical,535,-0.12,543,-0.12
 ,fast,640,-0.32,\-,\-
-"pmos_6p0
+"pfet_06v0
 
 (10/0.55)",slow ,-240,-0.98,\-,\-
 ,typical,-290,-0.85,-297.4,-0.849
diff --git a/docs/analog/model_parameters/LV/tables_clear/21_mos_6p0_2.csv b/docs/analog/model_parameters/LV/tables_clear/21_mos_6p0_2.csv
index 9951170..18c64d8 100644
--- a/docs/analog/model_parameters/LV/tables_clear/21_mos_6p0_2.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/21_mos_6p0_2.csv
@@ -1,11 +1,11 @@
 EP Specification,,,,
 Device (W/L) ,Model,Idsat (uA/um),Vth0 (V),Idlin (uA/um)
-"nmos_6p0_sab \*\*
+"nfet_06v0_dss \*\*
 
 (10/0.7)",slow ,477,0.85,38
 ,typical ,568,0.73,44
 ,fast ,657,0.6,49
-"pmos_6p0_sab \*\*
+"pfet_06v0_dss \*\*
 
 (10/0.55)",slow ,-238,-0.98,-12
 ,typical ,-288,-0.85,-15
diff --git a/docs/analog/model_parameters/LV/tables_clear/22_mos_6p0_1.csv b/docs/analog/model_parameters/LV/tables_clear/22_mos_6p0_1.csv
index 7ae9aae..0f00921 100644
--- a/docs/analog/model_parameters/LV/tables_clear/22_mos_6p0_1.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/22_mos_6p0_1.csv
@@ -1,11 +1,11 @@
 EP Specification,,,,Measurement,
 Device (W/L) ,Model,Idsat (uA/um),Vth0 (V),Idsat (uA/um),Vth0  (V)
-"nmos_6p0
+"nfet_06v0
 
 (10/0.6)",slow ,400,0.82,\-,\-
 ,typical ,500,0.7,,
 ,fast ,600,0.58,\-,\-
-"pmos_6p0
+"pfet_06v0
 
 (10/0.5)",slow ,-200,-0.96,\-,\-
 ,typical ,-240,-0.83,,
diff --git a/docs/analog/model_parameters/LV/tables_clear/22_mos_6p0_2.csv b/docs/analog/model_parameters/LV/tables_clear/22_mos_6p0_2.csv
index fd4e159..5bc3d70 100644
--- a/docs/analog/model_parameters/LV/tables_clear/22_mos_6p0_2.csv
+++ b/docs/analog/model_parameters/LV/tables_clear/22_mos_6p0_2.csv
@@ -1,11 +1,11 @@
 EP Specification,,,,
 Device (W/L) ,Model,Idsat (uA/um),Vth0 (V),Idlin (uA/um)
-"nmos_6p0_sab
+"nfet_06v0_dss
 
 (10/0.6)",Slow,398,0.84,39
 ,typical ,498,0.72,46
 ,fast,598,0.58,53
-"pmos_6p0_sab
+"pfet_06v0_dss
 
 (10/0.5)",slow ,-187,-0.97,-12
 ,typical ,-233,-0.84,-14
diff --git a/docs/physical_verification/design_manual/tables_clear/01_Document_rev2_3_4.csv b/docs/physical_verification/design_manual/tables_clear/01_Document_rev2_3_4.csv
index 299e271..e81956c 100644
--- a/docs/physical_verification/design_manual/tables_clear/01_Document_rev2_3_4.csv
+++ b/docs/physical_verification/design_manual/tables_clear/01_Document_rev2_3_4.csv
@@ -11,11 +11,11 @@
  ,Section 10.9,Add  LVS_BJT Mark Layer
  ,            ,Add  LVS_BJT.1 Minimum LVS_BJT enclosure of  NPN or PNP Emitter COMP layers: 0
  ,Appendix A  ,Add  Below devices to the device list:
- ,            ,nmos_6p0_nat 6V Native NMOS
- ,            ,nmoscap_3p3_b 3.3V NMOS capacitor (inside Nwell)
- ,            ,pmoscap_3p3_b 3.3V PMOS capacitor (inside Psub)
- ,            ,nmoscap_6p0_b 6V NMOS capacitor (inside NWell)
- ,            ,pmoscap_6p0_b 6V PMOS capacitor (inside Psub)
+ ,            ,nfet_06v0_nvt 6V Native NMOS
+ ,            ,cap_nmos_03v3_b 3.3V NMOS capacitor (inside Nwell)
+ ,            ,cap_pmos_03v3_b 3.3V PMOS capacitor (inside Psub)
+ ,            ,cap_nmos_06v0_b 6V NMOS capacitor (inside NWell)
+ ,            ,cap_pmos_06v0_b 6V PMOS capacitor (inside Psub)
  ,Section 13.4 and 13.5, Add  ESD related design rules.
 4,Section 4   ,Add MCU SONOS related layer information
 ,Section 4    ,Define OTP_MK in the notes of drawn layer table.
diff --git a/docs/physical_verification/design_manual/tables_clear/08_Topological_Truth_Table15.csv b/docs/physical_verification/design_manual/tables_clear/08_Topological_Truth_Table15.csv
index 21fd70c..0c80e02 100644
--- a/docs/physical_verification/design_manual/tables_clear/08_Topological_Truth_Table15.csv
+++ b/docs/physical_verification/design_manual/tables_clear/08_Topological_Truth_Table15.csv
@@ -81,17 +81,17 @@
 (7) N+ Poly Fuse (Optional):,X,0,X,X,X,1,1,0,0,X,1,X,0,1,0,0,X,0,0,0,0,0,0,0,0,0,0,0,0,0
 (8) Metal Fuse (Optional):,X,0,X,X,X,0,X,X,X,X,X,X,1,0,0,0,X,0,0,0,0,0,0,0,0,0,0,0,0,0
 (9) ESD,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
-nmos_3p3_dw_sab (SAB 3.3V NMOS inside DNWELL),1,1,0,1,0,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
-nmos_3p3_sab (SAB 3.3V NMOS outside DNWELL),0,1,0,X,0,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
-nmos_5p0_dw_sab (SAB 5V NMOS inside DNWELL),1,1,0,1,1,1,1,0,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0
-nmos_5p0_sab (SAB 5V NMOS outside DNWELL),0,1,0,X,1,1,1,0,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0
-nmos_6p0_dw_sab (SAB 6V NMOS inside DNWELL),1,1,0,1,1,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
-nmos_6p0_sab (SAB 6V NMOS outside DNWELL),0,1,0,X,1,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
-pmos_3p3_dw_sab (SAB 3.3V PMOS inside DNWELL),1,1,X,0,0,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
-pmos_3p3_sab (SAB 3.3V PMOS outside DNWELL),0,1,1,0,0,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
-pmos_5p0_dw_sab (SAB 5V PMOS inside DNWELL),1,1,X,0,1,1,0,1,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0
-pmos_5p0_sab (SAB 5V PMOS outside DNWELL),0,1,1,0,1,1,0,1,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0
-pmos_6p0_dw_sab (SAB 6V PMOS inside DNWELL),1,1,X,0,1,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
-pmos_6p0_sab (SAB 6V PMOS outside DNWELL),0,1,1,0,1,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+nfet_03v3_dn_dss (SAB 3.3V NMOS inside DNWELL),1,1,0,1,0,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+nfet_03v3_dss (SAB 3.3V NMOS outside DNWELL),0,1,0,X,0,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+nfet_05v0_dn_dss (SAB 5V NMOS inside DNWELL),1,1,0,1,1,1,1,0,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+nfet_05v0_dss (SAB 5V NMOS outside DNWELL),0,1,0,X,1,1,1,0,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+nfet_06v0_dn_dss (SAB 6V NMOS inside DNWELL),1,1,0,1,1,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+nfet_06v0_dss (SAB 6V NMOS outside DNWELL),0,1,0,X,1,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+pfet_03v3_dn_dss (SAB 3.3V PMOS inside DNWELL),1,1,X,0,0,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+pfet_03v3_dss (SAB 3.3V PMOS outside DNWELL),0,1,1,0,0,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+pfet_05v0_dn_dss (SAB 5V PMOS inside DNWELL),1,1,X,0,1,1,0,1,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+pfet_05v0_dss (SAB 5V PMOS outside DNWELL),0,1,1,0,1,1,0,1,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+pfet_06v0_dn_dss (SAB 6V PMOS inside DNWELL),1,1,X,0,1,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
+pfet_06v0_dss (SAB 6V PMOS outside DNWELL),0,1,1,0,1,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0
 (10) eFuse,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
 eFuse,X,0,0,X,X,1,0,1,0,0,0,0,0,0,0,X,0,0,0,0,0,0,1,0,1,1,0,0,0,0
diff --git a/docs/physical_verification/design_manual/tables_clear/69_Device_List_184.csv b/docs/physical_verification/design_manual/tables_clear/69_Device_List_184.csv
index 79c28e0..235ac54 100644
--- a/docs/physical_verification/design_manual/tables_clear/69_Device_List_184.csv
+++ b/docs/physical_verification/design_manual/tables_clear/69_Device_List_184.csv
@@ -1,46 +1,46 @@
 No.,Device Name,Model Name,Description,Spec
 MOSFET,,,,
-,nmos_3p3,nmos_3p3,3.3V NMOS (Outside DNWELL),YI-141-SM064
-,nmos_3p3_dw,nmos_3p3,3.3V NMOS (Inside DNWELL),YI-141-SM064
-,pmos_3p3,pmos_3p3,3.3V PMOS (Outside DNWELL),YI-141-SM064
-,pmos_3p3_dw,pmos_3p3,3.3V PMOS (Inside DNWELL),YI-141-SM064
-,nmos_5p0,nmos_6p0,5V NMOS (Outside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
-,nmos_5p0_dw,nmos_6p0,5V NMOS (Inside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
-,pmos_5p0,pmos_6p0,5V PMOS (Outside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
-,pmos_5p0_dw,pmos_6p0,5V PMOS (Inside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
-,nmos_6p0,nmos_6p0,6V NMOS (Outside DNWELL),YI-141-SM064
-,nmos_6p0_dw,nmos_6p0,6V NMOS (Inside DNWELL),YI-141-SM064
-,pmos_6p0,pmos_6p0,6V PMOS (Outside DNWELL),YI-141-SM064
-,pmos_6p0_dw,pmos_6p0,6V PMOS (Inside DNWELL),YI-141-SM064
-,nmos_6p0_nat,nmos_6p0_nat,6V Native NMOS,YI-141-SM064
-,nmos_10p0_asym,nmos_10p0_asym,LD-NMOS (Asymmetrical),SM-BB-000149
-,pmos_10p0_asym,pmos_10p0_asym,LD-PMOS (Asymmetrical),SM-BB-000149
+,nfet_03v3,nfet_03v3,3.3V NMOS (Outside DNWELL),YI-141-SM064
+,nfet_03v3_dn,nfet_03v3,3.3V NMOS (Inside DNWELL),YI-141-SM064
+,pfet_03v3,pfet_03v3,3.3V PMOS (Outside DNWELL),YI-141-SM064
+,pfet_03v3_dn,pfet_03v3,3.3V PMOS (Inside DNWELL),YI-141-SM064
+,nfet_05v0,nfet_06v0,5V NMOS (Outside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
+,nfet_05v0_dn,nfet_06v0,5V NMOS (Inside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
+,pfet_05v0,pfet_06v0,5V PMOS (Outside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
+,pfet_05v0_dn,pfet_06v0,5V PMOS (Inside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
+,nfet_06v0,nfet_06v0,6V NMOS (Outside DNWELL),YI-141-SM064
+,nfet_06v0_dn,nfet_06v0,6V NMOS (Inside DNWELL),YI-141-SM064
+,pfet_06v0,pfet_06v0,6V PMOS (Outside DNWELL),YI-141-SM064
+,pfet_06v0_dn,pfet_06v0,6V PMOS (Inside DNWELL),YI-141-SM064
+,nfet_06v0_nvt,nfet_06v0_nvt,6V Native NMOS,YI-141-SM064
+,nfet_10v0_asym,nfet_10v0_asym,LD-NMOS (Asymmetrical),SM-BB-000149
+,pfet_10v0_asym,pfet_10v0_asym,LD-PMOS (Asymmetrical),SM-BB-000149
 BJT,,,,
-,vnpn_10x10,vnpn_10x10,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 10um x 10um",YI-141-SM064
-,vnpn_5x5,vnpn_5x5,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 5um x 5um",YI-141-SM064
-,vnpn_0p54x16,vnpn_0p54x16,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 0p54um x 16um",YI-141-SM064
-,vnpn_0p54x8,vnpn_0p54x8,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 0p54um x 8um",YI-141-SM064
-,vnpn_0p54x4,vnpn_0p54x4,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 0p54um x 4um",YI-141-SM064
-,vnpn_0p54x2,vnpn_0p54x2,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 0p54um x 2um",YI-141-SM064
-,vpnp_10x10,vpnp_10x10,"VPNP (Pplus-Nwell-Psub), emitter size 10um x 10um",YI-141-SM064
-,vpnp_5x5,vpnp_5x5,"VPNP (Pplus-Nwell-Psub), emitter size 5um x 5um",YI-141-SM064
-,vpnp_0p42x10,vpnp_0p42x10,"VPNP (Pplus-Nwell-Psub), emitter size 0p42um x 10um",YI-141-SM064
-,vpnp_0p42x5,vpnp_0p42x5,"VPNP (Pplus-Nwell-Psub), emitter size 0p42um x 5um",YI-141-SM064
+,npn_10p00x10p00,npn_10p00x10p00,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 10um x 10um",YI-141-SM064
+,npn_05p00x05p00,npn_05p00x05p00,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 5um x 5um",YI-141-SM064
+,npn_00p54x16p00,npn_00p54x16p00,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 0p54um x 16um",YI-141-SM064
+,npn_00p54x08p00,npn_00p54x08p00,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 0p54um x 8um",YI-141-SM064
+,npn_00p54x04p00,npn_00p54x04p00,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 0p54um x 4um",YI-141-SM064
+,npn_00p54x02p00,npn_00p54x02p00,"VNPN (Nplus-LVPWELL-DNWELL), emitter size 0p54um x 2um",YI-141-SM064
+,pnp_10p00x10p00,pnp_10p00x10p00,"VPNP (Pplus-Nwell-Psub), emitter size 10um x 10um",YI-141-SM064
+,pnp_05p00x05p00,pnp_05p00x05p00,"VPNP (Pplus-Nwell-Psub), emitter size 5um x 5um",YI-141-SM064
+,pnp_10p00x00p42,pnp_10p00x00p42,"VPNP (Pplus-Nwell-Psub), emitter size 0p42um x 10um",YI-141-SM064
+,pnp_05p00x00p42,pnp_05p00x00p42,"VPNP (Pplus-Nwell-Psub), emitter size 0p42um x 5um",YI-141-SM064
 DIODE,,,,
-,np_3p3,np_3p3,3.3V N+/LVPWELL diode (Outside DNWELL),YI-141-SM064
-,np_3p3_dw,np_3p3,3.3V N+/LVPWELL diode (Inside DNWELL),YI-141-SM064
-,np_6p0,np_6p0,5V/6V N+/LVPWELL Diode (Outside DNWELL),YI-141-SM064
-,np_6p0_dw,np_6p0,5V/6V N+/LVPWELL Diode (Inside DNWELL),YI-141-SM064
-,pn_3p3,pn_3p3,3.3V  P+/Nwell diode (Outside DNWELL),YI-141-SM064
-,pn_3p3_dw,pn_3p3,3.3V  P+/Nwell diode (Inside DNWELL),YI-141-SM064
-,pn_6p0,pn_6p0,5V/6V P+/Nwell diode (Outside DNWELL),YI-141-SM064
-,pn_6p0_dw,pn_6p0,5V/6V P+/Nwell diode (Inside DNWELL),YI-141-SM064
-,nwp_3p3,nwp_3p3,3.3V Nwell/Psub diode,YI-141-SM064
-,nwp_6p0,nwp_6p0,5V/6V Nwell/Psub diode,YI-141-SM064
-,dnwpw_3p3,dnwpw,3.3V LVPWELL/DNWELL diode,YI-141-SM064
-,dnwpw_6p0,dnwpw,5V/6V LVPWELL/DNWELL diode,YI-141-SM064
-,dnwps_3p3,dnwps,3.3V DWENLL/Psub diode,YI-141-SM064
-,dnwps_6p0,dnwps,5V/6V DWENLL/Psub diode,YI-141-SM064
+,diode_nd2ps_03v3,diode_nd2ps_03v3,3.3V N+/LVPWELL diode (Outside DNWELL),YI-141-SM064
+,diode_nd2ps_03v3_dn,diode_nd2ps_03v3,3.3V N+/LVPWELL diode (Inside DNWELL),YI-141-SM064
+,diode_nd2ps_06v0,diode_nd2ps_06v0,5V/6V N+/LVPWELL Diode (Outside DNWELL),YI-141-SM064
+,diode_nd2ps_06v0_dn,diode_nd2ps_06v0,5V/6V N+/LVPWELL Diode (Inside DNWELL),YI-141-SM064
+,diode_pd2nw_03v3,diode_pd2nw_03v3,3.3V  P+/Nwell diode (Outside DNWELL),YI-141-SM064
+,diode_pd2nw_03v3_dn,diode_pd2nw_03v3,3.3V  P+/Nwell diode (Inside DNWELL),YI-141-SM064
+,diode_pd2nw_06v0,diode_pd2nw_06v0,5V/6V P+/Nwell diode (Outside DNWELL),YI-141-SM064
+,diode_pd2nw_06v0_dn,diode_pd2nw_06v0,5V/6V P+/Nwell diode (Inside DNWELL),YI-141-SM064
+,diode_nw2ps_03v3,diode_nw2ps_03v3,3.3V Nwell/Psub diode,YI-141-SM064
+,diode_nw2ps_06v0,diode_nw2ps_06v0,5V/6V Nwell/Psub diode,YI-141-SM064
+,diode_pw2dw_03v3,diode_pw2dw,3.3V LVPWELL/DNWELL diode,YI-141-SM064
+,diode_pw2dw_06v0,diode_pw2dw,5V/6V LVPWELL/DNWELL diode,YI-141-SM064
+,diode_dw2ps_03v3,diode_dw2ps,3.3V DWENLL/Psub diode,YI-141-SM064
+,diode_dw2ps_06v0,diode_dw2ps,5V/6V DWENLL/Psub diode,YI-141-SM064
 ,sc_diode,sc_diode,Schottky diode,YI-141-SM064
 RESISTOR,,,,
 ,nplus_u,nplus_u,3-terminal unsalicided n+ diffusion resistor (Outside DNWELL),YI-141-SM064
@@ -81,35 +81,35 @@
 ,tm11k,tm11k,2-terminal 11K Metal Top resistor,YI-141-SM064
 ,tm30k,tm30k,2-terminal 30K Top Metal resistor,YI-141-SM064
 CAPACITOR (MIM),,,,
-,mim_1p0fF,mim_1p0fF,1.0fF/um2 MIM capacitor,YI-141-SM064
-,mim_1p5fF,mim_1p5fF,1.5fF/um2 MIM capacitor,YI-141-SM064
-,mim_single_2p0fF,mim_2p0fF,2.0fF/um2 MIM capacitor,YI-141-SM064
+,cap_mim_1p0fF,cap_mim_1p0fF,1.0fF/um2 MIM capacitor,YI-141-SM064
+,cap_mim_1p5fF,cap_mim_1p5fF,1.5fF/um2 MIM capacitor,YI-141-SM064
+,cap_cap_mim_2p0fF,cap_mim_2p0fF,2.0fF/um2 MIM capacitor,YI-141-SM064
 CAPACITOR (MOS),,,,
-,nmoscap_3p3,nmoscap_3p3,3.3V NMOS capacitor (Outside DNWELL),YI-141-SM064
-,nmoscap_3p3_dw,nmoscap_3p3,3.3V NMOS capacitor (Inside DNWELL),YI-141-SM064
-,pmoscap_3p3,pmoscap_3p3,3.3V PMOS capacitor (Outside DNWELL),YI-141-SM064
-,pmoscap_3p3_dw,pmoscap_3p3,3.3V PMOS capacitor (Inside DNWELL),YI-141-SM064
-,nmoscap_6p0,nmoscap_6p0,5V/6V NMOS capacitor (Outside DNWELL),YI-141-SM064
-,nmoscap_6p0_dw,nmoscap_6p0,5V/6V NMOS capacitor (inside DNWELL),YI-141-SM064
-,pmoscap_6p0,pmoscap_6p0,5V/6V PMOS capacitor (Outside DNWELL),YI-141-SM064
-,pmoscap_6p0_dw,pmoscap_6p0,5V/6V PMOS capacitor (Outside DNWELL),YI-141-SM064
-,nmoscap_3p3_b,nmoscap_3p3_b,3.3V NMOS capacitor (inside NWell),YI-141-SM064
-,pmoscap_3p3_b,pmoscap_3p3_b,3.3V PMOS capacitor (inside Psub),YI-141-SM064
+,cap_nmos_03v3,cap_nmos_03v3,3.3V NMOS capacitor (Outside DNWELL),YI-141-SM064
+,cap_nmos_03v3_dn,cap_nmos_03v3,3.3V NMOS capacitor (Inside DNWELL),YI-141-SM064
+,cap_pmos_03v3,cap_pmos_03v3,3.3V PMOS capacitor (Outside DNWELL),YI-141-SM064
+,cap_pmos_03v3_dn,cap_pmos_03v3,3.3V PMOS capacitor (Inside DNWELL),YI-141-SM064
+,cap_nmos_06v0,cap_nmos_06v0,5V/6V NMOS capacitor (Outside DNWELL),YI-141-SM064
+,cap_nmos_06v0_dn,cap_nmos_06v0,5V/6V NMOS capacitor (inside DNWELL),YI-141-SM064
+,cap_pmos_06v0,cap_pmos_06v0,5V/6V PMOS capacitor (Outside DNWELL),YI-141-SM064
+,cap_pmos_06v0_dn,cap_pmos_06v0,5V/6V PMOS capacitor (Outside DNWELL),YI-141-SM064
+,cap_nmos_03v3_b,cap_nmos_03v3_b,3.3V NMOS capacitor (inside NWell),YI-141-SM064
+,cap_pmos_03v3_b,cap_pmos_03v3_b,3.3V PMOS capacitor (inside Psub),YI-141-SM064
 ,,,,
-,nmoscap_6p0_b,nmoscap_6p0_b,5V/6V NMOS capacitor (inside NWell),YI-141-SM064
-,pmoscap_6p0_b,pmoscap_6p0_b,5V/6V PMOS capacitor (inside Psub),YI-141-SM064
+,cap_nmos_06v0_b,cap_nmos_06v0_b,5V/6V NMOS capacitor (inside NWell),YI-141-SM064
+,cap_pmos_06v0_b,cap_pmos_06v0_b,5V/6V PMOS capacitor (inside Psub),YI-141-SM064
 ESD (SAB MOSFET),,,,
-,nmos_3p3_sab,nmos_3p3_sab,3.3V SAB NMOS (Outside DNWELL),YI-141-SM064
-,nmos_3p3_dw_sab,nmos_3p3_sab,3.3V SAB NMOS (Inside DNWELL),YI-141-SM064
-,nmos_5p0_sab,nmos_6p0_sab,5V SAB NMOS (Outside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
-,nmos_5p0_dw_sab,nmos_6p0_sab,5V SAB NMOS (Inside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
-,nmos_6p0_sab,nmos_6p0_sab,6V SAB NMOS (Outside DNWELL),YI-141-SM064
-,nmos_6p0_dw_sab,nmos_6p0_sab,6V SAB NMOS (Inside DNWELL),YI-141-SM064
-,pmos_3p3_sab,pmos_3p3_sab,3.3V SAB PMOS (Outside DNWELL),YI-141-SM064
-,pmos_3p3_dw_sab,pmos_3p3_sab,3.3V SAB PMOS (Inside DNWELL),YI-141-SM064
-,pmos_5p0_sab,pmos_6p0_sab,5V SAB PMOS (Outside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
-,pmos_5p0_dw_sab,pmos_6p0_sab,5V SAB PMOS (Inside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
-,pmos_6p0_sab,pmos_6p0_sab,6V SAB PMOS (Outside DNWELL),YI-141-SM064
-,pmos_6p0_dw_sab,pmos_6p0_sab,6V SAB PMOS (Inside DNWELL),YI-141-SM064
+,nfet_03v3_dss,nfet_03v3_dss,3.3V SAB NMOS (Outside DNWELL),YI-141-SM064
+,nfet_03v3_dn_dss,nfet_03v3_dss,3.3V SAB NMOS (Inside DNWELL),YI-141-SM064
+,nfet_05v0_dss,nfet_06v0_dss,5V SAB NMOS (Outside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
+,nfet_05v0_dn_dss,nfet_06v0_dss,5V SAB NMOS (Inside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
+,nfet_06v0_dss,nfet_06v0_dss,6V SAB NMOS (Outside DNWELL),YI-141-SM064
+,nfet_06v0_dn_dss,nfet_06v0_dss,6V SAB NMOS (Inside DNWELL),YI-141-SM064
+,pfet_03v3_dss,pfet_03v3_dss,3.3V SAB PMOS (Outside DNWELL),YI-141-SM064
+,pfet_03v3_dn_dss,pfet_03v3_dss,3.3V SAB PMOS (Inside DNWELL),YI-141-SM064
+,pfet_05v0_dss,pfet_06v0_dss,5V SAB PMOS (Outside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
+,pfet_05v0_dn_dss,pfet_06v0_dss,5V SAB PMOS (Inside DNWELL) (with V5_XTOR mark layer),YI-141-SM064
+,pfet_06v0_dss,pfet_06v0_dss,6V SAB PMOS (Outside DNWELL),YI-141-SM064
+,pfet_06v0_dn_dss,pfet_06v0_dss,6V SAB PMOS (Inside DNWELL),YI-141-SM064
 eFuse,,,,
 ,eFuse,efuse,Eletrically programmable fuse element,YI-141-SM064