# Variables information

This page describes configuration variables and list the defaults for skywater130 pdk.

## Required variables

| Variable      | Description                                           |
|---------------|-------------------------------------------------------|
| `DESIGN_NAME`   | The name of the top level module of the design        |
| `VERILOG_FILES` | The path of the design's verilog files |
| `CLOCK_PERIOD`  | The clock period for the design in ns       |
| `CLOCK_PORT`    | The name of the design's clock port    |

## Optional variables

These variables are optional that can be specified in the design configuration file.

### Synthesis

| Variable      | Description                                                   |
|---------------|---------------------------------------------------------------|
| `LIB_SYNTH` | The library used for synthesis by yosys. <br> (Default: `./pdks/skywater130/scc8lp/scs8lp_ss_1.65v_-40C.lib`)|
| `SYNTH_DRIVING_CELL`  | The cell to drive the input ports. <br>(Default: `scs8lp_inv_8`)|
| `SYNTH_DRIVING_CELL_PIN`  | The name of the SYNTH_DRIVING_CELL output pin. <br>(Default: `Y`)|
| `SYNTH_CAP_LOAD` | The capacitive load on the output ports in femtofarads. <br> (Default: `24.36` ff)|
| `SYNTH_MAX_FANOUT`  | The max load that the output ports can drive. <br> (Default: `5` cells) |
| `SYNTH_MAX_TRANS` | The max transition time (slew) from high to low or low to high on cell inputs in ns. Used in synthesis <br> (Default: Calculated at runtime as `10%` of the provided clock period)|
| `SYNTH_STRATEGY` | Stratgies for abc logic synthesis and technology mapping <br> Possible values are 0, 1 (delay), 2, and 3 (area)<br> (Default: `2`)|
| `SYNTH_BUFFERING` | Enables abc buffering <br> Enabled = 1, Disabled = 0 <br> (Default: `1`)|
| `LIB_MIN` | Library used for min delay calculation during STA. <br> (Default:`./pdks/skywater130/scc8lp/scs8lp_ss_1.65v_-40C.lib`) |
| `LIB_MAX`  | Library used for max delay calculation during STA. <br> (Default:`./pdks/skywater130/scc8lp/scs8lp_ff_1.65v_-40C.lib`) |
| `LIB_TYPICAL` | Library used for typical delay calculation during STA. <br> (Default`./pdks/skywater130/scc8lp/scs8lp_ss_1.65v_-40C.lib`:) |

### Floorplanning

| Variable      | Description                                                   |
|---------------|---------------------------------------------------------------|
| `FP_CORE_UTIL`  | The core utilization percentage. <br> (Default: `50` percent)|
| `FP_ASPECT_RATIO`  | The core's aspect ratio (height / width). <br> (Default: `1`)|
| `FP_CORE_MARGIN`  | The length of the margin surrounding the core area. <br> (Default: `3.36` microns)|
| `FP_IO_HMETAL`  | The metal layer on which to place the io pins horizontally (top and bottom of the die). <br>(Default: `3`)|
| `FP_IO_VMETAL`  | The metal layer on which to place the io pins vertically (sides of the die) <br> (Default: `2`)|
| `FP_WELLTAP_CELL`  | The name of the welltap cell during welltap insertion. <br> (Default: `scs8lp_tap_1`)|
| `FP_ENDCAP_CELL`  | The name of the endcap cell during endcap insertion. <br> (Default: `scs8lp_decap_3`)|
| `FP_PDN_VOFFSET`  | The offset of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `16.32`) |
| `FP_PDN_VPITCH`  | The pitch of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `153.6`) |
| `FP_PDN_HOFFSET`  | The offset of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `16.65`) |
| `FP_PDN_HPITCH`  | The pitch of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `153.18`) |

### Placement

| Variable      | Description                                                   |
|---------------|---------------------------------------------------------------|
| `PL_TARGET_DENSITY` | The desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread <br> (Default: `0.4`)|
| `PL_TIME_DIRVEN` | Specifies whether the placer should use time driven placement. 0 = false, 1 = true <br> (Default: `0`)|
| `PL_LIB` | Specifies the library for time driven placement <br> (Default: `LIB_TYPICAL`)|

### CTS

| Variable      | Description                                                   |
|---------------|---------------------------------------------------------------|
| `CTS_TARGET_SKEW` | The target clock skew in picoseconds. <br> (Default: `20` ps)|
| `CTS_ROOT_BUFFER`| The name of cell inserted at the root of the clock tree. <br> (Default: `scs8lp_clkbuf_16`)|
| `CTS_TECH_DIR` | The directory of look-up-tables for tirtonCTS. <br> (Default: `./pdks/skywater130/cts_lut_common`)|
| `CTS_TOLERANCE` | an integer value that represents a tradeoff of QoR and runtime. Higher values will produce smaller runtime but worse QoR <br> (Default: `100`) |

### Routing

| Variable      | Description                                                   |
|---------------|---------------------------------------------------------------|
| `GLB_RT_MAXLAYER` | The number of highest layer to be used in routing. <br> (Default: `6`)|
| `GLB_RT_ADJUSTMENT` | Reduction in the routing capacity of the edges between the cells in the global routing graph. Values range from 0 to 1. <br> 1 = most reduction, 0 = least reduction  <br> (Default: `0.15`)|
| `GLB_RT_LI1_ADJUSTMENT` | Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to li1 layer in skywater130. Values range from 0 to 1 <br> (Default: `0`) |
| `GLB_RT_MET1_ADJUSTMENT` | Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met1 in skywater130. Values range from 0 to 1 <br> (Default: `0`) |

### Misc
| Variable      | Description                                                   |
|---------------|---------------------------------------------------------------|
| `PDK` | Specifies the process design kit (pdk). <br> (Default: `skywater130` )|
| `PDK_VARIANT` | Specifies the process design kit (pdk) variant. <br> (Default: `scs8lp` )|
| `CELL_PAD` | Cell padding; increases the width of cells. <br> (Default: `0.96` microns -- 2 sites)|


## Available Designs

This repo has several designs that were used to validate the flow. The results of running the flow on some of these designs can be found [here][2]

### Flow control
| Variable      | Description                                                   |
|---------------|---------------------------------------------------------------|
| `RUN_ROUTING_DETAILED` | Enables detailed routing. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
| `RUN_MAGIC` | Enables running magic and GDSII streaming.1 = Enabled, 0 = Disabled <br> (Default: `0`)|
| `CLOCK_TREE_SYNTH` | Enables cts.1 = Enabled, 0 = Disabled <br> (Default: `0`)|
| `FILL_INSERTION` | Enables fill cells insertion after cts (if enabled) .1 = Enabled, 0 = Disabled <br> (Default: `0`)|

[1]: ./skywater130/spm.tcl
[2]: ./designs_results.md