set ::env(DESIGN_NAME) "cpu6502"

set ::env(VERILOG_FILES) "./designs/cpu6502/src/cpu6502.v"
set ::env(SDC_FILE) "./designs/cpu6502/src/cpu6502.sdc"

set ::env(CLOCK_PERIOD) "10.000"
set ::env(CLOCK_PORT) "clk"

set ::env(FP_CORE_MARGIN) 3.36
set ::env(GLB_RT_ADJUSTMENT) 0.1
set ::env(SYNTH_STRATEGY) 2
set ::env(CLOCK_NET) $::env(CLOCK_PORT)