set ::env(DESIGN_NAME) "TEA"

set ::env(VERILOG_FILES) "./designs/TEA/src/tea.v"
set ::env(SDC_FILE) "./designs/TEA/src/tea.sdc"

set ::env(CLOCK_PERIOD) "30"
set ::env(CLOCK_PORT) "clk"

set ::env(FP_CORE_UTIL) 40
set ::env(PL_TARGET_DENSITY) 0.4
set ::env(GLB_RT_ADJUSTMENT) 0.15