set ::env(DESIGN_NAME) "PPU"

set ::env(VERILOG_FILES) "./designs/PPU/src/PPU.v"

set ::env(CLOCK_PERIOD) "10.0"
set ::env(CLOCK_PORT) "clk"

set ::env(PL_TARGET_DENSITY) 0.5
set ::env(FP_CORE_UTIL)      50
set ::env(SYNTH_STRATEGY)    3