| commit | 9b2c6f60d58368b5f7a2938643c7812bb381dd90 | [log] [tgz] |
|---|---|---|
| author | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Sun Dec 22 11:07:14 2019 -0800 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Sun Dec 22 11:07:14 2019 -0800 |
| tree | 420cefa007d4e8f6e40cbe9e12014a830895e33a | |
| parent | ba1ad0e58e96230260b04600c44e77a0427e5ff3 [diff] |
new pdn - tapcell inversion - rail vios
___ ____ ___ ____ _ ____ ____ ___ / \ | \ / _]| \ | | / || \ / _] | || o ) [_ | _ || | | o || _ | / [_ | O || _/ _]| | || |___ | || | || _] | || | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____| ver 0.6
NOTICE
This software contains confidential information from SkyWater Technology Foundry. This software is provided to partners of Efabless Corporation through license agreement with SkyWater Technology Foundry Inc.
You must have an appropriate confidentiality and license aggrement with SkyWater Technology Foundry Inc in order to access and use this software.
OpenLane is an automated RTL to GDSII flow based on OpenRoad EDA tools configured for the SkyWater PDK. The flow performs ASIC implementation steps from RTL all the way down to GDSII.
Before running the flow, you need to build tools used by the flow. OpenLane uses the following tools:
The following instructions walk you through the process of using docker containers to build the needed tools then integrate them into OpenLane flow.
After building the docker image, issue the following command to open the docker container:
docker run -it openlane:latest
The docker container will open in the directory of the openlane flow.
You can also issue the following command from the project root, to ensure that the output files persist after exiting the container:
docker run -itv $(pwd):/openLANE_flow openlane:latest
Note: this will mirror the openlane directory inside the container.
Then, you can test the flow using one of the provided designs (spm: Serial-Parallel Adder) by running:
./flow.tcl -design spm
To add a new design, the following command creates configuration file for your design:
./flow.tcl -design <design_name> -init_design_config
This will create the following directory structure:
designs/<design_name> ├── config.tcl
In the configuration file, you should edit the required variables and the optional variables, if needed. Further information about the variables can be found here
It is recommended to place the design‘s verilog files in a src directory inside the design’s folder as following:
designs/<design_name> ├── config.tcl ├── src │ ├── design.v
Optionally, you can specify the configuration file name (without the extension) by using:
./flow.tcl -design <design_name> -init_design_config -tag <config_name>
After adding the design, you can specify the design name using a -design argument:
./flow.tcl -design <design_name>
Finally, you can specify the configuration file (belonging to that design) the flow should use:
./flow.tcl -design <design_name> -config <config_name>
NOTE: The design name should be named after the design's top level module.
The following are arguments that can be passed to flow.tcl
OpenLane flow consists of several stages. Each stage may consist of multiple sub-stages. The following diagram illustrates the flow:
yosys - Performs RTL synthesisabc - Performs technology mappingOpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reportsverilog2def - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)ioplacer - Places the macro input and output portspdn - Generates the power distribution networktapcell - Inserts welltap and decap cells in the floorplanRePLace - Performs global placementOpenDP Perfroms detailed placement to legalize the globally plced comoponentsTritonCTS - Synthesizes the clock distribution network (the clock tree)FastRoute - Performs global routing to generate a guide file for the detailed routerTritonRoute - Performs detailed routingmagic - Streams out the final GDSII layout file from the routed defAfter running a design, a directory called runs is created inside that design folder. Each run is placed under that directory. A run is either named after -tag or named with a timestamp of that run. A run folder contains:
logs - Runtime log of each tool. Can be useful in case of a crash.reports - Reports generated by some of the tools. (i.e. synthesis report, timing report, etc...)results - Final files created by completeing a stage. Can either be .def or .v or .gds.tmp - Files created by substages.The resulting directory tree is as follows:
designs/spm ├── config.tcl ├── runs │ ├── <tag> │ │ ├── config.tcl │ │ ├── logs │ │ │ ├── cts │ │ │ ├── floorplan │ │ │ ├── magic │ │ │ ├── placement │ │ │ ├── routing │ │ │ └── synthesis │ │ ├── reports │ │ │ ├── cts │ │ │ ├── floorplan │ │ │ ├── magic │ │ │ ├── placement │ │ │ ├── routing │ │ │ └── synthesis │ │ ├── results │ │ │ ├── cts │ │ │ ├── floorplan │ │ │ ├── magic │ │ │ ├── placement │ │ │ ├── routing │ │ │ └── synthesis │ │ └── tmp │ │ ├── cts │ │ ├── floorplan │ │ ├── magic │ │ ├── placement │ │ ├── routing │ │ └── synthesis
OpenLane requires some environment variables to be defined. These variables are split into three main categories:
A PDK should define at least one variant for the PDK. A common configuration file for all PDK variants is located in:
./pdks/<pdk>/common_config.tcl
A variant configuration file should define extra variables specific to that variant. It may also override vairables in the common PDK configuration file which is located in:
./pdks/<pdk>/<variant>/config.tcl
Flow specific variables are related to the flow and are initiallized with default values in:
./configuration/
Finally, each design should have it's own configuration file with some required variables which are available in this list. A design configuration file may override any of the variables defined in PDK or flow configuration files:
./designs/<design>/config.tcl
A list of all available variables can be found here.
OpenLane provides run_designs.py, a script that can do multiple runs in a parallel. A run consists of a design and a configuration file for the given design. For example the following has two runs: spm and xtea using their default configuration file config.tcl.:
python3 run_designs.py --designs spm xtea --tag test --threads 8
It can also do “regression” on the designs provided to the script. By providing a file that defines a predefined list of variables run_designs.py generates all possible combinations of configuration files per designs and runs the flow on each one of them.
In addition to files produced inside designs/<design>/runs/config_<tag>_<number> for each run on a design, three files are produced:
logs/<tag>_<timestamp>.log A log file that describes start and stopping time of a given run.logs/<tag>_<timestamp>.rpt A report file that provides a summary of each run. The summary conatins some metrics and the configuration of that runlogs/<tag>_<timestamp>_best.rpt A report file that selects the best configuration per design based on number of violationsThe script can be used in two ways
Running one or more designs.
python3 run_designs.py --designs spm xtea ...
A regression run that generates configuration files of all possible combinations of the passed regression file and runs them on the provided designs.
python3 run_designs.py --designs spm xtea --regression ./scripts/config/regression.config
These parameters must be provided in the file passed to --regression. Any file can be used. The file used above is just an example
adjustment_factor=(0.1 0.15)
utilization=(40 50)
density=(0.4)
synth_strategy=(1 3)
pdn_v_pitch=("153.6")
pdn_h_pitch=("153.18")
aspect_ratio=(1)
max_fanout=(5)
extra="
set ::env(PDK_VARIANT) scs8ms
"
In addition, extra is appended to every configuration file generated. So it is used to add some configurations sepecfic to this regression run.
Important Note: If you are going to launch two or more separate regression runs that include same design(s), make sure to set different tags for them.