set ::env(DESIGN_NAME) "genericfir"

set ::env(VERILOG_FILES) "./designs/genericfir/src/genericfir.v"

set ::env(CLOCK_PERIOD) "5.000"
set ::env(CLOCK_PORT) "i_clk"

set ::env(FP_CORE_UTIL) 30
set ::env(GLB_RT_ADJUSTMENT) 0.1
set ::env(SYNTH_STRAT) 2