set ::env(DESIGN_NAME) "y_huff"

set ::env(VERILOG_FILES) "./designs/y_huff/src/y_huff.v"
set ::env(SDC_FILE) "./designs/y_huff/src/y_huff.sdc"

set ::env(CLOCK_PERIOD) "2.000"
set ::env(CLOCK_PORT) "clk"

set ::env(FP_CORE_MARGIN) 3.36
set ::env(GLB_RT_ADJUSTMENT) 0.15
set ::env(SYNTH_STRATEGY) 2
set ::env(CLOCK_NET) $::env(CLOCK_PORT)