package require openlane
prep -design striVe_flat -tag toplevel2 -config config2 -overwrite

set padframe_cfg $::env(DESIGN_DIR)/src/padframe.cfg
set padframe_def $::env(DESIGN_DIR)/src/def/padframe.def
set diearea [padframe_extract_area -cfg $padframe_cfg]
set lefs 	 [glob $::env(DESIGN_DIR)/src/lef/*.lef]
set margin $::env(FP_CORE_MARGIN)
set corearea "[expr $margin + [lindex $diearea 0]] [expr $margin + [lindex $diearea 1]] [expr [lindex $diearea 2] - $margin] [expr [lindex $diearea 3] - $margin]"
set ::env(DIE_AREA) $diearea
set ::env(CORE_AREA) $corearea
set ::env(FP_SIZING) absolute

#config
# netlist verification
add_lefs -src $lefs
verilog_elaborate
init_floorplan
exec cp $::env(CURRENT_DEF) $::env(CURRENT_DEF).old
exec $::env(SCRIPTS_DIR)/remove_empty_nets.sh $::env(CURRENT_DEF)
exec python3 $::env(SCRIPTS_DIR)/padframe2fp.py -id $padframe_def -idn $::env(CURRENT_DEF) -il $::env(MERGED_LEF) |& tee $::env(TERMINAL_OUTPUT) $::env(CURRENT_DEF).pinsonly
set pinsonly $::env(CURRENT_DEF).pinsonly
set ::env(DESIGN_NAME) striVe_ChipCore
exec cp $::env(yosys_result_file_tag).v $::env(yosys_result_file_tag).v.old
run_synthesis
init_floorplan
place_io
#tap_decap
run_placement
gen_pdn
move_pins -from $pinsonly -to $::env(CURRENT_DEF)
run_routing
#run_magic