proc init_floorplan {args} {
	TIMER::timer_start
	set ::env(CURRENT_STAGE) floorplan
	if {$::env(FP_SIZING) == "absolute"} {
		try_catch verilog2def \
			-verilog $::env(yosys_result_file_tag).v \
			-lef $::env(MERGED_LEF) \
			-liberty $::env(LIB_SYNTH) \
			-top_module $::env(DESIGN_NAME) \
			-site $::env(PLACE_SITE) \
			-tracks $::env(TRACKS_INFO_FILE) \
			-units $::env(DEF_UNITS_PER_MICRON) \
			\
			-die_area $::env(DIE_AREA) \
			-core_area $::env(CORE_AREA) \
			\
			-def $::env(verilog2def_tmp_file_tag)_broken.def \
			-verbose \
			|& tee $::env(TERMINAL_OUTPUT) $::env(verilog2def_log_file_tag).log
	} else {
		try_catch verilog2def \
			-verilog $::env(yosys_result_file_tag).v \
			-lef $::env(MERGED_LEF) \
			-liberty $::env(LIB_SYNTH) \
			-top_module $::env(DESIGN_NAME) \
			-site $::env(PLACE_SITE) \
			-tracks $::env(TRACKS_INFO_FILE) \
			-units $::env(DEF_UNITS_PER_MICRON) \
			\
			-utilization $::env(FP_CORE_UTIL) \
			-aspect_ratio $::env(FP_ASPECT_RATIO) \
			-core_space $::env(FP_CORE_MARGIN) \
			\
			-def $::env(verilog2def_tmp_file_tag)_broken.def \
			-verbose \
			|& tee $::env(TERMINAL_OUTPUT) $::env(verilog2def_log_file_tag).log
	}
	exec cat $::env(verilog2def_tmp_file_tag)_broken.def | sed -r "s/(ROW.*) by /\\1 BY /g" > $::env(verilog2def_tmp_file_tag).def
	TIMER::timer_stop
	exec echo "[TIMER::get_runtime]" >> $::env(verilog2def_log_file_tag)_runtime.txt
	set_def $::env(verilog2def_tmp_file_tag).def
}

proc place_io {args} {
	TIMER::timer_start
#	try_catch ioPlacer \
#		-l $::env(MERGED_LEF) \
#		-d $::env(CURRENT_DEF) \
#		-h $::env(FP_IO_HMETAL) \
#		-v $::env(FP_IO_VMETAL) \
#		--random $::env(FP_IO_RANDOM) \
#		-w 1 \
#		\
#		-o $::env(ioPlacer_tmp_file_tag).def \
#		|& tee $::env(TERMINAL_OUTPUT) $::env(ioPlacer_log_file_tag).log
	try_catch openroad -exit $::env(SCRIPTS_DIR)/ioplacer.tcl |& tee $::env(TERMINAL_OUTPUT) $::env(ioPlacer_log_file_tag).log
	TIMER::timer_stop
	exec echo "[TIMER::get_runtime]" >> $::env(ioPlacer_log_file_tag)_runtime.txt
	set_def $::env(ioPlacer_tmp_file_tag).openroad.def
}

proc tap_decap {args} {
	try_catch cp $::env(CURRENT_DEF) $::env(tapcell_result_file_tag).def
	TIMER::timer_start
	try_catch tapcell -lef $::env(MERGED_LEF_UNPADDED) \
		-def $::env(tapcell_result_file_tag).def \
		-rule [expr $::env(FP_TAPCELL_DIST) * 2] \
		-welltap $::env(FP_WELLTAP_CELL) \
		-endcap $::env(FP_ENDCAP_CELL) \
		-outdef $::env(tapcell_result_file_tag).def \
		|& tee $::env(TERMINAL_OUTPUT) $::env(tapcell_log_file_tag).log
	TIMER::timer_stop
	exec echo "[TIMER::get_runtime]" >> $::env(tapcell_log_file_tag)_runtime.txt
	set_def $::env(tapcell_result_file_tag).def
}
proc tap_decap_or {args} {
	#try_catch cp $::env(CURRENT_DEF) $::env(tapcell_result_file_tag).def
	TIMER::timer_start
	set ::env(SAVE_DEF) $::env(tapcell_result_file_tag).def
	try_catch openroad -exit $::env(SCRIPTS_DIR)/openroad/or_tapcell.tcl |& tee $::env(TERMINAL_OUTPUT) $::env(tapcell_log_file_tag).log
	TIMER::timer_stop
	exec echo "[TIMER::get_runtime]" >> $::env(tapcell_log_file_tag)_runtime.txt
	set_def $::env(tapcell_result_file_tag).def
}


proc chip_floorplan {args} {
	# intial fp
	init_floorplan
	# remove pins section and others
	remove_pins -input $::env(CURRENT_DEF)
	remove_empty_nets -input $::env(CURRENT_DEF)
}

proc run_floorplan {args} {
# |----------------------------------------------------|
# |----------------   2. FLOORPLAN   ------------------|
# |----------------------------------------------------|
#
	# intial fp
	init_floorplan
	
	# place io
	place_io
	
#	# pdn generation
#	gen_pdn

	# tapcell
	tap_decap_or
}

package provide openlane 0.9