
# User config
set ::env(DESIGN_NAME) striVe_chipcore

# Change if needed
set ::env(VERILOG_FILES) [glob $::env(OPENLANE_ROOT)/designs/striVe_chipcore/src/verilog/*.v]
set ::env(EXTRA_LEFS) [glob $::env(DESIGN_DIR)/src/mag/*.lef]
set ::env(EXTRA_GDS_FILES) [glob $::env(DESIGN_DIR)/src/mag/*.gds]

# Fill this
set ::env(CLOCK_PERIOD) "50"

# check:
set ::env(CLOCK_PORT) "\\core.clk"
set ::env(CLOCK_NET) $::env(CLOCK_PORT)
set ::env(CELL_CLK_PORT) CLK

set ::env(FP_CORE_UTIL) 35

set ::env(FP_TAPCELL_DIST) 15

set ::env(FP_IO_VEXTEND) 2
set ::env(FP_IO_HEXTEND) 2
set ::env(FP_IO_VTHICKNESS_MULT) 4
set ::env(FP_IO_HTHICKNESS_MULT) 4

set ::env(MAGIC_PAD) 0
set ::env(MAGIC_ZEROIZE_ORIGIN) 1